drivers/video/tegra/dc/dp.c

   1 /*
   2  * drivers/video/tegra/dc/dp.c
   3  *
   4  * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/err.h>
  18 #include <linux/gpio.h>
  19 #include <linux/wait.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/debugfs.h>
  24 #include <linux/tegra-soc.h>
  25 #include <linux/clk/tegra.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #ifdef CONFIG_SWITCH
  31 #include <linux/switch.h>
  32 #endif
  33
  34 #include <mach/dc.h>
  35 #include <mach/fb.h>
  36
  37 #include "dp.h"
  38 #include "sor.h"
  39 #include "sor_regs.h"
  40 #include "dpaux_regs.h"
  41 #include "dpaux.h"
  42 #include "dc_priv.h"
  43 #include "edid.h"
  44 #include "dp_lt.h"
  45
  46 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
  47 #include "fake_panel.h"
  48 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
  49
  50 static bool tegra_dp_debug = true;
  51 module_param(tegra_dp_debug, bool, 0644);
  52 MODULE_PARM_DESC(tegra_dp_debug, "Enable to print all link configs");
  53
  54 static struct tegra_hpd_ops hpd_ops;
  55
  56 static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp);
  57 static inline void tegra_dp_default_int(struct tegra_dc_dp_data *dp,
  58                                         bool enable);
  59 static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp);
  60
  61 static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
  62 {
  63         return readl(dp->aux_base + reg * 4);
  64 }
  65
  66 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
  67         u32 reg, u32 val)
  68 {
  69         writel(val, dp->aux_base + reg * 4);
  70 }
  71
  72 static inline void tegra_dpaux_clk_enable(struct tegra_dc_dp_data *dp)
  73 {
  74         if (tegra_platform_is_linsim())
  75                 return;
  76         clk_prepare_enable(dp->dpaux_clk);
  77 }
  78
  79 static inline void tegra_dpaux_clk_disable(struct tegra_dc_dp_data *dp)
  80 {
  81         if (tegra_platform_is_linsim())
  82                 return;
  83         clk_disable_unprepare(dp->dpaux_clk);
  84 }
  85
  86 static inline void tegra_dp_clk_enable(struct tegra_dc_dp_data *dp)
  87 {
  88         if (!tegra_is_clk_enabled(dp->parent_clk))
  89                 clk_prepare_enable(dp->parent_clk);
  90 }
  91
  92 static inline void tegra_dp_clk_disable(struct tegra_dc_dp_data *dp)
  93 {
  94         if (tegra_is_clk_enabled(dp->parent_clk))
  95                 clk_disable_unprepare(dp->parent_clk);
  96 }
  97
  98 static inline void tegra_dpaux_write_field(struct tegra_dc_dp_data *dp,
  99                                         u32 reg, u32 mask, u32 val)
 100 {
 101         u32 reg_val = tegra_dpaux_readl(dp, reg);
 102         reg_val = (reg_val & ~mask) | (val & mask);
 103         tegra_dpaux_writel(dp, reg, reg_val);
 104 }
 105
 106 static inline void tegra_dp_int_en(struct tegra_dc_dp_data *dp, u32 intr)
 107 {
 108         u32 val;
 109
 110         /* clear pending interrupt */
 111         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, intr);
 112
 113         val = tegra_dpaux_readl(dp, DPAUX_INTR_EN_AUX);
 114         val |= intr;
 115
 116         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, val);
 117 }
 118
 119 static inline void tegra_dp_int_dis(struct tegra_dc_dp_data *dp, u32 intr)
 120 {
 121         u32 val;
 122
 123         val = tegra_dpaux_readl(dp, DPAUX_INTR_EN_AUX);
 124         val &= ~intr;
 125
 126         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, val);
 127 }
 128
 129 static inline void tegra_dp_enable_irq(u32 irq)
 130 {
 131         if (tegra_platform_is_fpga())
 132                 return;
 133
 134         enable_irq(irq);
 135 }
 136
 137 static inline void tegra_dp_disable_irq(u32 irq)
 138 {
 139         if (tegra_platform_is_fpga())
 140                 return;
 141
 142         disable_irq(irq);
 143 }
 144
 145 #define is_hotplug_supported(dp) \
 146 ({ \
 147         !tegra_platform_is_fpga() && \
 148         !tegra_platform_is_linsim() && \
 149         tegra_dc_is_ext_dp_panel(dp->dc) && \
 150         dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP; \
 151 })
 152
 153 static inline void tegra_dp_pending_hpd(struct tegra_dc_dp_data *dp)
 154 {
 155         if (!is_hotplug_supported(dp))
 156                 return;
 157
 158         tegra_hpd_set_pending_evt(&dp->hpd_data);
 159 }
 160
 161 static inline unsigned long
 162 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
 163                                 u32 reg, u32 mask, u32 exp_val,
 164                                 u32 poll_interval_us, u32 timeout_ms)
 165 {
 166         unsigned long   timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
 167         u32             reg_val    = 0;
 168
 169         if (tegra_platform_is_linsim())
 170                 return 0;
 171
 172         do {
 173                 usleep_range(poll_interval_us, poll_interval_us << 1);
 174                 reg_val = tegra_dpaux_readl(dp, reg);
 175         } while (((reg_val & mask) != exp_val) &&
 176                 time_after(timeout_jf, jiffies));
 177
 178         if ((reg_val & mask) == exp_val)
 179                 return 0;       /* success */
 180         dev_dbg(&dp->dc->ndev->dev,
 181                 "dpaux_poll_register 0x%x: timeout\n", reg);
 182         return jiffies - timeout_jf + 1;
 183 }
 184
 185 static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
 186 {
 187         int err = 0;
 188
 189         if (unlikely(tegra_platform_is_fpga())) {
 190                 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
 191                                 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
 192                                 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
 193                                 100, DP_AUX_TIMEOUT_MS) != 0)
 194                         err = -EFAULT;
 195         }
 196
 197         if (likely(tegra_platform_is_silicon())) {
 198                 INIT_COMPLETION(dp->aux_tx);
 199                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_TX_DONE);
 200                 if (tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL) &
 201                                 DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING) {
 202                         if (!wait_for_completion_timeout(&dp->aux_tx,
 203                                 msecs_to_jiffies(DP_AUX_TIMEOUT_MS)))
 204                                 err = -EBUSY;
 205                 }
 206                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_TX_DONE);
 207         }
 208
 209         if (err)
 210                 dev_err(&dp->dc->ndev->dev, "dp: aux tx timeout\n");
 211         return err;
 212 }
 213
 214
 215 /*
 216  * To config DPAUX Transaction Control
 217  * o Inputs
 218  *  - dp    : pointer to DP information
 219  *  - cmd   : transaction command DPAUX_DP_AUXCTL_CMD_xxx
 220  *  - addr  : transaction address (20 bit sink device AUX reg addr space)
 221  *  - p_wrdt: pointer to the write data buffer / NULL:no write data
 222  *  - size  : 1-16: number of byte to read/write
 223  *            0   : address only transaction
 224  * o Outputs
 225  *  - return: error status; 0:no error / !0:error
 226  */
 227 static int tegra_dp_aux_tx_config(struct tegra_dc_dp_data *dp,
 228                                 u32 cmd, u32 addr, u8 *p_wrdt, u32 size)
 229 {
 230         int i;
 231         u32  *data = (u32 *)p_wrdt;
 232
 233         if (DP_AUX_MAX_BYTES < size)
 234                 goto fail;
 235
 236         switch (cmd) {
 237         case DPAUX_DP_AUXCTL_CMD_I2CWR:
 238         case DPAUX_DP_AUXCTL_CMD_I2CRD:
 239         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
 240         case DPAUX_DP_AUXCTL_CMD_MOTWR:
 241         case DPAUX_DP_AUXCTL_CMD_MOTRD:
 242         case DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT:
 243         case DPAUX_DP_AUXCTL_CMD_AUXWR:
 244         case DPAUX_DP_AUXCTL_CMD_AUXRD:
 245                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
 246                                         DPAUX_DP_AUXCTL_CMD_MASK, cmd);
 247                 break;
 248         default:
 249                 goto fail;
 250         };
 251         tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
 252                                 DPAUX_DP_AUXCTL_CMDLEN_MASK,
 253                                 size ? size - 1 : 0);
 254         tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
 255                         DPAUX_DP_AUXCTL_ADDRESS_ONLY_MASK,
 256                         (0 == size) ? DPAUX_DP_AUXCTL_ADDRESS_ONLY_TRUE :
 257                                 DPAUX_DP_AUXCTL_ADDRESS_ONLY_FALSE);
 258
 259         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
 260         for (i = 0; size && data && i < (DP_AUX_MAX_BYTES / 4); ++i)
 261                 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), data[i]);
 262
 263         return 0;
 264 fail:
 265         return -EINVAL;
 266 }
 267
 268 int tegra_dc_dpaux_write_chunk_locked(struct tegra_dc_dp_data *dp,
 269         u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat)
 270 {
 271         int err = 0;
 272         u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
 273         u32 defer_retries       = DP_AUX_DEFER_MAX_TRIES;
 274
 275         WARN_ON(!mutex_is_locked(&dp->dpaux_lock));
 276
 277         switch (cmd) {
 278         case DPAUX_DP_AUXCTL_CMD_I2CWR:
 279         case DPAUX_DP_AUXCTL_CMD_MOTWR:
 280         case DPAUX_DP_AUXCTL_CMD_AUXWR:
 281                 break;
 282         default:
 283                 dev_err(&dp->dc->ndev->dev,
 284                         "dp: invalid aux write cmd: 0x%x\n", cmd);
 285                 return -EINVAL;
 286         };
 287
 288         err = tegra_dp_aux_tx_config(dp, cmd, addr, data, *size);
 289         if (err < 0) {
 290                 dev_err(&dp->dc->ndev->dev, "dp: incorrect aux tx params\n");
 291                 return err;
 292         }
 293
 294         if (tegra_platform_is_silicon()) {
 295                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 296                 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
 297                         dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
 298                         return -EFAULT;
 299                 }
 300         }
 301
 302         while ((timeout_retries > 0) && (defer_retries > 0)) {
 303                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
 304                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
 305                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
 306                                 DP_DPCP_RETRY_SLEEP_NS << 1);
 307
 308                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
 309                                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
 310                                         DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING);
 311
 312                 if (tegra_dpaux_wait_transaction(dp))
 313                         dev_err(&dp->dc->ndev->dev,
 314                                 "dp: aux write transaction timeout\n");
 315
 316                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 317
 318                 /* Ignore I2C errors on fpga */
 319                 if (tegra_platform_is_fpga())
 320                         *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
 321
 322                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
 323                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
 324                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
 325                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING) ||
 326                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_NACK) ||
 327                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK)) {
 328                         if (timeout_retries-- > 0) {
 329                                 dev_info(&dp->dc->ndev->dev,
 330                                         "dp: aux write retry (0x%x) -- %d\n",
 331                                         *aux_stat, timeout_retries);
 332                                 /* clear the error bits */
 333                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
 334                                         *aux_stat);
 335                                 continue;
 336                         } else {
 337                                 dev_err(&dp->dc->ndev->dev,
 338                                         "dp: aux write got error (0x%x)\n",
 339                                         *aux_stat);
 340                                 return -EFAULT;
 341                         }
 342                 }
 343
 344                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
 345                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
 346                         if (defer_retries-- > 0) {
 347                                 dev_info(&dp->dc->ndev->dev,
 348                                         "dp: aux write defer (0x%x) -- %d\n",
 349                                         *aux_stat, defer_retries);
 350                                 /* clear the error bits */
 351                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
 352                                         *aux_stat);
 353                                 continue;
 354                         } else {
 355                                 dev_err(&dp->dc->ndev->dev,
 356                                         "dp: aux write defer exceeds max retries "
 357                                         "(0x%x)\n",
 358                                         *aux_stat);
 359                                 return -EFAULT;
 360                         }
 361                 }
 362
 363                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
 364                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
 365                         (*size)++;
 366                         return 0;
 367                 } else {
 368                         dev_err(&dp->dc->ndev->dev,
 369                                 "dp: aux write failed (0x%x)\n", *aux_stat);
 370                         return -EFAULT;
 371                 }
 372         }
 373         /* Should never come to here */
 374         return -EFAULT;
 375 }
 376
 377 int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 378         u8 *data, u32 *size, u32 *aux_stat)
 379 {
 380         u32     cur_size = 0;
 381         u32     finished = 0;
 382         int     ret      = 0;
 383
 384         if (*size == 0) {
 385                 dev_err(&dp->dc->ndev->dev,
 386                         "dp: aux write size can't be 0\n");
 387                 return -EINVAL;
 388         }
 389
 390         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 391                 return ret;
 392
 393         mutex_lock(&dp->dpaux_lock);
 394         do {
 395                 cur_size = *size - finished;
 396                 if (cur_size > DP_AUX_MAX_BYTES)
 397                         cur_size = DP_AUX_MAX_BYTES;
 398
 399                 ret = tegra_dc_dpaux_write_chunk_locked(dp, cmd, addr,
 400                         data, &cur_size, aux_stat);
 401
 402                 finished += cur_size;
 403                 addr += cur_size;
 404                 data += cur_size;
 405
 406                 if (ret)
 407                         break;
 408         } while (*size > finished);
 409         mutex_unlock(&dp->dpaux_lock);
 410
 411         *size = finished;
 412         return ret;
 413 }
 414
 415 int tegra_dc_dpaux_read_chunk_locked(struct tegra_dc_dp_data *dp,
 416         u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat)
 417 {
 418         int err = 0;
 419         u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
 420         u32 defer_retries       = DP_AUX_DEFER_MAX_TRIES;
 421
 422         WARN_ON(!mutex_is_locked(&dp->dpaux_lock));
 423
 424         switch (cmd) {
 425         case DPAUX_DP_AUXCTL_CMD_I2CRD:
 426         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
 427         case DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT:
 428         case DPAUX_DP_AUXCTL_CMD_MOTRD:
 429         case DPAUX_DP_AUXCTL_CMD_AUXRD:
 430                 break;
 431         default:
 432                 dev_err(&dp->dc->ndev->dev,
 433                         "dp: invalid aux read cmd: 0x%x\n", cmd);
 434                 return -EINVAL;
 435         };
 436
 437         err = tegra_dp_aux_tx_config(dp, cmd, addr, NULL, *size);
 438         if (err < 0) {
 439                 dev_err(&dp->dc->ndev->dev, "dp: incorrect aux tx params\n");
 440                 return err;
 441         }
 442
 443         if (tegra_platform_is_silicon()) {
 444                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 445                 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
 446                         dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
 447                         return -EFAULT;
 448                 }
 449         }
 450
 451         while ((timeout_retries > 0) && (defer_retries > 0)) {
 452                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
 453                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
 454                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
 455                                 DP_DPCP_RETRY_SLEEP_NS << 1);
 456
 457                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
 458                                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
 459                                         DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING);
 460
 461                 if (tegra_dpaux_wait_transaction(dp))
 462                         dev_err(&dp->dc->ndev->dev,
 463                                 "dp: aux read transaction timeout\n");
 464
 465                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 466
 467                 /* Ignore I2C errors on fpga */
 468                 if (!tegra_platform_is_silicon())
 469                         *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
 470
 471                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
 472                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
 473                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
 474                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
 475                         if (timeout_retries-- > 0) {
 476                                 dev_info(&dp->dc->ndev->dev,
 477                                         "dp: aux read retry (0x%x) -- %d\n",
 478                                         *aux_stat, timeout_retries);
 479                                 /* clear the error bits */
 480                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
 481                                         *aux_stat);
 482                                 continue; /* retry */
 483                         } else {
 484                                 dev_err(&dp->dc->ndev->dev,
 485                                         "dp: aux read got error (0x%x)\n",
 486                                         *aux_stat);
 487                                 return -EFAULT;
 488                         }
 489                 }
 490
 491                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
 492                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
 493                         if (defer_retries-- > 0) {
 494                                 dev_info(&dp->dc->ndev->dev,
 495                                         "dp: aux read defer (0x%x) -- %d\n",
 496                                         *aux_stat, defer_retries);
 497                                 /* clear the error bits */
 498                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
 499                                         *aux_stat);
 500                                 continue;
 501                         } else {
 502                                 dev_err(&dp->dc->ndev->dev,
 503                                         "dp: aux read defer exceeds max retries "
 504                                         "(0x%x)\n", *aux_stat);
 505                                 return -EFAULT;
 506                         }
 507                 }
 508
 509                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
 510                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
 511                         int i;
 512                         u32 temp_data[4];
 513
 514                         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
 515                                 temp_data[i] = tegra_dpaux_readl(dp,
 516                                         DPAUX_DP_AUXDATA_READ_W(i));
 517
 518                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
 519                         memcpy(data, temp_data, *size);
 520
 521                         return 0;
 522                 } else {
 523                         dev_err(&dp->dc->ndev->dev,
 524                                 "dp: aux read failed (0x%x\n", *aux_stat);
 525                         return -EFAULT;
 526                 }
 527         }
 528         /* Should never come to here */
 529         return -EFAULT;
 530 }
 531
 532 int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 533         u8 *data, u32 *size, u32 *aux_stat)
 534 {
 535         u32     finished = 0;
 536         u32     cur_size;
 537         int     ret      = 0;
 538
 539         if (*size == 0) {
 540                 dev_err(&dp->dc->ndev->dev,
 541                         "dp: aux read size can't be 0\n");
 542                 return -EINVAL;
 543         }
 544
 545         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 546                 return  ret;
 547
 548         mutex_lock(&dp->dpaux_lock);
 549         do {
 550                 cur_size = *size - finished;
 551                 if (cur_size > DP_AUX_MAX_BYTES)
 552                         cur_size = DP_AUX_MAX_BYTES;
 553
 554                 ret = tegra_dc_dpaux_read_chunk_locked(dp, cmd, addr,
 555                         data, &cur_size, aux_stat);
 556
 557                 if (ret)
 558                         break;
 559
 560                 /* cur_size should be the real size returned */
 561                 addr += cur_size;
 562                 data += cur_size;
 563                 finished += cur_size;
 564
 565         } while (*size > finished);
 566         mutex_unlock(&dp->dpaux_lock);
 567
 568         *size = finished;
 569         return ret;
 570 }
 571
 572 /* I2C read over DPAUX cannot handle more than 16B per transaction due to
 573  * DPAUX transaction limitation.
 574  * This requires breaking each read into multiple i2c write/read transaction */
 575 static int tegra_dc_i2c_read(struct tegra_dc_dp_data *dp, u32 i2c_addr,
 576         u32 addr, u8 *data, u32 *size, u32 *aux_stat)
 577 {
 578         u32     finished = 0;
 579         u32     cur_size;
 580         int     ret      = 0;
 581         u32     len;
 582         u8      iaddr    = (u8)addr;
 583
 584         if (*size == 0) {
 585                 dev_err(&dp->dc->ndev->dev,
 586                         "dp: i2c read size can't be 0\n");
 587                 return -EINVAL;
 588         }
 589
 590         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 591                 return ret;
 592
 593         mutex_lock(&dp->dpaux_lock);
 594         do {
 595                 cur_size = *size - finished;
 596                 if (cur_size > DP_AUX_MAX_BYTES)
 597                         cur_size = DP_AUX_MAX_BYTES;
 598
 599                 len = 1;
 600                 ret = tegra_dc_dpaux_write_chunk_locked(dp,
 601                         DPAUX_DP_AUXCTL_CMD_MOTWR,
 602                         i2c_addr, &iaddr, &len, aux_stat);
 603                 if (!ret) {
 604                         ret = tegra_dc_dpaux_read_chunk_locked(dp,
 605                                 DPAUX_DP_AUXCTL_CMD_I2CRD,
 606                                 i2c_addr, data, &cur_size, aux_stat);
 607                 }
 608                 if (ret)
 609                         break;
 610
 611                 iaddr += cur_size;
 612                 data += cur_size;
 613                 finished += cur_size;
 614         } while (*size > finished);
 615         mutex_unlock(&dp->dpaux_lock);
 616
 617         *size = finished;
 618         return ret;
 619 }
 620
 621 int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
 622         u8 *data_ptr)
 623 {
 624         u32 size = 1;
 625         u32 status = 0;
 626         int ret = 0;
 627
 628         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 629                 return ret;
 630
 631         mutex_lock(&dp->dpaux_lock);
 632         ret = tegra_dc_dpaux_read_chunk_locked(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
 633                 cmd, data_ptr, &size, &status);
 634         mutex_unlock(&dp->dpaux_lock);
 635         if (ret)
 636                 dev_err(&dp->dc->ndev->dev,
 637                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
 638                         cmd, status);
 639
 640         return ret;
 641 }
 642
 643 static int tegra_dc_dp_i2c_xfer(struct tegra_dc *dc, struct i2c_msg *msgs,
 644         int num)
 645 {
 646         struct i2c_msg *pmsg;
 647         int i;
 648         u32 aux_stat;
 649         int status = 0;
 650         u32 len = 0;
 651         u32 start_addr;
 652         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
 653
 654         for (i = 0; i < num; ++i) {
 655                 pmsg = &msgs[i];
 656
 657                 if (!pmsg->flags) { /* write */
 658                         /* Ignore the write-for-read command now as it is
 659                            already handled in the read operations */
 660                 } else if (pmsg->flags & I2C_M_RD) { /* Read */
 661                         len = pmsg->len;
 662                         start_addr = 0;
 663                         status = tegra_dc_i2c_read(dp, pmsg->addr, start_addr,
 664                                 pmsg->buf, &len, &aux_stat);
 665                         if (status) {
 666                                 dev_err(&dp->dc->ndev->dev,
 667                                         "dp: Failed for I2C read"
 668                                         " addr:%d, size:%d, stat:0x%x\n",
 669                                         pmsg->addr, len, aux_stat);
 670                                 return status;
 671                         }
 672                 } else {
 673                         /* No other functionalities are supported for now */
 674                         dev_err(&dp->dc->ndev->dev,
 675                                 "dp: i2x_xfer: Unknown flag 0x%x\n",
 676                                 pmsg->flags);
 677                         return -EINVAL;
 678                 }
 679         }
 680         return i;
 681 }
 682
 683 static i2c_transfer_func_t tegra_dp_hpd_op_edid_read(void *drv_data)
 684 {
 685         struct tegra_dc_dp_data *dp = drv_data;
 686
 687         return (dp->edid_src == EDID_SRC_DT) ?
 688                 tegra_dc_edid_blob : tegra_dc_dp_i2c_xfer;
 689 }
 690
 691 int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
 692         u8 data)
 693 {
 694         u32 size = 1;
 695         u32 status = 0;
 696         int ret;
 697
 698         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 699                 return 0;
 700
 701         mutex_lock(&dp->dpaux_lock);
 702         ret = tegra_dc_dpaux_write_chunk_locked(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
 703                 cmd, &data, &size, &status);
 704         mutex_unlock(&dp->dpaux_lock);
 705         if (ret)
 706                 dev_err(&dp->dc->ndev->dev,
 707                         "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
 708                         cmd, status);
 709         return ret;
 710 }
 711
 712 static inline int tegra_dp_dpcd_write_field(struct tegra_dc_dp_data *dp,
 713                                         u32 cmd, u8 mask, u8 data)
 714 {
 715         u8 dpcd_data;
 716         int ret;
 717
 718         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
 719                 return 0;
 720
 721         might_sleep();
 722
 723         CHECK_RET(tegra_dc_dp_dpcd_read(dp, cmd, &dpcd_data));
 724         dpcd_data &= ~mask;
 725         dpcd_data |= data;
 726         CHECK_RET(tegra_dc_dp_dpcd_write(dp, cmd, dpcd_data));
 727
 728         return 0;
 729 }
 730
 731 static inline u64 tegra_div64(u64 dividend, u32 divisor)
 732 {
 733         do_div(dividend, divisor);
 734         return dividend;
 735 }
 736
 737 #ifdef CONFIG_DEBUG_FS
 738 static int dbg_dp_show(struct seq_file *s, void *unused)
 739 {
 740 #define DUMP_REG(a) seq_printf(s, "%-32s  %03x  %08x\n",        \
 741                 #a, a, tegra_dpaux_readl(dp, a))
 742
 743         struct tegra_dc_dp_data *dp = s->private;
 744
 745         tegra_dc_io_start(dp->dc);
 746         tegra_dpaux_clk_enable(dp);
 747
 748         DUMP_REG(DPAUX_INTR_EN_AUX);
 749         DUMP_REG(DPAUX_INTR_AUX);
 750         DUMP_REG(DPAUX_DP_AUXADDR);
 751         DUMP_REG(DPAUX_DP_AUXCTL);
 752         DUMP_REG(DPAUX_DP_AUXSTAT);
 753         DUMP_REG(DPAUX_HPD_CONFIG);
 754         DUMP_REG(DPAUX_HPD_IRQ_CONFIG);
 755         DUMP_REG(DPAUX_DP_AUX_CONFIG);
 756         DUMP_REG(DPAUX_HYBRID_PADCTL);
 757         DUMP_REG(DPAUX_HYBRID_SPARE);
 758
 759         tegra_dpaux_clk_disable(dp);
 760         tegra_dc_io_end(dp->dc);
 761
 762         return 0;
 763 }
 764
 765 static int dbg_dp_open(struct inode *inode, struct file *file)
 766 {
 767         return single_open(file, dbg_dp_show, inode->i_private);
 768 }
 769
 770 static const struct file_operations dbg_fops = {
 771         .open           = dbg_dp_open,
 772         .read           = seq_read,
 773         .llseek         = seq_lseek,
 774         .release        = single_release,
 775 };
 776
 777 static int lane_count_show(struct seq_file *s, void *unused)
 778 {
 779         struct tegra_dc_dp_data *dp = s->private;
 780         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
 781
 782         seq_puts(s, "\n");
 783         seq_printf(s,
 784                 "\tDP Lane_Count: \t%d\n",
 785                 cfg->lane_count);
 786         return 0;
 787 }
 788
 789 static ssize_t lane_count_set(struct file *file, const char __user *buf,
 790                                                 size_t count, loff_t *off)
 791 {
 792         struct seq_file *s = file->private_data;
 793         struct tegra_dc_dp_data *dp = s->private;
 794         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
 795         long lane_count = 0;
 796         int ret = 0;
 797
 798         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
 799                 return -EINVAL;
 800
 801         ret = kstrtol_from_user(buf, count, 10, &lane_count);
 802         if (ret < 0)
 803                 return ret;
 804
 805         if (cfg->lane_count == lane_count)
 806                 return -EINVAL;
 807
 808         /* disable the dc and output controllers */
 809         if (dp->dc->enabled)
 810                 tegra_dc_disable(dp->dc);
 811
 812         dev_info(&dp->dc->ndev->dev, "Setting the lanecount from %d to %ld\n",
 813                         cfg->lane_count, lane_count);
 814
 815         cfg->lane_count = lane_count;
 816
 817         /* check if needed or not for validity purpose */
 818         ret = tegra_dc_dp_calc_config(dp, dp->mode, cfg);
 819         if (!ret)
 820                 dev_info(&dp->dc->ndev->dev,
 821                         "Unable to set lane_count properly\n");
 822
 823         /* disable the dc and output controllers */
 824         if (!dp->dc->enabled)
 825                 tegra_dc_enable(dp->dc);
 826
 827         return count;
 828 }
 829
 830 static int lane_count_open(struct inode *inode, struct file *file)
 831 {
 832         return single_open(file, lane_count_show, inode->i_private);
 833 }
 834
 835 static const struct file_operations lane_count_fops = {
 836         .open           = lane_count_open,
 837         .read           = seq_read,
 838         .write          = lane_count_set,
 839         .llseek         = seq_lseek,
 840         .release        = single_release,
 841 };
 842
 843 static int link_speed_show(struct seq_file *s, void *unused)
 844 {
 845         struct tegra_dc_dp_data *dp = s->private;
 846         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
 847
 848         seq_puts(s, "\n");
 849         seq_printf(s,
 850                 "\tDP Link Speed: \t%d\n",
 851                 cfg->link_bw);
 852         return 0;
 853 }
 854
 855 static ssize_t link_speed_set(struct file *file, const char __user *buf,
 856                                                 size_t count, loff_t *off)
 857 {
 858         struct seq_file *s = file->private_data;
 859         struct tegra_dc_dp_data *dp = s->private;
 860         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
 861         long link_speed = 0;
 862         int ret = 0;
 863
 864         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
 865                 return -EINVAL;
 866
 867         ret = kstrtol_from_user(buf, count, 10, &link_speed);
 868         if (ret < 0)
 869                 return ret;
 870
 871         if (cfg->link_bw == link_speed)
 872                 return -EINVAL;
 873
 874         /* disable the dc and output controllers */
 875         if (dp->dc->enabled)
 876                 tegra_dc_disable(dp->dc);
 877
 878         dev_info(&dp->dc->ndev->dev, "Setting the linkspeed from %d to %ld\n",
 879                         cfg->link_bw, link_speed);
 880
 881         cfg->link_bw = link_speed;
 882
 883         /* check if needed or not for validity purpose */
 884         ret = tegra_dc_dp_calc_config(dp, dp->mode, cfg);
 885         if (!ret)
 886                 dev_info(&dp->dc->ndev->dev,
 887                         "Unable to set linkspeed properly\n");
 888
 889         /* disable the dc and output controllers */
 890         if (!dp->dc->enabled)
 891                 tegra_dc_enable(dp->dc);
 892
 893         return count;
 894 }
 895
 896 static int link_speed_open(struct inode *inode, struct file *file)
 897 {
 898         return single_open(file, link_speed_show, inode->i_private);
 899 }
 900
 901 static const struct file_operations link_speed_fops = {
 902         .open           = link_speed_open,
 903         .read           = seq_read,
 904         .write          = link_speed_set,
 905         .llseek         = seq_lseek,
 906         .release        = single_release,
 907 };
 908
 909 static int dbg_hotplug_show(struct seq_file *m, void *unused)
 910 {
 911         struct tegra_dc_dp_data *dp = m->private;
 912         struct tegra_dc *dc = dp->dc;
 913
 914         if (WARN_ON(!dp || !dc || !dc->out))
 915                 return -EINVAL;
 916
 917         seq_printf(m, "dp hpd state: %d\n", dc->out->hotplug_state);
 918         return 0;
 919 }
 920
 921 static int dbg_hotplug_open(struct inode *inode, struct file *file)
 922 {
 923         return single_open(file, dbg_hotplug_show, inode->i_private);
 924 }
 925
 926 /*
 927  * sw control for hpd.
 928  * 0 is normal state, hw drives hpd.
 929  * -1 is force deassert, sw drives hpd.
 930  * 1 is force assert, sw drives hpd.
 931  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
 932  */
 933 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
 934         size_t len, loff_t *pos)
 935 {
 936         struct seq_file *m = file->private_data; /* single_open() initialized */
 937         struct tegra_dc_dp_data *dp = m->private;
 938         struct tegra_dc *dc = dp->dc;
 939         int ret;
 940         long new_state;
 941
 942         if (WARN_ON(!dp || !dc || !dc->out))
 943                 return -EINVAL;
 944
 945         ret = kstrtol_from_user(addr, len, 10, &new_state);
 946         if (ret < 0)
 947                 return ret;
 948
 949         if (dc->out->hotplug_state == TEGRA_HPD_STATE_NORMAL
 950                 && new_state != TEGRA_HPD_STATE_NORMAL
 951                 && tegra_dc_hotplug_supported(dc)) {
 952                 /* SW controlled hotplug. Ignore hpd HW interrupts. */
 953                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_PLUG_EVENT |
 954                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT |
 955                                 DPAUX_INTR_EN_AUX_PLUG_EVENT);
 956         } else if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL
 957                 && new_state == TEGRA_HPD_STATE_NORMAL
 958                 && tegra_dc_hotplug_supported(dc)) {
 959                 /* Enable hpd HW interrupts */
 960                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_PLUG_EVENT |
 961                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT |
 962                                 DPAUX_INTR_EN_AUX_PLUG_EVENT);
 963         }
 964
 965         dc->out->hotplug_state = new_state;
 966
 967         tegra_dp_pending_hpd(dp);
 968
 969         return len;
 970 }
 971
 972 static const struct file_operations dbg_hotplug_fops = {
 973         .open = dbg_hotplug_open,
 974         .read = seq_read,
 975         .write = dbg_hotplug_write,
 976         .llseek = seq_lseek,
 977         .release = single_release,
 978 };
 979
 980 static struct dentry *dpdir;
 981
 982 static void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
 983 {
 984         struct dentry *retval;
 985
 986         dpdir = debugfs_create_dir("tegra_dp", NULL);
 987         if (!dpdir)
 988                 return;
 989         retval = debugfs_create_file("regs", S_IRUGO, dpdir, dp, &dbg_fops);
 990         if (!retval)
 991                 goto free_out;
 992         retval = debugfs_create_file("lanes", S_IRUGO, dpdir, dp,
 993                 &lane_count_fops);
 994         if (!retval)
 995                 goto free_out;
 996         retval = debugfs_create_file("linkspeed", S_IRUGO, dpdir, dp,
 997                 &link_speed_fops);
 998         if (!retval)
 999                 goto free_out;
1000
1001         /* hotplug not allowed for eDP */
1002         if (is_hotplug_supported(dp)) {
1003                 retval = debugfs_create_file("hotplug", S_IRUGO, dpdir, dp,
1004                         &dbg_hotplug_fops);
1005                 if (!retval)
1006                         goto free_out;
1007         }
1008
1009         return;
1010 free_out:
1011         debugfs_remove_recursive(dpdir);
1012         dpdir = NULL;
1013         return;
1014 }
1015 #else
1016 static inline void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
1017 { }
1018 #endif
1019
1020 static void tegra_dpaux_enable(struct tegra_dc_dp_data *dp)
1021 {
1022         /* do not enable interrupt for now. */
1023         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
1024
1025         /* clear interrupt */
1026         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
1027
1028         tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
1029                 DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
1030                 DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
1031                 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
1032                 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
1033
1034         tegra_dpaux_pad_power(dp->dc,
1035                 tegra_dc_which_sor(dp->dc) ? TEGRA_DPAUX_INSTANCE_1 :
1036                 TEGRA_DPAUX_INSTANCE_0, true);
1037 }
1038
1039 static int tegra_dp_panel_power_state(struct tegra_dc_dp_data *dp, u8 state)
1040 {
1041         u32 retry = 0;
1042         int ret;
1043
1044         do {
1045                 ret = tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER, state);
1046         } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1047
1048         return ret;
1049 }
1050
1051 __maybe_unused
1052 static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
1053         const struct tegra_dc_dp_link_config *cfg)
1054 {
1055         if (!tegra_dp_debug)
1056                 return;
1057
1058         BUG_ON(!cfg);
1059
1060         dev_info(&dp->dc->ndev->dev, "DP config: cfg_name               "
1061                 "cfg_value\n");
1062         dev_info(&dp->dc->ndev->dev, "           Lane Count             %d\n",
1063                 cfg->max_lane_count);
1064         dev_info(&dp->dc->ndev->dev, "           SupportEnhancedFraming %s\n",
1065                 cfg->support_enhanced_framing ? "Y" : "N");
1066         dev_info(&dp->dc->ndev->dev, "           SupportAltScrmbRstFffe %s\n",
1067                 cfg->alt_scramber_reset_cap ? "Y" : "N");
1068         dev_info(&dp->dc->ndev->dev, "           Bandwidth              %d\n",
1069                 cfg->max_link_bw);
1070         dev_info(&dp->dc->ndev->dev, "           bpp                    %d\n",
1071                 cfg->bits_per_pixel);
1072         dev_info(&dp->dc->ndev->dev, "           EnhancedFraming        %s\n",
1073                 cfg->enhanced_framing ? "Y" : "N");
1074         dev_info(&dp->dc->ndev->dev, "           Scramble_enabled       %s\n",
1075                 cfg->scramble_ena ? "Y" : "N");
1076         dev_info(&dp->dc->ndev->dev, "           LinkBW                 %d\n",
1077                 cfg->link_bw);
1078         dev_info(&dp->dc->ndev->dev, "           lane_count             %d\n",
1079                 cfg->lane_count);
1080         dev_info(&dp->dc->ndev->dev, "           activespolarity        %d\n",
1081                 cfg->activepolarity);
1082         dev_info(&dp->dc->ndev->dev, "           active_count           %d\n",
1083                 cfg->active_count);
1084         dev_info(&dp->dc->ndev->dev, "           tu_size                %d\n",
1085                 cfg->tu_size);
1086         dev_info(&dp->dc->ndev->dev, "           active_frac            %d\n",
1087                 cfg->active_frac);
1088         dev_info(&dp->dc->ndev->dev, "           watermark              %d\n",
1089                 cfg->watermark);
1090         dev_info(&dp->dc->ndev->dev, "           hblank_sym             %d\n",
1091                 cfg->hblank_sym);
1092         dev_info(&dp->dc->ndev->dev, "           vblank_sym             %d\n",
1093                 cfg->vblank_sym);
1094 };
1095
1096 /* Calcuate if given cfg can meet the mode request. */
1097 /* Return true if mode is possible, false otherwise. */
1098 bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
1099         const struct tegra_dc_mode *mode,
1100         struct tegra_dc_dp_link_config *cfg)
1101 {
1102         const u32       link_rate = 27 * cfg->link_bw * 1000 * 1000;
1103         const u64       f         = 100000;     /* precision factor */
1104
1105         u32     num_linkclk_line; /* Number of link clocks per line */
1106         u64     ratio_f; /* Ratio of incoming to outgoing data rate */
1107         u64     frac_f;
1108         u64     activesym_f;    /* Activesym per TU */
1109         u64     activecount_f;
1110         u32     activecount;
1111         u32     activepolarity;
1112         u64     approx_value_f;
1113         u32     activefrac                = 0;
1114         u64     accumulated_error_f       = 0;
1115         u32     lowest_neg_activecount    = 0;
1116         u32     lowest_neg_activepolarity = 0;
1117         u32     lowest_neg_tusize         = 64;
1118         u32     num_symbols_per_line;
1119         u64     lowest_neg_activefrac     = 0;
1120         u64     lowest_neg_error_f        = 64 * f;
1121         u64     watermark_f;
1122
1123         int     i;
1124         bool    neg;
1125         unsigned long rate;
1126
1127         cfg->is_valid = false;
1128
1129         rate = tegra_dc_pclk_round_rate(dp->sor->dc, dp->sor->dc->mode.pclk);
1130
1131         if (!link_rate || !cfg->lane_count || !rate ||
1132                 !cfg->bits_per_pixel)
1133                 return false;
1134
1135         if ((u64)rate * cfg->bits_per_pixel >=
1136                 (u64)link_rate * 8 * cfg->lane_count) {
1137                 dev_dbg(&dp->dc->ndev->dev,
1138                         "Requested rate calc > link_rate calc\n");
1139                 return false;
1140         }
1141
1142         num_linkclk_line = (u32)tegra_div64(
1143                 (u64)link_rate * mode->h_active, rate);
1144
1145         ratio_f = (u64)rate * cfg->bits_per_pixel * f;
1146         ratio_f /= 8;
1147         ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
1148
1149         for (i = 64; i >= 32; --i) {
1150                 activesym_f     = ratio_f * i;
1151                 activecount_f   = tegra_div64(activesym_f, (u32)f) * f;
1152                 frac_f          = activesym_f - activecount_f;
1153                 activecount     = (u32)tegra_div64(activecount_f, (u32)f);
1154
1155                 if (frac_f < (f / 2)) /* fraction < 0.5 */
1156                         activepolarity = 0;
1157                 else {
1158                         activepolarity = 1;
1159                         frac_f = f - frac_f;
1160                 }
1161
1162                 if (frac_f != 0) {
1163                         frac_f = tegra_div64((f * f),  frac_f); /* 1/fraction */
1164                         if (frac_f > (15 * f))
1165                                 activefrac = activepolarity ? 1 : 15;
1166                         else
1167                                 activefrac = activepolarity ?
1168                                         (u32)tegra_div64(frac_f, (u32)f) + 1 :
1169                                         (u32)tegra_div64(frac_f, (u32)f);
1170                 }
1171
1172                 if (activefrac == 1)
1173                         activepolarity = 0;
1174
1175                 if (activepolarity == 1)
1176                         approx_value_f = activefrac ? tegra_div64(
1177                                 activecount_f + (activefrac * f - f) * f,
1178                                 (activefrac * f)) :
1179                                 activecount_f + f;
1180                 else
1181                         approx_value_f = activefrac ?
1182                                 activecount_f + tegra_div64(f, activefrac) :
1183                                 activecount_f;
1184
1185                 if (activesym_f < approx_value_f) {
1186                         accumulated_error_f = num_linkclk_line *
1187                                 tegra_div64(approx_value_f - activesym_f, i);
1188                         neg = true;
1189                 } else {
1190                         accumulated_error_f = num_linkclk_line *
1191                                 tegra_div64(activesym_f - approx_value_f, i);
1192                         neg = false;
1193                 }
1194
1195                 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
1196                         (accumulated_error_f == 0)) {
1197                         lowest_neg_error_f = accumulated_error_f;
1198                         lowest_neg_tusize = i;
1199                         lowest_neg_activecount = activecount;
1200                         lowest_neg_activepolarity = activepolarity;
1201                         lowest_neg_activefrac = activefrac;
1202
1203                         if (accumulated_error_f == 0)
1204                                 break;
1205                 }
1206         }
1207
1208         if (lowest_neg_activefrac == 0) {
1209                 cfg->activepolarity = 0;
1210                 cfg->active_count   = lowest_neg_activepolarity ?
1211                         lowest_neg_activecount : lowest_neg_activecount - 1;
1212                 cfg->tu_size          = lowest_neg_tusize;
1213                 cfg->active_frac    = 1;
1214         } else {
1215                 cfg->activepolarity = lowest_neg_activepolarity;
1216                 cfg->active_count   = (u32)lowest_neg_activecount;
1217                 cfg->tu_size          = lowest_neg_tusize;
1218                 cfg->active_frac    = (u32)lowest_neg_activefrac;
1219         }
1220
1221         dev_dbg(&dp->dc->ndev->dev,
1222                 "dp: sor configuration: polarity: %d active count: %d "
1223                 "tu size: %d, active frac: %d\n",
1224                 cfg->activepolarity, cfg->active_count, cfg->tu_size,
1225                 cfg->active_frac);
1226
1227         watermark_f = tegra_div64(ratio_f * cfg->tu_size * (f - ratio_f), f);
1228         cfg->watermark = (u32)tegra_div64(watermark_f + lowest_neg_error_f,
1229                 f) + cfg->bits_per_pixel / 4 - 1;
1230         num_symbols_per_line = (mode->h_active * cfg->bits_per_pixel) /
1231                 (8 * cfg->lane_count);
1232         if (cfg->watermark > 30) {
1233                 dev_dbg(&dp->dc->ndev->dev,
1234                         "dp: sor setting: unable to get a good tusize, "
1235                         "force watermark to 30.\n");
1236                 cfg->watermark = 30;
1237                 return false;
1238         } else if (cfg->watermark > num_symbols_per_line) {
1239                 dev_dbg(&dp->dc->ndev->dev,
1240                         "dp: sor setting: force watermark to the number "
1241                         "of symbols in the line.\n");
1242                 cfg->watermark = num_symbols_per_line;
1243                 return false;
1244         }
1245
1246         /* Refer to dev_disp.ref for more information. */
1247         /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
1248         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
1249         /*                      - 3 * enhanced_framing - Y */
1250         /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
1251         cfg->hblank_sym = (int)tegra_div64((u64)(mode->h_back_porch +
1252                         mode->h_front_porch + mode->h_sync_width - 7)
1253                 * link_rate, rate)
1254                 - 3 * cfg->enhanced_framing - (12 / cfg->lane_count);
1255
1256         if (cfg->hblank_sym < 0)
1257                 cfg->hblank_sym = 0;
1258
1259
1260         /* Refer to dev_disp.ref for more information. */
1261         /* # symbols/vblank = ((SetRasterBlankStart.X - */
1262         /*                      SetRasterBlankEen.X - 25) * link_clk / pclk) */
1263         /*                      - Y - 1; */
1264         /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
1265         cfg->vblank_sym = (int)tegra_div64((u64)(mode->h_active - 25)
1266                 * link_rate, rate) - (36 / cfg->lane_count) - 4;
1267
1268         if (cfg->vblank_sym < 0)
1269                 cfg->vblank_sym = 0;
1270
1271         cfg->is_valid = true;
1272
1273         return true;
1274 }
1275
1276 static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
1277                                         struct tegra_dc_dp_link_config *cfg)
1278 {
1279
1280 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
1281         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
1282                 tegra_dc_init_fake_panel_link_cfg(cfg);
1283         else
1284 #endif
1285         {
1286                 u8 dpcd_data;
1287                 int ret;
1288
1289                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
1290                         &dpcd_data));
1291
1292                 cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
1293                 cfg->tps3_supported =
1294                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ?
1295                 true : false;
1296
1297                 cfg->support_enhanced_framing =
1298                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
1299                 true : false;
1300
1301                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
1302                         &dpcd_data));
1303                 cfg->downspread =
1304                 (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
1305                 true : false;
1306
1307                 cfg->support_fast_lt = (dpcd_data &
1308                 NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ? true : false;
1309
1310                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1311                         NV_DPCD_TRAINING_AUX_RD_INTERVAL, &dpcd_data));
1312                 cfg->aux_rd_interval = dpcd_data;
1313
1314                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
1315                         &cfg->max_link_bw));
1316
1317                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
1318                         &dpcd_data));
1319                 cfg->alt_scramber_reset_cap =
1320                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
1321                 true : false;
1322
1323                 cfg->only_enhanced_framing =
1324                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
1325                 true : false;
1326
1327                 cfg->edp_cap = (dpcd_data &
1328                 NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ? true : false;
1329         }
1330
1331         cfg->bits_per_pixel = dp->dc->out->depth ? : 24;
1332
1333         cfg->lane_count = cfg->max_lane_count;
1334
1335         cfg->link_bw = (dp->pdata && dp->pdata->link_bw) ?
1336                         dp->pdata->link_bw : cfg->max_link_bw;
1337
1338         cfg->enhanced_framing = cfg->support_enhanced_framing;
1339
1340         tegra_dc_dp_calc_config(dp, dp->mode, cfg);
1341
1342         dp->max_link_cfg = *cfg;
1343         return 0;
1344 }
1345
1346 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
1347 {
1348         int ret;
1349
1350         u8 dpcd_data = ena ?
1351                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
1352                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
1353
1354         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
1355                         dpcd_data));
1356
1357         /* Also reset the scrambler to 0xfffe */
1358         tegra_dc_sor_set_internal_panel(dp->sor, ena);
1359         return 0;
1360 }
1361
1362
1363 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
1364 {
1365         tegra_dc_sor_set_link_bandwidth(dp->sor, link_bw);
1366
1367         /* Sink side */
1368         return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
1369 }
1370
1371 static int tegra_dp_set_enhanced_framing(struct tegra_dc_dp_data *dp,
1372                                                 bool enable)
1373 {
1374         int ret;
1375
1376         if (enable) {
1377                 tegra_sor_write_field(dp->sor,
1378                         NV_SOR_DP_LINKCTL(dp->sor->portnum),
1379                         NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE,
1380                         NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE);
1381
1382                 CHECK_RET(tegra_dp_dpcd_write_field(dp, NV_DPCD_LANE_COUNT_SET,
1383                                 NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T,
1384                                 NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T));
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp, u8 lane_cnt)
1391 {
1392         int ret;
1393
1394         tegra_sor_power_lanes(dp->sor, lane_cnt, true);
1395
1396         CHECK_RET(tegra_dp_dpcd_write_field(dp, NV_DPCD_LANE_COUNT_SET,
1397                                 NV_DPCD_LANE_COUNT_SET_MASK,
1398                                 lane_cnt));
1399
1400         return 0;
1401 }
1402
1403 static void tegra_dp_link_cal(struct tegra_dc_dp_data *dp)
1404 {
1405         struct tegra_dc_sor_data *sor = dp->sor;
1406         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
1407         u32 load_adj;
1408
1409         switch (cfg->link_bw) {
1410         case SOR_LINK_SPEED_G1_62:
1411                 load_adj = 0x3;
1412                 break;
1413         case SOR_LINK_SPEED_G2_7:
1414                 load_adj = 0x4;
1415                 break;
1416         case SOR_LINK_SPEED_G5_4:
1417                 load_adj = 0x6;
1418                 break;
1419         default:
1420                 BUG();
1421         }
1422
1423         tegra_sor_write_field(sor, NV_SOR_PLL1,
1424                         NV_SOR_PLL1_LOADADJ_DEFAULT_MASK,
1425                         load_adj << NV_SOR_PLL1_LOADADJ_SHIFT);
1426 }
1427
1428 static void tegra_dp_irq_evt_worker(struct work_struct *work)
1429 {
1430 #define LANE0_1_CR_CE_SL_MASK (0x7 | (0x7 << 4))
1431 #define LANE0_CR_CE_SL_MASK (0x7)
1432 #define INTERLANE_ALIGN_MASK (0x1)
1433
1434         struct tegra_dc_dp_data *dp = container_of(to_delayed_work(work),
1435                                         struct tegra_dc_dp_data,
1436                                         irq_evt_dwork);
1437         u32 aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
1438         bool link_stable = !!true;
1439         u8 dpcd_200h_205h[6];
1440         u32 n_lanes = dp->lt_data.n_lanes;
1441
1442         tegra_dc_io_start(dp->dc);
1443
1444         if (aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) {
1445                 int cnt;
1446
1447                 /*
1448                  * HW failed to automatically read DPCD
1449                  * offsets 0x200-0x205. Initiate SW transaction.
1450                  */
1451                 for (cnt = 0; cnt < 6; cnt++) {
1452                         tegra_dc_dp_dpcd_read(dp, 0x200 + cnt,
1453                                                 &dpcd_200h_205h[cnt]);
1454                 }
1455         } else  {
1456                 u32 aux_sinkstat_lo = tegra_dpaux_readl(dp,
1457                                         DPAUX_DP_AUX_SINKSTATLO);
1458                 u32 aux_sinkstat_hi = tegra_dpaux_readl(dp,
1459                                         DPAUX_DP_AUX_SINKSTATHI);
1460
1461                 dpcd_200h_205h[0] = aux_sinkstat_lo & 0xff;
1462                 dpcd_200h_205h[1] = (aux_sinkstat_lo >> 8) & 0xff;
1463                 dpcd_200h_205h[2] = (aux_sinkstat_lo >> 16) & 0xff;
1464                 dpcd_200h_205h[3] = (aux_sinkstat_lo >> 24) & 0xff;
1465                 dpcd_200h_205h[4] = aux_sinkstat_hi & 0xff;
1466                 dpcd_200h_205h[5] = (aux_sinkstat_hi >> 8) & 0xff;
1467         }
1468
1469         switch (n_lanes) {
1470         case 4:
1471                 link_stable &= !!((dpcd_200h_205h[3] &
1472                                 LANE0_1_CR_CE_SL_MASK) ==
1473                                 LANE0_1_CR_CE_SL_MASK);
1474         case 2:
1475                 link_stable &= !!((dpcd_200h_205h[2] &
1476                                 LANE0_1_CR_CE_SL_MASK) ==
1477                                 LANE0_1_CR_CE_SL_MASK);
1478         case 1:
1479                 link_stable &= !!((dpcd_200h_205h[2] &
1480                                 LANE0_CR_CE_SL_MASK) ==
1481                                 LANE0_CR_CE_SL_MASK);
1482         default:
1483                 link_stable &= !!(dpcd_200h_205h[4] &
1484                                 INTERLANE_ALIGN_MASK);
1485         }
1486
1487         if (!link_stable)
1488                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
1489         else
1490                 dev_info(&dp->dc->ndev->dev,
1491                         "dp: link stable, ignore irq event\n");
1492
1493         tegra_dc_io_end(dp->dc);
1494
1495 #undef LANE0_1_CR_CE_SL_MASK
1496 #undef LANE0_CR_CE_SL_MASK
1497 #undef INTERLANE_ALIGN_MASK
1498 }
1499
1500 static irqreturn_t tegra_dp_irq(int irq, void *ptr)
1501 {
1502         struct tegra_dc_dp_data *dp = ptr;
1503         struct tegra_dc *dc = dp->dc;
1504         u32 status;
1505
1506         if (tegra_platform_is_fpga())
1507                 return IRQ_NONE;
1508
1509         if (dp->suspended) {
1510                 dev_info(&dc->ndev->dev,
1511                         "dp: irq received while suspended, ignoring\n");
1512                 return IRQ_HANDLED;
1513         }
1514
1515         tegra_dc_io_start(dc);
1516
1517         /* clear pending bits */
1518         status = tegra_dpaux_readl(dp, DPAUX_INTR_AUX);
1519         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, status);
1520
1521         tegra_dc_io_end(dc);
1522
1523         if (status & (DPAUX_INTR_AUX_PLUG_EVENT_PENDING |
1524                 DPAUX_INTR_AUX_UNPLUG_EVENT_PENDING)) {
1525                 if (status & DPAUX_INTR_AUX_PLUG_EVENT_PENDING) {
1526                         dev_info(&dp->dc->ndev->dev,
1527                                 "dp: plug event received\n");
1528                         complete_all(&dp->hpd_plug);
1529                 } else {
1530                         dev_info(&dp->dc->ndev->dev,
1531                                 "dp: unplug event received\n");
1532                         INIT_COMPLETION(dp->hpd_plug);
1533                 }
1534                 tegra_dp_pending_hpd(dp);
1535         } else if (status & DPAUX_INTR_AUX_IRQ_EVENT_PENDING) {
1536                 dev_info(&dp->dc->ndev->dev, "dp: irq event received%s\n",
1537                         dp->enabled ? "" : ", ignoring");
1538                 if (dp->enabled) {
1539                         cancel_delayed_work(&dp->irq_evt_dwork);
1540                         schedule_delayed_work(&dp->irq_evt_dwork,
1541                                                 msecs_to_jiffies(
1542                                                 HPD_IRQ_EVENT_TIMEOUT_MS));
1543                 }
1544         }
1545
1546         if (status & DPAUX_INTR_AUX_TX_DONE_PENDING)
1547                 complete_all(&dp->aux_tx);
1548
1549         return IRQ_HANDLED;
1550 }
1551
1552 static void _tegra_dpaux_init(struct tegra_dc_dp_data *dp)
1553 {
1554         if (dp->sor->safe_clk)
1555                 tegra_sor_safe_clk_enable(dp->sor);
1556         tegra_dpaux_clk_enable(dp);
1557
1558         tegra_dc_io_start(dp->dc);
1559
1560         tegra_dp_reset(dp);
1561
1562         tegra_dpaux_enable(dp);
1563
1564         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
1565                 tegra_dp_hpd_config(dp);
1566                 tegra_dp_default_int(dp, true);
1567         }
1568
1569         tegra_dc_io_end(dp->dc);
1570 }
1571
1572 static void tegra_dpaux_init(struct tegra_dc_dp_data *dp)
1573 {
1574         BUG_ON(!dp->dc || !dp);
1575
1576         tegra_set_dpaux_addr(dp->aux_base, tegra_dc_which_sor(dp->dc));
1577
1578         _tegra_dpaux_init(dp);
1579
1580         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
1581                 tegra_dp_enable_irq(dp->irq);
1582 }
1583
1584 static int tegra_dc_dp_hotplug_init(struct tegra_dc *dc)
1585 {
1586         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1587
1588         /* SOR partition must be awake for dpaux */
1589         tegra_dc_unpowergate_locked(dc);
1590
1591         /*
1592          * dp interrupts are received by dpaux.
1593          * Initialize dpaux to receive hotplug events.
1594          */
1595         tegra_dpaux_init(dp);
1596
1597         return 0;
1598 }
1599
1600 static int tegra_dc_dp_init(struct tegra_dc *dc)
1601 {
1602         struct tegra_dc_dp_data *dp;
1603         struct resource *res;
1604         struct resource *base_res;
1605         struct resource of_dp_res;
1606         void __iomem *base;
1607         struct clk *clk;
1608         struct clk *parent_clk;
1609         int err;
1610         u32 irq;
1611         struct device_node *np = dc->ndev->dev.of_node;
1612         int dp_num = tegra_dc_which_sor(dc);
1613         struct device_node *np_dp =
1614                 dp_num ? of_find_node_by_path(DPAUX1_NODE)
1615                 : of_find_node_by_path(DPAUX_NODE);
1616         struct device_node *np_panel = NULL;
1617
1618         dp = devm_kzalloc(&dc->ndev->dev, sizeof(*dp), GFP_KERNEL);
1619         if (!dp) {
1620                 of_node_put(np_dp);
1621                 return -ENOMEM;
1622         }
1623
1624         dp->edid_src = EDID_SRC_PANEL;
1625         if (np) {
1626                 if (np_dp && (of_device_is_available(np_dp) ||
1627                         (dc->out->type == TEGRA_DC_OUT_FAKE_DP))) {
1628                         irq = of_irq_to_resource(np_dp, 0, NULL);
1629                         if (!irq) {
1630                                 err = -ENOENT;
1631                                 goto err_free_dp;
1632                         }
1633                         of_address_to_resource(np_dp, 0, &of_dp_res);
1634                         res = &of_dp_res;
1635                         np_panel = tegra_get_panel_node_out_type_check(dc,
1636                                 TEGRA_DC_OUT_DP);
1637                         if (np_panel && of_device_is_available(np_panel)) {
1638                                 if (of_property_read_bool(np_panel,
1639                                         "nvidia,edid"))
1640                                         dp->edid_src = EDID_SRC_DT;
1641                         }
1642                 } else {
1643                         err = -EINVAL;
1644                         goto err_free_dp;
1645                 }
1646         } else {
1647                 irq = platform_get_irq_byname(dc->ndev, "irq_dp");
1648                 if (irq <= 0) {
1649                         dev_err(&dc->ndev->dev, "dp: no irq\n");
1650                         err = -ENOENT;
1651                         goto err_free_dp;
1652                 }
1653                 res = platform_get_resource_byname(dc->ndev,
1654                         IORESOURCE_MEM, "dpaux");
1655         }
1656         if (!res) {
1657                 dev_err(&dc->ndev->dev, "dp: no mem resources for dpaux\n");
1658                 err = -EFAULT;
1659                 goto err_free_dp;
1660         }
1661
1662         base_res = devm_request_mem_region(&dc->ndev->dev,
1663                 res->start, resource_size(res),
1664                 dc->ndev->name);
1665         if (!base_res) {
1666                 dev_err(&dc->ndev->dev, "dp: request_mem_region failed\n");
1667                 err = -EFAULT;
1668                 goto err_free_dp;
1669         }
1670
1671         base = devm_ioremap(&dc->ndev->dev, res->start, resource_size(res));
1672         if (!base) {
1673                 dev_err(&dc->ndev->dev, "dp: registers can't be mapped\n");
1674                 err = -EFAULT;
1675                 goto err_release_resource_reg;
1676         }
1677
1678
1679 #ifdef CONFIG_TEGRA_NVDISPLAY
1680         clk = clk_get(NULL, dp_num ? "dpaux1" : "dpaux");
1681 #else
1682         clk = clk_get_sys(dp_num ? "dpaux1" : "dpaux", NULL);
1683 #endif
1684         if (IS_ERR_OR_NULL(clk)) {
1685                 dev_err(&dc->ndev->dev, "dp: dc clock %s.edp unavailable\n",
1686                         dev_name(&dc->ndev->dev));
1687                 err = -EFAULT;
1688                 goto err_iounmap_reg;
1689         }
1690
1691 #ifdef CONFIG_TEGRA_NVDISPLAY
1692         parent_clk = clk_get(NULL, "pll_dp");
1693 #else
1694         parent_clk = tegra_get_clock_by_name("pll_dp");
1695 #endif
1696         if (IS_ERR_OR_NULL(parent_clk)) {
1697                 dev_err(&dc->ndev->dev, "dp: clock pll_dp unavailable\n");
1698                 err = -EFAULT;
1699                 goto err_iounmap_reg;
1700         }
1701
1702         if (!tegra_platform_is_fpga()) {
1703                 if (request_threaded_irq(irq, NULL, tegra_dp_irq,
1704                                         IRQF_ONESHOT, "tegra_dp", dp)) {
1705                         dev_err(&dc->ndev->dev,
1706                                 "dp: request_irq %u failed\n", irq);
1707                         err = -EBUSY;
1708                         goto err_get_clk;
1709                 }
1710         }
1711
1712         if (dc->out->type != TEGRA_DC_OUT_FAKE_DP)
1713                 tegra_dp_disable_irq(irq);
1714
1715         dp->dc = dc;
1716         dp->aux_base = base;
1717         dp->res = res;
1718         dp->aux_base_res = base_res;
1719         dp->dpaux_clk = clk;
1720         dp->parent_clk = parent_clk;
1721         dp->mode = &dc->mode;
1722         dp->sor = tegra_dc_sor_init(dc, &dp->link_cfg);
1723         dp->irq = irq;
1724         dp->pdata = dc->pdata->default_out->dp_out;
1725         dp->suspended = false;
1726
1727         if (IS_ERR_OR_NULL(dp->sor)) {
1728                 err = PTR_ERR(dp->sor);
1729                 dp->sor = NULL;
1730                 goto err_get_clk;
1731         }
1732
1733         init_completion(&dp->aux_tx);
1734         init_completion(&dp->hpd_plug);
1735
1736         mutex_init(&dp->dpaux_lock);
1737
1738         tegra_dc_set_outdata(dc, dp);
1739
1740         /*
1741          * We don't really need hpd driver for eDP.
1742          * Nevertheless, go ahead and init hpd driver.
1743          * eDP uses some of its fields to interact with panel.
1744          */
1745         tegra_hpd_init(&dp->hpd_data, dc, dp, &hpd_ops);
1746
1747         tegra_dp_lt_init(&dp->lt_data, dp);
1748
1749         INIT_DELAYED_WORK(&dp->irq_evt_dwork, tegra_dp_irq_evt_worker);
1750
1751         tegra_dc_dp_debug_create(dp);
1752         of_node_put(np_dp);
1753
1754         return 0;
1755
1756 err_get_clk:
1757         clk_put(clk);
1758 err_iounmap_reg:
1759         devm_iounmap(&dc->ndev->dev, base);
1760 err_release_resource_reg:
1761         devm_release_mem_region(&dc->ndev->dev,
1762                 res->start,
1763                 resource_size(res));
1764
1765         if (!np_dp || !of_device_is_available(np_dp))
1766                 release_resource(res);
1767 err_free_dp:
1768         devm_kfree(&dc->ndev->dev, dp);
1769         of_node_put(np_dp);
1770
1771         return err;
1772 }
1773
1774 static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp)
1775 {
1776 #define TEGRA_DP_HPD_UNPLUG_MIN_US      2000
1777 #define TEGRA_DP_HPD_PLUG_MIN_US        250
1778 #define TEGRA_DP_HPD_IRQ_MIN_US         250
1779
1780         u32 val;
1781
1782         val = TEGRA_DP_HPD_PLUG_MIN_US |
1783                 (TEGRA_DP_HPD_UNPLUG_MIN_US <<
1784                 DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT);
1785         tegra_dpaux_writel(dp, DPAUX_HPD_CONFIG, val);
1786
1787         tegra_dpaux_writel(dp, DPAUX_HPD_IRQ_CONFIG, TEGRA_DP_HPD_IRQ_MIN_US);
1788
1789 #undef TEGRA_DP_HPD_IRQ_MIN_US
1790 #undef TEGRA_DP_HPD_PLUG_MIN_US
1791 #undef TEGRA_DP_HPD_UNPLUG_MIN_US
1792 }
1793
1794 static void tegra_dp_dpcd_init(struct tegra_dc_dp_data *dp)
1795 {
1796         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
1797         u32 size_ieee_oui = 3, auxstat;
1798         u8 data_ieee_oui_be[3] = {(NV_IEEE_OUI >> 16) & 0xff,
1799                 (NV_IEEE_OUI >> 8) & 0xff,
1800                 NV_IEEE_OUI & 0xff};
1801
1802         /* Check DP version */
1803         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
1804                 dev_err(&dp->dc->ndev->dev,
1805                         "dp: failed to read the revision number from sink\n");
1806
1807         if (tegra_dp_init_max_link_cfg(dp, cfg))
1808                 dev_err(&dp->dc->ndev->dev,
1809                         "dp: failed to init link configuration\n");
1810
1811         tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
1812                 NV_DPCD_SOURCE_IEEE_OUI, data_ieee_oui_be, &size_ieee_oui,
1813                 &auxstat);
1814 }
1815
1816 void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes)
1817 {
1818         if (tp == TRAINING_PATTERN_DISABLE)
1819                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
1820                         (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F));
1821         else
1822                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
1823                         (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T));
1824
1825         tegra_sor_tpg(dp->sor, tp, n_lanes);
1826 }
1827
1828 static void tegra_dp_tu_config(struct tegra_dc_dp_data *dp,
1829                                 const struct tegra_dc_dp_link_config *cfg)
1830 {
1831         struct tegra_dc_sor_data *sor = dp->sor;
1832         u32 reg_val;
1833
1834         tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
1835                         NV_SOR_DP_LINKCTL_TUSIZE_MASK,
1836                         (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT));
1837
1838         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1839                                 NV_SOR_DP_CONFIG_WATERMARK_MASK,
1840                                 cfg->watermark);
1841
1842         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1843                                 NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK,
1844                                 (cfg->active_count <<
1845                                 NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT));
1846
1847         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1848                                 NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK,
1849                                 (cfg->active_frac <<
1850                                 NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT));
1851
1852         reg_val = cfg->activepolarity ?
1853                 NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE :
1854                 NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE;
1855         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1856                                 NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE,
1857                                 reg_val);
1858
1859         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1860                                 NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE,
1861                                 NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE);
1862
1863         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
1864                                 NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE,
1865                                 NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
1866 }
1867
1868 void tegra_dp_update_link_config(struct tegra_dc_dp_data *dp)
1869 {
1870         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
1871
1872         tegra_dp_set_link_bandwidth(dp, cfg->link_bw);
1873         tegra_dp_set_lane_count(dp, cfg->lane_count);
1874         tegra_dp_link_cal(dp);
1875         tegra_dp_tu_config(dp, cfg);
1876 }
1877
1878 static void tegra_dp_hpd_op_edid_ready(void *drv_data)
1879 {
1880         struct tegra_dc_dp_data *dp = drv_data;
1881         struct tegra_dc *dc = dp->dc;
1882
1883         /* in mm */
1884         dc->out->h_size = dc->out->h_size ? : dp->hpd_data.mon_spec.max_x * 10;
1885         dc->out->v_size = dc->out->v_size ? : dp->hpd_data.mon_spec.max_y * 10;
1886
1887         /*
1888          * EDID specifies either the acutal screen sizes or
1889          * the aspect ratios. The panel file can choose to
1890          * trust the value as the actual sizes by leaving
1891          * width/height to 0s
1892          */
1893         dc->out->width = dc->out->width ? : dc->out->h_size;
1894         dc->out->height = dc->out->height ? : dc->out->v_size;
1895 }
1896
1897 static void tegra_dp_hpd_op_edid_recheck(void *drv_data)
1898 {
1899         struct tegra_dc_dp_data *dp = drv_data;
1900
1901         /*
1902          * Hpd dropped but soon came back.
1903          * Panel might have gone out of sync.
1904          * Initiate LT if hpd driver found no
1905          * change in edid and DP controller is enabled.
1906          * Otherwise, next unblank would anyways
1907          * initiate LT.
1908          */
1909         if (tegra_hpd_get_state(&dp->hpd_data) ==
1910                 STATE_DONE_ENABLED && dp->enabled)
1911                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
1912 }
1913
1914 static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp)
1915 {
1916         if (tegra_platform_is_linsim())
1917                 return;
1918         tegra_periph_reset_assert(dp->dpaux_clk);
1919         mdelay(2);
1920         tegra_periph_reset_deassert(dp->dpaux_clk);
1921         mdelay(1);
1922 }
1923
1924 static inline void tegra_dp_default_int(struct tegra_dc_dp_data *dp,
1925                                         bool enable)
1926 {
1927         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
1928                 return;
1929
1930         if (enable)
1931                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_IRQ_EVENT |
1932                                 DPAUX_INTR_EN_AUX_PLUG_EVENT |
1933                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT);
1934         else
1935                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_IRQ_EVENT);
1936 }
1937
1938 static int tegra_edp_edid_read(struct tegra_dc_dp_data *dp)
1939 {
1940         struct tegra_hpd_data *data = &dp->hpd_data;
1941
1942         BUG_ON(!data);
1943
1944         memset(&data->mon_spec, 0, sizeof(data->mon_spec));
1945
1946         return tegra_edid_get_monspecs(data->edid, &data->mon_spec);
1947 }
1948
1949 static void tegra_edp_mode_set(struct tegra_dc_dp_data *dp)
1950 {
1951         struct fb_videomode *best_edp_fbmode = dp->hpd_data.mon_spec.modedb;
1952
1953         if (best_edp_fbmode)
1954                 tegra_dc_set_fb_mode(dp->dc, best_edp_fbmode, false);
1955         else
1956                 tegra_dc_set_default_videomode(dp->dc);
1957 }
1958
1959 static int tegra_edp_wait_plug_hpd(struct tegra_dc_dp_data *dp)
1960 {
1961 #define TEGRA_DP_HPD_PLUG_TIMEOUT_MS    1000
1962
1963         u32 val;
1964         int err = 0;
1965
1966         might_sleep();
1967
1968         if (!tegra_platform_is_silicon()) {
1969                 msleep(TEGRA_DP_HPD_PLUG_TIMEOUT_MS);
1970                 return 0;
1971         }
1972
1973         val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
1974         if (likely(val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED))
1975                 err = 0;
1976         else if (!wait_for_completion_timeout(&dp->hpd_plug,
1977                 msecs_to_jiffies(TEGRA_DP_HPD_PLUG_TIMEOUT_MS)))
1978                 err = -ENODEV;
1979
1980         return err;
1981
1982 #undef TEGRA_DP_HPD_PLUG_TIMEOUT_MS
1983 }
1984
1985 static void tegra_dc_dp_enable(struct tegra_dc *dc)
1986 {
1987         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1988         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
1989         struct tegra_dc_sor_data *sor = dp->sor;
1990         int ret;
1991
1992         if (dp->enabled)
1993                 return;
1994
1995         tegra_dc_io_start(dc);
1996
1997         /* For eDP, driver gets to decide the best mode. */
1998         if (!tegra_dc_is_ext_dp_panel(dc) &&
1999                 dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
2000                 int err;
2001
2002                 /*
2003                  * Hotplug for internal panels is not supported.
2004                  * Wait till the panel asserts hpd
2005                  */
2006                 err = tegra_edp_wait_plug_hpd(dp);
2007                 if (err < 0) {
2008                         tegra_dc_io_end(dc);
2009                         dc->connected = false;
2010                         dev_err(&dc->ndev->dev,
2011                                 "edp: plug hpd wait timeout\n");
2012                         return;
2013                 }
2014
2015                 err = tegra_edp_edid_read(dp);
2016                 if (err < 0)
2017                         dev_warn(&dc->ndev->dev, "edp: edid read failed\n");
2018                 else
2019                         tegra_dp_hpd_op_edid_ready(dp);
2020                 tegra_edp_mode_set(dp);
2021                 tegra_dc_setup_clk(dc, dc->clk);
2022         }
2023
2024         ret = tegra_dp_panel_power_state(dp, NV_DPCD_SET_POWER_VAL_D0_NORMAL);
2025         if (ret < 0) {
2026                 dev_err(&dp->dc->ndev->dev,
2027                         "dp: failed to power on panel (0x%x)\n", ret);
2028                 tegra_dc_io_end(dc);
2029                 return;
2030         }
2031
2032         tegra_dp_dpcd_init(dp);
2033
2034         tegra_dc_sor_enable_dp(dp->sor);
2035
2036         tegra_dp_set_enhanced_framing(dp, cfg->enhanced_framing);
2037
2038         if (cfg->alt_scramber_reset_cap)
2039                 tegra_dc_dp_set_assr(dp, true);
2040         else
2041                 tegra_dc_sor_set_internal_panel(dp->sor, false);
2042
2043         tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET,
2044                         NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B);
2045
2046         tegra_sor_writel(sor, NV_SOR_LVDS, 0);
2047
2048         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
2049                                 NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE,
2050                                 NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE);
2051
2052         tegra_dp_set_link_bandwidth(dp, cfg->link_bw);
2053         tegra_dp_set_lane_count(dp, cfg->lane_count);
2054         tegra_dp_link_cal(dp);
2055         tegra_dp_tu_config(dp, cfg);
2056
2057         tegra_dp_tpg(dp, TRAINING_PATTERN_DISABLE, cfg->lane_count);
2058
2059         tegra_sor_port_enable(sor, true);
2060         tegra_sor_config_xbar(dp->sor);
2061
2062         tegra_dp_clk_enable(dp);
2063         tegra_sor_config_dp_clk(dp->sor);
2064         tegra_dc_setup_clk(dc, dc->clk);
2065
2066         dp->enabled = true;
2067
2068         if (likely(dc->out->type != TEGRA_DC_OUT_FAKE_DP)) {
2069                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
2070                 ret = tegra_dp_lt_wait_for_completion(&dp->lt_data,
2071                                                         LT_TIMEOUT_MS);
2072                 if (!ret)
2073                         dev_err(&dp->dc->ndev->dev,
2074                                 "dp: link training failed\n");
2075         } else {
2076                 /*
2077                  * Fake panel. Just enable host.
2078                  * No not engage with panel.
2079                  */
2080                 tegra_sor_tpg(dp->sor, TRAINING_PATTERN_DISABLE,
2081                                 dp->link_cfg.lane_count);
2082                 tegra_dc_sor_attach(dp->sor);
2083         }
2084         #if 0
2085         if (tegra_dc_is_ext_dp_panel(dc) &&
2086                 dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2087                 tegra_dphdcp_set_plug(dp->dphdcp, true);
2088         #endif
2089         dc->connected = true;
2090         tegra_dc_io_end(dc);
2091
2092         return;
2093 }
2094
2095 void tegra_dc_dp_enable_link(struct tegra_dc_dp_data *dp)
2096 {
2097         if (!dp->enabled)
2098                 tegra_dc_dp_enable(dp->dc);
2099         else
2100                 tegra_dc_sor_attach(dp->sor);
2101 }
2102
2103 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
2104 {
2105         struct device_node *np_dp =
2106                 tegra_dc_which_sor(dc) ? of_find_node_by_path(DPAUX1_NODE) :
2107                 of_find_node_by_path(DPAUX_NODE);
2108         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2109
2110         if (dp->sor)
2111                 tegra_dc_sor_destroy(dp->sor);
2112
2113         tegra_hpd_shutdown(&dp->hpd_data);
2114
2115 #ifndef CONFIG_TEGRA_NVDISPLAY
2116         clk_put(dp->dpaux_clk);
2117         clk_put(dp->parent_clk);
2118 #endif
2119
2120         devm_iounmap(&dc->ndev->dev, dp->aux_base);
2121         devm_release_mem_region(&dc->ndev->dev,
2122                 dp->res->start,
2123                 resource_size(dp->res));
2124         if (!np_dp || !of_device_is_available(np_dp))
2125                 release_resource(dp->res);
2126         devm_kfree(&dc->ndev->dev, dp);
2127         of_node_put(np_dp);
2128 }
2129
2130 static void tegra_dc_dp_disable(struct tegra_dc *dc)
2131 {
2132         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2133         int ret;
2134
2135         if (!dp->enabled)
2136                 return;
2137
2138         dp->enabled = false;
2139
2140         tegra_dc_io_start(dc);
2141         #if 0
2142         if (tegra_dc_is_ext_dp_panel(dc) &&
2143                 dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2144                 tegra_dphdcp_set_plug(dp->dphdcp, false);
2145         #endif
2146         cancel_delayed_work_sync(&dp->irq_evt_dwork);
2147
2148         if (dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
2149                 tegra_dp_lt_force_disable(&dp->lt_data);
2150                 ret = tegra_dp_lt_wait_for_completion(&dp->lt_data,
2151                                                         LT_TIMEOUT_MS);
2152                 WARN_ON(!ret);
2153         }
2154
2155         tegra_dc_sor_detach(dp->sor);
2156         tegra_dc_sor_disable(dp->sor, false);
2157
2158         tegra_dp_clk_disable(dp);
2159
2160         tegra_dc_io_end(dc);
2161 }
2162
2163 void tegra_dc_dp_pre_disable_link(struct tegra_dc_dp_data *dp)
2164 {
2165         tegra_dc_sor_pre_detach(dp->sor);
2166 }
2167
2168 void tegra_dc_dp_disable_link(struct tegra_dc_dp_data *dp, bool powerdown)
2169 {
2170         tegra_dc_sor_detach(dp->sor);
2171
2172         if (powerdown)
2173                 tegra_dc_dp_disable(dp->dc);
2174 }
2175
2176 static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk)
2177 {
2178         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2179         struct clk *dc_parent_clk;
2180
2181         if (!tegra_platform_is_silicon())
2182                 return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2183
2184         if (clk == dc->clk) {
2185                 dc_parent_clk = clk_get_sys(NULL,
2186                                 dc->out->parent_clk ? : "pll_d_out0");
2187                 clk_set_parent(dc->clk, dc_parent_clk);
2188         }
2189
2190         tegra_sor_setup_clk(dp->sor, clk, false);
2191
2192         /* fixed pll_dp@270MHz */
2193         clk_set_rate(dp->parent_clk, 270000000);
2194
2195         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2196 }
2197
2198 static bool tegra_dc_dp_hpd_state(struct tegra_dc *dc)
2199 {
2200         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2201         u32 val;
2202
2203         if (WARN_ON(!dc || !dc->out))
2204                 return false;
2205
2206         if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
2207                 tegra_platform_is_linsim())
2208                 return true;
2209
2210         tegra_dpaux_clk_enable(dp);
2211         tegra_dc_io_start(dc);
2212         val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
2213         tegra_dc_io_end(dc);
2214
2215         return !!(val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED);
2216 }
2217
2218 /* used by tegra_dc_probe() to detect connection(HPD) status at boot */
2219 static bool tegra_dc_dp_detect(struct tegra_dc *dc)
2220 {
2221         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2222
2223         if (tegra_platform_is_linsim())
2224                 return true;
2225
2226         tegra_dp_pending_hpd(dp);
2227
2228         return tegra_dc_hpd(dc);
2229 }
2230
2231 static void tegra_dc_dp_suspend(struct tegra_dc *dc)
2232 {
2233         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2234
2235         if (dp->suspended)
2236                 return;
2237
2238         dp->suspended = true;
2239
2240         /* do not process hpd in suspend. Disable dpaux clocks. */
2241         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2242                 tegra_dp_disable_irq(dp->irq);
2243         if (dp->sor->safe_clk)
2244                 tegra_sor_safe_clk_disable(dp->sor);
2245         tegra_dpaux_clk_disable(dp);
2246
2247         tegra_dc_powergate_locked(dc);
2248 }
2249
2250 static void tegra_dc_dp_resume(struct tegra_dc *dc)
2251 {
2252         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2253
2254         if (!dp->suspended)
2255                 return;
2256
2257         tegra_dc_unpowergate_locked(dc);
2258
2259         /* Get ready to receive any hpd event */
2260         _tegra_dpaux_init(dp);
2261         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2262                 tegra_dp_enable_irq(dp->irq);
2263
2264         tegra_dp_pending_hpd(dp);
2265
2266         dp->suspended = false;
2267 }
2268
2269 static void tegra_dc_dp_modeset_notifier(struct tegra_dc *dc)
2270 {
2271         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2272
2273         tegra_dc_io_start(dc);
2274         tegra_dpaux_clk_enable(dp);
2275
2276         tegra_dc_sor_modeset_notifier(dp->sor, false);
2277         /* Pixel clock may be changed in new mode,
2278          * recalculate link config */
2279         if (!tegra_platform_is_linsim())
2280                 tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg);
2281
2282
2283         tegra_dpaux_clk_disable(dp);
2284         tegra_dc_io_end(dc);
2285 }
2286
2287 static bool tegra_dp_check_dc_constraint(const struct fb_videomode *mode)
2288 {
2289         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
2290                 (mode->lower_margin + mode->vsync_len +
2291                 mode->upper_margin > 1) &&
2292                 (mode->xres >= 16) && (mode->yres >= 16);
2293 }
2294
2295 static bool tegra_dp_mode_filter(const struct tegra_dc *dc,
2296                                 struct fb_videomode *mode)
2297 {
2298         if (!mode->pixclock)
2299                 return false;
2300
2301         if (mode->xres > 4096)
2302                 return false;
2303
2304         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
2305                 mode->pixclock > tegra_dc_get_out_max_pixclock(dc))
2306                 return false;
2307
2308         /*
2309          * Work around for modes that fail the constraint:
2310          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
2311          */
2312         if (mode->lower_margin == 1) {
2313                 mode->lower_margin++;
2314                 mode->upper_margin--;
2315         }
2316
2317         if (!tegra_dp_check_dc_constraint(mode))
2318                 return false;
2319
2320         return true;
2321 }
2322
2323 static bool (*tegra_dp_op_get_mode_filter(void *drv_data))
2324         (const struct tegra_dc *dc, struct fb_videomode *mode) {
2325         return tegra_dp_mode_filter;
2326 }
2327
2328 static bool tegra_dp_hpd_op_get_hpd_state(void *drv_data)
2329 {
2330         struct tegra_dc_dp_data *dp = drv_data;
2331
2332         return tegra_dc_hpd(dp->dc);
2333 }
2334
2335 static void tegra_dp_hpd_op_init(void *drv_data)
2336 {
2337         struct tegra_dc_dp_data *dp = drv_data;
2338
2339 #ifdef CONFIG_SWITCH
2340         if (tegra_dc_is_ext_dp_panel(dp->dc)) {
2341                 dp->hpd_data.hpd_switch_name = "dp";
2342                 dp->hpd_data.audio_switch_name = "dp_audio";
2343         }
2344 #endif
2345 }
2346
2347 static struct tegra_hpd_ops hpd_ops = {
2348         .edid_read = tegra_dp_hpd_op_edid_read,
2349         .edid_ready = tegra_dp_hpd_op_edid_ready,
2350         .edid_recheck = tegra_dp_hpd_op_edid_recheck,
2351         .get_mode_filter = tegra_dp_op_get_mode_filter,
2352         .get_hpd_state = tegra_dp_hpd_op_get_hpd_state,
2353         .init = tegra_dp_hpd_op_init,
2354 };
2355
2356 struct tegra_dc_out_ops tegra_dc_dp_ops = {
2357         .init      = tegra_dc_dp_init,
2358         .destroy   = tegra_dc_dp_destroy,
2359         .enable    = tegra_dc_dp_enable,
2360         .disable   = tegra_dc_dp_disable,
2361         .detect    = tegra_dc_dp_detect,
2362         .setup_clk = tegra_dc_dp_setup_clk,
2363         .modeset_notifier = tegra_dc_dp_modeset_notifier,
2364         .hpd_state = tegra_dc_dp_hpd_state,
2365         .suspend = tegra_dc_dp_suspend,
2366         .resume = tegra_dc_dp_resume,
2367         .hotplug_init = tegra_dc_dp_hotplug_init,
2368 };