2 * drivers/video/tegra/dc/dc_priv.h
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
21 #define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
23 #include <linux/mutex.h>
24 #include <linux/wait.h>
26 #include <linux/clk.h>
27 #include <linux/completion.h>
28 #include <linux/switch.h>
29 #include <linux/nvhost.h>
30 #include <linux/types.h>
31 #include <linux/clk/tegra.h>
32 #include <linux/tegra-soc.h>
36 #include <mach/tegra_dc_ext.h>
37 #include <linux/platform/tegra/isomgr.h>
38 #include <linux/sysedp.h>
42 #define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
44 /* 28 bit offset for window clip number */
45 #define CURSOR_CLIP_SHIFT_BITS(win) (win << 28)
46 #define CURSOR_CLIP_GET_WINDOW(reg) ((reg >> 28) & 3)
48 #define BLANK_ALL (~0)
50 static inline u32 ALL_UF_INT(void)
52 if (tegra_platform_is_fpga())
54 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || \
55 defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
56 defined(CONFIG_ARCH_TEGRA_11x_SOC)
57 return WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
59 return WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | HC_UF_INT |
60 WIN_D_UF_INT | WIN_T_UF_INT;
64 #if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
65 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
67 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
72 struct tegra_dc_blend {
73 unsigned z[DC_N_WINDOWS];
74 unsigned flags[DC_N_WINDOWS];
75 u8 alpha[DC_N_WINDOWS];
78 struct tegra_dc_out_ops {
79 /* initialize output. dc clocks are not on at this point */
80 int (*init)(struct tegra_dc *dc);
81 /* destroy output. dc clocks are not on at this point */
82 void (*destroy)(struct tegra_dc *dc);
83 /* shutdown output. dc clocks are on at this point */
84 void (*shutdown)(struct tegra_dc *dc);
85 /* detect connected display. can sleep.*/
86 bool (*detect)(struct tegra_dc *dc);
87 /* enable output. dc clocks are on at this point */
88 void (*enable)(struct tegra_dc *dc);
89 /* enable dc client. Panel is enable at this point */
90 void (*postpoweron)(struct tegra_dc *dc);
91 /* disable output. dc clocks are on at this point */
92 void (*disable)(struct tegra_dc *dc);
93 /* dc client is disabled. dc clocks are on at this point */
94 void (*postpoweroff) (struct tegra_dc *dc);
95 /* hold output. keeps dc clocks on. */
96 void (*hold)(struct tegra_dc *dc);
97 /* release output. dc clocks may turn off after this. */
98 void (*release)(struct tegra_dc *dc);
99 /* idle routine of output. dc clocks may turn off after this. */
100 void (*idle)(struct tegra_dc *dc);
101 /* suspend output. dc clocks are on at this point */
102 void (*suspend)(struct tegra_dc *dc);
103 /* resume output. dc clocks are on at this point */
104 void (*resume)(struct tegra_dc *dc);
105 /* mode filter. to provide a list of supported modes*/
106 bool (*mode_filter)(const struct tegra_dc *dc,
107 struct fb_videomode *mode);
108 /* setup pixel clock and parent clock programming */
109 long (*setup_clk)(struct tegra_dc *dc, struct clk *clk);
111 * return true if display client is suspended during OSidle.
112 * If true, dc will not wait on any display client event
115 bool (*osidle)(struct tegra_dc *dc);
116 /* callback before new mode is programmed.
117 * dc clocks are on at this point */
118 void (*modeset_notifier)(struct tegra_dc *dc);
119 /* Set up interface and sink for partial frame update.
121 int (*partial_update) (struct tegra_dc *dc, unsigned int *xoff,
122 unsigned int *yoff, unsigned int *width, unsigned int *height);
123 /* refcounted enable of pads and clocks before performing DDC/I2C. */
124 int (*ddc_enable)(struct tegra_dc *dc);
125 /* refcounted disable of pads and clocks after performing DDC/I2C. */
126 int (*ddc_disable)(struct tegra_dc *dc);
127 /* Enable/disable VRR */
128 void (*vrr_enable)(struct tegra_dc *dc, bool enable);
129 /* return if hpd asserted or deasserted */
130 bool (*hpd_state) (struct tegra_dc *dc);
131 /* Configure controller to receive hotplug events */
132 int (*hotplug_init)(struct tegra_dc *dc);
135 struct tegra_dc_shift_clk_div {
136 unsigned long mul; /* numerator */
137 unsigned long div; /* denominator */
140 struct tegra_dc_nvsr_data;
142 enum tegra_dc_cursor_size {
143 TEGRA_DC_CURSOR_SIZE_32X32 = 0,
144 TEGRA_DC_CURSOR_SIZE_64X64 = 1,
145 TEGRA_DC_CURSOR_SIZE_128X128 = 2,
146 TEGRA_DC_CURSOR_SIZE_256X256 = 3,
149 enum tegra_dc_cursor_format {
150 TEGRA_DC_CURSOR_FORMAT_2BIT_LEGACY = 0,
151 TEGRA_DC_CURSOR_FORMAT_RGBA_NON_PREMULT_ALPHA = 1,
152 TEGRA_DC_CURSOR_FORMAT_RGBA_PREMULT_ALPHA = 3,
153 TEGRA_DC_CURSOR_FORMAT_RGBA_XOR = 4,
157 struct platform_device *ndev;
158 struct tegra_dc_platform_data *pdata;
160 struct resource *base_res;
165 #ifdef CONFIG_TEGRA_ISOMGR
166 tegra_isomgr_handle isomgr_handle;
170 struct clk *emc_la_clk;
171 long bw_kbps; /* bandwidth in KBps */
173 struct tegra_dc_shift_clk_div shift_clk_div;
183 /* Some of the setup code could reset display even if
184 * DC is already by bootloader. This one-time mark is
185 * used to suppress such code blocks during system boot,
186 * a.k.a the call stack above tegra_dc_probe().
190 struct tegra_dc_out *out;
191 struct tegra_dc_out_ops *out_ops;
194 struct tegra_dc_mode mode;
197 #ifndef CONFIG_TEGRA_NVDISPLAY
198 struct tegra_dc_win windows[DC_N_WINDOWS];
200 struct tegra_dc_win shadow_windows[DC_N_WINDOWS];
202 struct tegra_dc_blend blend;
204 #ifdef CONFIG_TEGRA_DC_CMU
205 struct tegra_dc_cmu cmu;
206 struct tegra_dc_cmu cmu_shadow;
208 /* Is CMU set by bootloader */
210 bool cmu_shadow_dirty;
211 bool cmu_shadow_force_update;
214 wait_queue_head_t wq;
215 wait_queue_head_t timestamp_wq;
217 struct mutex lp_lock;
219 struct mutex one_shot_lock;
221 struct resource *fb_mem;
222 struct tegra_fb_info *fb;
223 #ifdef CONFIG_ADF_TEGRA
224 struct tegra_adf_info *adf;
229 unsigned long int valid_windows;
231 unsigned long underflow_mask;
232 struct work_struct reset_work;
235 struct switch_dev modeset_switch;
238 struct completion frame_end_complete;
239 struct completion crc_complete;
242 struct work_struct vblank_work;
243 long vblank_ref_count;
244 struct work_struct frame_end_work;
245 struct work_struct vpulse2_work;
246 long vpulse2_ref_count;
258 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
259 struct tegra_dc_ext *ext;
262 struct tegra_dc_feature *feature;
265 #ifdef CONFIG_DEBUG_FS
266 struct dentry *debugdir;
268 struct tegra_dc_lut fb_lut;
269 struct delayed_work underflow_work;
270 u32 one_shot_delay_ms;
271 struct delayed_work one_shot_work;
272 s64 frame_end_timestamp;
273 atomic_t frame_end_ref;
281 struct tegra_dc_win tmp_wins[DC_N_WINDOWS];
283 struct tegra_edid *edid;
285 struct tegra_dc_nvsr_data *nvsr;
287 bool disp_active_dirty;
289 struct tegra_dc_cursor {
292 dma_addr_t phys_addr;
298 enum tegra_dc_cursor_size size;
299 enum tegra_dc_cursor_format format;
303 bool switchdev_registered;
305 struct notifier_block slgc_notifier;
306 struct sysedp_consumer *sysedpc;