drivers/platform/tegra/common.c

   1 /*
   2  * drivers/platform/tegra/common.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2010-2015 NVIDIA Corporation. All rights reserved.
   6  *
   7  * Author:
   8  *      Colin Cross <ccross@android.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/platform_device.h>
  22 #include <linux/console.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/clk/tegra.h>
  28 #include <linux/highmem.h>
  29 #include <linux/memblock.h>
  30 #include <linux/bitops.h>
  31 #include <linux/sched.h>
  32 #include <linux/of.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_fdt.h>
  35 #include <linux/pstore_ram.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/sys_soc.h>
  38 #include <linux/tegra-pmc.h>
  39 #if defined(CONFIG_SMSC911X)
  40 #include <linux/smsc911x.h>
  41 #endif
  42 #include <linux/pm.h>
  43 #include <linux/tegra-powergate.h>
  44 #include <linux/reboot.h>
  45 #include <linux/export.h>
  46 #include <linux/bootmem.h>
  47 #include <linux/tegra-soc.h>
  48 #include <linux/dma-contiguous.h>
  49 #include <linux/tegra-fuse.h>
  50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
  51 #include <linux/ote_protocol.h>
  52 #endif
  53 #include <linux/gk20a.h>
  54 #include <linux/tegra_smmu.h>
  55 #include <linux/tegra_pm_domains.h>
  56
  57 #ifdef CONFIG_ARM64
  58 #include <linux/irqchip/arm-gic.h>
  59 #include <asm/system_info.h>
  60 #else
  61 #include <asm/system.h>
  62 #include <asm/hardware/cache-l2x0.h>
  63 #endif
  64 #include <asm/dma-mapping.h>
  65 #include <asm/dma-contiguous.h>
  66
  67 #include <mach/nct.h>
  68 #include <mach/dc.h>
  69
  70 #include "apbio.h"
  71 #include "board.h"
  72 #include <linux/platform/tegra/clock.h>
  73 #include <linux/platform/tegra/common.h>
  74 #include <linux/platform/tegra/dvfs.h>
  75 #include "iomap.h"
  76 #include "pm.h"
  77 #include "sleep.h"
  78 #include <linux/platform/tegra/reset.h>
  79 #include "devices.h"
  80
  81 #define MC_SECURITY_CFG2        0x7c
  82
  83 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
  84 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
  85 #define   PRIORITY_SELECT_USB   BIT(6)
  86 #define   PRIORITY_SELECT_USB2  BIT(18)
  87 #define   PRIORITY_SELECT_USB3  BIT(17)
  88 #define   PRIORITY_SELECT_SE BIT(14)
  89
  90 #define AHB_GIZMO_AHB_MEM               0xc
  91 #define   ENB_FAST_REARBITRATE  BIT(2)
  92 #define   DONT_SPLIT_AHB_WR     BIT(7)
  93 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
  94 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
  95
  96 #define   RECOVERY_MODE BIT(31)
  97 #define   BOOTLOADER_MODE       BIT(30)
  98 #define   FORCED_RECOVERY_MODE  BIT(1)
  99
 100 #define AHB_GIZMO_USB           0x1c
 101 #define AHB_GIZMO_USB2          0x78
 102 #define AHB_GIZMO_USB3          0x7c
 103 #define AHB_GIZMO_SE            0x4c
 104 #define   IMMEDIATE     BIT(18)
 105
 106 #define AHB_MEM_PREFETCH_CFG5   0xc8
 107 #define AHB_MEM_PREFETCH_CFG3   0xe0
 108 #define AHB_MEM_PREFETCH_CFG4   0xe4
 109 #define AHB_MEM_PREFETCH_CFG1   0xec
 110 #define AHB_MEM_PREFETCH_CFG2   0xf0
 111 #define AHB_MEM_PREFETCH_CFG6   0xcc
 112 #define   PREFETCH_ENB  BIT(31)
 113 #define   MST_ID(x)     (((x) & 0x1f) << 26)
 114 #define   AHBDMA_MST_ID MST_ID(5)
 115 #define   USB_MST_ID    MST_ID(6)
 116 #define SDMMC4_MST_ID   MST_ID(12)
 117 #define   USB2_MST_ID   MST_ID(18)
 118 #define   USB3_MST_ID   MST_ID(17)
 119 #define   SE_MST_ID     MST_ID(14)
 120 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
 121 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
 122
 123 #ifdef CONFIG_PSTORE_RAM
 124 #define RAMOOPS_MEM_SIZE SZ_2M
 125 #define RECORD_MEM_SIZE SZ_64K
 126 #define CONSOLE_MEM_SIZE SZ_512K
 127 #define FTRACE_MEM_SIZE SZ_512K
 128 #define RTRACE_MEM_SIZE SZ_512K
 129 #endif
 130
 131 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 132 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
 133 static struct of_device_id tegra_sata_pd[] = {
 134         { .compatible = "nvidia, tegra210-sata-pd", },
 135         { .compatible = "nvidia, tegra132-sata-pd", },
 136         { .compatible = "nvidia, tegra124-sata-pd", },
 137         {},
 138 };
 139 #endif
 140
 141 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
 142 static struct of_device_id tegra_pcie_pd[] = {
 143         { .compatible = "nvidia, tegra210-pcie-pd", },
 144         { .compatible = "nvidia, tegra132-pcie-pd", },
 145         { .compatible = "nvidia, tegra124-pcie-pd", },
 146         {},
 147 };
 148 #endif
 149
 150 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 151 static struct of_device_id tegra_xusba_pd[] = {
 152         { .compatible = "nvidia, tegra210-xusba-pd", },
 153         { .compatible = "nvidia, tegra132-xusba-pd", },
 154         { .compatible = "nvidia, tegra124-xusba-pd", },
 155         {},
 156 };
 157
 158 static struct of_device_id tegra_xusbb_pd[] = {
 159         { .compatible = "nvidia, tegra210-xusbb-pd", },
 160         { .compatible = "nvidia, tegra132-xusbb-pd", },
 161         { .compatible = "nvidia, tegra124-xusbb-pd", },
 162         {},
 163 };
 164
 165 static struct of_device_id tegra_xusbc_pd[] = {
 166         { .compatible = "nvidia, tegra210-xusbc-pd", },
 167         { .compatible = "nvidia, tegra132-xusbc-pd", },
 168         { .compatible = "nvidia, tegra124-xusbc-pd", },
 169         {},
 170 };
 171 #endif
 172 #endif
 173
 174 phys_addr_t tegra_bootloader_fb_start;
 175 phys_addr_t tegra_bootloader_fb_size;
 176 phys_addr_t tegra_bootloader_fb2_start;
 177 phys_addr_t tegra_bootloader_fb2_size;
 178 phys_addr_t tegra_fb_start;
 179 phys_addr_t tegra_fb_size;
 180 phys_addr_t tegra_fb2_start;
 181 phys_addr_t tegra_fb2_size;
 182 phys_addr_t tegra_carveout_start;
 183 phys_addr_t tegra_carveout_size;
 184 phys_addr_t tegra_vpr_start;
 185 phys_addr_t tegra_vpr_size;
 186 phys_addr_t tegra_tsec_start;
 187 phys_addr_t tegra_tsec_size;
 188 phys_addr_t tegra_lp0_vec_start;
 189 phys_addr_t tegra_lp0_vec_size;
 190 bool tegra_vpr_resize;
 191
 192 phys_addr_t tegra_bl_debug_data_start = 0;
 193 EXPORT_SYMBOL(tegra_bl_debug_data_start);
 194
 195 phys_addr_t tegra_bl_debug_data_size = 0;
 196 EXPORT_SYMBOL(tegra_bl_debug_data_size);
 197
 198 phys_addr_t tegra_bl_prof_start;
 199 EXPORT_SYMBOL(tegra_bl_prof_start);
 200
 201 phys_addr_t tegra_bl_prof_size;
 202 EXPORT_SYMBOL(tegra_bl_prof_size);
 203
 204 #ifdef CONFIG_TEGRA_NVDUMPER
 205 unsigned long nvdumper_reserved;
 206 #endif
 207 bool tegra_lp0_vec_relocate;
 208 unsigned long tegra_grhost_aperture = ~0ul;
 209 static struct board_info main_board_info;
 210 static struct board_info pmu_board_info;
 211 static struct board_info display_board_info;
 212 static int panel_id;
 213 static int battery_id;
 214 static struct board_info camera_board_info;
 215 static int touch_vendor_id;
 216 static int touch_panel_id;
 217 static struct board_info io_board_info;
 218 static struct board_info button_board_info;
 219 static struct board_info joystick_board_info;
 220 static struct board_info rightspeaker_board_info;
 221 static struct board_info leftspeaker_board_info;
 222 #ifdef CONFIG_TEGRA_USE_NCT
 223 unsigned long tegra_nck_start;
 224 unsigned long tegra_nck_size;
 225 #endif
 226
 227 int tegra_with_secure_firmware;
 228
 229 static int pmu_core_edp;
 230 static int board_panel_type;
 231 static int pwr_i2c_clk = 400;
 232 static u8 power_config;
 233 static u8 display_config;
 234
 235 static int tegra_split_mem_set;
 236
 237 /* Bootloader configured dfll frequency */
 238 static unsigned long int dfll_boot_req_khz;
 239
 240 struct device tegra_generic_cma_dev;
 241 struct device tegra_vpr_cma_dev;
 242
 243 struct device tegra_generic_dev;
 244
 245 struct device tegra_vpr_dev;
 246 EXPORT_SYMBOL(tegra_vpr_dev);
 247
 248 struct device tegra_iram_dev;
 249 EXPORT_SYMBOL(tegra_iram_dev);
 250
 251 #define CREATE_TRACE_POINTS
 252 #include <trace/events/nvsecurity.h>
 253
 254 static int tegra_update_resize_cfg(phys_addr_t base , size_t size)
 255 {
 256         int err = 0;
 257 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
 258 #define MAX_RETRIES 6
 259         int retries = MAX_RETRIES;
 260
 261 retry:
 262         err = gk20a_do_idle();
 263         if (!err) {
 264                 /* Config VPR_BOM/_SIZE in MC */
 265                 err = te_set_vpr_params((void *)(uintptr_t)base, size);
 266                 gk20a_do_unidle();
 267         } else {
 268                 if (retries--) {
 269                         pr_err("%s:%d: fail retry=%d",
 270                                 __func__, __LINE__, MAX_RETRIES - retries);
 271                         msleep(1);
 272                         goto retry;
 273                 }
 274         }
 275 #endif
 276         return err;
 277 }
 278
 279 struct dma_resize_notifier_ops vpr_dev_ops = {
 280         .resize = tegra_update_resize_cfg
 281 };
 282
 283 u32 notrace tegra_read_cycle(void)
 284 {
 285         u32 cycle_count;
 286
 287 #ifdef CONFIG_ARM64
 288         asm volatile("mrs %0, pmccntr_el0" : "=r"(cycle_count));
 289 #else
 290         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cycle_count));
 291 #endif
 292
 293         return cycle_count;
 294 }
 295
 296 /*
 297  * Storage for debug-macro.S's state.
 298  *
 299  * This must be in .data not .bss so that it gets initialized each time the
 300  * kernel is loaded. The data is declared here rather than debug-macro.S so
 301  * that multiple inclusions of debug-macro.S point at the same data.
 302  */
 303 u32 tegra_uart_config[4] = {
 304         /* Debug UART initialization required */
 305         1,
 306         /* Debug UART physical address */
 307         0,
 308         /* Debug UART virtual address */
 309         0,
 310         /* Scratch space for debug macro */
 311         0,
 312 };
 313
 314
 315 static DEFINE_SPINLOCK(ahb_lock);
 316
 317 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
 318 {
 319         unsigned long check;
 320         int retry = 10;
 321         unsigned long flags;
 322
 323         /* Read and check if write is successful,
 324          * if val doesn't match with read, retry write.
 325          */
 326         spin_lock_irqsave(&ahb_lock, flags);
 327         do {
 328                 writel(val, reg);
 329                 check = readl(reg);
 330                 if (likely(check == val))
 331                         break;
 332                 else
 333                         pr_err("AHB register access fail for reg\n");
 334         } while (--retry);
 335         spin_unlock_irqrestore(&ahb_lock, flags);
 336 }
 337
 338 static int modem_id;
 339 static int commchip_id;
 340 static int sku_override;
 341 static bool uart_over_sd;
 342 static enum audio_codec_type audio_codec_name;
 343 static enum image_type board_image_type = system_image;
 344 static int max_core_current;
 345 static int emc_max_dvfs;
 346 static unsigned int memory_type;
 347 static int usb_port_owner_info;
 348 static int lane_owner_info;
 349 static int chip_personality;
 350
 351 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
 352 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
 353         /* name         parent          rate            enabled */
 354         { "clk_m",      NULL,           0,              true },
 355         { "emc",        NULL,           0,              true },
 356         { "cpu",        NULL,           0,              true },
 357         { "kfuse",      NULL,           0,              true },
 358         { "fuse",       NULL,           0,              true },
 359         { "sclk",       NULL,           0,              true },
 360         { "pll_p",      NULL,           0,              true },
 361         { "pll_p_out1", "pll_p",        0,              false },
 362         { "pll_p_out3", "pll_p",        0,              false },
 363 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
 364         { "pll_m_out1", "pll_m",        275000000,      false },
 365         { "pll_p_out2",  "pll_p",       102000000,      false },
 366         { "sclk",        "pll_p_out2",  102000000,      true },
 367         { "pll_p_out4",  "pll_p",       204000000,      true },
 368         { "hclk",       "sclk",         102000000,      true },
 369         { "pclk",       "hclk",         51000000,       true },
 370         { "mselect",    "pll_p",        102000000,      true },
 371         { "host1x",     "pll_p",        102000000,      false },
 372         { "cl_dvfs_ref", "pll_p",       51000000,       true },
 373         { "cl_dvfs_soc", "pll_p",       51000000,       true },
 374         { "dsialp", "pll_p",    70000000,       false },
 375         { "dsiblp", "pll_p",    70000000,       false },
 376 #else
 377         { "pll_m_out1", "pll_m",        275000000,      true },
 378         { "pll_p_out2", "pll_p",        108000000,      false },
 379         { "sclk",       "pll_p_out2",   108000000,      true },
 380         { "pll_p_out4", "pll_p",        216000000,      true },
 381         { "hclk",       "sclk",         108000000,      true },
 382         { "pclk",       "hclk",         54000000,       true },
 383         { "mselect",    "pll_p",        108000000,      true },
 384         { "host1x",     "pll_p",        108000000,      false },
 385         { "cl_dvfs_ref", "clk_m",       13000000,       false },
 386         { "cl_dvfs_soc", "clk_m",       13000000,       false },
 387 #endif
 388 #ifdef CONFIG_TEGRA_SLOW_CSITE
 389         { "csite",      "clk_m",        1000000,        true },
 390 #else
 391         { "csite",      NULL,           0,              true },
 392 #endif
 393         { "pll_u",      NULL,           480000000,      true },
 394         { "pll_re_vco", NULL,           612000000,      true },
 395         { "xusb_falcon_src",    "pll_p",        204000000,      false},
 396         { "xusb_host_src",      "pll_p",        102000000,      false},
 397         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
 398         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
 399         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
 400         { "sdmmc1",     "pll_p",        48000000,       false},
 401         { "sdmmc3",     "pll_p",        48000000,       false},
 402         { "sdmmc4",     "pll_p",        48000000,       false},
 403         { "sbc1.sclk",  NULL,           40000000,       false},
 404         { "sbc2.sclk",  NULL,           40000000,       false},
 405         { "sbc3.sclk",  NULL,           40000000,       false},
 406         { "sbc4.sclk",  NULL,           40000000,       false},
 407         { "sbc5.sclk",  NULL,           40000000,       false},
 408         { "sbc6.sclk",  NULL,           40000000,       false},
 409 #ifdef CONFIG_TEGRA_DUAL_CBUS
 410         { "c2bus",      "pll_c2",       250000000,      false },
 411         { "c3bus",      "pll_c3",       250000000,      false },
 412         { "pll_c",      NULL,           624000000,      false },
 413 #else
 414         { "cbus",       "pll_c",        250000000,      false },
 415 #endif
 416         { "pll_c_out1", "pll_c",        150000000,      false },
 417 #ifdef CONFIG_TEGRA_PLLM_SCALED
 418         { "vi",         "pll_p",        0,              false},
 419 #endif
 420 #ifdef CONFIG_TEGRA_SOCTHERM
 421         { "soc_therm",  "pll_p",        136000000,      false },
 422         { "tsensor",    "clk_m",        500000,         false },
 423 #endif
 424         { "csite",      NULL,           0,              true },
 425         { NULL,         NULL,           0,              0},
 426 };
 427 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
 428 #ifdef CONFIG_TEGRA_DUAL_CBUS
 429         { "c2bus",      "pll_c2",       250000000,      false },
 430         { "c3bus",      "pll_c3",       250000000,      false },
 431         { "pll_c",      NULL,           624000000,      false },
 432 #else
 433         { "cbus",       "pll_c",        250000000,      false },
 434 #endif
 435         { "pll_c_out1", "pll_c",        150000000,      false },
 436         { NULL,         NULL,           0,              0},
 437 };
 438 #endif
 439 /*
 440  * Set system level PLLs and common clocks. If for a board, clock rate/parent
 441  * is different, it can be overridden in the board specific clock table.
 442  */
 443 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
 444 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
 445         /* name         parent          rate            enabled */
 446         { "clk_m",      NULL,           0,              true },
 447         { "mc",         NULL,           0,              true },
 448         { "cpu",        NULL,           0,              true },
 449         { "kfuse",      NULL,           0,              true },
 450         { "fuse",       NULL,           0,              true },
 451         { "sclk",       NULL,           0,              true },
 452         { "pll_p",      NULL,           0,              true,
 453                 TEGRA_CLK_INIT_PLATFORM_SI },
 454         { "pll_p_out1", "pll_p",        0,              false,
 455                 TEGRA_CLK_INIT_PLATFORM_SI },
 456         { "pll_p_out3", "pll_p",        0,              true,
 457                 TEGRA_CLK_INIT_PLATFORM_SI },
 458         { "pll_m_out1", "pll_m",        275000000,      false,
 459                 TEGRA_CLK_INIT_PLATFORM_SI },
 460         { "pll_p_out2", "pll_p",        102000000,      false,
 461                 TEGRA_CLK_INIT_PLATFORM_SI },
 462         { "sclk",       "pll_p_out2",   102000000,      true,
 463                 TEGRA_CLK_INIT_PLATFORM_SI },
 464         { "pll_p_out4", "pll_p",        204000000,      true,
 465                 TEGRA_CLK_INIT_PLATFORM_SI },
 466         { "host1x",     "pll_p",        102000000,      false,
 467                 TEGRA_CLK_INIT_PLATFORM_SI },
 468         { "cl_dvfs_ref", "pll_p",       54000000,       true,
 469                 TEGRA_CLK_INIT_PLATFORM_SI },
 470         { "cl_dvfs_soc", "pll_p",       54000000,       true,
 471                 TEGRA_CLK_INIT_PLATFORM_SI },
 472         { "hclk",       "sclk",         102000000,      true,
 473                 TEGRA_CLK_INIT_PLATFORM_SI },
 474         { "pclk",       "hclk",         51000000,       true,
 475                 TEGRA_CLK_INIT_PLATFORM_SI },
 476         { "mselect",    "pll_p",        102000000,      true,
 477                 TEGRA_CLK_INIT_PLATFORM_SI },
 478         { "pll_p_out5", "pll_p",        102000000,      true,
 479                 TEGRA_CLK_INIT_PLATFORM_SI },
 480 #ifdef CONFIG_TEGRA_SLOW_CSITE
 481         { "csite",      "clk_m",        1000000,        true },
 482 #else
 483         { "csite",      NULL,           0,              true },
 484 #endif
 485         { "pll_u",      NULL,           480000000,      true },
 486         { "pll_re_vco", NULL,           672000000,      true },
 487         { "xusb_falcon_src",    "pll_re_out",   336000000,      false},
 488         { "xusb_host_src",      "pll_re_out",   112000000,      false},
 489         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
 490         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
 491         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
 492         { "sdmmc1",     "pll_p",        48000000,       false},
 493         { "sdmmc3",     "pll_p",        48000000,       false},
 494         { "sdmmc4",     "pll_p",        48000000,       false},
 495         { "sdmmc1_ddr", "pll_p",        48000000,       false},
 496         { "sdmmc3_ddr", "pll_p",        48000000,       false},
 497         { "sdmmc4_ddr", "pll_p",        48000000,       false},
 498         { "cpu.mselect", NULL,          102000000,      true},
 499         { "gpu_ref",    NULL,           0,              true},
 500         { "gk20a.gbus", NULL,           252000000,      false},
 501 #ifdef CONFIG_TEGRA_PLLM_SCALED
 502         { "vi",         "pll_p",        0,              false},
 503         { "isp",        "pll_p",        0,              false},
 504 #endif
 505 #ifdef CONFIG_TEGRA_SOCTHERM
 506         { "soc_therm",  "pll_p",        51000000,       false },
 507         { "tsensor",    "clk_m",        500000,         false },
 508 #endif
 509         { "pll_d",      NULL,           0,              true },
 510         { "dsialp",     "pll_p",        70000000,       false },
 511         { "dsiblp",     "pll_p",        70000000,       false },
 512         { NULL,         NULL,           0,              0},
 513 };
 514
 515 #ifdef CONFIG_TEGRA_PLLCX_FIXED
 516         /* Set PLLCx rates for automotive */
 517 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
 518         /* Initialize c2bus, c3bus, or cbus at the end of the list
 519          * after all the clocks are moved under the proper parents.
 520          */
 521 #ifdef CONFIG_TEGRA_DUAL_CBUS
 522         { "c2bus",      "pll_c2",       372000000,      false },
 523         { "c3bus",      "pll_c3",       450000000,      false },
 524         { "pll_c",      NULL,           564000000,      false },
 525 #else
 526         { "cbus",       "pll_c",        564000000,      false },
 527 #endif
 528         { "pll_c_out1", "pll_c",        282000000,      false },
 529         { "c4bus",      "pll_c4",       600000000,      false },
 530         { NULL,         NULL,           0,              0},
 531 };
 532 #else
 533
 534 #ifdef CONFIG_TEGRA_DUAL_CBUS
 535 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
 536         /* Initialize c2bus, c3bus, or cbus at the end of the list
 537          * after all the clocks are moved under the proper parents.
 538          */
 539         { "c2bus",      "pll_c2",       250000000,      false },
 540         { "c3bus",      "pll_c3",       250000000,      false },
 541         { "pll_c",      NULL,           600000000,      false },
 542 #else
 543         { "cbus",       "pll_c",        200000000,      false },
 544 #endif
 545         { "pll_c_out1", "pll_c",        100000000,      false },
 546         { "c4bus",      "pll_c4",       200000000,      false },
 547         { NULL,         NULL,           0,              0},
 548 };
 549 #endif
 550
 551 static __initdata struct tegra_clk_init_table tegra12x_sbus_init_table[] = {
 552         /* Initialize sbus (system clock) users after cbus init PLLs */
 553         { "sbc1.sclk",  NULL,           40000000,       false},
 554         { "sbc2.sclk",  NULL,           40000000,       false},
 555         { "sbc3.sclk",  NULL,           40000000,       false},
 556         { "sbc4.sclk",  NULL,           40000000,       false},
 557         { "sbc5.sclk",  NULL,           40000000,       false},
 558         { "sbc6.sclk",  NULL,           40000000,       false},
 559         { "wake.sclk",  NULL,           40000000,       true, TEGRA_CLK_INIT_PLATFORM_SI },
 560         { NULL,         NULL,           0,              0},
 561 };
 562 #endif
 563
 564 #ifdef CONFIG_CACHE_L2X0
 565 static void tegra_cache_smc(bool enable, u32 arg)
 566 {
 567         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
 568         bool need_affinity_switch;
 569         bool can_switch_affinity;
 570         bool l2x0_enabled;
 571         cpumask_t local_cpu_mask;
 572         cpumask_t saved_cpu_mask;
 573         unsigned long flags;
 574         long ret;
 575
 576         /*
 577          * ISSUE : Some registers of PL310 controler must be written
 578          *              from Secure context (and from CPU0)!
 579          *
 580          * When called form Normal we obtain an abort or do nothing.
 581          * Instructions that must be called in Secure:
 582          *      - Write to Control register (L2X0_CTRL==0x100)
 583          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
 584          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
 585          *              mandatory at boot time.
 586          *      - Tag and Data RAM Latency Control Registers
 587          *              (0x108 & 0x10C) must be written in Secure.
 588          */
 589         need_affinity_switch = (smp_processor_id() != 0);
 590         can_switch_affinity = !irqs_disabled();
 591
 592         WARN_ON(need_affinity_switch && !can_switch_affinity);
 593         if (need_affinity_switch && can_switch_affinity) {
 594                 cpu_set(0, local_cpu_mask);
 595                 sched_getaffinity(0, &saved_cpu_mask);
 596                 ret = sched_setaffinity(0, &local_cpu_mask);
 597                 WARN_ON(ret != 0);
 598         }
 599
 600         local_irq_save(flags);
 601         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
 602         if (enable && !l2x0_enabled)
 603                 tegra_generic_smc(0x82000002, 0x00000001, arg);
 604         else if (!enable && l2x0_enabled)
 605                 tegra_generic_smc(0x82000002, 0x00000002, arg);
 606         local_irq_restore(flags);
 607
 608         if (need_affinity_switch && can_switch_affinity) {
 609                 ret = sched_setaffinity(0, &saved_cpu_mask);
 610                 WARN_ON(ret != 0);
 611         }
 612 }
 613
 614 static void tegra_l2x0_disable(void)
 615 {
 616         unsigned long flags;
 617         static u32 l2x0_way_mask;
 618
 619         if (!l2x0_way_mask) {
 620                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
 621                 u32 aux_ctrl;
 622                 u32 ways;
 623
 624                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
 625                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
 626                 l2x0_way_mask = (1 << ways) - 1;
 627         }
 628
 629         local_irq_save(flags);
 630         tegra_cache_smc(false, l2x0_way_mask);
 631         local_irq_restore(flags);
 632 }
 633
 634 void tegra_init_cache(bool init)
 635 {
 636         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
 637         u32 aux_ctrl;
 638         u32 cache_type;
 639         u32 tag_latency, data_latency;
 640
 641         if (tegra_cpu_is_secure()) {
 642                 /* issue the SMC to enable the L2 */
 643                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
 644                 trace_smc_init_cache(NVSEC_SMC_START);
 645                 tegra_cache_smc(true, aux_ctrl);
 646                 trace_smc_init_cache(NVSEC_SMC_DONE);
 647
 648                 /* after init, reread aux_ctrl and register handlers */
 649                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
 650                 l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
 651
 652                 /* override outer_disable() with our disable */
 653                 outer_cache.disable = tegra_l2x0_disable;
 654         } else {
 655 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
 656                 tag_latency = 0x331;
 657                 data_latency = 0x441;
 658 #else
 659                 if (!tegra_platform_is_silicon()) {
 660                         tag_latency = 0x770;
 661                         data_latency = 0x770;
 662                 } else if (is_lp_cluster()) {
 663                         tag_latency = tegra_cpu_c1_l2_tag_latency;
 664                         data_latency = tegra_cpu_c1_l2_data_latency;
 665                 } else {
 666                         tag_latency = tegra_cpu_c0_l2_tag_latency;
 667                         data_latency = tegra_cpu_c0_l2_data_latency;
 668                 }
 669 #endif
 670                 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
 671                 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 672
 673 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 674                 if (!tegra_platform_is_fpga()) {
 675                         writel(0x7, p + L2X0_PREFETCH_CTRL);
 676                         writel(0x3, p + L2X0_POWER_CTRL);
 677                 }
 678 #endif
 679                 cache_type = readl(p + L2X0_CACHE_TYPE);
 680                 aux_ctrl = (cache_type & 0x700) << (17-8);
 681                 aux_ctrl |= 0x7C400001;
 682                 if (init) {
 683                         l2x0_init(p, aux_ctrl, 0x8200c3fe);
 684                 } else {
 685                         u32 tmp;
 686
 687                         tmp = aux_ctrl;
 688                         aux_ctrl = readl(p + L2X0_AUX_CTRL);
 689                         aux_ctrl &= 0x8200c3fe;
 690                         aux_ctrl |= tmp;
 691                         writel(aux_ctrl, p + L2X0_AUX_CTRL);
 692                 }
 693                 l2x0_enable();
 694         }
 695 }
 696 #endif
 697
 698 static void __init tegra_perf_init(void)
 699 {
 700         u32 reg;
 701
 702 #ifdef CONFIG_ARM64
 703         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
 704         reg >>= 11;
 705         reg = (1 << (reg & 0x1f))-1;
 706         reg |= 0x80000000;
 707         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
 708         reg = 1;
 709         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
 710 #else
 711         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
 712         reg >>= 11;
 713         reg = (1 << (reg & 0x1f))-1;
 714         reg |= 0x80000000;
 715         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
 716         reg = 1;
 717         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
 718 #endif
 719 }
 720
 721 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 722 static void __init tegra_ramrepair_init(void)
 723 {
 724 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 725         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
 726 #endif
 727                 u32 reg;
 728                 reg = readl(FLOW_CTRL_RAM_REPAIR);
 729                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
 730                 writel(reg, FLOW_CTRL_RAM_REPAIR);
 731 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 732         }
 733 #endif
 734 }
 735 #endif
 736
 737 static void __init tegra_init_power(void)
 738 {
 739         int partition_id;
 740 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 741         int partition_id_xusba, partition_id_xusbb, partition_id_xusbc;
 742 #endif
 743
 744 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
 745 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 746         partition_id = tegra_pd_get_powergate_id(tegra_sata_pd);
 747         if (partition_id < 0)
 748                 return;
 749 #else
 750         partition_id = TEGRA_POWERGATE_SATA;
 751 #endif
 752         tegra_powergate_partition(partition_id);
 753 #endif
 754
 755 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
 756 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 757         partition_id = tegra_pd_get_powergate_id(tegra_pcie_pd);
 758         if (partition_id < 0)
 759                 return;
 760 #else
 761         partition_id = TEGRA_POWERGATE_PCIE;
 762 #endif
 763         tegra_powergate_partition(partition_id);
 764 #endif
 765
 766 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
 767         /* powergate xusb partitions by default */
 768 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 769         partition_id_xusbb = tegra_pd_get_powergate_id(tegra_xusbb_pd);
 770         if (partition_id_xusbb < 0)
 771                 return;
 772
 773         partition_id_xusba = tegra_pd_get_powergate_id(tegra_xusba_pd);
 774         if (partition_id_xusba < 0)
 775                 return;
 776
 777         partition_id_xusbc = tegra_pd_get_powergate_id(tegra_xusbc_pd);
 778         if (partition_id_xusbc < 0)
 779                 return;
 780 #else
 781         partition_id_xusbb = TEGRA_POWERGATE_XUSBB;
 782         partition_id_xusba = TEGRA_POWERGATE_XUSBA;
 783         partition_id_xusbc = TEGRA_POWERGATE_XUSBC;
 784 #endif
 785         tegra_powergate_partition(partition_id_xusbb);
 786         tegra_powergate_partition(partition_id_xusba);
 787         tegra_powergate_partition(partition_id_xusbc);
 788 #endif
 789
 790 }
 791
 792 static inline unsigned long gizmo_readl(unsigned long offset)
 793 {
 794         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
 795 }
 796
 797 static inline void gizmo_writel(unsigned long value, unsigned long offset)
 798 {
 799         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
 800 }
 801
 802 static void __init tegra_init_ahb_gizmo_settings(void)
 803 {
 804         unsigned long val;
 805
 806         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
 807         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
 808
 809         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
 810                 val |= WR_WAIT_COMMIT_ON_1K;
 811 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 812         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
 813 #endif
 814         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
 815
 816         val = gizmo_readl(AHB_GIZMO_USB);
 817         val |= IMMEDIATE;
 818         gizmo_writel(val, AHB_GIZMO_USB);
 819
 820         val = gizmo_readl(AHB_GIZMO_USB2);
 821         val |= IMMEDIATE;
 822         gizmo_writel(val, AHB_GIZMO_USB2);
 823
 824         val = gizmo_readl(AHB_GIZMO_USB3);
 825         val |= IMMEDIATE;
 826         gizmo_writel(val, AHB_GIZMO_USB3);
 827
 828         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
 829         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
 830                                 | AHB_PRIORITY_WEIGHT(7);
 831 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 832         val |= PRIORITY_SELECT_SE;
 833 #endif
 834
 835         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
 836
 837         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
 838         val &= ~MST_ID(~0);
 839         val |= PREFETCH_ENB | AHBDMA_MST_ID |
 840                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
 841         ahb_gizmo_writel(val,
 842                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
 843
 844         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
 845         val &= ~MST_ID(~0);
 846         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
 847                 INACTIVITY_TIMEOUT(0x1000);
 848         ahb_gizmo_writel(val,
 849                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
 850
 851         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
 852         val &= ~MST_ID(~0);
 853         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
 854                 INACTIVITY_TIMEOUT(0x1000);
 855         ahb_gizmo_writel(val,
 856                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
 857
 858         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
 859         val &= ~MST_ID(~0);
 860         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
 861                 INACTIVITY_TIMEOUT(0x1000);
 862         ahb_gizmo_writel(val,
 863                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
 864
 865         /*
 866          * SDMMC controller is removed from AHB interface in T124 and
 867          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
 868          * in T11x.
 869          */
 870 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 871         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
 872         val &= ~MST_ID(~0);
 873         val |= PREFETCH_ENB | SDMMC4_MST_ID;
 874         val &= ~SDMMC4_MST_ID;
 875         ahb_gizmo_writel(val,
 876                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
 877 #endif
 878
 879 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 880         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
 881         val &= ~MST_ID(~0);
 882         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
 883                 INACTIVITY_TIMEOUT(0x1000);
 884         ahb_gizmo_writel(val,
 885                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
 886 #endif
 887 }
 888
 889 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 890 void __init tegra20_init_early(void)
 891 {
 892         tegra_apb_io_init();
 893         tegra_perf_init();
 894         tegra_init_fuse();
 895         tegra_init_cache(true);
 896         tegra_powergate_init();
 897         tegra20_hotplug_init();
 898         tegra_init_power();
 899         tegra_init_ahb_gizmo_settings();
 900 }
 901 #endif
 902 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 903 void __init tegra30_init_early(void)
 904 {
 905         u32 speedo;
 906         u32 tag_latency, data_latency;
 907
 908         display_tegra_dt_info();
 909         tegra_apb_io_init();
 910         tegra_perf_init();
 911         tegra_init_fuse();
 912         /*
 913          * Store G/LP cluster L2 latencies to IRAM and DRAM
 914          */
 915         tegra_cpu_c1_l2_tag_latency = 0x221;
 916         tegra_cpu_c1_l2_data_latency = 0x221;
 917         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
 918         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
 919         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
 920         speedo = tegra_cpu_speedo_id();
 921         if (speedo == 4 || speedo == 5 || speedo == 6 ||
 922             speedo == 12 || speedo == 13) {
 923                 tag_latency = 0x442;
 924                 data_latency = 0x552;
 925         } else {
 926                 tag_latency = 0x441;
 927                 data_latency = 0x551;
 928         }
 929         tegra_cpu_c0_l2_tag_latency = tag_latency;
 930         tegra_cpu_c0_l2_data_latency = data_latency;
 931         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
 932         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
 933         tegra_init_cache(true);
 934         tegra_powergate_init();
 935         tegra30_hotplug_init();
 936         tegra_init_power();
 937         tegra_init_ahb_gizmo_settings();
 938
 939         init_dma_coherent_pool_size(SZ_1M);
 940 }
 941 #endif
 942 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
 943 void __init tegra11x_init_early(void)
 944 {
 945         display_tegra_dt_info();
 946         tegra_apb_io_init();
 947         tegra_perf_init();
 948         tegra_init_fuse();
 949         tegra_ramrepair_init();
 950         tegra11x_init_clocks();
 951         tegra11x_init_dvfs();
 952         tegra_common_init_clock();
 953         tegra_clk_init_from_table(tegra11x_clk_init_table);
 954         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
 955         tegra11x_clk_init_la();
 956         tegra_powergate_init();
 957         tegra30_hotplug_init();
 958         tegra_init_power();
 959         tegra_init_ahb_gizmo_settings();
 960
 961         init_dma_coherent_pool_size(SZ_2M);
 962 }
 963 #endif
 964 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
 965 void __init tegra12x_init_early(void)
 966 {
 967         if (of_find_compatible_node(NULL, NULL, "arm,psci-0.2"))
 968                 tegra_with_secure_firmware = 1;
 969
 970         display_tegra_dt_info();
 971         tegra_apb_io_init();
 972         tegra_perf_init();
 973         tegra_init_fuse();
 974         tegra_ramrepair_init();
 975         tegra12x_init_clocks();
 976 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
 977         tegra13x_init_dvfs();
 978 #else
 979         tegra12x_init_dvfs();
 980 #endif
 981         tegra_common_init_clock();
 982         tegra_clk_init_from_table(tegra12x_clk_init_table);
 983         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
 984         tegra_clk_init_from_table(tegra12x_sbus_init_table);
 985         tegra_non_dt_clock_reset_init();
 986         tegra_powergate_init();
 987 #ifndef CONFIG_ARM64
 988         tegra30_hotplug_init();
 989 #endif
 990         tegra_init_power();
 991         tegra_init_ahb_gizmo_settings();
 992 }
 993 #endif
 994 static int __init tegra_lp0_vec_arg(char *options)
 995 {
 996         char *p = options;
 997
 998         tegra_lp0_vec_size = memparse(p, &p);
 999         if (*p == '@')
1000                 tegra_lp0_vec_start = memparse(p+1, &p);
1001         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1002                 tegra_lp0_vec_size = 0;
1003                 tegra_lp0_vec_start = 0;
1004         }
1005
1006         return 0;
1007 }
1008 early_param("lp0_vec", tegra_lp0_vec_arg);
1009
1010 static int __init tegra_bl_prof_arg(char *option)
1011 {
1012         char *p = option;
1013
1014         tegra_bl_prof_size = memparse(p, &p);
1015         if (*p == '@')
1016                 tegra_bl_prof_start = memparse(p+1, &p);
1017
1018         if (!tegra_bl_prof_size || !tegra_bl_prof_start) {
1019                 tegra_bl_prof_size = 0;
1020                 tegra_bl_prof_start = 0;
1021         }
1022
1023         return 0;
1024 }
1025 early_param("bl_prof_dataptr", tegra_bl_prof_arg);
1026
1027 static int __init tegra_bl_debug_data_arg(char *options)
1028 {
1029         char *p = options;
1030
1031         tegra_bl_debug_data_size = memparse(p, &p);
1032         if (*p == '@')
1033                 tegra_bl_debug_data_start = memparse(p+1, &p);
1034         if (!tegra_bl_debug_data_size || !tegra_bl_debug_data_start) {
1035                 tegra_bl_debug_data_size = 0;
1036                 tegra_bl_debug_data_start = 0;
1037         }
1038
1039         return 0;
1040 }
1041 early_param("bl_debug_data", tegra_bl_debug_data_arg);
1042
1043 #ifdef CONFIG_TEGRA_NVDUMPER
1044 static int __init tegra_nvdumper_arg(char *options)
1045 {
1046         char *p = options;
1047
1048         nvdumper_reserved = memparse(p, &p);
1049         return 0;
1050 }
1051 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1052 #endif
1053
1054 static int __init tegra_bootloader_fb_arg(char *options)
1055 {
1056         char *p = options;
1057
1058         tegra_bootloader_fb_size = memparse(p, &p);
1059         if (*p == '@')
1060                 tegra_bootloader_fb_start = memparse(p+1, &p);
1061
1062         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1063                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1064
1065         return 0;
1066 }
1067 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1068
1069 static int __init tegra_bootloader_fb2_arg(char *options)
1070 {
1071         char *p = options;
1072
1073         tegra_bootloader_fb2_size = memparse(p, &p);
1074         if (*p == '@')
1075                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1076
1077         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1078                 (u64)tegra_bootloader_fb2_size,
1079                 (u64)tegra_bootloader_fb2_start);
1080
1081         return 0;
1082 }
1083 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1084
1085 static int __init tegra_sku_override(char *id)
1086 {
1087         char *p = id;
1088
1089         sku_override = memparse(p, &p);
1090
1091         return 0;
1092 }
1093 early_param("sku_override", tegra_sku_override);
1094
1095 int tegra_get_sku_override(void)
1096 {
1097         return sku_override;
1098 }
1099
1100 static int __init tegra_chip_personality(char *id)
1101 {
1102         char *p = id;
1103
1104         chip_personality = memparse(p, &p);
1105
1106         return 0;
1107 }
1108 early_param("chip_personality", tegra_chip_personality);
1109
1110 int tegra_get_chip_personality(void)
1111 {
1112         return chip_personality;
1113 }
1114
1115 static int __init tegra_vpr_resize_arg(char *options)
1116 {
1117         tegra_vpr_resize = true;
1118         return 0;
1119 }
1120 early_param("vpr_resize", tegra_vpr_resize_arg);
1121
1122 static int __init tegra_vpr_arg(char *options)
1123 {
1124         char *p = options;
1125
1126         tegra_vpr_size = memparse(p, &p);
1127         if (*p == '@')
1128                 tegra_vpr_start = memparse(p+1, &p);
1129         pr_info("Found vpr, start=0x%llx size=%llx",
1130                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1131         return 0;
1132 }
1133 early_param("vpr", tegra_vpr_arg);
1134
1135 static int __init tegra_tsec_arg(char *options)
1136 {
1137         char *p = options;
1138
1139         tegra_tsec_size = memparse(p, &p);
1140         if (*p == '@')
1141                 tegra_tsec_start = memparse(p+1, &p);
1142         pr_info("Found tsec, start=0x%llx size=%llx",
1143                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1144         return 0;
1145 }
1146 early_param("tsec", tegra_tsec_arg);
1147
1148 #ifdef CONFIG_TEGRA_USE_NCT
1149 static int __init tegra_nck_arg(char *options)
1150 {
1151         char *p = options;
1152
1153         tegra_nck_size = memparse(p, &p);
1154         if (*p == '@')
1155                 tegra_nck_start = memparse(p+1, &p);
1156         if (!tegra_nck_size || !tegra_nck_start) {
1157                 tegra_nck_size = 0;
1158                 tegra_nck_start = 0;
1159         }
1160
1161         return 0;
1162 }
1163 early_param("nck", tegra_nck_arg);
1164 #endif  /* CONFIG_TEGRA_USE_NCT */
1165
1166 enum panel_type get_panel_type(void)
1167 {
1168         return board_panel_type;
1169 }
1170 static int __init tegra_board_panel_type(char *options)
1171 {
1172         if (!strcmp(options, "lvds"))
1173                 board_panel_type = panel_type_lvds;
1174         else if (!strcmp(options, "dsi"))
1175                 board_panel_type = panel_type_dsi;
1176         else
1177                 return 0;
1178         return 1;
1179 }
1180 __setup("panel=", tegra_board_panel_type);
1181
1182 int tegra_get_board_panel_id(void)
1183 {
1184         return panel_id;
1185 }
1186 static int __init tegra_board_panel_id(char *options)
1187 {
1188         char *p = options;
1189         panel_id = memparse(p, &p);
1190         return panel_id;
1191 }
1192 __setup("display_panel=", tegra_board_panel_id);
1193
1194 /* returns true if bl initialized the display */
1195 bool tegra_is_bl_display_initialized(int instance)
1196 {
1197         /* display initialized implies non-zero
1198          * fb size is passed from bl to kernel
1199          */
1200         switch (instance) {
1201         case 0:
1202                 return tegra_bootloader_fb_start && tegra_bootloader_fb_size;
1203         case 1:
1204                 return tegra_bootloader_fb2_start && tegra_bootloader_fb2_size;
1205         default:
1206                 return false;
1207         }
1208 }
1209
1210 int tegra_get_board_battery_id(void)
1211 {
1212         return battery_id;
1213 }
1214
1215 static int __init tegra_board_battery_id(char *options)
1216 {
1217         char *p = options;
1218         battery_id = memparse(p, &p);
1219         return battery_id;
1220 }
1221 __setup("androidboot.batterytype=", tegra_board_battery_id);
1222
1223 int tegra_get_touch_vendor_id(void)
1224 {
1225         return touch_vendor_id;
1226 }
1227 int tegra_get_touch_panel_id(void)
1228 {
1229         return touch_panel_id;
1230 }
1231 static int __init tegra_touch_id(char *options)
1232 {
1233         char *p = options;
1234         touch_vendor_id = memparse(p, &p);
1235         if (*p == '@')
1236                 touch_panel_id = memparse(p+1, &p);
1237         return 1;
1238 }
1239 __setup("touch_id=", tegra_touch_id);
1240
1241 u8 get_power_config(void)
1242 {
1243         return power_config;
1244 }
1245 static int __init tegra_board_power_config(char *options)
1246 {
1247         char *p = options;
1248         power_config = memparse(p, &p);
1249         return 1;
1250 }
1251 __setup("power-config=", tegra_board_power_config);
1252
1253 u8 get_display_config(void)
1254 {
1255         return display_config;
1256 }
1257 static int __init tegra_board_display_config(char *options)
1258 {
1259         char *p = options;
1260         display_config = memparse(p, &p);
1261         return 1;
1262 }
1263 __setup("display-config=", tegra_board_display_config);
1264
1265 int get_core_edp(void)
1266 {
1267         return pmu_core_edp;
1268 }
1269 static int __init tegra_pmu_core_edp(char *options)
1270 {
1271         char *p = options;
1272         int core_edp = memparse(p, &p);
1273         if (core_edp != 0)
1274                 pmu_core_edp = core_edp;
1275         return 0;
1276 }
1277 early_param("core_edp_mv", tegra_pmu_core_edp);
1278
1279 int get_maximum_core_current_supported(void)
1280 {
1281         return max_core_current;
1282 }
1283 static int __init tegra_max_core_current(char *options)
1284 {
1285         char *p = options;
1286         max_core_current = memparse(p, &p);
1287         return 0;
1288 }
1289 early_param("core_edp_ma", tegra_max_core_current);
1290
1291 int get_emc_max_dvfs(void)
1292 {
1293         return emc_max_dvfs;
1294 }
1295 static int __init tegra_emc_max_dvfs(char *options)
1296 {
1297         char *p = options;
1298         emc_max_dvfs = memparse(p, &p);
1299         return 1;
1300 }
1301 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1302
1303 int tegra_get_memory_type(void)
1304 {
1305         return memory_type;
1306 }
1307 static int __init tegra_memory_type(char *options)
1308 {
1309         char *p = options;
1310         memory_type = memparse(p, &p);
1311         return 1;
1312 }
1313 __setup("memtype=", tegra_memory_type);
1314
1315 static int tegra_get_uart_over_sd_property(void)
1316 {
1317         struct device_node *np;
1318         u32 pval;
1319         int ret;
1320
1321         np = of_find_node_by_path("/chosen");
1322         if (!np)
1323                 return -EINVAL;
1324
1325         ret = of_property_read_u32(np, "nvidia,debug-console-over-sd", &pval);
1326         if (ret < 0) {
1327                 pr_err("/chosen/nvidia,debug-console-over-sd read failed: %d\n",
1328                         ret);
1329                 return ret;
1330         }
1331         return (int)pval;
1332 }
1333
1334 static int __init tegra_debug_uartport(char *info)
1335 {
1336         char *p = info;
1337         unsigned long long port_id;
1338         int uart_port_id;
1339
1340         if (p[6] == ',') {
1341                 if (p[7] != '-') {
1342                         port_id = memparse(p + 7, &p);
1343                         uart_port_id = (int) port_id;
1344                         if (uart_port_id == 5)
1345                                 uart_over_sd = true;
1346                 }
1347         }
1348
1349         return 1;
1350 }
1351
1352 bool is_uart_over_sd_enabled(void)
1353 {
1354         static bool dt_parsed = 0;
1355         int ret;
1356
1357         if (!dt_parsed) {
1358                 dt_parsed = 1;
1359                 ret = tegra_get_uart_over_sd_property();
1360                 if (ret == 1)
1361                          uart_over_sd = true;
1362         }
1363         return uart_over_sd;
1364 }
1365 __setup("debug_uartport=", tegra_debug_uartport);
1366
1367 static int __init tegra_image_type(char *options)
1368 {
1369         if (!strcmp(options, "RCK"))
1370                 board_image_type = rck_image;
1371
1372         return 0;
1373 }
1374
1375 enum image_type get_tegra_image_type(void)
1376 {
1377         return board_image_type;
1378 }
1379
1380 __setup("image=", tegra_image_type);
1381
1382 static int __init tegra_audio_codec_type(char *info)
1383 {
1384         char *p = info;
1385         if (!strncmp(p, "wm8903", 6))
1386                 audio_codec_name = audio_codec_wm8903;
1387         else
1388                 audio_codec_name = audio_codec_none;
1389
1390         return 1;
1391 }
1392
1393 enum audio_codec_type get_audio_codec_type(void)
1394 {
1395         return audio_codec_name;
1396 }
1397 __setup("audio_codec=", tegra_audio_codec_type);
1398
1399 static int tegra_get_pwr_i2c_clk_rate(char *options)
1400 {
1401         int clk = simple_strtol(options, NULL, 16);
1402         if (clk != 0)
1403                 pwr_i2c_clk = clk;
1404         return 0;
1405 }
1406
1407 int get_pwr_i2c_clk_rate(void)
1408 {
1409         return pwr_i2c_clk;
1410 }
1411 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1412
1413 #ifdef CONFIG_OF
1414 void find_dc_node(struct device_node **dc1_node,
1415                 struct device_node **dc2_node) {
1416         *dc1_node =
1417                 of_find_node_by_path("/host1x/dc@54200000");
1418         *dc2_node =
1419                 of_find_node_by_path("/host1x/dc@54240000");
1420 }
1421 #else
1422 void find_dc_node(struct device_node *dc1_node,
1423                 struct device_node *dc2_node) {
1424         return;
1425 }
1426 #endif
1427
1428 static int tegra_get_board_info_properties(struct board_info *bi,
1429                 const char *property_name)
1430 {
1431         struct device_node *board_info;
1432         char board_info_path[50] = {0};
1433         u32 prop_val;
1434         int err;
1435
1436         strcpy(board_info_path, "/chosen/");
1437         strcat(board_info_path, property_name);
1438
1439         board_info = of_find_node_by_path(board_info_path);
1440         memset(bi, 0, sizeof(*bi));
1441
1442         if (board_info) {
1443                 err = of_property_read_u32(board_info, "id", &prop_val);
1444                 if (err < 0) {
1445                         pr_err("failed to read %s/id\n", board_info_path);
1446                         goto out;
1447                 }
1448                 bi->board_id = prop_val;
1449
1450                 err = of_property_read_u32(board_info, "sku", &prop_val);
1451                 if (err < 0) {
1452                         pr_err("failed to read %s/sku\n", board_info_path);
1453                         goto out;
1454                 }
1455                 bi->sku = prop_val;
1456
1457                 err = of_property_read_u32(board_info, "fab", &prop_val);
1458                 if (err < 0) {
1459                         pr_err("failed to read %s/fab\n", board_info_path);
1460                         goto out;
1461                 }
1462                 bi->fab = prop_val;
1463
1464                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1465                 if (err < 0) {
1466                         pr_err("failed to read %s/major_revision\n",
1467                                         board_info_path);
1468                         goto out;
1469                 }
1470                 bi->major_revision = prop_val;
1471
1472                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1473                 if (err < 0) {
1474                         pr_err("failed to read %s/minor_revision\n",
1475                                         board_info_path);
1476                         goto out;
1477                 }
1478                 bi->minor_revision = prop_val;
1479                 return 0;
1480         }
1481
1482         pr_err("Node path %s not found\n", board_info_path);
1483 out:
1484         return -1;
1485 }
1486
1487 void tegra_get_board_info(struct board_info *bi)
1488 {
1489         int ret;
1490         static bool parsed = 0;
1491
1492         if (!parsed) {
1493                 parsed = 1;
1494                 ret = tegra_get_board_info_properties(bi, "proc-board");
1495                 if (!ret) {
1496                         memcpy(&main_board_info, bi, sizeof(struct board_info));
1497                         system_serial_high = (bi->board_id << 16) | bi->sku;
1498                         system_serial_low = (bi->fab << 24) |
1499                                                 (bi->major_revision << 16) |
1500                                                 (bi->minor_revision << 8);
1501                         return;
1502                 }
1503
1504                 if (system_serial_high || system_serial_low) {
1505                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1506                         bi->sku = (system_serial_high) & 0xFFFF;
1507                         bi->fab = (system_serial_low >> 24) & 0xFF;
1508                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1509                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1510                         memcpy(&main_board_info, bi, sizeof(struct board_info));
1511                         return;
1512                 }
1513         }
1514         memcpy(bi, &main_board_info, sizeof(struct board_info));
1515 }
1516 EXPORT_SYMBOL(tegra_get_board_info);
1517
1518 void tegra_get_pmu_board_info(struct board_info *bi)
1519 {
1520         static bool parsed = 0;
1521
1522         if (!parsed) {
1523                 int ret;
1524                 parsed = 1;
1525                 ret = tegra_get_board_info_properties(bi, "pmu-board");
1526                 if (!ret)
1527                         memcpy(&pmu_board_info, bi, sizeof(struct board_info));
1528         }
1529         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1530 }
1531
1532 void tegra_get_display_board_info(struct board_info *bi)
1533 {
1534         static bool parsed = 0;
1535
1536         if (!parsed) {
1537                 int ret;
1538                 parsed = 1;
1539                 ret = tegra_get_board_info_properties(bi, "display-board");
1540                 if (!ret)
1541                         memcpy(&display_board_info, bi, sizeof(struct board_info));
1542         }
1543         memcpy(bi, &display_board_info, sizeof(struct board_info));
1544 }
1545
1546 void tegra_get_camera_board_info(struct board_info *bi)
1547 {
1548         static bool parsed = 0;
1549
1550         if (!parsed) {
1551                 int ret;
1552                 parsed = 1;
1553
1554                 ret = tegra_get_board_info_properties(bi, "camera-board");
1555                 if (!ret)
1556                         memcpy(&camera_board_info, bi, sizeof(*bi));
1557         }
1558         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1559 }
1560
1561 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1562 {
1563         static bool parsed = 0;
1564
1565         if (!parsed) {
1566                 int ret;
1567                 parsed = 1;
1568
1569                 ret = tegra_get_board_info_properties(bi, "left-speaker-board");
1570                 if (!ret)
1571                         memcpy(&leftspeaker_board_info, bi, sizeof(*bi));
1572         }
1573         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1574 }
1575
1576 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1577 {
1578         static bool parsed = 0;
1579
1580         if (!parsed) {
1581                 int ret;
1582                 parsed = 1;
1583
1584                 ret = tegra_get_board_info_properties(bi, "right-speaker-board");
1585                 if (!ret)
1586                         memcpy(&rightspeaker_board_info, bi, sizeof(*bi));
1587         }
1588         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1589 }
1590
1591 void tegra_get_joystick_board_info(struct board_info *bi)
1592 {
1593         static bool parsed = 0;
1594
1595         if (!parsed) {
1596                 int ret;
1597                 parsed = 1;
1598
1599                 ret = tegra_get_board_info_properties(bi, "joystick-board");
1600                 if (!ret)
1601                         memcpy(&joystick_board_info, bi, sizeof(*bi));
1602         }
1603         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1604 }
1605
1606 void tegra_get_button_board_info(struct board_info *bi)
1607 {
1608         static bool parsed = 0;
1609
1610         if (!parsed) {
1611                 int ret;
1612                 parsed = 1;
1613
1614                 ret = tegra_get_board_info_properties(bi, "button-board");
1615                 if (!ret)
1616                         memcpy(&button_board_info, bi, sizeof(*bi));
1617         }
1618         memcpy(bi, &button_board_info, sizeof(struct board_info));
1619 }
1620
1621 void tegra_get_io_board_info(struct board_info *bi)
1622 {
1623         static bool parsed = 0;
1624
1625         if (!parsed) {
1626                 int ret;
1627                 parsed = 1;
1628
1629                 ret = tegra_get_board_info_properties(bi, "io-board");
1630                 if (!ret)
1631                         memcpy(&io_board_info, bi, sizeof(*bi));
1632         }
1633         memcpy(bi, &io_board_info, sizeof(struct board_info));
1634 }
1635
1636 static int __init tegra_modem_id(char *id)
1637 {
1638         char *p = id;
1639
1640         modem_id = memparse(p, &p);
1641         return 1;
1642 }
1643
1644 int tegra_get_modem_id(void)
1645 {
1646         return modem_id;
1647 }
1648 EXPORT_SYMBOL(tegra_get_modem_id);
1649
1650 __setup("modem_id=", tegra_modem_id);
1651
1652 static int __init tegra_usb_port_owner_info(char *id)
1653 {
1654         char *p = id;
1655
1656         usb_port_owner_info = memparse(p, &p);
1657         return 1;
1658 }
1659
1660 int tegra_get_usb_port_owner_info(void)
1661 {
1662         return usb_port_owner_info;
1663 }
1664 EXPORT_SYMBOL(tegra_get_usb_port_owner_info);
1665
1666 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1667
1668 static int __init tegra_lane_owner_info(char *id)
1669 {
1670         char *p = id;
1671
1672         lane_owner_info = memparse(p, &p);
1673         return 1;
1674 }
1675
1676 int tegra_get_lane_owner_info(void)
1677 {
1678         return lane_owner_info;
1679 }
1680 EXPORT_SYMBOL(tegra_get_lane_owner_info);
1681
1682 __setup("lane_owner_info=", tegra_lane_owner_info);
1683
1684 static int __init tegra_commchip_id(char *id)
1685 {
1686         char *p = id;
1687
1688         if (get_option(&p, &commchip_id) != 1)
1689                 return 0;
1690         return 1;
1691 }
1692
1693 int tegra_get_commchip_id(void)
1694 {
1695         return commchip_id;
1696 }
1697
1698 __setup("commchip_id=", tegra_commchip_id);
1699
1700 #ifdef CONFIG_ANDROID
1701 static bool androidboot_mode_charger;
1702
1703 bool get_androidboot_mode_charger(void)
1704 {
1705         return androidboot_mode_charger;
1706 }
1707 static int __init tegra_androidboot_mode(char *options)
1708 {
1709         if (!strcmp(options, "charger"))
1710                 androidboot_mode_charger = true;
1711         else
1712                 androidboot_mode_charger = false;
1713         return 1;
1714 }
1715 __setup("androidboot.mode=", tegra_androidboot_mode);
1716 #endif
1717
1718 /*
1719  * Tegra has a protected aperture that prevents access by most non-CPU
1720  * memory masters to addresses above the aperture value.  Enabling it
1721  * secures the CPU's memory from the GPU, except through the GART.
1722  */
1723 void __init tegra_protected_aperture_init(unsigned long aperture)
1724 {
1725         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1726         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1727         writel(aperture, mc_base + MC_SECURITY_CFG2);
1728 }
1729
1730 /*
1731  * Due to conflicting restrictions on the placement of the framebuffer,
1732  * the bootloader is likely to leave the framebuffer pointed at a location
1733  * in memory that is outside the grhost aperture.  This function will move
1734  * the framebuffer contents from a physical address that is anywhere (lowmem,
1735  * highmem, or outside the memory map) to a physical address that is outside
1736  * the memory map.
1737  */
1738 void __tegra_move_framebuffer(struct platform_device *pdev,
1739         phys_addr_t to, phys_addr_t from,
1740         size_t size)
1741 {
1742         struct page *page;
1743         void __iomem *to_io;
1744         void *from_virt;
1745         unsigned long i;
1746
1747         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1748         BUG_ON(PAGE_ALIGN(from) != from);
1749         BUG_ON(PAGE_ALIGN(size) != size);
1750
1751         to_io = ioremap_wc(to, size);
1752         if (!to_io) {
1753                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1754                 return;
1755         }
1756
1757         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1758                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1759                         page = phys_to_page(from + i);
1760                         from_virt = kmap(page);
1761                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1762                         kunmap(page);
1763                 }
1764         } else if (from) {
1765                 void __iomem *from_io = ioremap_wc(from, size);
1766                 if (!from_io) {
1767                         pr_err("%s: Failed to map source framebuffer\n",
1768                                 __func__);
1769                         goto out;
1770                 }
1771
1772                 for (i = 0; i < size; i += 4)
1773                         writel_relaxed(readl_relaxed(from_io + i), to_io + i);
1774                 dmb();
1775
1776                 iounmap(from_io);
1777         }
1778
1779 out:
1780         iounmap(to_io);
1781 }
1782
1783 void __tegra_clear_framebuffer(struct platform_device *pdev,
1784                                unsigned long to, unsigned long size)
1785 {
1786         void __iomem *to_io;
1787         unsigned long i;
1788
1789         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1790         BUG_ON(PAGE_ALIGN(size) != size);
1791
1792         to_io = ioremap_wc(to, size);
1793         if (!to_io) {
1794                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1795                 return;
1796         }
1797
1798         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1799                 for (i = 0 ; i < size; i += PAGE_SIZE)
1800                         memset(to_io + i, 0, PAGE_SIZE);
1801         } else {
1802                 for (i = 0; i < size; i += 4)
1803                         writel_relaxed(0, to_io + i);
1804                 dmb();
1805         }
1806
1807         iounmap(to_io);
1808 }
1809
1810 #ifdef CONFIG_PSTORE_RAM
1811 static struct ramoops_platform_data ramoops_data;
1812
1813 static struct platform_device ramoops_dev  = {
1814         .name = "ramoops",
1815         .dev = {
1816                 .platform_data = &ramoops_data,
1817         },
1818 };
1819
1820
1821 static void __init tegra_reserve_ramoops_memory(unsigned long reserve_size)
1822 {
1823         ramoops_data.mem_size = reserve_size;
1824 #ifndef CONFIG_ANDROID
1825         /* Uboot touches non carved out memory during reboot. But for this
1826          * feature to work, memory should not be overwritten by bootloader
1827          * (cboot/u-boot). L4T does not uses NCT carveout region. So, have
1828          * repurposed this carveout memory for pstore
1829          */
1830 #define RAMOOPS_CARVEOUT_START 0xff03f000
1831         ramoops_data.mem_address = RAMOOPS_CARVEOUT_START;
1832 #else
1833         ramoops_data.mem_address = memblock_end_of_4G() - reserve_size;
1834 #endif
1835         ramoops_data.record_size = RECORD_MEM_SIZE;
1836 #ifdef CONFIG_PSTORE_CONSOLE
1837         ramoops_data.console_size = CONSOLE_MEM_SIZE;
1838 #endif
1839 #ifdef CONFIG_PSTORE_FTRACE
1840         ramoops_data.ftrace_size = FTRACE_MEM_SIZE;
1841 #endif
1842 #ifdef CONFIG_PSTORE_RTRACE
1843         ramoops_data.rtrace_size = RTRACE_MEM_SIZE;
1844 #endif
1845         ramoops_data.dump_oops = 1;
1846         if (memblock_remove(ramoops_data.mem_address, ramoops_data.mem_size))
1847                 pr_err("Failed to remove carveout %08lx@%08llx from memory map\n",
1848                         reserve_size, (u64)ramoops_data.mem_address);
1849 }
1850
1851 static int __init tegra_register_ramoops_device(void)
1852 {
1853         int ret = platform_device_register(&ramoops_dev);
1854         if (ret) {
1855                 pr_info("Unable to register ramoops platform device\n");
1856                 return ret;
1857         }
1858         return ret;
1859 }
1860 core_initcall(tegra_register_ramoops_device);
1861 #endif
1862
1863 phys_addr_t __init tegra_reserve_adsp(unsigned long size)
1864 {
1865         phys_addr_t reserve = memblock_end_of_4G() - size;
1866         if (memblock_remove(reserve, size)) {
1867                 pr_err("%s failed for %llx:%lx\n",
1868                                 __func__, (u64)reserve, size);
1869         }
1870         pr_info("%s: reserved %llx:%lx\n",
1871                                 __func__, (u64)reserve, size);
1872         return reserve;
1873 }
1874
1875 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1876         unsigned long fb2_size)
1877 {
1878         struct iommu_linear_map map[4];
1879
1880         if (!tegra_vpr_resize && carveout_size) {
1881                 /*
1882                  * Place the carveout below the 4 GB physical address limit
1883                  * because IOVAs are only 32 bit wide.
1884                  */
1885                 BUG_ON(memblock_end_of_4G() == 0);
1886                 tegra_carveout_start = memblock_end_of_4G() - carveout_size;
1887                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1888                         pr_err("Failed to remove carveout %08lx@%08llx "
1889                                 "from memory map\n",
1890                                 carveout_size, (u64)tegra_carveout_start);
1891                         tegra_carveout_start = 0;
1892                         tegra_carveout_size = 0;
1893                 } else
1894                         tegra_carveout_size = carveout_size;
1895         }
1896
1897         if (fb2_size) {
1898 #ifdef CONFIG_MODS
1899                 if (fb2_size < (70 * SZ_1M))
1900                         fb2_size = 70 * SZ_1M;
1901 #endif
1902                 /*
1903                  * Place fb2 below the 4 GB physical address limit because
1904                  * IOVAs are only 32 bit wide.
1905                  */
1906                 BUG_ON(memblock_end_of_4G() == 0);
1907                 tegra_fb2_start = memblock_end_of_4G() - fb2_size;
1908                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1909                         pr_err("Failed to remove second framebuffer "
1910                                 "%08lx@%08llx from memory map\n",
1911                                 fb2_size, (u64)tegra_fb2_start);
1912                         tegra_fb2_start = 0;
1913                         tegra_fb2_size = 0;
1914                 } else
1915                         tegra_fb2_size = fb2_size;
1916         }
1917
1918         if (fb_size) {
1919 #ifdef CONFIG_MODS
1920                 if (fb_size < (70 * SZ_1M))
1921                         fb_size = 70 * SZ_1M;
1922 #endif
1923                 /*
1924                  * Place fb below the 4 GB physical address limit because
1925                  * IOVAs are only 32 bit wide.
1926                  */
1927                 BUG_ON(memblock_end_of_4G() == 0);
1928                 tegra_fb_start = memblock_end_of_4G() - fb_size;
1929                 if (memblock_remove(tegra_fb_start, fb_size)) {
1930                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1931                                 "from memory map\n",
1932                                 fb_size, (u64)tegra_fb_start);
1933                         tegra_fb_start = 0;
1934                         tegra_fb_size = 0;
1935                 } else
1936                         tegra_fb_size = fb_size;
1937         }
1938
1939         if (tegra_split_mem_active()) {
1940                 tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1941                 tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1942
1943                 if (tegra_vpr_size == 0) {
1944                         tegra_carveout_start =
1945                            TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1946                         tegra_carveout_size =
1947                            TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1948                 } else if (
1949                             (tegra_vpr_start <
1950                              TEGRA_ASIM_QT_FB_START +
1951                              TEGRA_ASIM_QT_FB_SIZE) ||
1952                              (tegra_vpr_start + tegra_vpr_size - 1 >
1953                              TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1954                              TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1955                         /*
1956                          * On ASIM/ASIM + QT with
1957                          * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1958                          * the VPR region needs to be within the front
1959                          * door memory region. Moreover, the VPR region
1960                          * can't exist where the framebuffer resides.
1961                          */
1962                         BUG();
1963                 } else if (
1964                                 (tegra_vpr_start -
1965                                  (TEGRA_ASIM_QT_FB_START +
1966                                   TEGRA_ASIM_QT_FB_SIZE) <
1967                                  TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1968                                 (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1969                                  TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1970                                  (tegra_vpr_start + tegra_vpr_size) <
1971                                  TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1972                         /*
1973                          * The tegra ASIM/QT carveout has a min size:-
1974                          * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1975                          * regions in front door mem are smaller than
1976                          * the min carveout size. Therefore, we can't
1977                          * fit the carveout in front door mem.
1978                          */
1979                         BUG();
1980                 } else if (
1981                                 (tegra_vpr_start -
1982                                  (TEGRA_ASIM_QT_FB_START +
1983                                   TEGRA_ASIM_QT_FB_SIZE)) >=
1984                                 (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1985                                  TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1986                                  (tegra_vpr_start + tegra_vpr_size))) {
1987                         /*
1988                          * Place the tegra ASIM/QT carveout between the
1989                          * framebuffer and VPR.
1990                          */
1991                         tegra_carveout_start =
1992                           TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1993                         tegra_carveout_size = tegra_vpr_start -
1994                                 (TEGRA_ASIM_QT_FB_START +
1995                                  TEGRA_ASIM_QT_FB_SIZE);
1996                 } else {
1997                         /*
1998                          * Place the tegra ASIM/QT carveout after VPR.
1999                          */
2000                         tegra_carveout_start = tegra_vpr_start +
2001                                                  tegra_vpr_size;
2002                         tegra_carveout_size =
2003                                 TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
2004                                 TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
2005                                 (tegra_vpr_start + tegra_vpr_size);
2006                 }
2007         }
2008
2009         if (tegra_fb_size)
2010                 tegra_grhost_aperture = tegra_fb_start;
2011
2012         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
2013                 tegra_grhost_aperture = tegra_fb2_start;
2014
2015         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
2016                 tegra_grhost_aperture = tegra_carveout_start;
2017
2018         if (tegra_lp0_vec_size &&
2019            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
2020                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
2021                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
2022                                 (u64)tegra_lp0_vec_size,
2023                                 (u64)tegra_lp0_vec_start);
2024                         tegra_lp0_vec_start = 0;
2025                         tegra_lp0_vec_size = 0;
2026                 }
2027                 tegra_lp0_vec_relocate = false;
2028         } else
2029                 tegra_lp0_vec_relocate = true;
2030
2031         if (tegra_bl_debug_data_size &&
2032                 (tegra_bl_debug_data_start < memblock_end_of_DRAM())) {
2033                 if (memblock_reserve(tegra_bl_debug_data_start, tegra_bl_debug_data_size)) {
2034                         pr_err("Failed to reserve bl_debug_data %08llx@%08llx\n",
2035                                 (u64)tegra_bl_debug_data_size,
2036                                 (u64)tegra_bl_debug_data_start);
2037                         tegra_bl_debug_data_start = 0;
2038                         tegra_bl_debug_data_size = 0;
2039                 }
2040         } else if (tegra_bl_debug_data_size) {
2041                 unsigned char *reloc_bl_debug_data;
2042                 unsigned long tmp;
2043                 void __iomem *orig;
2044                 reloc_bl_debug_data = kmalloc(tegra_bl_debug_data_size + L1_CACHE_BYTES - 1,
2045                                 GFP_KERNEL);
2046                 WARN_ON(!reloc_bl_debug_data);
2047                 if (!reloc_bl_debug_data) {
2048                         pr_err("%s: Failed to allocate reloc_bl_debug_data\n",
2049                                 __func__);
2050                         goto out;
2051                 }
2052
2053                 orig = ioremap(tegra_bl_debug_data_start, tegra_bl_debug_data_size);
2054                 WARN_ON(!orig);
2055                 if (!orig) {
2056                         pr_err("%s: Failed to map tegra_bl_debug_data_start %08x\n",
2057                                 __func__, (unsigned int) tegra_bl_debug_data_start);
2058                         kfree(reloc_bl_debug_data);
2059                         goto out;
2060                 }
2061
2062                 tmp = (unsigned long) reloc_bl_debug_data;
2063                 tmp = (tmp + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1);
2064                 reloc_bl_debug_data = (unsigned char *)tmp;
2065                 memcpy(reloc_bl_debug_data, orig, tegra_bl_debug_data_size);
2066                 iounmap(orig);
2067                 tegra_bl_debug_data_start = virt_to_phys(reloc_bl_debug_data);
2068         }
2069
2070 out:
2071         if (tegra_bl_prof_size &&
2072                 tegra_bl_prof_start) {
2073                 if (memblock_reserve(tegra_bl_prof_start, tegra_bl_prof_size)) {
2074                         pr_err("Failed to reserve bl_prof %08llx@%08llx\n",
2075                                 (u64)tegra_bl_prof_size,
2076                                 (u64)tegra_bl_prof_start);
2077                                 tegra_bl_prof_start = 0;
2078                                 tegra_bl_prof_size = 0;
2079                 }
2080         }
2081
2082 #ifdef CONFIG_TEGRA_NVDUMPER
2083         if (nvdumper_reserved) {
2084                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
2085                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
2086                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
2087                         nvdumper_reserved = 0;
2088                 }
2089         }
2090 #endif
2091
2092 #ifdef CONFIG_TEGRA_USE_NCT
2093         if (tegra_nck_size &&
2094            (tegra_nck_start < memblock_end_of_DRAM())) {
2095                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
2096                         pr_err("Failed to reserve nck %08lx@%08lx\n",
2097                                 tegra_nck_size, tegra_nck_start);
2098                         tegra_nck_start = 0;
2099                         tegra_nck_size = 0;
2100                 }
2101         }
2102 #endif
2103
2104         /*
2105          * We copy the bootloader's framebuffer to the framebuffer allocated
2106          * above, and then free this one.
2107          * */
2108         if (tegra_bootloader_fb_size) {
2109                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2110                 if (memblock_reserve(tegra_bootloader_fb_start,
2111                                 tegra_bootloader_fb_size)) {
2112                         pr_err("Failed to reserve bootloader frame buffer "
2113                                 "%08llx@%08llx\n",
2114                                 (u64)tegra_bootloader_fb_size,
2115                                 (u64)tegra_bootloader_fb_start);
2116                         tegra_bootloader_fb_start = 0;
2117                         tegra_bootloader_fb_size = 0;
2118                 }
2119         }
2120
2121         if (tegra_bootloader_fb2_size) {
2122                 tegra_bootloader_fb2_size =
2123                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2124                 if (memblock_reserve(tegra_bootloader_fb2_start,
2125                                 tegra_bootloader_fb2_size)) {
2126                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2127                                 (u64)tegra_bootloader_fb2_size,
2128                                 (u64)tegra_bootloader_fb2_start);
2129                         tegra_bootloader_fb2_start = 0;
2130                         tegra_bootloader_fb2_size = 0;
2131                 }
2132         }
2133
2134         pr_info("Tegra reserved memory:\n"
2135                 "LP0:                    %08llx - %08llx\n"
2136                 "Bootloader framebuffer: %08llx - %08llx\n"
2137                 "Bootloader framebuffer2: %08llx - %08llx\n"
2138                 "Framebuffer:            %08llx - %08llx\n"
2139                 "2nd Framebuffer:        %08llx - %08llx\n"
2140                 "Carveout:               %08llx - %08llx\n"
2141                 "Vpr:                    %08llx - %08llx\n"
2142                 "Tsec:                   %08llx - %08llx\n"
2143 #ifdef CONFIG_TEGRA_BOOTLOADER_DEBUG
2144                 "Bootloader Debug Data:  %08llx - %08llx\n"
2145 #endif
2146                 ,
2147                 (u64)tegra_lp0_vec_start,
2148                 (u64)(tegra_lp0_vec_size ?
2149                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2150                 (u64)tegra_bootloader_fb_start,
2151                 (u64)(tegra_bootloader_fb_size ?
2152                         tegra_bootloader_fb_start +
2153                         tegra_bootloader_fb_size - 1 : 0),
2154                 (u64)tegra_bootloader_fb2_start,
2155                 (u64)(tegra_bootloader_fb2_size ?
2156                         tegra_bootloader_fb2_start +
2157                         tegra_bootloader_fb2_size - 1 : 0),
2158                 (u64)tegra_fb_start,
2159                 (u64)(tegra_fb_size ?
2160                         tegra_fb_start + tegra_fb_size - 1 : 0),
2161                 (u64)tegra_fb2_start,
2162                 (u64)(tegra_fb2_size ?
2163                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2164                 (u64)tegra_carveout_start,
2165                 (u64)(tegra_carveout_size ?
2166                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2167                 (u64)tegra_vpr_start,
2168                 (u64)(tegra_vpr_size ?
2169                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2170                 (u64)tegra_tsec_start,
2171                 (u64)(tegra_tsec_size ?
2172                         tegra_tsec_start + tegra_tsec_size - 1 : 0)
2173 #ifdef CONFIG_TEGRA_BOOTLOADER_DEBUG
2174                 ,
2175                 (u64)(tegra_bl_debug_data_start),
2176                 (u64)(tegra_bl_debug_data_size ?
2177                         tegra_bl_debug_data_start + tegra_bl_debug_data_size - 1 : 0)
2178 #endif
2179                 );
2180
2181 #ifdef CONFIG_TEGRA_NVDUMPER
2182         if (nvdumper_reserved) {
2183                 pr_info("Nvdumper:               %08lx - %08lx\n",
2184                         nvdumper_reserved,
2185                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2186         }
2187 #endif
2188
2189 #ifdef CONFIG_TEGRA_USE_NCT
2190         if (tegra_nck_size) {
2191                 pr_info("Nck:                    %08lx - %08lx\n",
2192                         tegra_nck_start,
2193                         tegra_nck_size ?
2194                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2195         }
2196 #endif
2197
2198 #ifdef CONFIG_PSTORE_RAM
2199         tegra_reserve_ramoops_memory(RAMOOPS_MEM_SIZE);
2200 #endif
2201
2202         /* Keep these at the end */
2203         if (tegra_vpr_resize && carveout_size &&
2204             !dev_get_cma_area(&tegra_generic_cma_dev)) {
2205                 if (dma_declare_contiguous(&tegra_generic_cma_dev,
2206                         carveout_size, 0, memblock_end_of_4G()))
2207                         pr_err("dma_declare_contiguous failed for generic\n");
2208                 tegra_carveout_size = carveout_size;
2209         }
2210
2211         if (tegra_vpr_resize && tegra_vpr_size &&
2212             !dev_get_cma_area(&tegra_vpr_cma_dev))
2213                 if (dma_declare_contiguous(&tegra_vpr_cma_dev,
2214                         tegra_vpr_size, 0, memblock_end_of_4G()))
2215                         pr_err("dma_declare_contiguous failed VPR carveout\n");
2216
2217         tegra_fb_linear_set(map);
2218 }
2219
2220 void tegra_reserve4(ulong carveout_size, ulong fb_size,
2221                        ulong fb2_size, ulong vpr_size)
2222 {
2223         if (tegra_vpr_resize) {
2224                 tegra_vpr_start = 0;
2225                 tegra_vpr_size = vpr_size;
2226         }
2227         tegra_reserve(carveout_size, fb_size, fb2_size);
2228 }
2229
2230 void tegra_get_fb_resource(struct resource *fb_res)
2231 {
2232         fb_res->start = (resource_size_t) tegra_bootloader_fb_start;
2233         fb_res->end = fb_res->start +
2234                         (resource_size_t) tegra_bootloader_fb_size - 1;
2235 }
2236
2237 void tegra_get_fb2_resource(struct resource *fb2_res)
2238 {
2239         fb2_res->start = (resource_size_t) tegra_bootloader_fb2_start;
2240         fb2_res->end = fb2_res->start +
2241                         (resource_size_t) tegra_bootloader_fb2_size - 1;
2242 }
2243
2244
2245
2246 int __init tegra_register_fuse(void)
2247 {
2248         return platform_device_register(&tegra_fuse_device);
2249 }
2250
2251 int __init tegra_release_bootloader_fb(void)
2252 {
2253         /* Since bootloader fb is reserved in common.c, it is freed here. */
2254         if (tegra_bootloader_fb_size) {
2255                 if (memblock_free(tegra_bootloader_fb_start,
2256                                                 tegra_bootloader_fb_size))
2257                         pr_err("Failed to free bootloader fb.\n");
2258                 else
2259                         free_bootmem_late(tegra_bootloader_fb_start,
2260                                                 tegra_bootloader_fb_size);
2261         }
2262         if (tegra_bootloader_fb2_size) {
2263                 if (memblock_free(tegra_bootloader_fb2_start,
2264                                                 tegra_bootloader_fb2_size))
2265                         pr_err("Failed to free bootloader fb2.\n");
2266                 else
2267                         free_bootmem_late(tegra_bootloader_fb2_start,
2268                                                 tegra_bootloader_fb2_size);
2269         }
2270         return 0;
2271 }
2272 late_initcall(tegra_release_bootloader_fb);
2273
2274 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2275         [TEGRA_REVISION_UNKNOWN] = "unknown",
2276         [TEGRA_REVISION_A01]     = "A01",
2277         [TEGRA_REVISION_A01q]    = "A01Q",
2278         [TEGRA_REVISION_A02]     = "A02",
2279         [TEGRA_REVISION_A03]     = "A03",
2280         [TEGRA_REVISION_A03p]    = "A03 prime",
2281         [TEGRA_REVISION_A04]     = "A04",
2282         [TEGRA_REVISION_A04p]    = "A04 prime",
2283 };
2284
2285 static const char * __init tegra_get_revision(void)
2286 {
2287         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2288 }
2289
2290 static const char * __init tegra_get_family(void)
2291 {
2292         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2293         u32 cid = readl(chip_id);
2294         cid = (cid >> 8) & 0xFF;
2295
2296         switch (cid) {
2297         case TEGRA_CHIPID_TEGRA2:
2298                 cid = 2;
2299                 break;
2300         case TEGRA_CHIPID_TEGRA3:
2301                 cid = 3;
2302                 break;
2303         case TEGRA_CHIPID_TEGRA11:
2304                 cid = 11;
2305                 break;
2306         case TEGRA_CHIPID_TEGRA12:
2307                 cid = 12;
2308                 break;
2309         case TEGRA_CHIPID_TEGRA13:
2310                 cid = 13;
2311                 break;
2312         case TEGRA_CHIPID_TEGRA14:
2313                 cid = 14;
2314                 break;
2315         case TEGRA_CHIPID_TEGRA21:
2316                 cid = 21;
2317                 break;
2318
2319         case TEGRA_CHIPID_UNKNOWN:
2320         default:
2321                 cid = 0;
2322         }
2323         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2324 }
2325
2326 static const char * __init tegra_get_soc_id(void)
2327 {
2328         int package_id = tegra_package_id();
2329
2330         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2331                 tegra_revision_name[tegra_revision],
2332                 tegra_get_sku_id(), package_id);
2333 }
2334
2335 static void __init tegra_soc_info_populate(struct soc_device_attribute
2336         *soc_dev_attr, const char *machine)
2337 {
2338         soc_dev_attr->soc_id = tegra_get_soc_id();
2339         soc_dev_attr->machine  = machine;
2340         soc_dev_attr->family   = tegra_get_family();
2341         soc_dev_attr->revision = tegra_get_revision();
2342 }
2343
2344 int __init tegra_soc_device_init(const char *machine)
2345 {
2346         struct soc_device *soc_dev;
2347         struct soc_device_attribute *soc_dev_attr;
2348
2349         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2350         if (!soc_dev_attr)
2351                 return -ENOMEM;
2352
2353         tegra_soc_info_populate(soc_dev_attr, machine);
2354
2355         soc_dev = soc_device_register(soc_dev_attr);
2356         if (IS_ERR_OR_NULL(soc_dev)) {
2357                 kfree(soc_dev_attr);
2358                 return -1;
2359         }
2360
2361         return 0;
2362 }
2363
2364 void __init tegra_init_late(void)
2365 {
2366 #ifndef CONFIG_COMMON_CLK
2367         tegra_clk_debugfs_init();
2368 #endif
2369         tegra_powergate_debugfs_init();
2370 }
2371
2372 int tegra_split_mem_active(void)
2373 {
2374         return tegra_split_mem_set;
2375 }
2376
2377 static int __init set_tegra_split_mem(char *options)
2378 {
2379         tegra_split_mem_set = 1;
2380         return 0;
2381 }
2382 early_param("tegra_split_mem", set_tegra_split_mem);
2383
2384 unsigned long int tegra_dfll_boot_req_khz(void)
2385 {
2386         return dfll_boot_req_khz;
2387 }
2388
2389 static int __init dfll_freq_cmd_line(char *line)
2390 {
2391         int status = kstrtoul(line, 0, &dfll_boot_req_khz);
2392         if (status) {
2393                 pr_err("\n%s:Error in parsing dfll_boot_req_khz:%d\n",
2394                         __func__, status);
2395                 dfll_boot_req_khz = 0;
2396         }
2397         return status;
2398 }
2399 early_param("dfll_boot_req_khz", dfll_freq_cmd_line);
2400
2401 void __init display_tegra_dt_info(void)
2402 {
2403         int ret_d;
2404         int ret_t;
2405         unsigned long dt_root;
2406         const char *dts_fname;
2407         const char *dtb_bdate;
2408         const char *dtb_btime;
2409
2410         dt_root = of_get_flat_dt_root();
2411
2412         dts_fname = of_get_flat_dt_prop(dt_root, "nvidia,dtsfilename", NULL);
2413         if (dts_fname)
2414                 pr_info("DTS File Name: %s\n", dts_fname);
2415         else
2416                 pr_info("DTS File Name: <unknown>\n");
2417
2418         ret_d = of_property_read_string_index(of_find_node_by_path("/"),
2419                         "nvidia,dtbbuildtime", 0, &dtb_bdate);
2420         ret_t = of_property_read_string_index(of_find_node_by_path("/"),
2421                         "nvidia,dtbbuildtime", 1, &dtb_btime);
2422         if (!ret_d && !ret_t)
2423                 pr_info("DTB Build time: %s %s\n", dtb_bdate, dtb_btime);
2424         else
2425                 pr_info("DTB Build time: <unknown>\n");
2426 }
2427
2428 static void tegra_get_bl_reset_status(void)
2429 {
2430         struct device_node *reset_info;
2431         u32 prop_val;
2432         int err;
2433
2434         reset_info = of_find_node_by_path("/chosen/reset");
2435         if (reset_info) {
2436                 err = of_property_read_u32(reset_info, "pmc_reset_status",
2437                                 &prop_val);
2438                 if (err < 0)
2439                         goto out;
2440                 else
2441                         pr_info("BL: PMC reset status reg: 0x%x\n",
2442                                         prop_val);
2443
2444                 err = of_property_read_u32(reset_info, "pmic_reset_status",
2445                                 &prop_val);
2446                 if (err < 0)
2447                         goto out;
2448                 else
2449                         pr_info("BL: PMIC poweroff Event Recorder: 0x%x\n",
2450                                         prop_val);
2451         }
2452 out:
2453         return;
2454 }
2455
2456 static int __init tegra_get_last_reset_reason(void)
2457 {
2458 #define PMC_RST_STATUS 0x1b4
2459 #define RESET_STR(REASON) "last reset is due to "#REASON"\n"
2460         char *reset_reason[] = {
2461                 RESET_STR(power on reset),
2462                 RESET_STR(tegra watchdog timeout),
2463                 RESET_STR(sensor),
2464                 RESET_STR(software reset),
2465                 RESET_STR(deep sleep reset),
2466                 RESET_STR(pmic watchdog timeout),
2467         };
2468         /* read PMC_SCRATCH203, if last reset due to pmic watchdog, stored by
2469          * nvtboot
2470          */
2471         u32 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_SCRATCH203);
2472         if (val & 0x2)
2473                 /* reset-reason due to pmic watchdog, set val to index of array
2474                  * reset_reason so that it points to "pmic watchdog timeout"
2475                  */
2476                 val = 5;
2477         else
2478                 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_RST_STATUS) & 0x7;
2479
2480         if (val >= ARRAY_SIZE(reset_reason))
2481                 pr_info("last reset value is invalid 0x%x\n", val);
2482         else {
2483                 pr_info("%s\n", reset_reason[val]);
2484                 pr_info("KERNEL: PMC reset status reg: 0x%x\n", val);
2485         }
2486
2487         tegra_get_bl_reset_status();
2488         return 0;
2489 }
2490 late_initcall(tegra_get_last_reset_reason);