drivers/i2c/busses/i2c-tegra-vi.c

   1 /*
   2  * drivers/i2c/busses/vii2c-tegra.c
   3  *
   4  * Copyright (C) 2014-2015 NVIDIA Corporation.  All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <linux/i2c.h>
  23 #include <linux/i2c-algo-bit.h>
  24 #include <linux/i2c-gpio.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/gpio.h>
  28 #include <linux/delay.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/slab.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_i2c.h>
  35 #include <linux/module.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/clk/tegra.h>
  39 #include <linux/tegra-pm.h>
  40 #include <linux/pinctrl/consumer.h>
  41 #include <linux/regulator/consumer.h>
  42 #include <linux/tegra-powergate.h>
  43
  44 #include <asm/unaligned.h>
  45
  46 #define TEGRA_I2C_TIMEOUT                       (msecs_to_jiffies(1000))
  47 #define TEGRA_I2C_RETRIES                       3
  48 #define BYTES_PER_FIFO_WORD                     4
  49
  50 /* vi i2c specific registers and bit masks */
  51 #define I2C_CNFG                                (0x300 << 2)
  52 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  53 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  54 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  55 #define I2C_CNFG_NOACK                          (1<<8)
  56 #define I2C_STATUS                              (0x31C << 2)
  57 #define I2C_STATUS_BUSY                         (1<<8)
  58 #define I2C_TLOW_SEXT                           (0x334 << 2)
  59 #define I2C_TX_FIFO                             (0x350 << 2)
  60 #define I2C_RX_FIFO                             (0x354 << 2)
  61 #define I2C_PACKET_TRANSFER_STATUS              (0x358 << 2)
  62 #define I2C_FIFO_CONTROL                        (0x35C << 2)
  63 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  64 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  65 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  66 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  67 #define I2C_FIFO_STATUS                         (0x360 << 2)
  68 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  69 #define I2C_FIFO_STATUS_TX_SHIFT                4
  70 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  71 #define I2C_FIFO_STATUS_RX_SHIFT                0
  72 #define I2C_INT_MASK                            (0x364 << 2)
  73 #define I2C_INT_STATUS                          (0x368 << 2)
  74 #define I2C_INT_BUS_CLEAR_DONE                  (1<<11)
  75 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  76 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  77 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  78 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  79 #define I2C_INT_NO_ACK                          (1<<3)
  80 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  81 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  82 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  83
  84 #define I2C_CLK_DIVISOR                         (0x36C << 2)
  85 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  86 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  87
  88 #define I2C_ERR_NONE                            0x00
  89 #define I2C_ERR_NO_ACK                          0x01
  90 #define I2C_ERR_ARBITRATION_LOST                0x02
  91 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  92 #define I2C_ERR_UNEXPECTED_STATUS               0x08
  93
  94 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  95 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  96 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  97 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  98
  99 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
 100 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
 101 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
 102 #define I2C_HEADER_READ                         (1<<19)
 103 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
 104 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 105 #define I2C_HEADER_REPEAT_START                 (1<<16)
 106 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 107 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 108 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 109
 110 #define I2C_BUS_CLEAR_CNFG                      (0x384 << 2)
 111 #define I2C_BC_SCLK_THRESHOLD                   (9<<16)
 112 #define I2C_BC_STOP_COND                        (1<<2)
 113 #define I2C_BC_TERMINATE                        (1<<1)
 114 #define I2C_BC_ENABLE                           (1<<0)
 115
 116 #define I2C_BUS_CLEAR_STATUS                    (0x388 << 2)
 117 #define I2C_BC_STATUS                           (1<<0)
 118
 119 #define I2C_CONFIG_LOAD                         (0x38C << 2)
 120 #define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
 121 #define I2C_SLV_CONFIG_LOAD                     (1 << 1)
 122 #define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
 123
 124 #define I2C_INTERFACE_TIMING_0                  (0x394 << 2)
 125 #define I2C_TLOW                                4
 126 #define I2C_TLOW_SHIFT                          0
 127 #define I2C_THIGH                               2
 128 #define I2C_THIGH_SHIFT                         8
 129 #define I2C_INTERFACE_TIMING_1                  (0x398 << 2)
 130 #define I2C_HS_INTERFACE_TIMING_0               (0x39C << 2)
 131 #define I2C_HS_INTERFACE_TIMING_1               (0x3A0 << 2)
 132
 133 #define MAX_BUSCLEAR_CLOCK                      (9 * 8 + 1)
 134
 135 /*
 136  * msg_end_type: The bus control which need to be send at end of transfer.
 137  * @MSG_END_STOP: Send stop pulse at end of transfer.
 138  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 139  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 140  *              stop or repeat start.
 141  */
 142 enum msg_end_type {
 143         MSG_END_STOP,
 144         MSG_END_REPEAT_START,
 145         MSG_END_CONTINUE,
 146 };
 147
 148 struct tegra_vi_i2c_chipdata {
 149         bool timeout_irq_occurs_before_bus_inactive;
 150         bool has_xfer_complete_interrupt;
 151         bool has_hw_arb_support;
 152         bool has_fast_clock;
 153         bool has_clk_divisor_std_fast_mode;
 154         bool has_continue_xfer_support;
 155         u16 clk_divisor_std_fast_mode;
 156         u16 clk_divisor_fast_plus_mode;
 157         u16 clk_divisor_hs_mode;
 158         int clk_multiplier_hs_mode;
 159         bool has_config_load_reg;
 160 };
 161
 162 /**
 163  * struct tegra_vi_i2c_dev      - per device i2c context
 164  * @dev: device reference for power management
 165  * @adapter: core i2c layer adapter information
 166  * @div_clk: clock reference for div clock of i2c controller.
 167  * @fast_clk: clock reference for fast clock of i2c controller.
 168  * @base: ioremapped registers cookie
 169  * @cont_id: i2c controller id, used for for packet header
 170  * @irq: irq number of transfer complete interrupt
 171  * @msg_complete: transfer completion notifier
 172  * @msg_err: error code for completed message
 173  * @msg_buf: pointer to current message data
 174  * @msg_buf_remaining: size of unsent data in the message buffer
 175  * @msg_read: identifies read transfers
 176  * @bus_clk_rate: current i2c bus clock rate
 177  * @is_suspended: prevents i2c controller accesses after suspend is called
 178  */
 179 struct tegra_vi_i2c_dev {
 180         struct device *dev;
 181         struct i2c_adapter adapter;
 182         struct regulator *reg;
 183         struct clk *div_clk;
 184         struct clk *fast_clk;
 185         struct clk *slow_clk;
 186         struct clk *host1x_clk;
 187         bool needs_cl_dvfs_clock;
 188         struct clk *dvfs_ref_clk;
 189         struct clk *dvfs_soc_clk;
 190         spinlock_t fifo_lock;
 191         spinlock_t mem_lock;
 192         void __iomem *base;
 193         int cont_id;
 194         int irq;
 195         bool irq_disabled;
 196         struct completion msg_complete;
 197         int msg_err;
 198         int next_msg_err;
 199         u8 *msg_buf;
 200         u8 *next_msg_buf;
 201         u32 packet_header;
 202         u32 next_packet_header;
 203         u32 payload_size;
 204         u32 next_payload_size;
 205         u32 io_header;
 206         u32 next_io_header;
 207         size_t msg_buf_remaining;
 208         size_t next_msg_buf_remaining;
 209         int msg_read;
 210         int next_msg_read;
 211         struct i2c_msg *msgs;
 212         int msg_add;
 213         int next_msg_add;
 214         int msgs_num;
 215         unsigned long bus_clk_rate;
 216         bool is_suspended;
 217         u16 slave_addr;
 218         bool is_clkon_always;
 219         bool is_high_speed_enable;
 220         u16 hs_master_code;
 221         u16 clk_divisor_non_hs_mode;
 222         bool use_single_xfer_complete;
 223         const struct tegra_vi_i2c_chipdata *chipdata;
 224         int scl_gpio;
 225         int sda_gpio;
 226         struct i2c_algo_bit_data bit_data;
 227         const struct i2c_algorithm *bit_algo;
 228         bool bit_banging_xfer_after_shutdown;
 229         bool is_shutdown;
 230         struct notifier_block pm_nb;
 231         struct regulator *pull_up_supply;
 232 };
 233
 234 static void i2c_writel(struct tegra_vi_i2c_dev *i2c_dev, u32 val,
 235         unsigned long reg)
 236 {
 237         writel(val, i2c_dev->base + reg);
 238
 239         /* Read back register to make sure that register writes completed */
 240         if (reg != I2C_TX_FIFO)
 241                 readl(i2c_dev->base + reg);
 242 }
 243
 244 static u32 i2c_readl(struct tegra_vi_i2c_dev *i2c_dev, unsigned long reg)
 245 {
 246         return readl(i2c_dev->base + reg);
 247 }
 248
 249 static void i2c_writesl(struct tegra_vi_i2c_dev *i2c_dev, void *data,
 250         unsigned long reg, int len)
 251 {
 252         u32 *buf = data;
 253         unsigned long flags;
 254
 255         spin_lock_irqsave(&i2c_dev->mem_lock, flags);
 256         while (len--)
 257                 writel(*buf++, i2c_dev->base + reg);
 258         spin_unlock_irqrestore(&i2c_dev->mem_lock, flags);
 259 }
 260
 261 static void i2c_readsl(struct tegra_vi_i2c_dev *i2c_dev, void *data,
 262         unsigned long reg, int len)
 263 {
 264         u32 *buf = data;
 265         unsigned long flags;
 266
 267         spin_lock_irqsave(&i2c_dev->mem_lock, flags);
 268         while (len--)
 269                 *buf++ = readl(i2c_dev->base + reg);
 270         spin_unlock_irqrestore(&i2c_dev->mem_lock, flags);
 271 }
 272
 273 static inline void tegra_vi_i2c_gpio_setscl(void *data, int state)
 274 {
 275         struct tegra_vi_i2c_dev *i2c_dev = data;
 276
 277         gpio_set_value(i2c_dev->scl_gpio, state);
 278 }
 279
 280 static inline int tegra_vi_i2c_gpio_getscl(void *data)
 281 {
 282         struct tegra_vi_i2c_dev *i2c_dev = data;
 283
 284         return gpio_get_value(i2c_dev->scl_gpio);
 285 }
 286
 287 static inline void tegra_vi_i2c_gpio_setsda(void *data, int state)
 288 {
 289         struct tegra_vi_i2c_dev *i2c_dev = data;
 290
 291         gpio_set_value(i2c_dev->sda_gpio, state);
 292 }
 293
 294 static inline int tegra_vi_i2c_gpio_getsda(void *data)
 295 {
 296         struct tegra_vi_i2c_dev *i2c_dev = data;
 297
 298         return gpio_get_value(i2c_dev->sda_gpio);
 299 }
 300
 301 static int tegra_vi_i2c_gpio_request(struct tegra_vi_i2c_dev *i2c_dev)
 302 {
 303         int ret;
 304
 305         ret = gpio_request_one(i2c_dev->scl_gpio,
 306                                 GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN,
 307                                 "i2c-gpio-scl");
 308         if (ret < 0) {
 309                 dev_err(i2c_dev->dev, "GPIO request for gpio %d failed %d\n",
 310                                 i2c_dev->scl_gpio, ret);
 311                 return ret;
 312         }
 313
 314         ret = gpio_request_one(i2c_dev->sda_gpio,
 315                                 GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN,
 316                                 "i2c-gpio-sda");
 317         if (ret < 0) {
 318                 dev_err(i2c_dev->dev, "GPIO request for gpio %d failed %d\n",
 319                                 i2c_dev->sda_gpio, ret);
 320                 gpio_free(i2c_dev->scl_gpio);
 321                 return ret;
 322         }
 323         return ret;
 324 }
 325
 326 static void tegra_vi_i2c_gpio_free(struct tegra_vi_i2c_dev *i2c_dev)
 327 {
 328         gpio_free(i2c_dev->scl_gpio);
 329         gpio_free(i2c_dev->sda_gpio);
 330 }
 331
 332 static int tegra_vi_i2c_gpio_xfer(struct i2c_adapter *adap,
 333         struct i2c_msg msgs[], int num)
 334 {
 335         struct tegra_vi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 336         int ret;
 337
 338         ret = tegra_vi_i2c_gpio_request(i2c_dev);
 339         if (ret < 0)
 340                 return ret;
 341
 342         ret = i2c_dev->bit_algo->master_xfer(adap, msgs, num);
 343         if (ret < 0)
 344                 dev_err(i2c_dev->dev, "i2c-bit-algo xfer failed %d\n", ret);
 345
 346         tegra_vi_i2c_gpio_free(i2c_dev);
 347         return ret;
 348 }
 349
 350 static int tegra_vi_i2c_gpio_init(struct tegra_vi_i2c_dev *i2c_dev)
 351 {
 352         struct i2c_algo_bit_data *bit_data = &i2c_dev->bit_data;
 353
 354         bit_data->setsda = tegra_vi_i2c_gpio_setsda;
 355         bit_data->getsda = tegra_vi_i2c_gpio_getsda;
 356         bit_data->setscl = tegra_vi_i2c_gpio_setscl;
 357         bit_data->getscl = tegra_vi_i2c_gpio_getscl;
 358         bit_data->data = i2c_dev;
 359         bit_data->udelay = 20; /* 50KHz */
 360         bit_data->timeout = HZ; /* 10 ms*/
 361         i2c_dev->bit_algo = &i2c_bit_algo;
 362         i2c_dev->adapter.algo_data = bit_data;
 363         return 0;
 364 }
 365
 366 static void tegra_vi_i2c_mask_irq(struct tegra_vi_i2c_dev *i2c_dev, u32 mask)
 367 {
 368         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 369         int_mask &= ~mask;
 370         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 371 }
 372
 373 static void tegra_vi_i2c_unmask_irq(struct tegra_vi_i2c_dev *i2c_dev, u32 mask)
 374 {
 375         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 376         int_mask |= mask;
 377         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 378 }
 379
 380 static int tegra_vi_i2c_flush_fifos(struct tegra_vi_i2c_dev *i2c_dev)
 381 {
 382         unsigned long timeout = jiffies + HZ;
 383         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 384         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 385         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 386
 387         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 388                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 389                 if (time_after(jiffies, timeout)) {
 390                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 391                         return -ETIMEDOUT;
 392                 }
 393                 usleep_range(1000, 1100);
 394         }
 395         return 0;
 396 }
 397
 398 static int tegra_vi_i2c_empty_rx_fifo(struct tegra_vi_i2c_dev *i2c_dev)
 399 {
 400         u32 val;
 401         int rx_fifo_avail;
 402         u8 *buf = i2c_dev->msg_buf;
 403         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 404         int words_to_transfer;
 405
 406         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 407         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 408                 I2C_FIFO_STATUS_RX_SHIFT;
 409
 410         /* Rounds down to not include partial word at the end of buf */
 411         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 412         if (words_to_transfer > rx_fifo_avail)
 413                 words_to_transfer = rx_fifo_avail;
 414
 415         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 416
 417         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 418         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 419         rx_fifo_avail -= words_to_transfer;
 420
 421         /*
 422          * If there is a partial word at the end of buf, handle it manually to
 423          * prevent overwriting past the end of buf
 424          */
 425         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 426                 BUG_ON(buf_remaining > 3);
 427                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 428                 memcpy(buf, &val, buf_remaining);
 429                 buf_remaining = 0;
 430                 rx_fifo_avail--;
 431         }
 432
 433         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 434         i2c_dev->msg_buf_remaining = buf_remaining;
 435         i2c_dev->msg_buf = buf;
 436         return 0;
 437 }
 438
 439 static int tegra_vi_i2c_fill_tx_fifo(struct tegra_vi_i2c_dev *i2c_dev)
 440 {
 441         u32 val;
 442         int tx_fifo_avail;
 443         u8 *buf;
 444         size_t buf_remaining;
 445         int words_to_transfer;
 446
 447         if (!i2c_dev->msg_buf_remaining)
 448                 return 0;
 449         buf = i2c_dev->msg_buf;
 450         buf_remaining = i2c_dev->msg_buf_remaining;
 451
 452         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 453         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 454                 I2C_FIFO_STATUS_TX_SHIFT;
 455
 456         /* Rounds down to not include partial word at the end of buf */
 457         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 458
 459         /* It's very common to have < 4 bytes, so optimize that case. */
 460         if (words_to_transfer) {
 461                 if (words_to_transfer > tx_fifo_avail)
 462                         words_to_transfer = tx_fifo_avail;
 463
 464                 /*
 465                  * Update state before writing to FIFO.  If this casues us
 466                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 467                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 468                  * not maskable).  We need to make sure that the isr sees
 469                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 470                  */
 471                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 472                 tx_fifo_avail -= words_to_transfer;
 473                 i2c_dev->msg_buf_remaining = buf_remaining;
 474                 i2c_dev->msg_buf = buf +
 475                         words_to_transfer * BYTES_PER_FIFO_WORD;
 476                 barrier();
 477
 478                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 479
 480                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 481         }
 482
 483         /*
 484          * If there is a partial word at the end of buf, handle it manually to
 485          * prevent reading past the end of buf, which could cross a page
 486          * boundary and fault.
 487          */
 488         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 489                 if (buf_remaining > 3) {
 490                         dev_err(i2c_dev->dev,
 491                                 "Remaining buffer more than 3 %zd\n",
 492                                 buf_remaining);
 493                         BUG();
 494                 }
 495                 memcpy(&val, buf, buf_remaining);
 496
 497                 /* Again update before writing to FIFO to make sure isr sees. */
 498                 i2c_dev->msg_buf_remaining = 0;
 499                 i2c_dev->msg_buf = NULL;
 500                 barrier();
 501
 502                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 503         }
 504
 505         return 0;
 506 }
 507
 508 static inline int tegra_vi_i2c_power_enable(struct tegra_vi_i2c_dev *i2c_dev)
 509 {
 510         int ret;
 511
 512         if (i2c_dev->pull_up_supply) {
 513                 ret = regulator_enable(i2c_dev->pull_up_supply);
 514                 if (ret < 0) {
 515                         dev_err(i2c_dev->dev, "Pull up regulator supply failed: %d\n",
 516                                 ret);
 517                         return ret;
 518                 }
 519         }
 520
 521         ret = regulator_enable(i2c_dev->reg);
 522         if (ret)
 523                 return ret;
 524
 525         tegra_unpowergate_partition(TEGRA_POWERGATE_VE);
 526
 527         return 0;
 528 }
 529
 530 static inline int tegra_vi_i2c_power_disable(struct tegra_vi_i2c_dev *i2c_dev)
 531 {
 532         int ret = 0;
 533
 534         if (tegra_powergate_is_powered(TEGRA_POWERGATE_VE))
 535                 tegra_powergate_partition(TEGRA_POWERGATE_VE);
 536
 537         ret = regulator_disable(i2c_dev->reg);
 538         if (ret)
 539                 dev_err(i2c_dev->dev, "%s: regulator err\n", __func__);
 540
 541         if (i2c_dev->pull_up_supply) {
 542                 ret = regulator_disable(i2c_dev->pull_up_supply);
 543                 if (ret)
 544                         dev_err(i2c_dev->dev, "%s: pull_up_supply err\n",
 545                                         __func__);
 546         }
 547
 548         return ret;
 549 }
 550
 551 static int tegra_vi_i2c_clock_enable(struct tegra_vi_i2c_dev *i2c_dev)
 552 {
 553         int ret;
 554
 555         if (i2c_dev->chipdata->has_fast_clock) {
 556                 ret = clk_prepare_enable(i2c_dev->fast_clk);
 557                 if (ret < 0) {
 558                         dev_err(i2c_dev->dev,
 559                                 "Enabling fast clk failed, err %d\n", ret);
 560                         goto fast_clk_err;
 561                 }
 562         }
 563         ret = clk_prepare_enable(i2c_dev->div_clk);
 564         if (ret < 0) {
 565                 dev_err(i2c_dev->dev,
 566                         "Enabling div clk failed, err %d\n", ret);
 567                 goto div_clk_err;
 568         }
 569         ret = clk_prepare_enable(i2c_dev->slow_clk);
 570         if (ret < 0) {
 571                 dev_err(i2c_dev->dev,
 572                         "Enabling slow clk failed, err %d\n", ret);
 573                 goto slow_clk_err;
 574         }
 575         ret = clk_prepare_enable(i2c_dev->host1x_clk);
 576         if (ret < 0) {
 577                 dev_err(i2c_dev->dev,
 578                         "Enabling host1x clk failed, err %d\n", ret);
 579                 goto host1x_clk_err;
 580         }
 581         return 0;
 582
 583 host1x_clk_err:
 584         clk_disable_unprepare(i2c_dev->slow_clk);
 585 slow_clk_err:
 586         clk_disable_unprepare(i2c_dev->div_clk);
 587 div_clk_err:
 588         if (i2c_dev->chipdata->has_fast_clock)
 589                 clk_disable_unprepare(i2c_dev->fast_clk);
 590 fast_clk_err:
 591         return ret;
 592 }
 593
 594 static void tegra_vi_i2c_clock_disable(struct tegra_vi_i2c_dev *i2c_dev)
 595 {
 596         clk_disable_unprepare(i2c_dev->host1x_clk);
 597         clk_disable_unprepare(i2c_dev->slow_clk);
 598         clk_disable_unprepare(i2c_dev->div_clk);
 599         if (i2c_dev->chipdata->has_fast_clock)
 600                 clk_disable_unprepare(i2c_dev->fast_clk);
 601 }
 602
 603 static void tegra_vi_i2c_set_clk_rate(struct tegra_vi_i2c_dev *i2c_dev)
 604 {
 605         u32 clk_multiplier;
 606         if (i2c_dev->is_high_speed_enable)
 607                 clk_multiplier = i2c_dev->chipdata->clk_multiplier_hs_mode
 608                         * (i2c_dev->chipdata->clk_divisor_hs_mode + 1);
 609         else
 610                 clk_multiplier = (I2C_TLOW + I2C_THIGH + 3)
 611                         * (i2c_dev->clk_divisor_non_hs_mode + 1);
 612
 613         clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier);
 614         /* slow i2c clock is always 1M */
 615         clk_set_rate(i2c_dev->slow_clk, 1000000);
 616 }
 617
 618 static int tegra_vi_i2c_init(struct tegra_vi_i2c_dev *i2c_dev)
 619 {
 620         u32 val;
 621         int err = 0;
 622         u32 clk_divisor = 0;
 623         unsigned long timeout = jiffies + HZ;
 624
 625         if (!i2c_dev->reg || !regulator_is_enabled(i2c_dev->reg))
 626                 return -ENODEV;
 627
 628         tegra_periph_reset_assert(i2c_dev->div_clk);
 629         udelay(2);
 630         tegra_periph_reset_deassert(i2c_dev->div_clk);
 631
 632         val = I2C_CNFG_NEW_MASTER_FSM;
 633         if (!i2c_dev->is_high_speed_enable)
 634                 val |= (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 635
 636         i2c_writel(i2c_dev, val, I2C_CNFG);
 637         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 638         i2c_writel(i2c_dev, (I2C_TLOW << I2C_TLOW_SHIFT) |
 639                 (I2C_THIGH << I2C_THIGH_SHIFT), I2C_INTERFACE_TIMING_0);
 640         i2c_writel(i2c_dev, 0x04070404, I2C_INTERFACE_TIMING_1);
 641         i2c_writel(i2c_dev, 0x308, I2C_HS_INTERFACE_TIMING_0);
 642         i2c_writel(i2c_dev, 0x0B0B0B, I2C_HS_INTERFACE_TIMING_1);
 643         i2c_writel(i2c_dev, 0x90004, I2C_BUS_CLEAR_CNFG);
 644         i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 645
 646         tegra_vi_i2c_set_clk_rate(i2c_dev);
 647
 648         clk_divisor |= i2c_dev->chipdata->clk_divisor_hs_mode;
 649         if (i2c_dev->chipdata->has_clk_divisor_std_fast_mode)
 650                 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode
 651                                 << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 652         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 653
 654         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 655                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 656         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 657
 658         if (tegra_vi_i2c_flush_fifos(i2c_dev))
 659                 err = -ETIMEDOUT;
 660
 661         if (i2c_dev->chipdata->has_config_load_reg) {
 662                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 663                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 664                         if (time_after(jiffies, timeout)) {
 665                                 dev_warn(i2c_dev->dev, "timeout waiting for config load\n");
 666                                 return -ETIMEDOUT;
 667                         }
 668                         usleep_range(1000, 1100);
 669                 }
 670         }
 671
 672         if (i2c_dev->irq_disabled) {
 673                 i2c_dev->irq_disabled = 0;
 674                 enable_irq(i2c_dev->irq);
 675         }
 676
 677         return err;
 678 }
 679 static int tegra_vi_i2c_copy_next_to_current(struct tegra_vi_i2c_dev *i2c_dev)
 680 {
 681         i2c_dev->msg_buf = i2c_dev->next_msg_buf;
 682         i2c_dev->msg_buf_remaining = i2c_dev->next_msg_buf_remaining;
 683         i2c_dev->msg_err = i2c_dev->next_msg_err;
 684         i2c_dev->msg_read = i2c_dev->next_msg_read;
 685         i2c_dev->msg_add = i2c_dev->next_msg_add;
 686         i2c_dev->packet_header = i2c_dev->next_packet_header;
 687         i2c_dev->io_header = i2c_dev->next_io_header;
 688         i2c_dev->payload_size = i2c_dev->next_payload_size;
 689
 690         return 0;
 691 }
 692
 693 static irqreturn_t tegra_vi_i2c_isr(int irq, void *dev_id)
 694 {
 695         u32 status;
 696         unsigned long flags = 0;
 697
 698         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
 699                                         | I2C_INT_TX_FIFO_OVERFLOW;
 700         struct tegra_vi_i2c_dev *i2c_dev = dev_id;
 701         u32 mask;
 702
 703         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 704
 705         if (status == 0) {
 706                 dev_dbg(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
 707                                                 i2c_dev->msg_add);
 708                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 709
 710                 if (!i2c_dev->irq_disabled) {
 711                         disable_irq_nosync(i2c_dev->irq);
 712                         i2c_dev->irq_disabled = 1;
 713                 }
 714                 goto err;
 715         }
 716
 717         if (unlikely(status & status_err)) {
 718                 dev_dbg(i2c_dev->dev, "I2c error status 0x%08x\n", status);
 719                 if (status & I2C_INT_NO_ACK) {
 720                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 721                         dev_dbg(i2c_dev->dev,
 722                                 "no acknowledge from address 0x%x\n",
 723                                 i2c_dev->msg_add);
 724                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 725                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 726                 }
 727
 728                 if (status & I2C_INT_ARBITRATION_LOST) {
 729                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 730                         dev_dbg(i2c_dev->dev,
 731                                 "arbitration lost during talk to add 0x%x\n",
 732                                 i2c_dev->msg_add);
 733                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 734                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 735                 }
 736
 737                 if (status & I2C_INT_TX_FIFO_OVERFLOW) {
 738                         i2c_dev->msg_err |= I2C_INT_TX_FIFO_OVERFLOW;
 739                         dev_dbg(i2c_dev->dev,
 740                                 "Tx fifo overflow during talk to add 0x%x\n",
 741                                 i2c_dev->msg_add);
 742                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 743                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 744                 }
 745                 goto err;
 746         }
 747
 748         if (i2c_dev->chipdata->has_hw_arb_support &&
 749                         (status & I2C_INT_BUS_CLEAR_DONE))
 750                 goto err;
 751
 752         if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
 753                                 && (status == I2C_INT_TX_FIFO_DATA_REQ)
 754                                 && i2c_dev->msg_read
 755                                 && i2c_dev->msg_buf_remaining)) {
 756                 dev_dbg(i2c_dev->dev, "unexpected status\n");
 757                 i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
 758
 759                 if (!i2c_dev->irq_disabled) {
 760                         disable_irq_nosync(i2c_dev->irq);
 761                         i2c_dev->irq_disabled = 1;
 762                 }
 763
 764                 goto err;
 765         }
 766
 767         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 768                 if (i2c_dev->msg_buf_remaining)
 769                         tegra_vi_i2c_empty_rx_fifo(i2c_dev);
 770                 else
 771                         BUG();
 772         }
 773
 774         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 775                 if (i2c_dev->msg_buf_remaining) {
 776
 777                         spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
 778
 779                         tegra_vi_i2c_fill_tx_fifo(i2c_dev);
 780
 781                         spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
 782
 783                 } else
 784                         tegra_vi_i2c_mask_irq(
 785                                 i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 786         }
 787
 788         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 789
 790         if (status & I2C_INT_ALL_PACKETS_XFER_COMPLETE) {
 791                 BUG_ON(i2c_dev->msg_buf_remaining);
 792                 complete(&i2c_dev->msg_complete);
 793         } else if ((status & I2C_INT_PACKET_XFER_COMPLETE)
 794                                 && i2c_dev->use_single_xfer_complete) {
 795                 BUG_ON(i2c_dev->msg_buf_remaining);
 796                 complete(&i2c_dev->msg_complete);
 797         }
 798
 799         return IRQ_HANDLED;
 800
 801 err:
 802         dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 803                  i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
 804                  i2c_readl(i2c_dev, I2C_INT_STATUS),
 805                  i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 806
 807         dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
 808                  i2c_dev->packet_header, i2c_dev->payload_size,
 809                  i2c_dev->io_header);
 810
 811         if (i2c_dev->msgs) {
 812                 struct i2c_msg *msgs = i2c_dev->msgs;
 813                 int i;
 814
 815                 for (i = 0; i < i2c_dev->msgs_num; i++)
 816                         dev_dbg(i2c_dev->dev,
 817                                  "msgs[%d] %c, addr=0x%04x, len=%d\n",
 818                                  i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
 819                                  msgs[i].addr, msgs[i].len);
 820         }
 821
 822         mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 823                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 824                 I2C_INT_RX_FIFO_DATA_REQ | I2C_INT_TX_FIFO_OVERFLOW;
 825
 826         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 827
 828         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
 829                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
 830
 831         if (!(i2c_dev->use_single_xfer_complete &&
 832                         i2c_dev->chipdata->has_xfer_complete_interrupt))
 833                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
 834
 835         if (i2c_dev->chipdata->has_hw_arb_support)
 836                 mask |= I2C_INT_BUS_CLEAR_DONE;
 837
 838         /* An error occurred, mask all interrupts */
 839         tegra_vi_i2c_mask_irq(i2c_dev, mask);
 840
 841         complete(&i2c_dev->msg_complete);
 842
 843         return IRQ_HANDLED;
 844 }
 845
 846 static int tegra_vi_i2c_send_next_read_msg_pkt_header(
 847         struct tegra_vi_i2c_dev *i2c_dev,
 848         struct i2c_msg *next_msg,
 849         enum msg_end_type end_state)
 850 {
 851         i2c_dev->next_msg_buf = next_msg->buf;
 852         i2c_dev->next_msg_buf_remaining = next_msg->len;
 853         i2c_dev->next_msg_err = I2C_ERR_NONE;
 854         i2c_dev->next_msg_read = 1;
 855         i2c_dev->next_msg_add = next_msg->addr;
 856         i2c_dev->next_packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 857                         PACKET_HEADER0_PROTOCOL_I2C |
 858                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 859                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 860
 861         i2c_writel(i2c_dev, i2c_dev->next_packet_header, I2C_TX_FIFO);
 862
 863         i2c_dev->next_payload_size = next_msg->len - 1;
 864         i2c_writel(i2c_dev, i2c_dev->next_payload_size, I2C_TX_FIFO);
 865
 866         i2c_dev->next_io_header = I2C_HEADER_IE_ENABLE;
 867
 868         if (end_state == MSG_END_CONTINUE)
 869                 i2c_dev->next_io_header |= I2C_HEADER_CONTINUE_XFER;
 870         else if (end_state == MSG_END_REPEAT_START)
 871                 i2c_dev->next_io_header |= I2C_HEADER_REPEAT_START;
 872
 873         if (next_msg->flags & I2C_M_TEN) {
 874                 i2c_dev->next_io_header |= next_msg->addr;
 875                 i2c_dev->next_io_header |= I2C_HEADER_10BIT_ADDR;
 876         } else {
 877                 i2c_dev->next_io_header |=
 878                         (next_msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
 879         }
 880         if (next_msg->flags & I2C_M_IGNORE_NAK)
 881                 i2c_dev->next_io_header |= I2C_HEADER_CONT_ON_NAK;
 882
 883         i2c_dev->next_io_header |= I2C_HEADER_READ;
 884
 885         if (i2c_dev->is_high_speed_enable) {
 886                 i2c_dev->next_io_header |= I2C_HEADER_HIGHSPEED_MODE;
 887                 i2c_dev->next_io_header |= ((i2c_dev->hs_master_code & 0x7)
 888                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
 889         }
 890         i2c_writel(i2c_dev, i2c_dev->next_io_header, I2C_TX_FIFO);
 891
 892         return 0;
 893 }
 894
 895 static int tegra_vi_i2c_xfer_msg(struct tegra_vi_i2c_dev *i2c_dev,
 896         struct i2c_msg *msg, enum msg_end_type end_state,
 897         struct i2c_msg *next_msg, enum msg_end_type next_msg_end_state)
 898 {
 899         u32 int_mask;
 900         int ret;
 901         unsigned long flags = 0;
 902         unsigned long timeout = jiffies + HZ;
 903         u32 cnfg;
 904         u32 val;
 905
 906         if (msg->len == 0)
 907                 return -EINVAL;
 908
 909         tegra_vi_i2c_flush_fifos(i2c_dev);
 910
 911
 912         i2c_dev->msg_buf = msg->buf;
 913         i2c_dev->msg_buf_remaining = msg->len;
 914         i2c_dev->msg_err = I2C_ERR_NONE;
 915         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 916         INIT_COMPLETION(i2c_dev->msg_complete);
 917
 918         spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
 919
 920         cnfg = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
 921         if (!i2c_dev->is_high_speed_enable)
 922                 cnfg |= (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 923
 924         i2c_writel(i2c_dev, cnfg, I2C_CNFG);
 925
 926         if (i2c_dev->chipdata->has_config_load_reg) {
 927                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
 928                                         I2C_CONFIG_LOAD);
 929                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 930                         if (time_after(jiffies, timeout)) {
 931                                 dev_warn(i2c_dev->dev,
 932                                         "timeout config_load");
 933                                 return -ETIMEDOUT;
 934                         }
 935                         udelay(2);
 936                 }
 937         }
 938         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 939
 940         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 941                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 942         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 943
 944         i2c_dev->msg_add = msg->addr;
 945
 946         i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 947                         PACKET_HEADER0_PROTOCOL_I2C |
 948                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 949                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 950         i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
 951
 952         i2c_dev->payload_size = msg->len - 1;
 953         i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
 954
 955         i2c_dev->use_single_xfer_complete = true;
 956         i2c_dev->io_header = 0;
 957         if (next_msg == NULL)
 958                 i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
 959
 960         if (end_state == MSG_END_CONTINUE)
 961                 i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
 962         else if (end_state == MSG_END_REPEAT_START)
 963                 i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
 964         if (msg->flags & I2C_M_TEN) {
 965                 i2c_dev->io_header |= msg->addr;
 966                 i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
 967         } else {
 968                 i2c_dev->io_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 969         }
 970         if (msg->flags & I2C_M_IGNORE_NAK)
 971                 i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
 972         if (msg->flags & I2C_M_RD)
 973                 i2c_dev->io_header |= I2C_HEADER_READ;
 974         if (i2c_dev->is_high_speed_enable) {
 975                 i2c_dev->io_header |= I2C_HEADER_HIGHSPEED_MODE;
 976                 i2c_dev->io_header |= ((i2c_dev->hs_master_code & 0x7)
 977                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
 978         }
 979         i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
 980
 981         if (!(msg->flags & I2C_M_RD))
 982                 tegra_vi_i2c_fill_tx_fifo(i2c_dev);
 983
 984         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
 985                                         | I2C_INT_TX_FIFO_OVERFLOW;
 986         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
 987                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 988
 989         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
 990                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
 991
 992         if (msg->flags & I2C_M_RD)
 993                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 994         else if (i2c_dev->msg_buf_remaining)
 995                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 996
 997         if (next_msg != NULL) {
 998                 tegra_vi_i2c_send_next_read_msg_pkt_header(i2c_dev, next_msg,
 999                                                         next_msg_end_state);
1000                 tegra_vi_i2c_copy_next_to_current(i2c_dev);
1001                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1002                 i2c_dev->use_single_xfer_complete = false;
1003         }
1004
1005         if (!(i2c_dev->use_single_xfer_complete &&
1006                         i2c_dev->chipdata->has_xfer_complete_interrupt))
1007                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
1008
1009         spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
1010
1011         tegra_vi_i2c_unmask_irq(i2c_dev, int_mask);
1012
1013         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1014                 i2c_readl(i2c_dev, I2C_INT_MASK));
1015
1016         ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
1017                                         TEGRA_I2C_TIMEOUT);
1018         if (ret == 0) {
1019                 dev_err(i2c_dev->dev, "--- register dump for debugging ----\n");
1020                 dev_err(i2c_dev->dev, "I2C_CNFG - 0x%x\n",
1021                         i2c_readl(i2c_dev, I2C_CNFG));
1022                 dev_err(i2c_dev->dev, "I2C_PACKET_TRANSFER_STATUS - 0x%x\n",
1023                         i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
1024                 dev_err(i2c_dev->dev, "I2C_FIFO_CONTROL - 0x%x\n",
1025                         i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
1026                 dev_err(i2c_dev->dev, "I2C_FIFO_STATUS - 0x%x\n",
1027                         i2c_readl(i2c_dev, I2C_FIFO_STATUS));
1028                 dev_err(i2c_dev->dev, "I2C_INT_MASK - 0x%x\n",
1029                         i2c_readl(i2c_dev, I2C_INT_MASK));
1030                 dev_err(i2c_dev->dev, "I2C_INT_STATUS - 0x%x\n",
1031                         i2c_readl(i2c_dev, I2C_INT_STATUS));
1032
1033                 dev_err(i2c_dev->dev, "msg->len - %d\n", msg->len);
1034                 dev_err(i2c_dev->dev, "is_msg_write - %d\n",
1035                         !(msg->flags & I2C_M_RD));
1036                 if (next_msg != NULL) {
1037                         dev_err(i2c_dev->dev, "next_msg->len - %d\n",
1038                                 next_msg->len);
1039                         dev_err(i2c_dev->dev, "is_next_msg_write - %d\n",
1040                                 !(next_msg->flags & I2C_M_RD));
1041                 }
1042
1043                 dev_err(i2c_dev->dev, "buf_remaining - %zd\n",
1044                         i2c_dev->msg_buf_remaining);
1045         }
1046
1047         tegra_vi_i2c_mask_irq(i2c_dev, int_mask);
1048
1049         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
1050         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
1051                 i2c_writel(i2c_dev, cnfg & (~I2C_CNFG_PACKET_MODE_EN),
1052                                                                 I2C_CNFG);
1053         else
1054                 dev_err(i2c_dev->dev, "i2c_cnfg PACKET_MODE_EN not set\n");
1055
1056         if (i2c_dev->chipdata->has_config_load_reg) {
1057                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
1058                                         I2C_CONFIG_LOAD);
1059                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
1060                         if (time_after(jiffies, timeout)) {
1061                                 dev_warn(i2c_dev->dev,
1062                                         "timeout config_load");
1063                                 return -ETIMEDOUT;
1064                         }
1065                         udelay(2);
1066                 }
1067         }
1068
1069         if (ret == 0) {
1070                 dev_err(i2c_dev->dev,
1071                         "i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
1072                         msg->addr, msg->buf[0]);
1073
1074                 ret = tegra_vi_i2c_init(i2c_dev);
1075                 if (!ret)
1076                         ret = -ETIMEDOUT;
1077                 else
1078                         WARN_ON(1);
1079                 return ret;
1080         }
1081
1082         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
1083                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
1084
1085         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1086                 return 0;
1087
1088         /* Prints errors */
1089         if (i2c_dev->msg_err & I2C_ERR_UNKNOWN_INTERRUPT)
1090                 dev_warn(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
1091                                 i2c_dev->msg_add);
1092         if (i2c_dev->msg_err & I2C_ERR_NO_ACK)
1093                 dev_warn(i2c_dev->dev, "no acknowledge from address 0x%x\n",
1094                                 i2c_dev->msg_add);
1095         if (i2c_dev->msg_err & I2C_ERR_ARBITRATION_LOST)
1096                 dev_warn(i2c_dev->dev, "arb lost in communicate to add 0x%x\n",
1097                                 i2c_dev->msg_add);
1098         if (i2c_dev->msg_err & I2C_INT_TX_FIFO_OVERFLOW)
1099                 dev_warn(i2c_dev->dev, "Tx fifo overflow to add 0x%x\n",
1100                                 i2c_dev->msg_add);
1101         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
1102                 dev_warn(i2c_dev->dev, "unexpected status to add 0x%x\n",
1103                                 i2c_dev->msg_add);
1104
1105         if ((i2c_dev->chipdata->timeout_irq_occurs_before_bus_inactive) &&
1106                 (i2c_dev->msg_err == I2C_ERR_NO_ACK)) {
1107                 /*
1108                 * In NACK error condition resetting of I2C controller happens
1109                 * before STOP condition is properly completed by I2C controller,
1110                 * so wait for 2 clock cycle to complete STOP condition.
1111                 */
1112                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
1113         }
1114
1115         /*
1116          * NACK interrupt is generated before the I2C controller generates the
1117          * STOP condition on the bus. So wait for 2 clk periods before resetting
1118          * the controller so that STOP condition has been delivered properly.
1119          */
1120         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
1121                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
1122
1123         ret = tegra_vi_i2c_init(i2c_dev);
1124         if (ret) {
1125                 WARN_ON(1);
1126                 return ret;
1127         }
1128
1129         /* Arbitration Lost occurs, Start recovery */
1130         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1131                 if (i2c_dev->chipdata->has_hw_arb_support) {
1132                         INIT_COMPLETION(i2c_dev->msg_complete);
1133                         i2c_writel(i2c_dev, I2C_BC_ENABLE
1134                                         | I2C_BC_SCLK_THRESHOLD
1135                                         | I2C_BC_STOP_COND
1136                                         | I2C_BC_TERMINATE
1137                                         , I2C_BUS_CLEAR_CNFG);
1138
1139                         if (i2c_dev->chipdata->has_config_load_reg) {
1140                                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
1141                                                         I2C_CONFIG_LOAD);
1142                                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD)
1143                                         != 0) {
1144                                         if (time_after(jiffies, timeout)) {
1145                                                 dev_warn(i2c_dev->dev,
1146                                                         "timeout config_load");
1147                                                 return -ETIMEDOUT;
1148                                         }
1149                                         usleep_range(1000, 1100);
1150                                 }
1151                         }
1152
1153                         tegra_vi_i2c_unmask_irq(
1154                                 i2c_dev, I2C_INT_BUS_CLEAR_DONE);
1155
1156                         wait_for_completion_timeout(&i2c_dev->msg_complete,
1157                                 TEGRA_I2C_TIMEOUT);
1158
1159                         if (!(i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS)
1160                                 & I2C_BC_STATUS))
1161                                 dev_warn(i2c_dev->dev,
1162                                         "Un-recovered Arbitration lost\n");
1163                 } else {
1164                         i2c_algo_busclear_gpio(i2c_dev->dev,
1165                                 i2c_dev->scl_gpio, GPIOF_OPEN_DRAIN,
1166                                 i2c_dev->sda_gpio, GPIOF_OPEN_DRAIN,
1167                                 MAX_BUSCLEAR_CLOCK, 100000);
1168                 }
1169                 return -EAGAIN;
1170         }
1171
1172         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1173                 if (msg->flags & I2C_M_IGNORE_NAK)
1174                         return 0;
1175                 return -EREMOTEIO;
1176         }
1177
1178         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
1179                 return -EAGAIN;
1180
1181         return -EIO;
1182 }
1183
1184 static int tegra_vi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1185         int num)
1186 {
1187         struct tegra_vi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1188         int i = 0;
1189         int ret = 0;
1190         BUG_ON(!rt_mutex_is_locked(&(adap->bus_lock)));
1191         if (i2c_dev->is_suspended)
1192                 return -EBUSY;
1193
1194         if ((i2c_dev->is_shutdown || adap->atomic_xfer_only)
1195                 && i2c_dev->bit_banging_xfer_after_shutdown) {
1196                 ret = tegra_vi_i2c_gpio_xfer(adap, msgs, num);
1197                 i = num;
1198                 goto end;
1199         }
1200
1201         if (adap->atomic_xfer_only) {
1202                 ret = -EBUSY;
1203                 goto end;
1204         }
1205
1206         i2c_dev->msgs = msgs;
1207         i2c_dev->msgs_num = num;
1208
1209         ret = pm_runtime_get_sync(&adap->dev);
1210         if (ret < 0)
1211                 goto i2c_xfer_pwr_fail;
1212
1213         tegra_vi_i2c_init(i2c_dev);
1214
1215         for (i = 0; i < num; i++) {
1216                 enum msg_end_type end_type = MSG_END_STOP;
1217                 enum msg_end_type next_msg_end_type = MSG_END_STOP;
1218
1219                 if (i < (num - 1)) {
1220                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1221                                 end_type = MSG_END_CONTINUE;
1222                         else
1223                                 end_type = MSG_END_REPEAT_START;
1224                         if (i < num - 2) {
1225                                 if (msgs[i + 2].flags & I2C_M_NOSTART)
1226                                         next_msg_end_type = MSG_END_CONTINUE;
1227                                 else
1228                                         next_msg_end_type =
1229                                                 MSG_END_REPEAT_START;
1230                         }
1231                         if ((!(msgs[i].flags & I2C_M_RD))
1232                                 && (msgs[i].len <= 8)
1233                                 && (msgs[i+1].flags & I2C_M_RD)
1234                                 && (next_msg_end_type != MSG_END_CONTINUE)
1235                                 && (end_type == MSG_END_REPEAT_START)) {
1236                                 ret = tegra_vi_i2c_xfer_msg(i2c_dev, &msgs[i],
1237                                         end_type, &msgs[i+1],
1238                                         next_msg_end_type);
1239                                 if (ret)
1240                                         break;
1241                                 i++;
1242                         } else {
1243                                 ret = tegra_vi_i2c_xfer_msg(i2c_dev, &msgs[i],
1244                                         end_type, NULL, next_msg_end_type);
1245                                 if (ret)
1246                                         break;
1247                         }
1248                 } else {
1249                         ret = tegra_vi_i2c_xfer_msg(i2c_dev, &msgs[i],
1250                                 end_type, NULL, next_msg_end_type);
1251                         if (ret)
1252                                 break;
1253                 }
1254         }
1255
1256         pm_runtime_mark_last_busy(&adap->dev);
1257         pm_runtime_put_autosuspend(&adap->dev);
1258
1259 i2c_xfer_pwr_fail:
1260         i2c_dev->msgs = NULL;
1261         i2c_dev->msgs_num = 0;
1262
1263 end:
1264         return ret ?: i;
1265 }
1266
1267 static u32 tegra_vi_i2c_func(struct i2c_adapter *adap)
1268 {
1269         struct tegra_vi_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1270         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
1271                                 I2C_FUNC_PROTOCOL_MANGLING;
1272
1273         if (i2c_dev->chipdata->has_continue_xfer_support)
1274                 ret |= I2C_FUNC_NOSTART;
1275         return ret;
1276 }
1277
1278 static const struct i2c_algorithm tegra_vi_i2c_algo = {
1279         .master_xfer    = tegra_vi_i2c_xfer,
1280         .functionality  = tegra_vi_i2c_func,
1281 };
1282
1283 static int __tegra_vi_i2c_suspend_noirq(struct tegra_vi_i2c_dev *i2c_dev);
1284 static int __tegra_vi_i2c_resume_noirq(struct tegra_vi_i2c_dev *i2c_dev);
1285
1286 static int tegra_vi_i2c_pm_notifier(struct notifier_block *nb,
1287                 unsigned long event, void *data)
1288 {
1289         struct tegra_vi_i2c_dev *i2c_dev =
1290                 container_of(nb, struct tegra_vi_i2c_dev, pm_nb);
1291
1292         if (event == TEGRA_PM_SUSPEND)
1293                 __tegra_vi_i2c_suspend_noirq(i2c_dev);
1294         else if (event == TEGRA_PM_RESUME)
1295                 __tegra_vi_i2c_resume_noirq(i2c_dev);
1296
1297         return NOTIFY_OK;
1298 }
1299
1300 static struct tegra_i2c_platform_data *parse_i2c_tegra_dt(
1301         struct platform_device *pdev)
1302 {
1303         struct tegra_i2c_platform_data *pdata;
1304         struct device_node *np = pdev->dev.of_node;
1305         u32 prop;
1306
1307         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1308         if (!pdata)
1309                 return ERR_PTR(-ENOMEM);
1310
1311         if (!of_property_read_u32(np, "clock-frequency", &prop))
1312                 pdata->bus_clk_rate = prop;
1313
1314         pdata->is_clkon_always = of_property_read_bool(np,
1315                                         "nvidia,clock-always-on");
1316
1317         if (!of_property_read_u32(np, "nvidia,hs-master-code", &prop)) {
1318                 pdata->hs_master_code = prop;
1319                 pdata->is_high_speed_enable = true;
1320         }
1321
1322         pdata->bit_banging_xfer_after_shutdown = of_property_read_bool(np,
1323                                 "nvidia,bit-banging-xfer-after-shutdown");
1324
1325         pdata->scl_gpio = of_get_named_gpio(np, "scl-gpio", 0);
1326         pdata->sda_gpio = of_get_named_gpio(np, "sda-gpio", 0);
1327
1328         /* Default configuration for device tree initiated driver */
1329         pdata->slave_addr = 0xFC;
1330         return pdata;
1331 }
1332
1333 static struct tegra_vi_i2c_chipdata tegra210_vii2c_chipdata = {
1334         .timeout_irq_occurs_before_bus_inactive = false,
1335         .has_xfer_complete_interrupt = true,
1336         .has_continue_xfer_support = true,
1337         .has_hw_arb_support = true,
1338         .has_fast_clock = false,
1339         .has_clk_divisor_std_fast_mode = true,
1340         .clk_divisor_std_fast_mode = 0x1f,
1341         .clk_divisor_fast_plus_mode = 0x10,
1342         .clk_divisor_hs_mode = 2,
1343         .clk_multiplier_hs_mode = 13,
1344         .has_config_load_reg = true,
1345 };
1346
1347 /* Match table for of_platform binding */
1348 static const struct of_device_id tegra_vii2c_of_match[] = {
1349         {
1350                 .compatible = "nvidia,tegra210-vii2c",
1351                 .data = &tegra210_vii2c_chipdata, },
1352         {},
1353 };
1354 MODULE_DEVICE_TABLE(of, tegra_vii2c_of_match);
1355
1356 static struct platform_device_id tegra_vi_i2c_devtype[] = {
1357         {
1358                 .name = "tegra21-vii2c",
1359                 .driver_data = (unsigned long)&tegra210_vii2c_chipdata,
1360         },
1361 };
1362
1363 static int tegra_vi_i2c_probe(struct platform_device *pdev)
1364 {
1365         struct tegra_vi_i2c_dev *i2c_dev;
1366         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
1367         struct resource *res;
1368         struct clk *div_clk;
1369         struct clk *slow_clk;
1370         struct clk *host1x_clk;
1371         struct clk *fast_clk = NULL;
1372         void __iomem *base;
1373         int irq;
1374         int ret = 0;
1375         const struct tegra_vi_i2c_chipdata *chip_data = NULL;
1376         const struct of_device_id *match;
1377         int bus_num = -1;
1378         struct pinctrl *pin;
1379         struct pinctrl_state *s;
1380
1381         if (pdev->dev.of_node) {
1382                 match = of_match_device(
1383                         of_match_ptr(tegra_vii2c_of_match), &pdev->dev);
1384                 if (!match) {
1385                         dev_err(&pdev->dev, "Device Not matching\n");
1386                         return -ENODEV;
1387                 }
1388                 chip_data = match->data;
1389                 if (!pdata)
1390                         pdata = parse_i2c_tegra_dt(pdev);
1391         } else {
1392                 chip_data = (struct tegra_vi_i2c_chipdata *)
1393                         pdev->id_entry->driver_data;
1394                 bus_num = pdev->id;
1395         }
1396
1397         if (IS_ERR(pdata) || !pdata || !chip_data) {
1398                 dev_err(&pdev->dev, "no platform/chip data?\n");
1399                 return IS_ERR(pdata) ? PTR_ERR(pdata) : -ENODEV;
1400         }
1401
1402         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1403         if (!res) {
1404                 dev_err(&pdev->dev, "no mem resource\n");
1405                 return -EINVAL;
1406         }
1407
1408         base = devm_ioremap_resource(&pdev->dev, res);
1409         if (IS_ERR(base))
1410                 return PTR_ERR(base);
1411
1412         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1413         if (!res) {
1414                 dev_err(&pdev->dev, "no irq resource\n");
1415                 return -EINVAL;
1416         }
1417         irq = res->start;
1418
1419         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1420         if (!i2c_dev) {
1421                 dev_err(&pdev->dev, "Could not allocate struct tegra_vi_i2c_dev");
1422                 return -ENOMEM;
1423         }
1424
1425         i2c_dev->chipdata = chip_data;
1426         i2c_dev->dev = &pdev->dev;
1427
1428         div_clk = devm_clk_get(&pdev->dev, "vii2c");
1429         if (IS_ERR(div_clk)) {
1430                 dev_err(&pdev->dev, "missing controller clock");
1431                 return PTR_ERR(div_clk);
1432         }
1433
1434         slow_clk = devm_clk_get(&pdev->dev, "i2cslow");
1435         if (IS_ERR(slow_clk)) {
1436                 dev_err(&pdev->dev, "missing slow clock");
1437                 return PTR_ERR(slow_clk);
1438         }
1439
1440         host1x_clk = devm_clk_get(&pdev->dev, "host1x");
1441         if (IS_ERR(host1x_clk)) {
1442                 dev_err(&pdev->dev, "missing host1x clock");
1443                 return PTR_ERR(host1x_clk);
1444         }
1445
1446         if (i2c_dev->chipdata->has_fast_clock) {
1447                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1448                 if (IS_ERR(fast_clk)) {
1449                         dev_err(&pdev->dev, "missing bus clock");
1450                         return PTR_ERR(fast_clk);
1451                 }
1452         }
1453
1454         if (pdata->is_high_speed_enable) {
1455                 pin = devm_pinctrl_get(&pdev->dev);
1456                 if (IS_ERR(pin)) {
1457                         dev_warn(&pdev->dev, "Missing pinctrl device\n");
1458                         goto skip_pinctrl;
1459                 }
1460
1461                 s = pinctrl_lookup_state(pin, "hs_mode");
1462                 if (IS_ERR(s)) {
1463                         dev_warn(&pdev->dev, "Missing hs_mode state\n");
1464                         goto skip_pinctrl;
1465                 }
1466
1467                 ret = pinctrl_select_state(pin, s);
1468                 if (ret < 0)
1469                         dev_err(&pdev->dev, "setting state failed\n");
1470         }
1471
1472 skip_pinctrl:
1473
1474         i2c_dev->pull_up_supply = devm_regulator_get(&pdev->dev, "bus-pullup");
1475         if (IS_ERR(i2c_dev->pull_up_supply)) {
1476                 ret = PTR_ERR(i2c_dev->pull_up_supply);
1477                 if (ret  == -EPROBE_DEFER)
1478                         return -EPROBE_DEFER;
1479                 dev_err(&pdev->dev, "bus-pullup regulator not found: %d\n",
1480                         ret);
1481                 i2c_dev->pull_up_supply = NULL;
1482         }
1483
1484         /* get regulator */
1485         i2c_dev->reg = devm_regulator_get(&pdev->dev, "avdd_dsi_csi");
1486         if (IS_ERR(i2c_dev->reg)) {
1487                 dev_err(&pdev->dev, "could not get regulator: %ld",
1488                         PTR_ERR(i2c_dev->reg));
1489                 return PTR_ERR(i2c_dev->reg);
1490         }
1491
1492         i2c_dev->base = base;
1493         i2c_dev->div_clk = div_clk;
1494         i2c_dev->slow_clk = slow_clk;
1495         i2c_dev->host1x_clk = host1x_clk;
1496         if (i2c_dev->chipdata->has_fast_clock)
1497                 i2c_dev->fast_clk = fast_clk;
1498         i2c_dev->irq = irq;
1499         i2c_dev->cont_id = pdev->id & 0xff;
1500         i2c_dev->dev = &pdev->dev;
1501         i2c_dev->is_clkon_always = pdata->is_clkon_always;
1502         i2c_dev->bus_clk_rate =
1503                 pdata->bus_clk_rate ? pdata->bus_clk_rate : 100000;
1504         i2c_dev->is_high_speed_enable = pdata->is_high_speed_enable;
1505         i2c_dev->clk_divisor_non_hs_mode =
1506                         i2c_dev->chipdata->clk_divisor_std_fast_mode;
1507         if (i2c_dev->bus_clk_rate == 1000000)
1508                 i2c_dev->clk_divisor_non_hs_mode =
1509                         i2c_dev->chipdata->clk_divisor_fast_plus_mode;
1510         i2c_dev->msgs = NULL;
1511         i2c_dev->msgs_num = 0;
1512         i2c_dev->slave_addr = pdata->slave_addr;
1513         i2c_dev->hs_master_code = pdata->hs_master_code;
1514         i2c_dev->bit_banging_xfer_after_shutdown =
1515                         pdata->bit_banging_xfer_after_shutdown;
1516         init_completion(&i2c_dev->msg_complete);
1517
1518         spin_lock_init(&i2c_dev->fifo_lock);
1519
1520         spin_lock_init(&i2c_dev->mem_lock);
1521
1522         platform_set_drvdata(pdev, i2c_dev);
1523
1524         if (i2c_dev->is_clkon_always)
1525                 tegra_vi_i2c_clock_enable(i2c_dev);
1526
1527         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1528                         tegra_vi_i2c_isr, IRQF_NO_SUSPEND,
1529                         dev_name(&pdev->dev), i2c_dev);
1530         if (ret) {
1531                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1532                 return ret;
1533         }
1534
1535         pm_runtime_enable(&pdev->dev);
1536
1537         i2c_dev->scl_gpio = pdata->scl_gpio;
1538         i2c_dev->sda_gpio = pdata->sda_gpio;
1539         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1540         i2c_dev->adapter.owner = THIS_MODULE;
1541         i2c_dev->adapter.class = I2C_CLASS_HWMON;
1542         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
1543                 sizeof(i2c_dev->adapter.name));
1544         i2c_dev->adapter.algo = &tegra_vi_i2c_algo;
1545         i2c_dev->adapter.dev.parent = &pdev->dev;
1546         i2c_dev->adapter.nr = bus_num;
1547         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1548
1549         if (pdata->retries)
1550                 i2c_dev->adapter.retries = pdata->retries;
1551         else
1552                 i2c_dev->adapter.retries = TEGRA_I2C_RETRIES;
1553
1554         if (pdata->timeout)
1555                 i2c_dev->adapter.timeout = pdata->timeout;
1556
1557         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1558         if (ret) {
1559                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1560                 return ret;
1561         }
1562
1563         i2c_dev->pm_nb.notifier_call = tegra_vi_i2c_pm_notifier;
1564
1565         tegra_register_pm_notifier(&i2c_dev->pm_nb);
1566
1567         pm_runtime_enable(&i2c_dev->adapter.dev);
1568         of_i2c_register_devices(&i2c_dev->adapter);
1569         tegra_vi_i2c_gpio_init(i2c_dev);
1570
1571         /* set 100ms autosuspend delay for the adapter device */
1572         pm_runtime_set_autosuspend_delay(&i2c_dev->adapter.dev, 100);
1573         pm_runtime_use_autosuspend(&i2c_dev->adapter.dev);
1574
1575         return 0;
1576 }
1577
1578 static int tegra_vi_i2c_remove(struct platform_device *pdev)
1579 {
1580         struct tegra_vi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1581
1582         tegra_unregister_pm_notifier(&i2c_dev->pm_nb);
1583         i2c_del_adapter(&i2c_dev->adapter);
1584         pm_runtime_disable(&i2c_dev->adapter.dev);
1585
1586         if (i2c_dev->is_clkon_always)
1587                 tegra_vi_i2c_clock_disable(i2c_dev);
1588
1589         pm_runtime_disable(&pdev->dev);
1590         return 0;
1591 }
1592
1593 static void tegra_vi_i2c_shutdown(struct platform_device *pdev)
1594 {
1595         struct tegra_vi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1596
1597         dev_info(i2c_dev->dev, "Bus is shutdown down..\n");
1598         i2c_shutdown_adapter(&i2c_dev->adapter);
1599         i2c_dev->is_shutdown = true;
1600 }
1601
1602 #ifdef CONFIG_PM_SLEEP
1603 static int __tegra_vi_i2c_suspend_noirq(struct tegra_vi_i2c_dev *i2c_dev)
1604 {
1605         i2c_dev->is_suspended = true;
1606         if (i2c_dev->is_clkon_always)
1607                 tegra_vi_i2c_clock_disable(i2c_dev);
1608
1609         return 0;
1610 }
1611
1612 static int tegra_vi_i2c_suspend_noirq(struct device *dev)
1613 {
1614         struct platform_device *pdev = to_platform_device(dev);
1615         struct tegra_vi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1616
1617         /*
1618          * device_prepare takes one ref, so expect usage count to
1619          * be 1 at this point.
1620          */
1621 #ifdef CONFIG_PM_RUNTIME
1622         if (atomic_read(&dev->power.usage_count) > 1)
1623                 return -EBUSY;
1624 #endif
1625
1626         i2c_lock_adapter(&i2c_dev->adapter);
1627
1628         __tegra_vi_i2c_suspend_noirq(i2c_dev);
1629
1630         i2c_unlock_adapter(&i2c_dev->adapter);
1631
1632         return 0;
1633 }
1634
1635 static int __tegra_vi_i2c_resume_noirq(struct tegra_vi_i2c_dev *i2c_dev)
1636 {
1637         if (i2c_dev->is_clkon_always)
1638                 tegra_vi_i2c_clock_enable(i2c_dev);
1639
1640         i2c_dev->is_suspended = false;
1641
1642         return 0;
1643 }
1644
1645 static int tegra_vi_i2c_resume_noirq(struct device *dev)
1646 {
1647         struct platform_device *pdev = to_platform_device(dev);
1648         struct tegra_vi_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1649
1650         i2c_lock_adapter(&i2c_dev->adapter);
1651
1652         __tegra_vi_i2c_resume_noirq(i2c_dev);
1653
1654         i2c_unlock_adapter(&i2c_dev->adapter);
1655
1656         return 0;
1657 }
1658 #endif
1659
1660 #ifdef CONFIG_PM_RUNTIME
1661
1662 int tegra_vi_i2c_runtime_resume(struct device *dev)
1663 {
1664         struct tegra_vi_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1665         int ret;
1666
1667         ret = tegra_vi_i2c_power_enable(i2c_dev);
1668         if (ret)
1669                 goto err_power_enable;
1670
1671         ret = tegra_vi_i2c_clock_enable(i2c_dev);
1672         if (ret)
1673                 goto err_clock_enable;
1674
1675         return 0;
1676
1677 err_clock_enable:
1678         tegra_vi_i2c_power_disable(i2c_dev);
1679 err_power_enable:
1680         return ret;
1681 }
1682
1683 int tegra_vi_i2c_runtime_suspend(struct device *dev)
1684 {
1685         struct tegra_vi_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1686         int ret;
1687
1688         tegra_vi_i2c_clock_disable(i2c_dev);
1689
1690         ret = tegra_vi_i2c_power_disable(i2c_dev);
1691         WARN_ON(ret);
1692
1693         return 0;
1694 }
1695 #endif
1696
1697 static const struct dev_pm_ops tegra_vii2c_pm = {
1698 #ifdef CONFIG_PM_SLEEP
1699         .suspend_noirq = tegra_vi_i2c_suspend_noirq,
1700         .resume_noirq = tegra_vi_i2c_resume_noirq,
1701 #endif
1702 #ifdef CONFIG_PM_RUNTIME
1703         .runtime_suspend = tegra_vi_i2c_runtime_suspend,
1704         .runtime_resume = tegra_vi_i2c_runtime_resume,
1705 #endif
1706 };
1707
1708 static struct platform_driver tegra_vii2c_driver = {
1709         .probe   = tegra_vi_i2c_probe,
1710         .remove  = tegra_vi_i2c_remove,
1711         .shutdown = tegra_vi_i2c_shutdown,
1712         .id_table = tegra_vi_i2c_devtype,
1713         .driver  = {
1714                 .name  = "tegra-vii2c",
1715                 .owner = THIS_MODULE,
1716                 .of_match_table = of_match_ptr(tegra_vii2c_of_match),
1717                 .pm    = &tegra_vii2c_pm,
1718         },
1719 };
1720
1721 module_platform_driver(tegra_vii2c_driver);
1722
1723 MODULE_DESCRIPTION("nVidia Tegra VI-I2C Bus Controller driver");
1724 MODULE_LICENSE("GPL v2");