2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/i2c.h>
17 #include <linux/gpio.h>
18 #include <linux/mpu.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/nct1008.h>
22 #include <linux/pid_thermal_gov.h>
23 #include <linux/tegra-fuse.h>
24 #include <linux/of_platform.h>
26 #include <mach/pinmux-t12.h>
27 #include <mach/pinmux.h>
28 #include <mach/io_dpd.h>
29 #include <media/camera.h>
30 #include <media/ar0330.h>
31 #include <media/ar0261.h>
32 #include <media/ar1335.h>
33 #include <media/imx135.h>
34 #include <media/imx179.h>
35 #include <media/imx185.h>
36 #include <media/dw9718.h>
37 #include <media/as364x.h>
38 #include <media/ov5693.h>
39 #include <media/ov7695.h>
40 #include <media/mt9m114.h>
41 #include <media/ad5823.h>
42 #include <media/max77387.h>
44 #include <media/ov4689.h>
45 #include <linux/platform_device.h>
46 #include <media/soc_camera.h>
47 #include <media/soc_camera_platform.h>
48 #include <media/tegra_v4l2_camera.h>
49 #include <linux/generic_adc_thermal.h>
51 #include "cpu-tegra.h"
54 #include "board-common.h"
55 #include "board-ardbeg.h"
56 #include "tegra-board-id.h"
58 #if defined(ARCH_TEGRA_12x_SOC)
59 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
61 I2C_BOARD_INFO("cm32181", 0x48),
66 /* MPU board file definition */
67 static struct mpu_platform_data mpu9250_gyro_data = {
70 /* Located in board_[platformname].h */
71 .orientation = MPU_GYRO_ORIENTATION,
72 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
73 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
74 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
77 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
80 /* Located in board_[platformname].h */
81 .orientation = MPU_GYRO_ORIENTATION_E1762,
82 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
83 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
84 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
87 static struct mpu_platform_data mpu_compass_data = {
88 .orientation = MPU_COMPASS_ORIENTATION,
89 .config = NVI_CONFIG_BOOT_MPU,
92 static struct mpu_platform_data mpu_bmp_pdata = {
93 .config = NVI_CONFIG_BOOT_MPU,
96 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
98 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
99 .platform_data = &mpu9250_gyro_data,
102 /* The actual BMP180 address is 0x77 but because this conflicts
103 * with another device, this address is hacked so Linux will
104 * call the driver. The conflict is technically okay since the
105 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
106 * hard-coded address of 0x77 since it can't be changed anyway.
108 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
109 .platform_data = &mpu_bmp_pdata,
112 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
113 .platform_data = &mpu_compass_data,
117 static void mpuirq_init(void)
120 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
121 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
122 char *gyro_name = MPU_GYRO_NAME;
123 struct board_info board_info;
125 pr_info("*** MPU START *** mpuirq_init...\n");
127 tegra_get_board_info(&board_info);
129 ret = gpio_request(gyro_irq_gpio, gyro_name);
131 pr_err("%s: gpio_request failed %d\n", __func__, ret);
135 ret = gpio_direction_input(gyro_irq_gpio);
137 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
138 gpio_free(gyro_irq_gpio);
141 pr_info("*** MPU END *** mpuirq_init...\n");
143 /* TN8 with diferent Compass address from ardbeg */
144 if (of_machine_is_compatible("nvidia,tn8"))
145 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
147 if (board_info.board_id == BOARD_E1762)
148 inv_mpu9250_i2c0_board_info[0].platform_data =
149 &mpu9250_gyro_data_e1762;
150 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
151 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
152 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
156 * Soc Camera platform driver for testing
158 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
159 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
160 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
162 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
165 /* TODO: probably add clk opertaion here */
166 return 0; /* camera sensor always enabled */
169 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
170 .format_name = "RGB4",
173 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
174 .colorspace = V4L2_COLORSPACE_SRGB,
175 .field = V4L2_FIELD_NONE,
179 .set_capture = ardbeg_soc_camera_set_capture,
182 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
185 .port = TEGRA_CAMERA_PORT_CSI_A,
190 static struct soc_camera_link ardbeg_soc_camera_link = {
191 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
192 .add_device = ardbeg_soc_camera_add,
193 .del_device = ardbeg_soc_camera_del,
194 .module_name = "soc_camera_platform",
195 .priv = &ardbeg_camera_platform_data,
196 .dev_priv = &ardbeg_soc_camera_info,
199 static struct platform_device *ardbeg_pdev;
201 static void ardbeg_soc_camera_release(struct device *dev)
203 soc_camera_platform_release(&ardbeg_pdev);
206 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
208 return soc_camera_platform_add(icd, &ardbeg_pdev,
209 &ardbeg_soc_camera_link,
210 ardbeg_soc_camera_release, 0);
213 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
215 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
218 static struct platform_device ardbeg_soc_camera_device = {
219 .name = "soc-camera-pdrv",
222 .platform_data = &ardbeg_soc_camera_link,
227 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
228 static int ardbeg_imx135_power(struct device *dev, int enable)
233 struct imx135_platform_data ardbeg_imx135_data;
235 static struct i2c_board_info ardbeg_imx135_camera_i2c_device = {
236 I2C_BOARD_INFO("imx135_v4l2", 0x10),
237 .platform_data = &ardbeg_imx135_data,
240 static struct tegra_camera_platform_data ardbeg_imx135_camera_platform_data = {
243 .port = TEGRA_CAMERA_PORT_CSI_A,
248 static struct soc_camera_link imx135_iclink = {
249 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
250 .board_info = &ardbeg_imx135_camera_i2c_device,
251 .module_name = "imx135_v4l2",
253 .power = ardbeg_imx135_power,
254 .priv = &ardbeg_imx135_camera_platform_data,
257 static struct platform_device ardbeg_imx135_soc_camera_device = {
258 .name = "soc-camera-pdrv",
261 .platform_data = &imx135_iclink,
266 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
267 static int ardbeg_ar0261_power(struct device *dev, int enable)
272 struct ar0261_platform_data ardbeg_ar0261_data;
274 static struct i2c_board_info ardbeg_ar0261_camera_i2c_device = {
275 I2C_BOARD_INFO("ar0261_v4l2", 0x36),
276 .platform_data = &ardbeg_ar0261_data,
279 static struct tegra_camera_platform_data ardbeg_ar0261_camera_platform_data = {
282 .port = TEGRA_CAMERA_PORT_CSI_C,
287 static struct soc_camera_link ar0261_iclink = {
288 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
289 .board_info = &ardbeg_ar0261_camera_i2c_device,
290 .module_name = "ar0261_v4l2",
292 .power = ardbeg_ar0261_power,
293 .priv = &ardbeg_ar0261_camera_platform_data,
296 static struct platform_device ardbeg_ar0261_soc_camera_device = {
297 .name = "soc-camera-pdrv",
300 .platform_data = &ar0261_iclink,
305 static struct regulator *ardbeg_vcmvdd;
307 static int ardbeg_get_extra_regulators(void)
309 if (!ardbeg_vcmvdd) {
310 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
311 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
312 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
313 __func__, PTR_ERR(ardbeg_vcmvdd));
314 regulator_put(ardbeg_vcmvdd);
315 ardbeg_vcmvdd = NULL;
323 static struct tegra_io_dpd csia_io = {
325 .io_dpd_reg_index = 0,
329 static struct tegra_io_dpd csib_io = {
331 .io_dpd_reg_index = 0,
335 static struct tegra_io_dpd csie_io = {
337 .io_dpd_reg_index = 1,
341 static int ardbeg_ar0330_front_power_on(struct ar0330_power_rail *pw)
345 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
348 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
349 tegra_io_dpd_disable(&csie_io);
351 gpio_set_value(CAM2_PWDN, 0);
353 err = regulator_enable(pw->iovdd);
355 goto ar0330_front_iovdd_fail;
357 usleep_range(1000, 1100);
358 err = regulator_enable(pw->avdd);
360 goto ar0330_front_avdd_fail;
363 gpio_set_value(CAM2_PWDN, 1);
366 ar0330_front_avdd_fail:
367 regulator_disable(pw->iovdd);
369 ar0330_front_iovdd_fail:
370 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
371 tegra_io_dpd_enable(&csie_io);
372 pr_err("%s failed.\n", __func__);
376 static int ardbeg_ar0330_front_power_off(struct ar0330_power_rail *pw)
378 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
379 /* put CSIE IOs into DPD mode to
380 * save additional power for ardbeg
382 tegra_io_dpd_enable(&csie_io);
386 gpio_set_value(CAM2_PWDN, 0);
390 regulator_disable(pw->iovdd);
391 regulator_disable(pw->avdd);
392 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
393 tegra_io_dpd_enable(&csie_io);
397 struct ar0330_platform_data ardbeg_ar0330_front_data = {
398 .power_on = ardbeg_ar0330_front_power_on,
399 .power_off = ardbeg_ar0330_front_power_off,
400 .dev_name = "ar0330.1",
401 .mclk_name = "mclk2",
404 static int ardbeg_ar0330_power_on(struct ar0330_power_rail *pw)
408 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
411 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
412 tegra_io_dpd_disable(&csia_io);
413 tegra_io_dpd_disable(&csib_io);
415 gpio_set_value(CAM1_PWDN, 0);
417 err = regulator_enable(pw->iovdd);
419 goto ar0330_iovdd_fail;
421 usleep_range(1000, 1100);
422 err = regulator_enable(pw->avdd);
424 goto ar0330_avdd_fail;
427 gpio_set_value(CAM1_PWDN, 1);
431 regulator_disable(pw->iovdd);
434 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
435 tegra_io_dpd_enable(&csia_io);
436 tegra_io_dpd_enable(&csib_io);
437 pr_err("%s failed.\n", __func__);
441 static int ardbeg_ar0330_power_off(struct ar0330_power_rail *pw)
443 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
444 /* put CSIE IOs into DPD mode to
445 * save additional power for ardbeg
447 tegra_io_dpd_enable(&csia_io);
448 tegra_io_dpd_enable(&csib_io);
452 gpio_set_value(CAM1_PWDN, 0);
456 regulator_disable(pw->iovdd);
457 regulator_disable(pw->avdd);
458 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
459 tegra_io_dpd_enable(&csia_io);
460 tegra_io_dpd_enable(&csib_io);
464 struct ar0330_platform_data ardbeg_ar0330_data = {
465 .power_on = ardbeg_ar0330_power_on,
466 .power_off = ardbeg_ar0330_power_off,
467 .dev_name = "ar0330",
470 static int ardbeg_ov4689_power_on(struct ov4689_power_rail *pw)
472 pr_info("%s: ++\n", __func__);
473 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
474 tegra_io_dpd_disable(&csia_io);
475 tegra_io_dpd_disable(&csib_io);
477 gpio_set_value(TEGRA_GPIO_PBB5, 0);
478 usleep_range(10, 20);
479 gpio_set_value(TEGRA_GPIO_PBB5, 1);
480 usleep_range(820, 1000);
485 static int ardbeg_ov4689_power_off(struct ov4689_power_rail *pw)
487 pr_info("%s: ++\n", __func__);
489 gpio_set_value(TEGRA_GPIO_PBB5, 0);
491 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
492 tegra_io_dpd_enable(&csia_io);
493 tegra_io_dpd_enable(&csib_io);
498 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
502 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
505 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
506 tegra_io_dpd_disable(&csie_io);
508 if (ardbeg_get_extra_regulators())
509 goto ardbeg_ar0261_poweron_fail;
511 gpio_set_value(CAM_RSTN, 0);
512 gpio_set_value(CAM_AF_PWDN, 1);
515 err = regulator_enable(ardbeg_vcmvdd);
517 goto ar0261_vcm_fail;
519 err = regulator_enable(pw->dvdd);
521 goto ar0261_dvdd_fail;
523 err = regulator_enable(pw->avdd);
525 goto ar0261_avdd_fail;
527 err = regulator_enable(pw->iovdd);
529 goto ar0261_iovdd_fail;
532 gpio_set_value(CAM2_PWDN, 1);
534 gpio_set_value(CAM_RSTN, 1);
538 regulator_disable(pw->dvdd);
541 regulator_disable(pw->avdd);
544 regulator_disable(ardbeg_vcmvdd);
547 pr_err("%s vcmvdd failed.\n", __func__);
550 ardbeg_ar0261_poweron_fail:
551 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
552 tegra_io_dpd_enable(&csie_io);
553 pr_err("%s failed.\n", __func__);
557 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
559 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
561 /* put CSIE IOs into DPD mode to
562 * save additional power for ardbeg
564 tegra_io_dpd_enable(&csie_io);
568 gpio_set_value(CAM_RSTN, 0);
572 regulator_disable(pw->iovdd);
573 regulator_disable(pw->dvdd);
574 regulator_disable(pw->avdd);
575 regulator_disable(ardbeg_vcmvdd);
576 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
577 tegra_io_dpd_enable(&csie_io);
581 struct ar0261_platform_data ardbeg_ar0261_data = {
582 .power_on = ardbeg_ar0261_power_on,
583 .power_off = ardbeg_ar0261_power_off,
584 .mclk_name = "mclk2",
587 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
590 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
591 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
592 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
593 __func__, PTR_ERR(pw->ext_reg1));
600 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
601 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
602 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
603 __func__, PTR_ERR(pw->ext_reg2));
612 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
616 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
619 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
620 tegra_io_dpd_disable(&csia_io);
621 tegra_io_dpd_disable(&csib_io);
623 if (ardbeg_imx135_get_extra_regulators(pw))
624 goto imx135_poweron_fail;
626 err = regulator_enable(pw->ext_reg1);
628 goto imx135_ext_reg1_fail;
630 err = regulator_enable(pw->ext_reg2);
632 goto imx135_ext_reg2_fail;
635 gpio_set_value(CAM_AF_PWDN, 1);
636 gpio_set_value(CAM1_PWDN, 0);
637 usleep_range(10, 20);
639 err = regulator_enable(pw->avdd);
641 goto imx135_avdd_fail;
643 err = regulator_enable(pw->iovdd);
645 goto imx135_iovdd_fail;
648 gpio_set_value(CAM1_PWDN, 1);
650 usleep_range(300, 310);
656 regulator_disable(pw->avdd);
660 regulator_disable(pw->ext_reg2);
662 imx135_ext_reg2_fail:
664 regulator_disable(pw->ext_reg1);
665 gpio_set_value(CAM_AF_PWDN, 0);
667 imx135_ext_reg1_fail:
669 tegra_io_dpd_enable(&csia_io);
670 tegra_io_dpd_enable(&csib_io);
671 pr_err("%s failed.\n", __func__);
675 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
677 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
678 tegra_io_dpd_enable(&csia_io);
679 tegra_io_dpd_enable(&csib_io);
683 regulator_disable(pw->iovdd);
684 regulator_disable(pw->avdd);
686 regulator_disable(pw->ext_reg1);
687 regulator_disable(pw->ext_reg2);
689 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
690 tegra_io_dpd_enable(&csia_io);
691 tegra_io_dpd_enable(&csib_io);
695 static int ardbeg_ar1335_power_on(struct ar1335_power_rail *pw)
699 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
702 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
703 tegra_io_dpd_disable(&csia_io);
704 tegra_io_dpd_disable(&csib_io);
706 gpio_set_value(CAM_RSTN, 0);
707 usleep_range(10, 20);
709 err = regulator_enable(pw->avdd);
711 goto ar1335_avdd_fail;
713 err = regulator_enable(pw->iovdd);
715 goto ar1335_iovdd_fail;
717 err = regulator_enable(pw->dvdd);
719 goto ar1335_dvdd_fail;
722 gpio_set_value(CAM_RSTN, 1);
724 usleep_range(300, 310);
729 regulator_disable(pw->iovdd);
732 regulator_disable(pw->avdd);
735 tegra_io_dpd_enable(&csia_io);
736 tegra_io_dpd_enable(&csib_io);
737 pr_err("%s failed.\n", __func__);
741 static int ardbeg_ar1335_power_off(struct ar1335_power_rail *pw)
743 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
744 tegra_io_dpd_enable(&csia_io);
745 tegra_io_dpd_enable(&csib_io);
749 regulator_disable(pw->iovdd);
750 regulator_disable(pw->avdd);
751 regulator_disable(pw->dvdd);
753 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
754 tegra_io_dpd_enable(&csia_io);
755 tegra_io_dpd_enable(&csib_io);
759 static int ardbeg_imx179_power_on(struct imx179_power_rail *pw)
763 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
766 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
767 tegra_io_dpd_disable(&csia_io);
768 tegra_io_dpd_disable(&csib_io);
770 gpio_set_value(CAM_AF_PWDN, 1);
771 gpio_set_value(CAM_RSTN, 0);
772 gpio_set_value(CAM1_PWDN, 0);
773 usleep_range(10, 20);
775 err = regulator_enable(pw->avdd);
777 goto imx179_avdd_fail;
779 err = regulator_enable(pw->iovdd);
781 goto imx179_iovdd_fail;
783 err = regulator_enable(pw->dvdd);
785 goto imx179_dvdd_fail;
788 gpio_set_value(CAM_RSTN, 1);
790 usleep_range(300, 310);
796 regulator_disable(pw->iovdd);
799 regulator_disable(pw->avdd);
802 tegra_io_dpd_enable(&csia_io);
803 tegra_io_dpd_enable(&csib_io);
804 pr_err("%s failed.\n", __func__);
808 static int ardbeg_imx179_power_off(struct imx179_power_rail *pw)
810 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
811 tegra_io_dpd_enable(&csia_io);
812 tegra_io_dpd_enable(&csib_io);
816 regulator_disable(pw->dvdd);
817 regulator_disable(pw->iovdd);
818 regulator_disable(pw->avdd);
820 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
821 tegra_io_dpd_enable(&csia_io);
822 tegra_io_dpd_enable(&csib_io);
826 struct ar1335_platform_data ardbeg_ar1335_data = {
834 .power_on = ardbeg_ar1335_power_on,
835 .power_off = ardbeg_ar1335_power_off,
837 static int ardbeg_imx185_power_on(struct imx185_power_rail *pw)
841 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
844 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
845 tegra_io_dpd_disable(&csia_io);
846 tegra_io_dpd_disable(&csib_io);
848 gpio_set_value(CAM1_PWDN, 0);
849 usleep_range(10, 20);
851 err = regulator_enable(pw->dvdd);
853 goto imx185_dvdd_fail;
855 err = regulator_enable(pw->iovdd);
857 goto imx185_iovdd_fail;
859 err = regulator_enable(pw->avdd);
861 goto imx185_avdd_fail;
864 gpio_set_value(CAM1_PWDN, 1);
866 usleep_range(300, 310);
872 regulator_disable(pw->iovdd);
875 regulator_disable(pw->dvdd);
878 tegra_io_dpd_enable(&csia_io);
879 tegra_io_dpd_enable(&csib_io);
880 pr_err("%s failed.\n", __func__);
884 static int ardbeg_imx185_power_off(struct imx185_power_rail *pw)
886 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
887 tegra_io_dpd_enable(&csia_io);
888 tegra_io_dpd_enable(&csib_io);
892 regulator_disable(pw->avdd);
893 regulator_disable(pw->iovdd);
894 regulator_disable(pw->dvdd);
896 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
897 tegra_io_dpd_enable(&csia_io);
898 tegra_io_dpd_enable(&csib_io);
902 struct imx135_platform_data ardbeg_imx135_data = {
911 .power_on = ardbeg_imx135_power_on,
912 .power_off = ardbeg_imx135_power_off,
915 struct imx179_platform_data ardbeg_imx179_data = {
923 .power_on = ardbeg_imx179_power_on,
924 .power_off = ardbeg_imx179_power_off,
927 struct ov4689_platform_data ardbeg_ov4689_data = {
935 .power_on = ardbeg_ov4689_power_on,
936 .power_off = ardbeg_ov4689_power_off,
939 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
942 pr_info("%s\n", __func__);
944 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
947 err = regulator_enable(pw->vdd);
949 goto dw9718_vdd_fail;
951 err = regulator_enable(pw->vdd_i2c);
953 goto dw9718_i2c_fail;
955 err = regulator_enable(pw->vana);
957 goto dw9718_ana_fail;
959 usleep_range(1000, 1020);
961 /* return 1 to skip the in-driver power_on sequence */
962 pr_debug("%s --\n", __func__);
966 regulator_disable(pw->vdd_i2c);
969 regulator_disable(pw->vdd);
972 pr_err("%s FAILED\n", __func__);
976 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
978 pr_info("%s\n", __func__);
980 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
983 regulator_disable(pw->vdd);
984 regulator_disable(pw->vdd_i2c);
985 regulator_disable(pw->vana);
990 static u16 dw9718_devid;
991 static int ardbeg_dw9718_detect(void *buf, size_t size)
993 dw9718_devid = 0x9718;
997 static struct nvc_focus_cap dw9718_cap = {
999 .slew_rate = 0x3A200C,
1001 .focus_infinity = 200,
1005 static struct dw9718_platform_data ardbeg_dw9718_data = {
1006 .cfg = NVC_CFG_NODEV,
1009 .dev_name = "focuser",
1011 .power_on = ardbeg_dw9718_power_on,
1012 .power_off = ardbeg_dw9718_power_off,
1013 .detect = ardbeg_dw9718_detect,
1016 static struct as364x_platform_data ardbeg_as3648_data = {
1019 .max_total_current_mA = 1000,
1020 .max_peak_current_mA = 600,
1021 .max_torch_current_mA = 600,
1022 .vin_low_v_run_mV = 3070,
1026 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
1027 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
1029 .dev_name = "torch",
1031 .gpio_strobe = CAM_FLASH_STROBE,
1034 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
1038 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
1041 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
1042 tegra_io_dpd_disable(&csie_io);
1044 gpio_set_value(CAM2_PWDN, 0);
1045 usleep_range(1000, 1020);
1047 err = regulator_enable(pw->avdd);
1049 goto ov7695_avdd_fail;
1050 usleep_range(300, 320);
1052 err = regulator_enable(pw->iovdd);
1054 goto ov7695_iovdd_fail;
1055 usleep_range(1000, 1020);
1057 gpio_set_value(CAM2_PWDN, 1);
1058 usleep_range(1000, 1020);
1063 regulator_disable(pw->avdd);
1066 gpio_set_value(CAM_RSTN, 0);
1067 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1068 tegra_io_dpd_enable(&csie_io);
1072 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
1074 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
1075 /* put CSIE IOs into DPD mode to
1076 * save additional power for ardbeg
1078 tegra_io_dpd_enable(&csie_io);
1081 usleep_range(100, 120);
1083 gpio_set_value(CAM2_PWDN, 0);
1084 usleep_range(100, 120);
1086 regulator_disable(pw->iovdd);
1087 usleep_range(100, 120);
1089 regulator_disable(pw->avdd);
1091 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1092 tegra_io_dpd_enable(&csie_io);
1096 struct ov7695_platform_data ardbeg_ov7695_pdata = {
1097 .power_on = ardbeg_ov7695_power_on,
1098 .power_off = ardbeg_ov7695_power_off,
1099 .mclk_name = "mclk2",
1102 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
1105 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
1108 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
1109 tegra_io_dpd_disable(&csie_io);
1111 gpio_set_value(CAM_RSTN, 0);
1112 gpio_set_value(CAM2_PWDN, 1);
1113 usleep_range(1000, 1020);
1115 err = regulator_enable(pw->iovdd);
1117 goto mt9m114_iovdd_fail;
1119 err = regulator_enable(pw->avdd);
1121 goto mt9m114_avdd_fail;
1123 usleep_range(1000, 1020);
1124 gpio_set_value(CAM_RSTN, 1);
1125 gpio_set_value(CAM2_PWDN, 0);
1126 usleep_range(1000, 1020);
1128 /* return 1 to skip the in-driver power_on swquence */
1132 regulator_disable(pw->iovdd);
1135 gpio_set_value(CAM_RSTN, 0);
1136 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1137 tegra_io_dpd_enable(&csie_io);
1141 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
1143 if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
1144 /* put CSIE IOs into DPD mode to
1145 * save additional power for ardbeg
1147 tegra_io_dpd_enable(&csie_io);
1151 usleep_range(100, 120);
1152 gpio_set_value(CAM_RSTN, 0);
1153 usleep_range(100, 120);
1154 regulator_disable(pw->avdd);
1155 usleep_range(100, 120);
1156 regulator_disable(pw->iovdd);
1158 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1159 tegra_io_dpd_enable(&csie_io);
1163 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
1164 .power_on = ardbeg_mt9m114_power_on,
1165 .power_off = ardbeg_mt9m114_power_off,
1166 .mclk_name = "mclk2",
1170 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
1174 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1177 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
1178 tegra_io_dpd_disable(&csia_io);
1179 tegra_io_dpd_disable(&csib_io);
1181 if (ardbeg_get_extra_regulators())
1182 goto ov5693_poweron_fail;
1184 gpio_set_value(CAM1_PWDN, 0);
1185 usleep_range(10, 20);
1187 err = regulator_enable(pw->avdd);
1189 goto ov5693_avdd_fail;
1191 err = regulator_enable(pw->dovdd);
1193 goto ov5693_iovdd_fail;
1196 gpio_set_value(CAM1_PWDN, 1);
1198 err = regulator_enable(ardbeg_vcmvdd);
1200 goto ov5693_vcmvdd_fail;
1202 usleep_range(1000, 1110);
1207 regulator_disable(pw->dovdd);
1210 regulator_disable(pw->avdd);
1213 gpio_set_value(CAM1_PWDN, 0);
1215 ov5693_poweron_fail:
1216 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1217 tegra_io_dpd_enable(&csia_io);
1218 tegra_io_dpd_enable(&csib_io);
1219 pr_err("%s FAILED\n", __func__);
1223 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
1225 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1226 /* put CSIA/B IOs into DPD mode to
1227 * save additional power for ardbeg
1229 tegra_io_dpd_enable(&csia_io);
1230 tegra_io_dpd_enable(&csib_io);
1234 usleep_range(21, 25);
1235 gpio_set_value(CAM1_PWDN, 0);
1238 regulator_disable(ardbeg_vcmvdd);
1239 regulator_disable(pw->dovdd);
1240 regulator_disable(pw->avdd);
1242 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1243 tegra_io_dpd_enable(&csia_io);
1244 tegra_io_dpd_enable(&csib_io);
1248 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
1249 { OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0, },
1252 #define NV_GUID(a, b, c, d, e, f, g, h) \
1253 ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
1254 (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
1255 (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
1256 (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
1258 static struct nvc_imager_cap ov5693_cap = {
1259 .identifier = "OV5693",
1260 .sensor_nvc_interface = 3,
1261 .pixel_types[0] = 0x101,
1264 .initial_clock_rate_khz = 6000,
1265 .clock_profiles[0] = {
1266 .external_clock_khz = 24000,
1267 .clock_multiplier = 8000000, /* value * 1000000 */
1269 .clock_profiles[1] = {
1270 .external_clock_khz = 0,
1271 .clock_multiplier = 0,
1278 .virtual_channel_id = 0,
1279 .discontinuous_clk_mode = 1,
1280 .cil_threshold_settle = 0,
1281 .min_blank_time_width = 16,
1282 .min_blank_time_height = 16,
1283 .preferred_mode_index = 0,
1285 NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
1287 NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
1288 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1289 .flash_control_enabled = 0,
1290 .adjustable_flash_timing = 0,
1295 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
1296 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
1297 .gpio = ov5693_gpio_pdata,
1298 .power_on = ardbeg_ov5693_power_on,
1299 .power_off = ardbeg_ov5693_power_off,
1300 .dev_name = "ov5693",
1302 .mclk_name = "mclk",
1304 .avdd = "avdd_ov5693",
1311 static struct imx185_platform_data ardbeg_imx185_data = {
1312 .power_on = ardbeg_imx185_power_on,
1313 .power_off = ardbeg_imx185_power_off,
1314 .mclk_name = "mclk",
1317 static int ardbeg_ov5693_front_power_on(struct ov5693_power_rail *pw)
1321 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1324 if (ardbeg_get_extra_regulators())
1325 goto ov5693_front_poweron_fail;
1327 gpio_set_value(CAM2_PWDN, 0);
1328 gpio_set_value(CAM_RSTN, 0);
1329 usleep_range(10, 20);
1331 err = regulator_enable(pw->avdd);
1333 goto ov5693_front_avdd_fail;
1335 err = regulator_enable(pw->dovdd);
1337 goto ov5693_front_iovdd_fail;
1340 gpio_set_value(CAM2_PWDN, 1);
1341 gpio_set_value(CAM_RSTN, 1);
1343 err = regulator_enable(ardbeg_vcmvdd);
1345 goto ov5693_front_vcmvdd_fail;
1347 usleep_range(1000, 1110);
1351 ov5693_front_vcmvdd_fail:
1352 regulator_disable(pw->dovdd);
1354 ov5693_front_iovdd_fail:
1355 regulator_disable(pw->avdd);
1357 ov5693_front_avdd_fail:
1358 gpio_set_value(CAM2_PWDN, 0);
1359 gpio_set_value(CAM_RSTN, 0);
1361 ov5693_front_poweron_fail:
1362 pr_err("%s FAILED\n", __func__);
1366 static int ardbeg_ov5693_front_power_off(struct ov5693_power_rail *pw)
1368 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1372 usleep_range(21, 25);
1373 gpio_set_value(CAM2_PWDN, 0);
1374 gpio_set_value(CAM_RSTN, 0);
1377 regulator_disable(ardbeg_vcmvdd);
1378 regulator_disable(pw->dovdd);
1379 regulator_disable(pw->avdd);
1384 static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
1385 { OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0, },
1386 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
1389 static struct nvc_imager_cap ov5693_front_cap = {
1390 .identifier = "OV5693.1",
1391 .sensor_nvc_interface = 4,
1392 .pixel_types[0] = 0x101,
1395 .initial_clock_rate_khz = 6000,
1396 .clock_profiles[0] = {
1397 .external_clock_khz = 24000,
1398 .clock_multiplier = 8000000, /* value * 1000000 */
1400 .clock_profiles[1] = {
1401 .external_clock_khz = 0,
1402 .clock_multiplier = 0,
1409 .virtual_channel_id = 0,
1410 .discontinuous_clk_mode = 1,
1411 .cil_threshold_settle = 0,
1412 .min_blank_time_width = 16,
1413 .min_blank_time_height = 16,
1414 .preferred_mode_index = 0,
1417 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1418 .flash_control_enabled = 0,
1419 .adjustable_flash_timing = 0,
1423 static struct ov5693_platform_data ardbeg_ov5693_front_pdata = {
1424 .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
1425 .gpio = ov5693_front_gpio_pdata,
1426 .power_on = ardbeg_ov5693_front_power_on,
1427 .power_off = ardbeg_ov5693_front_power_off,
1428 .dev_name = "ov5693.1",
1429 .mclk_name = "mclk2",
1430 .cap = &ov5693_front_cap,
1439 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
1443 pr_info("%s\n", __func__);
1444 gpio_set_value_cansleep(pdata->gpio, 1);
1445 pdata->pwr_dev = AD5823_PWR_DEV_ON;
1450 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
1452 pr_info("%s\n", __func__);
1453 gpio_set_value_cansleep(pdata->gpio, 0);
1454 pdata->pwr_dev = AD5823_PWR_DEV_OFF;
1459 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
1460 .gpio = CAM_AF_PWDN,
1461 .power_on = ardbeg_ad5823_power_on,
1462 .power_off = ardbeg_ad5823_power_off,
1465 static struct camera_data_blob ardbeg_camera_lut[] = {
1466 {"ardbeg_imx135_pdata", &ardbeg_imx135_data},
1467 {"ardbeg_imx185_pdata", &ardbeg_imx185_data},
1468 {"ardbeg_dw9718_pdata", &ardbeg_dw9718_data},
1469 {"ardbeg_ar0261_pdata", &ardbeg_ar0261_data},
1470 {"ardbeg_mt9m114_pdata", &ardbeg_mt9m114_pdata},
1471 {"ardbeg_ov5693_pdata", &ardbeg_ov5693_pdata},
1472 {"ardbeg_ad5823_pdata", &ardbeg_ad5823_pdata},
1473 {"ardbeg_as3648_pdata", &ardbeg_as3648_data},
1474 {"ardbeg_ov7695_pdata", &ardbeg_ov7695_pdata},
1475 {"ardbeg_ov5693f_pdata", &ardbeg_ov5693_front_pdata},
1476 {"ardbeg_ar0330_pdata", &ardbeg_ar0330_data},
1477 {"ardbeg_ar0330_front_pdata", &ardbeg_ar0330_front_data},
1478 {"ardbeg_ov4689_pdata", &ardbeg_ov4689_data},
1479 {"ardbeg_ar1335_pdata", &ardbeg_ar1335_data},
1483 void __init ardbeg_camera_auxdata(void *data)
1485 struct of_dev_auxdata *aux_lut = data;
1486 while (aux_lut && aux_lut->compatible) {
1487 if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
1488 pr_info("%s: update camera lookup table.\n", __func__);
1489 aux_lut->platform_data = ardbeg_camera_lut;
1495 static int ardbeg_camera_init(void)
1497 struct board_info board_info;
1499 pr_debug("%s: ++\n", __func__);
1500 tegra_get_board_info(&board_info);
1502 /* put CSIA/B/C/D/E IOs into DPD mode to
1503 * save additional power for ardbeg
1505 tegra_io_dpd_enable(&csia_io);
1506 tegra_io_dpd_enable(&csib_io);
1507 tegra_io_dpd_enable(&csie_io);
1509 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
1510 platform_device_register(&ardbeg_soc_camera_device);
1513 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
1514 platform_device_register(&ardbeg_imx135_soc_camera_device);
1517 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
1518 platform_device_register(&ardbeg_ar0261_soc_camera_device);
1523 static struct pid_thermal_gov_params cpu_pid_params = {
1524 .max_err_temp = 4000,
1525 .max_err_gain = 1000,
1530 .up_compensation = 15,
1531 .down_compensation = 15,
1534 static struct thermal_zone_params cpu_tzp = {
1535 .governor_name = "pid_thermal_gov",
1536 .governor_params = &cpu_pid_params,
1539 static struct thermal_zone_params board_tzp = {
1540 .governor_name = "pid_thermal_gov"
1543 static struct throttle_table cpu_throttle_table[] = {
1544 /* CPU_THROT_LOW cannot be used by other than CPU */
1545 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1546 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1547 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1548 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1549 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1550 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1551 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1552 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1553 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1554 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1555 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1556 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1557 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1558 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1559 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1560 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1561 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1562 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1563 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1564 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1565 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1566 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1567 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1568 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1569 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1570 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1571 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1572 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1573 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1574 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1575 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1576 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1577 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1578 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1579 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1580 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1581 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1582 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1583 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1584 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1585 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1586 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1587 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1588 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1589 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1590 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1591 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1592 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1593 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1594 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1595 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1596 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1597 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1598 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1599 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1600 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1601 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1602 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1603 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1604 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1605 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1606 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1607 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1608 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1609 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1610 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1611 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1612 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1613 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1614 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1615 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1616 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1617 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1618 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1619 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1620 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1621 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1622 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1623 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1624 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1625 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1626 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1627 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1628 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1631 static struct balanced_throttle cpu_throttle = {
1632 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1633 .throt_tab = cpu_throttle_table,
1636 static struct throttle_table gpu_throttle_table[] = {
1637 /* CPU_THROT_LOW cannot be used by other than CPU */
1638 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1639 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1640 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1641 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1642 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1643 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1644 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1645 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1646 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1647 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1648 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1649 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1650 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1651 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1652 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1653 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1654 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1655 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1656 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1657 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1658 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1659 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1660 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1661 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1662 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1663 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1664 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1665 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1666 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1667 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1668 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1669 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1670 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1671 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1672 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1673 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1674 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1675 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1676 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1677 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1678 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1679 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1680 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1681 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1682 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1683 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1684 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1685 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1686 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1687 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1688 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1689 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1690 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1691 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1692 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1693 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1694 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1695 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1696 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1697 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1698 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1699 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1700 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1701 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1702 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1703 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1704 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1705 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1706 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1707 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1708 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1709 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1710 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1711 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1712 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1713 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1714 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1715 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1716 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1717 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1718 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1719 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1720 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1721 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1724 static struct balanced_throttle gpu_throttle = {
1725 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1726 .throt_tab = gpu_throttle_table,
1729 /* throttle table that sets all clocks to approximately 50% of their max */
1730 static struct throttle_table emergency_throttle_table[] = {
1731 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1732 { { 1122000, 391000, 288000, 420000, 252000, 396000 } },
1735 static struct balanced_throttle emergency_throttle = {
1736 .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
1737 .throt_tab = emergency_throttle_table,
1740 static int __init ardbeg_balanced_throttle_init(void)
1742 if (of_machine_is_compatible("nvidia,ardbeg") ||
1743 of_machine_is_compatible("nvidia,norrin") ||
1744 of_machine_is_compatible("nvidia,bowmore") ||
1745 of_machine_is_compatible("nvidia,tn8")) {
1747 if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
1748 pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
1749 if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
1750 pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
1751 if (!balanced_throttle_register(&emergency_throttle,
1752 "emergency-balanced"))
1753 pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
1758 late_initcall(ardbeg_balanced_throttle_init);
1760 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1761 static struct thermal_trip_info skin_trips[] = {
1763 .cdev_type = "skin-balanced",
1765 .trip_type = THERMAL_TRIP_PASSIVE,
1766 .upper = THERMAL_NO_LIMIT,
1767 .lower = THERMAL_NO_LIMIT,
1772 static struct therm_est_subdevice skin_devs[] = {
1774 .dev_data = "Tdiode_tegra",
1784 .dev_data = "Tboard_tegra",
1795 static struct therm_est_subdevice tn8ffd_skin_devs[] = {
1797 .dev_data = "Tdiode",
1807 .dev_data = "Tboard",
1818 static struct therm_est_subdevice tn8ffd_t132_skin_devs[] = {
1820 .dev_data = "Tdiode",
1830 .dev_data = "Tboard",
1841 static struct pid_thermal_gov_params skin_pid_params = {
1842 .max_err_temp = 4000,
1843 .max_err_gain = 1000,
1848 .up_compensation = 15,
1849 .down_compensation = 15,
1852 static struct thermal_zone_params skin_tzp = {
1853 .governor_name = "pid_thermal_gov",
1854 .governor_params = &skin_pid_params,
1857 static struct therm_est_data skin_data = {
1858 .num_trips = ARRAY_SIZE(skin_trips),
1859 .trips = skin_trips,
1860 .polling_period = 1100,
1861 .passive_delay = 15000,
1868 static struct throttle_table skin_throttle_table[] = {
1869 /* CPU_THROT_LOW cannot be used by other than CPU */
1870 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1871 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1872 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1873 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1874 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1875 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1876 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1877 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1878 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1879 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1880 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1881 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1882 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1883 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1884 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1885 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1886 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1887 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1888 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1889 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1890 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1891 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1892 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1893 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1894 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1895 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1896 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1897 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1898 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1899 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1900 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1901 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1902 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1903 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1904 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1905 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1906 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1907 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1908 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1909 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1910 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1911 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1912 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1913 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1914 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1915 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1916 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1917 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1918 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1919 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1920 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1921 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1922 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1923 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1924 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1925 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1926 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1927 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1928 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1929 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1930 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1931 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1932 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1933 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1934 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1935 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1936 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1937 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1938 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1939 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1940 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1941 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1942 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1943 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1944 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1945 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1946 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1947 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1948 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1949 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1950 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1951 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1952 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1953 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1956 static struct balanced_throttle skin_throttle = {
1957 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1958 .throt_tab = skin_throttle_table,
1961 static int __init ardbeg_skin_init(void)
1963 struct board_info board_info;
1965 if (of_machine_is_compatible("nvidia,ardbeg") ||
1966 of_machine_is_compatible("nvidia,norrin") ||
1967 of_machine_is_compatible("nvidia,bowmore") ||
1968 of_machine_is_compatible("nvidia,tn8")) {
1970 tegra_get_board_info(&board_info);
1972 if (board_info.board_id == BOARD_P1761 &&
1973 board_info.fab == BOARD_FAB_D) {
1974 skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
1975 skin_data.devs = tn8ffd_t132_skin_devs;
1976 skin_data.toffset = 708;
1977 } else if (board_info.board_id == BOARD_P1761 ||
1978 board_info.board_id == BOARD_E1784 ||
1979 board_info.board_id == BOARD_E1971 ||
1980 board_info.board_id == BOARD_E1991 ||
1981 board_info.board_id == BOARD_E1922) {
1982 skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
1983 skin_data.devs = tn8ffd_skin_devs;
1984 skin_data.toffset = 4034;
1986 skin_data.ndevs = ARRAY_SIZE(skin_devs);
1987 skin_data.devs = skin_devs;
1988 skin_data.toffset = 9793;
1991 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1992 platform_device_register(&tegra_skin_therm_est_device);
1994 if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
1995 pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
2000 late_initcall(ardbeg_skin_init);
2003 static struct nct1008_platform_data ardbeg_nct72_pdata = {
2004 .loc_name = "tegra",
2005 .supported_hwrev = true,
2006 .conv_rate = 0x06, /* 4Hz conversion rate */
2008 .extended_range = true,
2013 .shutdown_limit = 120, /* C */
2014 .passive_delay = 1000,
2018 .cdev_type = "therm_est_activ",
2020 .trip_type = THERMAL_TRIP_ACTIVE,
2022 .upper = THERMAL_NO_LIMIT,
2023 .lower = THERMAL_NO_LIMIT,
2030 .shutdown_limit = 95, /* C */
2031 .passive_delay = 1000,
2035 .cdev_type = "shutdown_warning",
2037 .trip_type = THERMAL_TRIP_PASSIVE,
2038 .upper = THERMAL_NO_LIMIT,
2039 .lower = THERMAL_NO_LIMIT,
2043 .cdev_type = "cpu-balanced",
2045 .trip_type = THERMAL_TRIP_PASSIVE,
2046 .upper = THERMAL_NO_LIMIT,
2047 .lower = THERMAL_NO_LIMIT,
2056 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
2057 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
2060 .supported_hwrev = true,
2061 .conv_rate = 0x06, /* 4Hz conversion rate */
2063 .extended_range = true,
2067 .shutdown_limit = 95, /* C */
2072 .shutdown_limit = 85, /* C */
2073 .passive_delay = 10000,
2074 .polling_delay = 1000,
2079 .cdev_type = "skin-balanced",
2081 .trip_type = THERMAL_TRIP_PASSIVE,
2082 .upper = THERMAL_NO_LIMIT,
2083 .lower = THERMAL_NO_LIMIT,
2092 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
2094 I2C_BOARD_INFO("nct72", 0x4c),
2095 .platform_data = &ardbeg_nct72_pdata,
2098 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
2100 I2C_BOARD_INFO("nct72", 0x4d),
2101 .platform_data = &ardbeg_nct72_tskin_pdata,
2107 static int ardbeg_nct72_init(void)
2109 int nct72_port = TEGRA_GPIO_PI6;
2112 struct thermal_trip_info *trip_state;
2113 struct board_info board_info;
2115 tegra_get_board_info(&board_info);
2116 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
2117 if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
2118 (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
2119 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit += 20;
2120 for (i = 0; i < ardbeg_nct72_pdata.sensors[EXT].num_trips;
2122 trip_state = &ardbeg_nct72_pdata.sensors[EXT].trips[i];
2123 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
2124 THERMAL_NAME_LENGTH)) {
2125 trip_state->cdev_type = "_none_";
2130 tegra_platform_edp_init(
2131 ardbeg_nct72_pdata.sensors[EXT].trips,
2132 &ardbeg_nct72_pdata.sensors[EXT].num_trips,
2133 12000); /* edp temperature margin */
2134 tegra_add_cpu_vmax_trips(
2135 ardbeg_nct72_pdata.sensors[EXT].trips,
2136 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2137 tegra_add_tgpu_trips(
2138 ardbeg_nct72_pdata.sensors[EXT].trips,
2139 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2141 ardbeg_nct72_pdata.sensors[EXT].trips,
2142 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2143 tegra_add_core_vmax_trips(
2144 ardbeg_nct72_pdata.sensors[EXT].trips,
2145 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2148 /* vmin trips are bound to soctherm on norrin */
2149 if (!(board_info.board_id == BOARD_PM374) &&
2150 !(board_info.board_id == BOARD_PM375))
2151 tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
2152 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2154 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
2156 ret = gpio_request(nct72_port, "temp_alert");
2160 ret = gpio_direction_input(nct72_port);
2162 pr_info("%s: calling gpio_free(nct72_port)", __func__);
2163 gpio_free(nct72_port);
2166 /* norrin has thermal sensor on GEN1-I2C i.e. instance 0 */
2167 if (board_info.board_id == BOARD_PM374)
2168 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2169 1); /* only register device[0] */
2170 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
2171 else if (board_info.board_id == BOARD_PM358 ||
2172 board_info.board_id == BOARD_PM359 ||
2173 board_info.board_id == BOARD_PM370 ||
2174 board_info.board_id == BOARD_PM363)
2175 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2176 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2177 else if (board_info.board_id == BOARD_PM375 ||
2178 board_info.board_id == BOARD_PM377) {
2179 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 105;
2180 ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 100;
2181 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2182 1); /* only register device[0] */
2185 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2186 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2191 struct ntc_thermistor_adc_table {
2192 int temp; /* degree C */
2196 static struct ntc_thermistor_adc_table tn8_thermistor_table[] = {
2197 { -40, 2578 }, { -39, 2577 }, { -38, 2576 }, { -37, 2575 },
2198 { -36, 2574 }, { -35, 2573 }, { -34, 2572 }, { -33, 2571 },
2199 { -32, 2569 }, { -31, 2568 }, { -30, 2567 }, { -29, 2565 },
2200 { -28, 2563 }, { -27, 2561 }, { -26, 2559 }, { -25, 2557 },
2201 { -24, 2555 }, { -23, 2553 }, { -22, 2550 }, { -21, 2548 },
2202 { -20, 2545 }, { -19, 2542 }, { -18, 2539 }, { -17, 2536 },
2203 { -16, 2532 }, { -15, 2529 }, { -14, 2525 }, { -13, 2521 },
2204 { -12, 2517 }, { -11, 2512 }, { -10, 2507 }, { -9, 2502 },
2205 { -8, 2497 }, { -7, 2492 }, { -6, 2486 }, { -5, 2480 },
2206 { -4, 2473 }, { -3, 2467 }, { -2, 2460 }, { -1, 2452 },
2207 { 0, 2445 }, { 1, 2437 }, { 2, 2428 }, { 3, 2419 },
2208 { 4, 2410 }, { 5, 2401 }, { 6, 2391 }, { 7, 2380 },
2209 { 8, 2369 }, { 9, 2358 }, { 10, 2346 }, { 11, 2334 },
2210 { 12, 2322 }, { 13, 2308 }, { 14, 2295 }, { 15, 2281 },
2211 { 16, 2266 }, { 17, 2251 }, { 18, 2236 }, { 19, 2219 },
2212 { 20, 2203 }, { 21, 2186 }, { 22, 2168 }, { 23, 2150 },
2213 { 24, 2131 }, { 25, 2112 }, { 26, 2092 }, { 27, 2072 },
2214 { 28, 2052 }, { 29, 2030 }, { 30, 2009 }, { 31, 1987 },
2215 { 32, 1964 }, { 33, 1941 }, { 34, 1918 }, { 35, 1894 },
2216 { 36, 1870 }, { 37, 1845 }, { 38, 1820 }, { 39, 1795 },
2217 { 40, 1769 }, { 41, 1743 }, { 42, 1717 }, { 43, 1691 },
2218 { 44, 1664 }, { 45, 1637 }, { 46, 1610 }, { 47, 1583 },
2219 { 48, 1555 }, { 49, 1528 }, { 50, 1500 }, { 51, 1472 },
2220 { 52, 1445 }, { 53, 1417 }, { 54, 1390 }, { 55, 1362 },
2221 { 56, 1334 }, { 57, 1307 }, { 58, 1280 }, { 59, 1253 },
2222 { 60, 1226 }, { 61, 1199 }, { 62, 1172 }, { 63, 1146 },
2223 { 64, 1120 }, { 65, 1094 }, { 66, 1069 }, { 67, 1044 },
2224 { 68, 1019 }, { 69, 994 }, { 70, 970 }, { 71, 946 },
2225 { 72, 922 }, { 73, 899 }, { 74, 877 }, { 75, 854 },
2226 { 76, 832 }, { 77, 811 }, { 78, 789 }, { 79, 769 },
2227 { 80, 748 }, { 81, 729 }, { 82, 709 }, { 83, 690 },
2228 { 84, 671 }, { 85, 653 }, { 86, 635 }, { 87, 618 },
2229 { 88, 601 }, { 89, 584 }, { 90, 568 }, { 91, 552 },
2230 { 92, 537 }, { 93, 522 }, { 94, 507 }, { 95, 493 },
2231 { 96, 479 }, { 97, 465 }, { 98, 452 }, { 99, 439 },
2232 { 100, 427 }, { 101, 415 }, { 102, 403 }, { 103, 391 },
2233 { 104, 380 }, { 105, 369 }, { 106, 359 }, { 107, 349 },
2234 { 108, 339 }, { 109, 329 }, { 110, 320 }, { 111, 310 },
2235 { 112, 302 }, { 113, 293 }, { 114, 285 }, { 115, 277 },
2236 { 116, 269 }, { 117, 261 }, { 118, 254 }, { 119, 247 },
2237 { 120, 240 }, { 121, 233 }, { 122, 226 }, { 123, 220 },
2238 { 124, 214 }, { 125, 208 },
2241 static struct ntc_thermistor_adc_table *thermistor_table;
2242 static int thermistor_table_size;
2244 static int gadc_thermal_thermistor_adc_to_temp(
2245 struct gadc_thermal_platform_data *pdata, int val, int val2)
2247 int temp = 0, adc_hi, adc_lo;
2250 for (i = 0; i < thermistor_table_size; i++)
2251 if (val >= thermistor_table[i].adc)
2255 temp = thermistor_table[i].temp * 1000;
2256 } else if (i >= (thermistor_table_size - 1)) {
2257 temp = thermistor_table[thermistor_table_size - 1].temp * 1000;
2259 adc_hi = thermistor_table[i - 1].adc;
2260 adc_lo = thermistor_table[i].adc;
2261 temp = thermistor_table[i].temp * 1000;
2262 temp -= ((val - adc_lo) * 1000 / (adc_hi - adc_lo));
2268 #define TDIODE_PRECISION_MULTIPLIER 1000000000LL
2269 #define TDIODE_MIN_TEMP -25000LL
2270 #define TDIODE_MAX_TEMP 125000LL
2272 static int gadc_thermal_tdiode_adc_to_temp(
2273 struct gadc_thermal_platform_data *pdata, int val, int val2)
2276 * Series resistance cancellation using multi-current ADC measurement.
2277 * diode temp = ((adc2 - k * adc1) - (b2 - k * b1)) / (m2 - k * m1)
2278 * - adc1 : ADC raw with current source 400uA
2279 * - m1, b1 : calculated with current source 400uA
2280 * - adc2 : ADC raw with current source 800uA
2281 * - m2, b2 : calculated with current source 800uA
2282 * - k : 2 (= 800uA / 400uA)
2284 const s64 m1 = -0.00571005 * TDIODE_PRECISION_MULTIPLIER;
2285 const s64 b1 = 2524.29891 * TDIODE_PRECISION_MULTIPLIER;
2286 const s64 m2 = -0.005519811 * TDIODE_PRECISION_MULTIPLIER;
2287 const s64 b2 = 2579.354349 * TDIODE_PRECISION_MULTIPLIER;
2288 s64 temp = TDIODE_PRECISION_MULTIPLIER;
2290 temp *= (s64)((val2) - 2 * (val));
2291 temp -= (b2 - 2 * b1);
2292 temp = div64_s64(temp, (m2 - 2 * m1));
2293 temp = min_t(s64, max_t(s64, temp, TDIODE_MIN_TEMP), TDIODE_MAX_TEMP);
2297 static struct gadc_thermal_platform_data gadc_thermal_thermistor_pdata = {
2298 .iio_channel_name = "thermistor",
2299 .tz_name = "Tboard",
2301 .adc_to_temp = gadc_thermal_thermistor_adc_to_temp,
2303 .polling_delay = 15000,
2307 .cdev_type = "therm_est_activ",
2309 .trip_type = THERMAL_TRIP_ACTIVE,
2311 .upper = THERMAL_NO_LIMIT,
2312 .lower = THERMAL_NO_LIMIT,
2319 static struct gadc_thermal_platform_data gadc_thermal_tdiode_pdata = {
2320 .iio_channel_name = "tdiode",
2321 .tz_name = "Tdiode",
2324 .adc_to_temp = gadc_thermal_tdiode_adc_to_temp,
2327 static struct platform_device gadc_thermal_thermistor = {
2328 .name = "generic-adc-thermal",
2331 .platform_data = &gadc_thermal_thermistor_pdata,
2335 static struct platform_device gadc_thermal_tdiode = {
2336 .name = "generic-adc-thermal",
2339 .platform_data = &gadc_thermal_tdiode_pdata,
2343 static struct platform_device *gadc_thermal_devices[] = {
2344 &gadc_thermal_thermistor,
2345 &gadc_thermal_tdiode,
2348 int __init ardbeg_sensors_init(void)
2350 struct board_info board_info;
2351 tegra_get_board_info(&board_info);
2352 /* PM363 and PM359 don't have mpu 9250 mounted */
2353 /* TN8 sensors use Device Tree */
2354 if (board_info.board_id != BOARD_PM363 &&
2355 board_info.board_id != BOARD_PM359 &&
2356 !of_machine_is_compatible("nvidia,tn8") &&
2357 !of_machine_is_compatible("nvidia,bowmore") &&
2358 board_info.board_id != BOARD_PM375 &&
2359 board_info.board_id != BOARD_PM377)
2361 ardbeg_camera_init();
2363 if (board_info.board_id == BOARD_P1761 ||
2364 board_info.board_id == BOARD_E1784 ||
2365 board_info.board_id == BOARD_E1971 ||
2366 board_info.board_id == BOARD_E1991 ||
2367 board_info.board_id == BOARD_E1922) {
2368 platform_add_devices(gadc_thermal_devices,
2369 ARRAY_SIZE(gadc_thermal_devices));
2370 thermistor_table = &tn8_thermistor_table[0];
2371 thermistor_table_size = ARRAY_SIZE(tn8_thermistor_table);
2373 ardbeg_nct72_init();
2375 #if defined(ARCH_TEGRA_12x_SOC)
2376 /* TN8 and PM359 don't have ALS CM32181 */
2377 if (!of_machine_is_compatible("nvidia,tn8") &&
2378 board_info.board_id != BOARD_PM359 &&
2379 board_info.board_id != BOARD_PM375 &&
2380 board_info.board_id != BOARD_PM377)
2381 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
2382 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));