drivers/usb/gadget/tegra_udc.c

   1 /*
   2  * Copyright (c) 2012-2016, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * Description:
   5  * High-speed USB device controller driver.
   6  * The driver is based on Freescale driver code from Li Yang and Jiang Bo.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #undef VERBOSE
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/ioport.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/mm.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/device.h>
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/otg.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dmapool.h>
  35 #include <linux/delay.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/extcon.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/err.h>
  40 #include <linux/io.h>
  41 #include <linux/of.h>
  42 #include <linux/of_device.h>
  43 #include <linux/pm_qos.h>
  44 #include <linux/usb/tegra_usb_phy.h>
  45 #include <linux/platform_data/tegra_usb.h>
  46 #include <linux/timer.h>
  47 #include <linux/tegra-soc.h>
  48
  49 #include <asm/byteorder.h>
  50 #include <asm/io.h>
  51 #include <asm/unaligned.h>
  52 #include <asm/dma.h>
  53
  54 /* HACK! This needs to come from DT */
  55 #include "../../../arch/arm/mach-tegra/iomap.h"
  56
  57 #include "tegra_udc.h"
  58
  59
  60 #define DRIVER_DESC     "Nvidia Tegra High-Speed USB Device Controller driver"
  61
  62 #define DRIVER_AUTHOR   "Venkat Moganty/Rakesh Bodla"
  63 #define DRIVER_VERSION  "Apr 30, 2012"
  64
  65 #define USB1_PREFETCH_ID        6
  66
  67 #define AHB_PREFETCH_BUFFER     SZ_128
  68
  69 #define get_ep_by_pipe(udc, pipe)       ((pipe == 1) ? &udc->eps[0] : \
  70                                                 &udc->eps[pipe])
  71 #define get_pipe_by_windex(windex)      ((windex & USB_ENDPOINT_NUMBER_MASK) \
  72                                         * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
  73
  74 #define ep_index(EP)    ((EP)->desc->bEndpointAddress&0xF)
  75 #define ep_is_in(EP)    ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
  76                                 USB_DIR_IN) : ((EP)->desc->bEndpointAddress \
  77                                 & USB_DIR_IN) == USB_DIR_IN)
  78
  79
  80 static const char driver_name[] = "tegra-udc";
  81 static const char driver_desc[] = DRIVER_DESC;
  82
  83 static void tegra_ep_fifo_flush(struct usb_ep *_ep);
  84 static int reset_queues(struct tegra_udc *udc);
  85
  86 /*
  87  * High speed test mode packet(53 bytes).
  88  * See USB 2.0 spec, section 7.1.20.
  89  */
  90 static const u8 tegra_udc_test_packet[53] = {
  91         /* JKJKJKJK x9 */
  92         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  93         /* JJKKJJKK x8 */
  94         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
  95         /* JJJJKKKK x8 */
  96         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
  97         /* JJJJJJJKKKKKKK x8 */
  98         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  99         /* JJJJJJJK x8 */
 100         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
 101         /* JKKKKKKK x10, JK */
 102         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
 103 };
 104
 105 static struct tegra_udc *the_udc;
 106
 107 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
 108 static struct pm_qos_request boost_cpu_freq_req;
 109 static u32 ep_queue_request_count;
 110 static u8 boost_cpufreq_work_flag, set_cpufreq_normal_flag;
 111 static struct timer_list boost_timer;
 112 static bool boost_enable = true;
 113 static int boost_enable_set(const char *arg, const struct kernel_param *kp)
 114 {
 115         bool old_boost = boost_enable;
 116         int ret = param_set_bool(arg, kp);
 117         if (ret == 0 && old_boost && !boost_enable)
 118                 pm_qos_update_request(&boost_cpu_freq_req,
 119                                       PM_QOS_DEFAULT_VALUE);
 120         return ret;
 121 }
 122 static int boost_enable_get(char *buffer, const struct kernel_param *kp)
 123 {
 124         return param_get_bool(buffer, kp);
 125 }
 126 static struct kernel_param_ops boost_enable_ops = {
 127         .set = boost_enable_set,
 128         .get = boost_enable_get,
 129 };
 130 module_param_cb(boost_enable, &boost_enable_ops, &boost_enable, 0644);
 131 #endif
 132
 133 static char *const tegra_udc_extcon_cable[] = {
 134         [CONNECT_TYPE_NONE] = "",
 135         [CONNECT_TYPE_SDP] = "USB",
 136         [CONNECT_TYPE_DCP] = "TA",
 137         [CONNECT_TYPE_DCP_QC2] = "QC2",
 138         [CONNECT_TYPE_DCP_MAXIM] = "MAXIM",
 139         [CONNECT_TYPE_CDP] = "Charge-downstream",
 140         [CONNECT_TYPE_NV_CHARGER] = "Fast-charger",
 141         [CONNECT_TYPE_NON_STANDARD_CHARGER] = "Slow-charger",
 142         [CONNECT_TYPE_APPLE_500MA]  = "Apple 500mA-charger",
 143         [CONNECT_TYPE_APPLE_1000MA] = "Apple 1A-charger",
 144         [CONNECT_TYPE_APPLE_2000MA] = "Apple 2A-charger",
 145         [CONNECT_TYPE_ACA_NV_CHARGER] = "ACA NV-Charger",
 146         [CONNECT_TYPE_ACA_RID_B] = "ACA RID-B",
 147         [CONNECT_TYPE_ACA_RID_C] = "ACA RID-C",
 148         NULL,
 149 };
 150
 151 static inline void udc_writel(struct tegra_udc *udc, u32 val, u32 offset)
 152 {
 153         writel(val, udc->regs + offset);
 154 }
 155
 156 static inline unsigned int udc_readl(struct tegra_udc *udc, u32 offset)
 157 {
 158         return readl(udc->regs + offset);
 159 }
 160
 161 /* checks vbus status */
 162 static inline bool vbus_enabled(struct tegra_udc *udc)
 163 {
 164         bool status = false;
 165         if (tegra_platform_is_fpga()) {
 166                 /* On FPGA VBUS is detected through VBUS A Session instead
 167                  * of VBUS status.*/
 168                 status = (udc_readl(udc, VBUS_SENSOR_REG_OFFSET)
 169                                                 & USB_SYS_VBUS_ASESSION);
 170         } else if (udc->support_pmu_vbus) {
 171                 if (udc->vbus_extcon_dev &&
 172                         extcon_get_cable_state(udc->vbus_extcon_dev, "USB"))
 173                         return true;
 174
 175                 if (udc->aca_nv_extcon_cable &&
 176                         extcon_get_cable_state_(udc->aca_nv_extcon_dev,
 177                         udc->aca_nv_extcon_cable->cable_index))
 178                         return true;
 179
 180                 if (udc->aca_rid_b_ecable &&
 181                         extcon_get_cable_state_(udc->aca_rid_b_ecable->edev,
 182                         udc->aca_rid_b_ecable->cable_index))
 183                         return true;
 184
 185                 if (udc->aca_rid_c_ecable &&
 186                         extcon_get_cable_state_(udc->aca_rid_c_ecable->edev,
 187                         udc->aca_rid_c_ecable->cable_index))
 188                         return true;
 189         } else
 190                 status = (udc_readl(udc, VBUS_WAKEUP_REG_OFFSET)
 191                                                 & USB_SYS_VBUS_STATUS);
 192
 193         return status;
 194 }
 195
 196 /**
 197  * done() - retire a request; caller blocked irqs
 198  * @status : request status to be set, only works when
 199  * request is still in progress.
 200  */
 201 static void done(struct tegra_ep *ep, struct tegra_req *req, int status)
 202 {
 203         struct tegra_udc *udc = NULL;
 204         unsigned char stopped = ep->stopped;
 205         struct ep_td_struct *curr_td, *next_td = NULL;
 206         int j;
 207         int count;
 208
 209         BUG_ON(!(in_irq() || irqs_disabled()));
 210         udc = (struct tegra_udc *)ep->udc;
 211         /* Removed the req from tegra_ep->queue */
 212         list_del_init(&req->queue);
 213
 214         /* req.status should be set as -EINPROGRESS in ep_queue() */
 215         if (req->req.status == -EINPROGRESS)
 216                 req->req.status = status;
 217         else
 218                 status = req->req.status;
 219
 220         /* Free dtd for the request */
 221         count = 0;
 222         if (ep->last_td) {
 223                 next_td = ep->last_td;
 224                 count = ep->last_dtd_count;
 225         }
 226         ep->last_td = req->head;
 227         ep->last_dtd_count = req->dtd_count;
 228
 229         for (j = 0; j < count; j++) {
 230                 curr_td = next_td;
 231                 if (j != count - 1) {
 232                         next_td = curr_td->next_td_virt;
 233                 }
 234                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 235         }
 236
 237         if (req->mapped) {
 238                 DEFINE_DMA_ATTRS(attrs);
 239                 struct device *dev = ep->udc->gadget.dev.parent;
 240                 size_t orig = req->req.length;
 241                 size_t ext = orig + AHB_PREFETCH_BUFFER;
 242                 enum dma_data_direction dir =
 243                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
 244
 245                 dma_sync_single_for_cpu(dev, req->req.dma, orig, dir);
 246                 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
 247                 dma_unmap_single_attrs(dev, req->req.dma, ext, dir, &attrs);
 248
 249                 req->req.dma = DMA_ADDR_INVALID;
 250                 req->mapped = 0;
 251         } else
 252                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 253                         req->req.dma, req->req.length,
 254                         ep_is_in(ep)
 255                                 ? DMA_TO_DEVICE
 256                                 : DMA_FROM_DEVICE);
 257
 258         if (status && (status != -ESHUTDOWN))
 259                 VDBG("complete %s req %p stat %d len %u/%u",
 260                         ep->ep.name, &req->req, status,
 261                         req->req.actual, req->req.length);
 262
 263         ep->stopped = 1;
 264 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
 265         if (req->req.complete && req->req.length >= BOOST_TRIGGER_SIZE)
 266                 ep_queue_request_count--;
 267 #endif
 268
 269         /* complete() is from gadget layer,
 270          * eg fsg->bulk_in_complete() */
 271         if (req->req.complete) {
 272                 spin_unlock(&ep->udc->lock);
 273                 req->req.complete(&ep->ep, &req->req);
 274                 spin_lock(&ep->udc->lock);
 275         }
 276
 277         ep->stopped = stopped;
 278 }
 279
 280 /*
 281  * nuke(): delete all requests related to this ep
 282  * Must be called with spinlock held and interrupt disabled
 283  */
 284 static void nuke(struct tegra_ep *ep, int status)
 285 {
 286         ep->stopped = 1;
 287
 288         /* Flush fifo */
 289         tegra_ep_fifo_flush(&ep->ep);
 290
 291         /* Whether this eq has request linked */
 292         while (!list_empty(&ep->queue)) {
 293                 struct tegra_req *req = NULL;
 294
 295                 req = list_entry(ep->queue.next, struct tegra_req, queue);
 296                 done(ep, req, status);
 297         }
 298 }
 299
 300 static int can_pullup(struct tegra_udc *udc)
 301 {
 302         DBG("%s(%d) driver = %d softconnect = %d vbus_active = %d\n", __func__,
 303                 __LINE__, udc->driver ? 1 : 0, udc->softconnect,
 304                 udc->vbus_active);
 305         return udc->driver && udc->softconnect && udc->vbus_active;
 306 }
 307
 308 static int dr_controller_reset(struct tegra_udc *udc)
 309 {
 310         unsigned int tmp;
 311         unsigned long timeout;
 312         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
 313
 314         /* Stop and reset the usb controller */
 315         tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
 316         tmp &= ~USB_CMD_RUN_STOP;
 317         udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
 318
 319         tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
 320         tmp |= USB_CMD_CTRL_RESET;
 321         udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
 322
 323         /* Wait for reset to complete */
 324         timeout = jiffies + UDC_RESET_TIMEOUT_MS;
 325         while (udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_CTRL_RESET) {
 326                 if (time_after(jiffies, timeout)) {
 327                         ERR("udc reset timeout!\n");
 328                         return -ETIMEDOUT;
 329                 }
 330                 cpu_relax();
 331         }
 332
 333         DBG("%s(%d) END\n", __func__, __LINE__);
 334         return 0;
 335 }
 336
 337 static int dr_controller_setup(struct tegra_udc *udc)
 338 {
 339         unsigned int tmp, portctrl;
 340         unsigned long timeout;
 341         int status;
 342         unsigned int port_control_reg_offset;
 343         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
 344
 345         if (udc->has_hostpc)
 346                 port_control_reg_offset = USB_HOSTPCX_DEVLC_REG_OFFSET;
 347         else
 348                 port_control_reg_offset = PORTSCX_REG_OFFSET;
 349
 350         /* Config PHY interface */
 351         portctrl = udc_readl(udc, port_control_reg_offset);
 352         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 353         portctrl |= PORTSCX_PTS_UTMI;
 354         udc_writel(udc, portctrl, port_control_reg_offset);
 355
 356         status = dr_controller_reset(udc);
 357         if (status)
 358                 return status;
 359
 360         /* Set the controller as device mode */
 361         tmp = udc_readl(udc, USB_MODE_REG_OFFSET);
 362         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 363         /* Disable Setup Lockout */
 364         tmp |= USB_MODE_SETUP_LOCK_OFF;
 365         udc_writel(udc, tmp, USB_MODE_REG_OFFSET);
 366
 367         /* Wait for controller to switch to device mode */
 368         timeout = jiffies + UDC_RESET_TIMEOUT_MS;
 369         while ((udc_readl(udc, USB_MODE_REG_OFFSET) &
 370                 USB_MODE_CTRL_MODE_DEVICE) != USB_MODE_CTRL_MODE_DEVICE) {
 371                 if (time_after(jiffies, timeout)) {
 372                         ERR("udc device mode setup timeout!\n");
 373                         return -ETIMEDOUT;
 374                 }
 375                 cpu_relax();
 376         }
 377
 378         /* Clear the setup status */
 379         udc_writel(udc, 0, USB_STS_REG_OFFSET);
 380
 381         tmp = udc->ep_qh_dma;
 382         tmp &= USB_EP_LIST_ADDRESS_MASK;
 383         udc_writel(udc, tmp, USB_EP_LIST_ADDRESS_REG_OFFSET);
 384
 385         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 386                 udc->ep_qh, (int)tmp,
 387                 udc_readl(udc, USB_EP_LIST_ADDRESS_REG_OFFSET));
 388
 389         DBG("%s(%d) END\n", __func__, __LINE__);
 390         return 0;
 391 }
 392
 393 /* Enable DR irq and set controller to run state */
 394 static void dr_controller_run(struct tegra_udc *udc)
 395 {
 396         u32 temp;
 397         unsigned long timeout;
 398         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
 399
 400         /* Clear stopped bit */
 401         udc->stopped = 0;
 402
 403         /* If OTG transceiver is available, then it handles the VBUS detection*/
 404         if (!udc->transceiver) {
 405                 if (tegra_platform_is_fpga()) {
 406                         /* On FPGA VBUS is detected through VBUS A Session
 407                          * instead of VBUS status.*/
 408                         temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
 409                         temp |= USB_SYS_VBUS_ASESSION_INT_EN;
 410                         temp &= ~USB_SYS_VBUS_ASESSION_CHANGED;
 411                         udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
 412                 } else {
 413                         /* Enable cable detection interrupt, without setting the
 414                          * USB_SYS_VBUS_WAKEUP_INT bit. USB_SYS_VBUS_WAKEUP_INT
 415                          * is clear on write */
 416                         temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
 417                         temp |= (USB_SYS_VBUS_WAKEUP_INT_ENABLE
 418                                         | USB_SYS_VBUS_WAKEUP_ENABLE);
 419                         temp &= ~USB_SYS_VBUS_WAKEUP_INT_STATUS;
 420                         udc_writel(udc, temp, VBUS_WAKEUP_REG_OFFSET);
 421                 }
 422         } else
 423                 udc_writel(udc, 0, VBUS_SENSOR_REG_OFFSET);
 424
 425         /* Enable DR irq reg */
 426         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 427                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 428                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 429
 430         udc_writel(udc, temp, USB_INTR_REG_OFFSET);
 431
 432         /* Set the controller as device mode */
 433         temp = udc_readl(udc, USB_MODE_REG_OFFSET);
 434         temp |= USB_MODE_CTRL_MODE_DEVICE;
 435         udc_writel(udc, temp, USB_MODE_REG_OFFSET);
 436
 437         if (udc->support_pmu_vbus) {
 438                 temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
 439                 temp |= (USB_SYS_VBUS_A_VLD_SW_VALUE |
 440                                         USB_SYS_VBUS_A_VLD_SW_EN |
 441                                         USB_SYS_VBUS_ASESSION_VLD_SW_VALUE |
 442                                         USB_SYS_VBUS_ASESSION_VLD_SW_EN);
 443                 udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
 444         }
 445
 446         /* set interrupt latency to 125 uS (1 uFrame) */
 447         /* Set controller to Run */
 448         temp = udc_readl(udc, USB_CMD_REG_OFFSET);
 449         temp &= ~USB_CMD_ITC;
 450         temp |= USB_CMD_ITC_1_MICRO_FRM;
 451         if (can_pullup(udc)) {
 452                 temp |= USB_CMD_RUN_STOP;
 453                 if (udc->charging_supported &&
 454                         ((udc->connect_type == CONNECT_TYPE_SDP) ||
 455                         (udc->connect_type == CONNECT_TYPE_CDP)))
 456                         schedule_delayed_work(&udc->non_std_charger_work,
 457                                 msecs_to_jiffies(NON_STD_CHARGER_DET_TIME_MS));
 458         }
 459         else
 460                 temp &= ~USB_CMD_RUN_STOP;
 461         udc_writel(udc, temp, USB_CMD_REG_OFFSET);
 462
 463         if (can_pullup(udc)) {
 464                 /* Wait for controller to start */
 465                 timeout = jiffies + UDC_RUN_TIMEOUT_MS;
 466                 while ((udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_RUN_STOP)
 467                         != USB_CMD_RUN_STOP) {
 468                         if (time_after(jiffies, timeout)) {
 469                                 ERR("udc start timeout!\n");
 470                                 return;
 471                         }
 472                         cpu_relax();
 473                 }
 474         }
 475
 476         DBG("%s(%d) END\n", __func__, __LINE__);
 477         return;
 478 }
 479
 480 static void dr_controller_stop(struct tegra_udc *udc)
 481 {
 482         unsigned int tmp;
 483         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
 484
 485         /* Clear pending interrupt status bits */
 486         tmp = udc_readl(udc, USB_STS_REG_OFFSET);
 487         udc_writel(udc, tmp, USB_STS_REG_OFFSET);
 488
 489         /* disable all INTR */
 490         udc_writel(udc, 0, USB_INTR_REG_OFFSET);
 491
 492         /* Set stopped bit for isr */
 493         udc->stopped = 1;
 494
 495         /* set controller to Stop */
 496         tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
 497         tmp &= ~USB_CMD_RUN_STOP;
 498         udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
 499
 500         DBG("%s(%d) END\n", __func__, __LINE__);
 501         return;
 502 }
 503
 504 static void dr_ep_setup(struct tegra_udc *udc, unsigned char ep_num,
 505                         unsigned char dir, unsigned char ep_type)
 506 {
 507         unsigned int tmp_epctrl = 0;
 508
 509         tmp_epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 510         if (dir) {
 511                 if (ep_num)
 512                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 513                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 514                 tmp_epctrl |= ((unsigned int)(ep_type)
 515                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 516         } else {
 517                 if (ep_num)
 518                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 519                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 520                 tmp_epctrl |= ((unsigned int)(ep_type)
 521                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 522         }
 523
 524         udc_writel(udc, tmp_epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 525 }
 526
 527 static void dr_ep_change_stall(struct tegra_udc *udc, unsigned char ep_num,
 528                         unsigned char dir, int value)
 529 {
 530         u32 tmp_epctrl = 0;
 531
 532         tmp_epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 533         if (value) {
 534                 /* set the stall bit */
 535                 if (dir)
 536                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 537                 else
 538                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 539         } else {
 540                 /* clear the stall bit and reset data toggle */
 541                 if (dir) {
 542                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 543                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 544                 } else {
 545                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 546                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 547                 }
 548         }
 549         udc_writel(udc, tmp_epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 550 }
 551
 552 /* Get stall status of a specific ep
 553    Return: 0: not stalled; 1:stalled */
 554 static int dr_ep_get_stall(struct tegra_udc *udc, unsigned char ep_num,
 555                 unsigned char dir)
 556 {
 557         u32 epctrl;
 558
 559         epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 560         if (dir)
 561                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 562         else
 563                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 564 }
 565
 566 /**
 567  * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 568  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 569  * @mult: Mult field
 570  */
 571 static void struct_ep_qh_setup(struct tegra_udc *udc, unsigned char ep_num,
 572                 unsigned char dir, unsigned char ep_type,
 573                 unsigned int max_pkt_len, unsigned int zlt, unsigned char mult)
 574 {
 575         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 576         unsigned int tmp = 0;
 577
 578         /* set the Endpoint Capabilites in QH */
 579         switch (ep_type) {
 580         case USB_ENDPOINT_XFER_CONTROL:
 581                 /* Interrupt On Setup (IOS). for control ep  */
 582                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 583                         | EP_QUEUE_HEAD_IOS;
 584                 break;
 585         case USB_ENDPOINT_XFER_ISOC:
 586                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 587                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 588                 break;
 589         case USB_ENDPOINT_XFER_BULK:
 590         case USB_ENDPOINT_XFER_INT:
 591                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 592                 break;
 593         default:
 594                 VDBG("error ep type is %d", ep_type);
 595                 return;
 596         }
 597         if (zlt)
 598                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 599
 600         p_QH->max_pkt_length = cpu_to_le32(tmp);
 601         p_QH->next_dtd_ptr = 1;
 602         p_QH->size_ioc_int_sts = 0;
 603
 604         return;
 605 }
 606
 607 /* Setup qh structure and ep register for ep0. */
 608 static void ep0_setup(struct tegra_udc *udc)
 609 {
 610         /* the intialization of an ep includes: fields in QH, Regs,
 611          * tegra_ep struct */
 612         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 613                         USB_MAX_CTRL_PAYLOAD, 1, 0);
 614         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 615                         USB_MAX_CTRL_PAYLOAD, 1, 0);
 616         dr_ep_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 617         dr_ep_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 618
 619         return;
 620
 621 }
 622
 623 /**
 624  * when configurations are set, or when interface settings change
 625  * for example the do_set_interface() in gadget layer,
 626  * the driver will enable or disable the relevant endpoints
 627  * ep0 doesn't use this routine. It is always enabled.
 628  */
 629 static int tegra_ep_enable(struct usb_ep *_ep,
 630                 const struct usb_endpoint_descriptor *desc)
 631 {
 632         struct tegra_udc *udc = NULL;
 633         struct tegra_ep *ep = NULL;
 634         unsigned short max = 0;
 635         unsigned char mult = 0, zlt;
 636         int retval = -EINVAL;
 637         unsigned long flags = 0;
 638
 639         ep = container_of(_ep, struct tegra_ep, ep);
 640
 641         /* catch various bogus parameters */
 642         if (!_ep || !desc || ep->desc
 643                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 644                 return -EINVAL;
 645
 646         udc = ep->udc;
 647
 648         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 649                 return -ESHUTDOWN;
 650
 651         max = le16_to_cpu(desc->wMaxPacketSize);
 652
 653         /* Disable automatic zlp generation.  Driver is responsible to indicate
 654          * explicitly through req->req.zero.  This is needed to enable multi-td
 655          * request.
 656          */
 657         zlt = 1;
 658
 659         /* Assume the max packet size from gadget is always correct */
 660         switch (desc->bmAttributes & 0x03) {
 661         case USB_ENDPOINT_XFER_CONTROL:
 662         case USB_ENDPOINT_XFER_BULK:
 663         case USB_ENDPOINT_XFER_INT:
 664                 /* mult = 0.  Execute N Transactions as demonstrated by
 665                  * the USB variable length packet protocol where N is
 666                  * computed using the Maximum Packet Length (dQH) and
 667                  * the Total Bytes field (dTD) */
 668                 mult = 0;
 669                 break;
 670         case USB_ENDPOINT_XFER_ISOC:
 671                 /* Calculate transactions needed for high bandwidth iso */
 672                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 673                 max = max & 0x7ff;      /* bit 0~10 */
 674                 /* 3 transactions at most */
 675                 if (mult > 3)
 676                         goto en_done;
 677                 break;
 678         default:
 679                 goto en_done;
 680         }
 681
 682         spin_lock_irqsave(&udc->lock, flags);
 683         ep->ep.maxpacket = max;
 684         ep->desc = desc;
 685         ep->stopped = 0;
 686         ep->last_td = NULL;
 687         ep->last_dtd_count = 0;
 688
 689         /* Controller related setup
 690          * Init EPx Queue Head (Ep Capabilites field in QH
 691          * according to max, zlt, mult)
 692          */
 693         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 694                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 695                                         ?  USB_SEND : USB_RECV),
 696                         (unsigned char) (desc->bmAttributes
 697                                         & USB_ENDPOINT_XFERTYPE_MASK),
 698                         max, zlt, mult);
 699
 700         /* Init endpoint ctrl register */
 701         dr_ep_setup(udc, (unsigned char) ep_index(ep),
 702                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 703                                         ? USB_SEND : USB_RECV),
 704                         (unsigned char) (desc->bmAttributes
 705                                         & USB_ENDPOINT_XFERTYPE_MASK));
 706
 707         spin_unlock_irqrestore(&udc->lock, flags);
 708         retval = 0;
 709
 710         VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
 711                         ep->desc->bEndpointAddress & 0x0f,
 712                         (desc->bEndpointAddress & USB_DIR_IN)
 713                                 ? "in" : "out", max);
 714 en_done:
 715         return retval;
 716 }
 717
 718 /**
 719  * @ep : the ep being unconfigured. May not be ep0
 720  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 721  */
 722 static int tegra_ep_disable(struct usb_ep *_ep)
 723 {
 724         struct tegra_udc *udc = NULL;
 725         struct tegra_ep *ep = NULL;
 726
 727         unsigned long flags = 0;
 728         u32 epctrl;
 729         int ep_num;
 730         struct ep_td_struct *curr_td, *next_td;
 731         int j;
 732
 733         ep = container_of(_ep, struct tegra_ep, ep);
 734         if (!_ep || !ep->desc) {
 735                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 736                 return -EINVAL;
 737         }
 738         udc = (struct tegra_udc *)ep->udc;
 739
 740         /* disable ep on controller */
 741         ep_num = ep_index(ep);
 742
 743         /* Touch the registers if cable is connected and phy is on */
 744         if (udc->vbus_active) {
 745                 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 746                 if (ep_is_in(ep))
 747                         epctrl &= ~EPCTRL_TX_ENABLE;
 748                 else
 749                         epctrl &= ~EPCTRL_RX_ENABLE;
 750                 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
 751         }
 752
 753         spin_lock_irqsave(&udc->lock, flags);
 754
 755         /* nuke all pending requests (does flush) */
 756         nuke(ep, -ESHUTDOWN);
 757
 758         ep->desc = NULL;
 759         ep->stopped = 1;
 760         if (ep->last_td) {
 761                 next_td = ep->last_td;
 762                 for (j = 0; j < ep->last_dtd_count; j++) {
 763                         curr_td = next_td;
 764                         dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 765                         if (j != ep->last_dtd_count - 1) {
 766                                 next_td = curr_td->next_td_virt;
 767                         }
 768                 }
 769         }
 770         ep->last_td = NULL;
 771         ep->last_dtd_count = 0;
 772         spin_unlock_irqrestore(&udc->lock, flags);
 773
 774         VDBG("disabled %s OK", _ep->name);
 775         return 0;
 776 }
 777
 778 /**
 779  * Allocate a request object used by this endpoint
 780  * the main operation is to insert the req->queue to the eq->queue
 781  * Returns the request, or null if one could not be allocated
 782  */
 783 static struct usb_request *
 784 tegra_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 785 {
 786         struct tegra_req *req = NULL;
 787
 788         req = kzalloc(sizeof *req, gfp_flags);
 789         if (!req)
 790                 return NULL;
 791
 792         req->req.dma = DMA_ADDR_INVALID;
 793         INIT_LIST_HEAD(&req->queue);
 794
 795         return &req->req;
 796 }
 797
 798 static void tegra_free_request(struct usb_ep *_ep, struct usb_request *_req)
 799 {
 800         struct tegra_req *req = NULL;
 801
 802         req = container_of(_req, struct tegra_req, req);
 803
 804         if (_req)
 805                 kfree(req);
 806 }
 807
 808 static void tegra_queue_td(struct tegra_ep *ep, struct tegra_req *req)
 809 {
 810         int i = ep_index(ep) * 2 + ep_is_in(ep);
 811         u32 temp, bitmask, tmp_stat;
 812         struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
 813         struct tegra_udc *udc = ep->udc;
 814
 815         bitmask = ep_is_in(ep)
 816                 ? (1 << (ep_index(ep) + 16))
 817                 : (1 << (ep_index(ep)));
 818
 819         /* Flush all the dTD structs out to memory */
 820         wmb();
 821
 822         /* check if the pipe is empty */
 823         if (!(list_empty(&ep->queue))) {
 824                 /* Add td to the end */
 825                 struct tegra_req *lastreq;
 826                 lastreq = list_entry(ep->queue.prev, struct tegra_req, queue);
 827                 lastreq->tail->next_td_ptr =
 828                         cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
 829                 wmb();
 830                 /* Read prime bit, if 1 goto done */
 831                 if (udc_readl(udc, EP_PRIME_REG_OFFSET) & bitmask)
 832                         goto out;
 833
 834                 do {
 835                         /* Set ATDTW bit in USBCMD */
 836                         temp = udc_readl(udc, USB_CMD_REG_OFFSET);
 837                         temp |= USB_CMD_ATDTW;
 838                         udc_writel(udc, temp, USB_CMD_REG_OFFSET);
 839
 840                         /* Read correct status bit */
 841                         tmp_stat = udc_readl(udc, EP_STATUS_REG_OFFSET)
 842                                                 & bitmask;
 843
 844                 } while (!(udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_ATDTW));
 845
 846                 /* Write ATDTW bit to 0 */
 847                 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
 848                 udc_writel(udc, temp & ~USB_CMD_ATDTW, USB_CMD_REG_OFFSET);
 849
 850                 if (tmp_stat)
 851                         goto out;
 852         }
 853
 854         /* Write dQH next pointer and terminate bit to 0 */
 855         temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 856         dQH->next_dtd_ptr = cpu_to_le32(temp);
 857
 858         /* Clear active and halt bit */
 859         temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 860                         | EP_QUEUE_HEAD_STATUS_HALT));
 861         dQH->size_ioc_int_sts &= temp;
 862
 863         tegra_usb_phy_memory_prefetch_on(udc->phy);
 864
 865         /* Ensure that updates to the QH will occur before priming. */
 866         wmb();
 867
 868         /* Prime endpoint by writing 1 to ENDPTPRIME */
 869         temp = ep_is_in(ep)
 870                 ? (1 << (ep_index(ep) + 16))
 871                 : (1 << (ep_index(ep)));
 872         udc_writel(udc, temp, EP_PRIME_REG_OFFSET);
 873 out:
 874         return;
 875 }
 876
 877 /**
 878  * Fill in the dTD structure
 879  * @req     : request that the transfer belongs to
 880  * @length  : return actually data length of the dTD
 881  * @dma     : return dma address of the dTD
 882  * @is_last : return flag if it is the last dTD of the request
 883  * return   : pointer to the built dTD
 884  */
 885 static struct ep_td_struct *tegra_build_dtd(struct tegra_req *req,
 886         unsigned *length, dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 887 {
 888         u32 swap_temp;
 889         struct ep_td_struct *dtd;
 890
 891         /* how big will this transfer be? */
 892         *length = min(req->req.length - req->req.actual,
 893                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 894
 895         dtd = dma_pool_alloc(the_udc->td_pool, gfp_flags, dma);
 896         if (dtd == NULL)
 897                 return dtd;
 898
 899         dtd->td_dma = *dma;
 900         /* Clear reserved field */
 901         swap_temp = cpu_to_le32(dtd->size_ioc_sts);
 902         swap_temp &= ~DTD_RESERVED_FIELDS;
 903         dtd->size_ioc_sts = cpu_to_le32(swap_temp);
 904
 905         /* Init all of buffer page pointers */
 906         swap_temp = (u32) (req->req.dma + req->req.actual);
 907         dtd->buff_ptr0 = cpu_to_le32(swap_temp);
 908         dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
 909         dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
 910         dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
 911         dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
 912
 913         req->req.actual += *length;
 914
 915         /* zlp is needed if req->req.zero is set */
 916         if (req->req.zero) {
 917                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 918                         *is_last = 1;
 919                 else
 920                         *is_last = 0;
 921         } else if (req->req.length == req->req.actual)
 922                 *is_last = 1;
 923         else
 924                 *is_last = 0;
 925
 926         if ((*is_last) == 0)
 927                 VDBG("multi-dtd request!");
 928
 929         /* Fill in the transfer size; set active bit */
 930         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 931
 932         /* Enable interrupt for the last dtd of a request */
 933         if (*is_last && !req->req.no_interrupt)
 934                 swap_temp |= DTD_IOC;
 935
 936         dtd->size_ioc_sts = cpu_to_le32(swap_temp);
 937
 938         mb();
 939
 940         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 941
 942         return dtd;
 943 }
 944
 945 /* Generate dtd chain for a request */
 946 static int tegra_req_to_dtd(struct tegra_req *req, gfp_t gfp_flags)
 947 {
 948         unsigned        count;
 949         int             is_last;
 950         int             is_first = 1;
 951         struct ep_td_struct     *last_dtd = NULL, *dtd;
 952         dma_addr_t dma;
 953
 954         tegra_usb_phy_memory_prefetch_off(the_udc->phy);
 955
 956         do {
 957                 dtd = tegra_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 958                 if (dtd == NULL)
 959                         return -ENOMEM;
 960
 961                 if (is_first) {
 962                         is_first = 0;
 963                         req->head = dtd;
 964                 } else {
 965                         last_dtd->next_td_ptr = cpu_to_le32(dma);
 966                         last_dtd->next_td_virt = dtd;
 967                 }
 968                 last_dtd = dtd;
 969
 970                 req->dtd_count++;
 971         } while (!is_last);
 972
 973         dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
 974
 975         req->tail = dtd;
 976
 977         return 0;
 978 }
 979
 980 /* queues (submits) an I/O request to an endpoint */
 981 static int
 982 tegra_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 983 {
 984         struct tegra_ep *ep = container_of(_ep, struct tegra_ep, ep);
 985         struct tegra_req *req = container_of(_req, struct tegra_req, req);
 986         struct tegra_udc *udc = ep->udc;
 987         unsigned long flags;
 988         enum dma_data_direction dir;
 989         int status;
 990
 991         /* catch various bogus parameters */
 992         if (!_req || !req->req.complete || !req->req.buf
 993                         || !list_empty(&req->queue)) {
 994                 VDBG("%s, bad params", __func__);
 995                 return -EINVAL;
 996         }
 997
 998         spin_lock_irqsave(&udc->lock, flags);
 999
1000         if (unlikely(!ep->desc)) {
1001                 VDBG("%s, bad ep", __func__);
1002                 spin_unlock_irqrestore(&udc->lock, flags);
1003                 return -EINVAL;
1004         }
1005
1006         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1007                 if (req->req.length > ep->ep.maxpacket) {
1008                         spin_unlock_irqrestore(&udc->lock, flags);
1009                         return -EMSGSIZE;
1010                 }
1011         }
1012
1013 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
1014         if (req->req.length >= BOOST_TRIGGER_SIZE) {
1015                 ep_queue_request_count++;
1016                 schedule_work(&udc->boost_cpufreq_work);
1017         }
1018 #endif
1019
1020         dir = ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1021
1022         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1023                 spin_unlock_irqrestore(&udc->lock, flags);
1024                 return -ESHUTDOWN;
1025         }
1026
1027         req->ep = ep;
1028
1029         /* map virtual address to hardware */
1030         if (req->req.dma == DMA_ADDR_INVALID) {
1031                 DEFINE_DMA_ATTRS(attrs);
1032                 struct device *dev = udc->gadget.dev.parent;
1033                 size_t orig = req->req.length;
1034                 size_t ext = orig + AHB_PREFETCH_BUFFER;
1035
1036                 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1037                 req->req.dma = dma_map_single_attrs(dev, req->req.buf, ext, dir,
1038                                                     &attrs);
1039                 if (dma_mapping_error(dev, req->req.dma)) {
1040                         spin_unlock_irqrestore(&udc->lock, flags);
1041                         return -EAGAIN;
1042                 }
1043
1044                 dma_sync_single_for_device(dev, req->req.dma, orig, dir);
1045
1046                 req->mapped = 1;
1047         } else {
1048                 dma_sync_single_for_device(udc->gadget.dev.parent,
1049                                         req->req.dma, req->req.length, dir);
1050                 req->mapped = 0;
1051         }
1052
1053         req->req.status = -EINPROGRESS;
1054         req->req.actual = 0;
1055         req->dtd_count = 0;
1056
1057
1058         /* build dtds and push them to device queue */
1059         status = tegra_req_to_dtd(req, GFP_ATOMIC);
1060         if (status) {
1061                 spin_unlock_irqrestore(&udc->lock, flags);
1062                 goto err_unmap;
1063         }
1064
1065         /* re-check if the ep has not been disabled */
1066         if (unlikely(!ep->desc)) {
1067                 spin_unlock_irqrestore(&udc->lock, flags);
1068                 status = -EINVAL;
1069                 goto err_unmap;
1070         }
1071
1072         tegra_queue_td(ep, req);
1073
1074         /* Update ep0 state */
1075         if ((ep_index(ep) == 0))
1076                 udc->ep0_state = DATA_STATE_XMIT;
1077
1078         /* irq handler advances the queue */
1079         list_add_tail(&req->queue, &ep->queue);
1080         spin_unlock_irqrestore(&udc->lock, flags);
1081
1082         return 0;
1083
1084 err_unmap:
1085         if (req->mapped) {
1086                 DEFINE_DMA_ATTRS(attrs);
1087                 struct device *dev = udc->gadget.dev.parent;
1088                 size_t orig = req->req.length;
1089                 size_t ext = orig + AHB_PREFETCH_BUFFER;
1090
1091                 dma_sync_single_for_cpu(dev, req->req.dma, orig, dir);
1092                 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1093                 dma_unmap_single_attrs(dev, req->req.dma, ext, dir, &attrs);
1094
1095                 req->req.dma = DMA_ADDR_INVALID;
1096                 req->mapped = 0;
1097         }
1098         return status;
1099 }
1100
1101 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
1102 static int tegra_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1103 {
1104         struct tegra_ep *ep = container_of(_ep, struct tegra_ep, ep);
1105         struct tegra_req *req;
1106         struct tegra_udc *udc = ep->udc;
1107         unsigned long flags;
1108         int ep_num, stopped, ret = 0;
1109         u32 epctrl;
1110
1111         if (!_ep || !_req)
1112                 return -EINVAL;
1113
1114         spin_lock_irqsave(&ep->udc->lock, flags);
1115         if (!ep->desc) {
1116                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1117                 return -EINVAL;
1118         }
1119         stopped = ep->stopped;
1120
1121         /* Stop the ep before we deal with the queue */
1122         ep->stopped = 1;
1123         ep_num = ep_index(ep);
1124
1125         /* Touch the registers if cable is connected and phy is on */
1126         if (udc->vbus_active) {
1127                 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1128                 if (ep_is_in(ep))
1129                         epctrl &= ~EPCTRL_TX_ENABLE;
1130                 else
1131                         epctrl &= ~EPCTRL_RX_ENABLE;
1132                 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1133         }
1134
1135         /* make sure it's actually queued on this endpoint */
1136         list_for_each_entry(req, &ep->queue, queue) {
1137                 if (&req->req == _req)
1138                         break;
1139         }
1140         if (&req->req != _req) {
1141                 ret = -EINVAL;
1142                 goto out;
1143         }
1144
1145         /* The request is in progress, or completed but not dequeued */
1146         if (ep->queue.next == &req->queue) {
1147                 _req->status = -ECONNRESET;
1148                 tegra_ep_fifo_flush(_ep);       /* flush current transfer */
1149
1150                 /* The request isn't the last request in this ep queue */
1151                 if (req->queue.next != &ep->queue) {
1152                         struct ep_queue_head *qh;
1153                         struct tegra_req *next_req;
1154
1155                         qh = ep->qh;
1156                         next_req = list_entry(req->queue.next, struct tegra_req,
1157                                         queue);
1158
1159                         /* Point the QH to the first TD of next request */
1160                         writel((u32) (uintptr_t) next_req->head,
1161                                         (void __iomem *)&qh->curr_dtd_ptr);
1162                 }
1163
1164                 /* The request hasn't been processed, patch up the TD chain */
1165         } else {
1166                 struct tegra_req *prev_req;
1167
1168                 prev_req = list_entry(req->queue.prev, struct tegra_req, queue);
1169                 writel(readl((void __iomem *)&req->tail->next_td_ptr),
1170                                 (void __iomem *)&prev_req->tail->next_td_ptr);
1171         }
1172
1173         done(ep, req, -ECONNRESET);
1174
1175         /* Enable EP */
1176 out:
1177         /* Touch the registers if cable is connected and phy is on */
1178         if (udc->vbus_active && ep->desc) {
1179                 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1180                 if (ep_is_in(ep))
1181                         epctrl |= EPCTRL_TX_ENABLE;
1182                 else
1183                         epctrl |= EPCTRL_RX_ENABLE;
1184                 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1185         }
1186         ep->stopped = stopped;
1187
1188         spin_unlock_irqrestore(&ep->udc->lock, flags);
1189         return ret;
1190 }
1191
1192 /**
1193  * modify the endpoint halt feature
1194  * @ep: the non-isochronous endpoint being stalled
1195  * @value: 1--set halt  0--clear halt
1196  * Returns zero, or a negative error code.
1197  */
1198 static int tegra_ep_set_halt(struct usb_ep *_ep, int value)
1199 {
1200         struct tegra_ep *ep = NULL;
1201         unsigned long flags = 0;
1202         int status = -EOPNOTSUPP;       /* operation not supported */
1203         unsigned char ep_dir = 0, ep_num = 0;
1204         struct tegra_udc *udc = NULL;
1205
1206         ep = container_of(_ep, struct tegra_ep, ep);
1207         udc = ep->udc;
1208         if (!_ep || !ep->desc) {
1209                 status = -EINVAL;
1210                 goto out;
1211         }
1212
1213         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1214                 status = -EOPNOTSUPP;
1215                 goto out;
1216         }
1217
1218         /* Attempt to halt IN ep will fail if any transfer requests
1219          * are still queue */
1220         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1221                 status = -EAGAIN;
1222                 goto out;
1223         }
1224
1225         status = 0;
1226         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1227         ep_num = (unsigned char)(ep_index(ep));
1228         spin_lock_irqsave(&ep->udc->lock, flags);
1229         dr_ep_change_stall(udc, ep_num, ep_dir, value);
1230         spin_unlock_irqrestore(&ep->udc->lock, flags);
1231
1232         if (ep_index(ep) == 0) {
1233                 udc->ep0_state = WAIT_FOR_SETUP;
1234                 udc->ep0_dir = 0;
1235         }
1236 out:
1237         VDBG(" %s %s halt stat %d", ep->ep.name,
1238                         value ?  "set" : "clear", status);
1239
1240         return status;
1241 }
1242
1243 static int tegra_ep_fifo_status(struct usb_ep *_ep)
1244 {
1245         struct tegra_ep *ep;
1246         struct tegra_udc *udc;
1247         int size = 0;
1248         u32 bitmask;
1249         struct ep_queue_head *d_qh;
1250
1251         ep = container_of(_ep, struct tegra_ep, ep);
1252         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1253                 return -ENODEV;
1254
1255         udc = (struct tegra_udc *)ep->udc;
1256
1257         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1258                 return -ESHUTDOWN;
1259
1260         d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1261
1262         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1263             (1 << (ep_index(ep)));
1264
1265         if (udc_readl(udc, EP_STATUS_REG_OFFSET) & bitmask)
1266                 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1267                     >> DTD_LENGTH_BIT_POS;
1268
1269         pr_debug("%s %u\n", __func__, size);
1270         return size;
1271 }
1272
1273 static void tegra_ep_fifo_flush(struct usb_ep *_ep)
1274 {
1275         struct tegra_ep *ep;
1276         struct tegra_udc *udc;
1277         int ep_num, ep_dir;
1278         u32 bits;
1279         unsigned long timeout;
1280
1281         if (!_ep) {
1282                 return;
1283         } else {
1284                 ep = container_of(_ep, struct tegra_ep, ep);
1285                 if (!ep->desc)
1286                         return;
1287         }
1288         ep_num = ep_index(ep);
1289         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1290         udc = ep->udc;
1291
1292         if (ep_num == 0)
1293                 bits = (1 << 16) | 1;
1294         else if (ep_dir == USB_SEND)
1295                 bits = 1 << (16 + ep_num);
1296         else
1297                 bits = 1 << ep_num;
1298
1299         /* Touch the registers if cable is connected and phy is on */
1300         if (!udc->vbus_active)
1301                 return;
1302
1303         timeout = jiffies + UDC_FLUSH_TIMEOUT_MS;
1304         do {
1305                 udc_writel(udc, bits, EPFLUSH_REG_OFFSET);
1306
1307                 /* Wait until flush complete */
1308                 while (udc_readl(udc, EPFLUSH_REG_OFFSET)) {
1309                         if (time_after(jiffies, timeout)) {
1310                                 ERR("ep flush timeout\n");
1311                                 return;
1312                         }
1313                         cpu_relax();
1314                 }
1315                 /* See if we need to flush again */
1316         } while (udc_readl(udc, EP_STATUS_REG_OFFSET) & bits);
1317 }
1318
1319 static struct usb_ep_ops tegra_ep_ops = {
1320         .enable = tegra_ep_enable,
1321         .disable = tegra_ep_disable,
1322
1323         .alloc_request = tegra_alloc_request,
1324         .free_request = tegra_free_request,
1325
1326         .queue = tegra_ep_queue,
1327         .dequeue = tegra_ep_dequeue,
1328
1329         .set_halt = tegra_ep_set_halt,
1330         .fifo_status = tegra_ep_fifo_status,
1331         .fifo_flush = tegra_ep_fifo_flush,      /* flush fifo */
1332 };
1333
1334
1335 static struct usb_phy *get_usb_phy(struct tegra_usb_phy *x)
1336 {
1337         return (struct usb_phy *)x;
1338 }
1339
1340 /* Get the current frame number (from DR frame_index Reg ) */
1341 static int tegra_get_frame(struct usb_gadget *gadget)
1342 {
1343         struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1344         return (int)(udc_readl(udc, USB_FRINDEX_REG_OFFSET)
1345                                                 & USB_FRINDEX_MASKS);
1346 }
1347
1348 #ifndef CONFIG_USB_ANDROID
1349 /* Tries to wake up the host connected to this gadget */
1350 static int tegra_wakeup(struct usb_gadget *gadget)
1351 {
1352         struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1353         u32 portsc;
1354
1355         /* Remote wakeup feature not enabled by host */
1356         if (!udc->remote_wakeup)
1357                 return -ENOTSUPP;
1358
1359         portsc = udc_readl(udc, PORTSCX_REG_OFFSET);
1360         /* not suspended? */
1361         if (!(portsc & PORTSCX_PORT_SUSPEND))
1362                 return 0;
1363
1364         /* trigger force resume */
1365         portsc |= PORTSCX_PORT_FORCE_RESUME;
1366         udc_writel(udc, portsc, PORTSCX_REG_OFFSET);
1367         return 0;
1368 }
1369 #endif
1370
1371 static int tegra_set_selfpowered(struct usb_gadget *gadget, int is_on)
1372 {
1373         struct tegra_udc *udc;
1374         udc = container_of(gadget, struct tegra_udc, gadget);
1375         udc->selfpowered = (is_on != 0);
1376         return 0;
1377 }
1378
1379 static void tegra_udc_set_charger_type(struct tegra_udc *udc,
1380                 enum tegra_connect_type type)
1381 {
1382         udc->prev_connect_type = udc->connect_type;
1383         udc->connect_type = type;
1384 }
1385
1386 static void tegra_udc_set_extcon_state(struct tegra_udc *udc)
1387 {
1388         struct device *dev = &udc->pdev->dev;
1389         const char **cables;
1390         struct extcon_dev *edev;
1391         u32 old_state, new_state;
1392
1393         if (udc->edev == NULL || udc->edev->supported_cable == NULL)
1394                 return;
1395         edev = udc->edev;
1396         cables = udc->edev->supported_cable;
1397         old_state = extcon_get_state(edev);
1398         /* set previous cable type to false, then set current type to true */
1399         if (udc->prev_connect_type != CONNECT_TYPE_NONE)
1400                 extcon_set_state(edev, 0x0);
1401         if (udc->connect_type != udc->connect_type_lp0
1402                         && udc->connect_type != CONNECT_TYPE_NONE)
1403                 extcon_set_cable_state(edev, cables[udc->connect_type], true);
1404         new_state = extcon_get_state(edev);
1405         dev_info(dev, "notification status (%d,%d,%d) (0x%x, 0x%x)\n",
1406                         udc->prev_connect_type, udc->connect_type,
1407                         udc->connect_type_lp0, old_state, new_state);
1408 }
1409
1410 static void tegra_udc_notify_event(struct tegra_udc *udc, int event)
1411 {
1412         if (udc->transceiver) {
1413                 udc->transceiver->last_event = event;
1414                 atomic_notifier_call_chain(&udc->transceiver->notifier,
1415                                 event, udc->transceiver->otg->gadget);
1416         }
1417 }
1418
1419 static int tegra_usb_set_charging_current(struct tegra_udc *udc)
1420 {
1421         int max_ua;
1422         struct device *dev;
1423         int ret;
1424
1425         dev = &udc->pdev->dev;
1426         switch (udc->connect_type) {
1427         case CONNECT_TYPE_NONE:
1428                 dev_info(dev, "USB cable/charger disconnected\n");
1429                 max_ua = 0;
1430                 /* Notify if HOST(SDP/CDP) is connected */
1431                 if ((udc->prev_connect_type == CONNECT_TYPE_SDP) ||
1432                         (udc->prev_connect_type == CONNECT_TYPE_CDP) ||
1433                         (udc->prev_connect_type ==
1434                                 CONNECT_TYPE_ACA_NV_CHARGER) ||
1435                         (udc->prev_connect_type == CONNECT_TYPE_ACA_RID_B) ||
1436                         (udc->prev_connect_type == CONNECT_TYPE_ACA_RID_C))
1437                         tegra_udc_notify_event(udc, USB_EVENT_NONE);
1438                 break;
1439         case CONNECT_TYPE_SDP:
1440                 if (udc->current_limit > 2)
1441                         dev_info(dev, "connected to SDP\n");
1442                 max_ua = min(udc->current_limit * 1000,
1443                                 USB_CHARGING_SDP_CURRENT_LIMIT_UA);
1444                 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1445                 break;
1446         case CONNECT_TYPE_DCP:
1447                 dev_info(dev, "connected to DCP(wall charger)\n");
1448                 max_ua = udc->dcp_current_limit;
1449                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1450                 break;
1451         case CONNECT_TYPE_DCP_QC2:
1452                 dev_info(dev, "connected to QuickCharge 2(wall charger)\n");
1453                 max_ua = udc->qc2_current_limit;
1454                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1455                 break;
1456         case CONNECT_TYPE_DCP_MAXIM:
1457                 dev_info(dev, "connected to Maxim(wall charger)\n");
1458                 max_ua = udc->dcp_current_limit;
1459                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1460                 break;
1461         case CONNECT_TYPE_CDP:
1462                 dev_info(dev, "connected to CDP(1.5A)\n");
1463                 /*
1464                  * if current is more than VBUS suspend current, we draw CDP
1465                  * allowed maximum current (override SDP max current which is
1466                  * set by the upper level driver).
1467                  */
1468                 if (udc->current_limit > 2)
1469                         max_ua = USB_CHARGING_CDP_CURRENT_LIMIT_UA;
1470                 else
1471                         max_ua = udc->current_limit * 1000;
1472                 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1473                 break;
1474         case CONNECT_TYPE_NV_CHARGER:
1475                 dev_info(dev, "connected to NV charger\n");
1476                 max_ua = USB_CHARGING_NV_CHARGER_CURRENT_LIMIT_UA;
1477                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1478                 break;
1479         case CONNECT_TYPE_NON_STANDARD_CHARGER:
1480                 dev_info(dev, "connected to non-standard charger\n");
1481                 max_ua = USB_CHARGING_NON_STANDARD_CHARGER_CURRENT_LIMIT_UA;
1482                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1483                 break;
1484         case CONNECT_TYPE_APPLE_500MA:
1485                 dev_info(dev, "connected to Apple/Other 0.5A custom charger\n");
1486                 max_ua = USB_CHARGING_APPLE_CHARGER_500mA_CURRENT_LIMIT_UA;
1487                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1488                 break;
1489         case CONNECT_TYPE_APPLE_1000MA:
1490                 dev_info(dev, "connected to Apple/Other 1A custom charger\n");
1491                 max_ua = USB_CHARGING_APPLE_CHARGER_1000mA_CURRENT_LIMIT_UA;
1492                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1493                 break;
1494         case CONNECT_TYPE_APPLE_2000MA:
1495                 dev_info(dev, "connected to Apple/Other/NV 2A custom charger\n");
1496                 max_ua = USB_CHARGING_APPLE_CHARGER_2000mA_CURRENT_LIMIT_UA;
1497                 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1498                 break;
1499         case CONNECT_TYPE_ACA_NV_CHARGER:
1500                 dev_info(dev, "connected to ACA-NV Y-Cable 17V/2.1A custom charger\n");
1501                 max_ua = USB_CHARGING_ACA_NV_CHARGER_CURRENT_LIMIT_UA;
1502                 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1503                 break;
1504         case CONNECT_TYPE_ACA_RID_B:
1505                 dev_info(dev, "connected to ACA RID_B\n");
1506                 max_ua = USB_CHARGING_ACA_RID_B_CHARGER_CURRENT_LIMIT_UA;
1507                 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1508                 break;
1509         case CONNECT_TYPE_ACA_RID_C:
1510                 dev_info(dev, "connected to ACA RID_C\n");
1511                 max_ua = USB_CHARGING_ACA_RID_C_CHARGER_CURRENT_LIMIT_UA;
1512                 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1513                 break;
1514         default:
1515                 dev_info(dev, "connected to unknown USB port\n");
1516                 max_ua = 0;
1517         }
1518
1519         ret = 0;
1520         /*
1521          * we set charging regulator's maximum charging current 1st, then
1522          * notify the charging type.
1523          */
1524         if (NULL != udc->vbus_reg && !udc->vbus_in_lp0) {
1525                 if (udc->connect_type != udc->connect_type_lp0 ||
1526                                         udc->connect_type == CONNECT_TYPE_NONE)
1527                         ret = regulator_set_current_limit(udc->vbus_reg,
1528                                                                  0, max_ua);
1529         }
1530
1531         if (!udc->vbus_in_lp0) {
1532                 tegra_udc_set_extcon_state(udc);
1533                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
1534         }
1535         return ret;
1536 }
1537
1538 static int tegra_detect_cable_type(struct tegra_udc *udc)
1539 {
1540         int index;
1541
1542         if (!udc->charging_supported) {
1543                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1544                 return 0;
1545         }
1546
1547         if (udc->support_aca_nv_cable && udc->aca_nv_extcon_cable) {
1548                 index = udc->aca_nv_extcon_cable->cable_index;
1549                 if (extcon_get_cable_state_(udc->aca_nv_extcon_dev, index)) {
1550                         tegra_udc_set_charger_type(udc,
1551                                         CONNECT_TYPE_ACA_NV_CHARGER);
1552                         tegra_usb_set_charging_current(udc);
1553                         return 0;
1554                 }
1555         }
1556
1557         if (udc->support_aca_rid && udc->aca_rid_b_ecable) {
1558                 index = udc->aca_rid_b_ecable->cable_index;
1559                 if (extcon_get_cable_state_(udc->aca_rid_b_ecable->edev,
1560                                         index)) {
1561                         tegra_udc_set_charger_type(udc,
1562                                         CONNECT_TYPE_ACA_RID_B);
1563                         tegra_usb_set_charging_current(udc);
1564                         udc->aca_status = true;
1565                         return 0;
1566                 }
1567         }
1568
1569         if (udc->support_aca_rid && udc->aca_rid_c_ecable) {
1570                 index = udc->aca_rid_c_ecable->cable_index;
1571                 if (extcon_get_cable_state_(udc->aca_rid_c_ecable->edev,
1572                                         index)) {
1573                         tegra_udc_set_charger_type(udc,
1574                                         CONNECT_TYPE_ACA_RID_C);
1575                         tegra_usb_set_charging_current(udc);
1576                         udc->aca_status = true;
1577                         return 0;
1578                 }
1579         }
1580
1581         if (udc->support_aca_rid && udc->aca_status) {
1582                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1583                 tegra_usb_set_charging_current(udc);
1584                 udc->aca_status = false;
1585                 return 0;
1586         }
1587
1588         if (tegra_usb_phy_charger_detected(udc->phy)) {
1589                 if (tegra_usb_phy_cdp_charger_detected(udc->phy))
1590                         tegra_udc_set_charger_type(udc, CONNECT_TYPE_CDP);
1591                 else if (tegra_usb_phy_maxim_charger_detected(udc->phy))
1592                         tegra_udc_set_charger_type(udc,
1593                                                 CONNECT_TYPE_DCP_MAXIM);
1594                 else if (udc->qc2_voltage) {
1595                         /* Must be DCP -- figure out if Quick Charge 2 or DCP.
1596                          * Initially set low current since QC2 will reset to
1597                          * 5V if current is too high when it changes to higher
1598                          * voltage during detection. So setting to non-standard
1599                          * which sets for low current. Also, setting current
1600                          * early allows the charging icon to show up on UI.
1601                          */
1602                         tegra_udc_set_charger_type(udc,
1603                                         CONNECT_TYPE_NON_STANDARD_CHARGER);
1604                         tegra_usb_set_charging_current(udc);
1605
1606                         if (tegra_usb_phy_qc2_charger_detected(udc->phy,
1607                                         udc->qc2_voltage))
1608                                 tegra_udc_set_charger_type(udc,
1609                                         CONNECT_TYPE_DCP_QC2);
1610                         else
1611                                 tegra_udc_set_charger_type(udc,
1612                                         CONNECT_TYPE_DCP);
1613                 } else
1614                         tegra_udc_set_charger_type(udc, CONNECT_TYPE_DCP);
1615         }
1616 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
1617         else if (tegra_usb_phy_apple_500ma_charger_detected(udc->phy))
1618                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_500MA);
1619         else if (tegra_usb_phy_apple_1000ma_charger_detected(udc->phy))
1620                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_1000MA);
1621         else if (tegra_usb_phy_apple_2000ma_charger_detected(udc->phy))
1622                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_2000MA);
1623 #endif
1624         else if (tegra_usb_phy_nv_charger_detected(udc->phy))
1625                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_NV_CHARGER);
1626         else
1627                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1628
1629         /*
1630          * If it is charger type, we start charging now. If it is connected to
1631          * USB host(CDP/SDP), we let upper gadget driver to decide the current
1632          * capability.
1633          */
1634         if ((udc->connect_type != CONNECT_TYPE_SDP) &&
1635                 (udc->connect_type != CONNECT_TYPE_CDP))
1636                 tegra_usb_set_charging_current(udc);
1637
1638         return 0;
1639 }
1640
1641 /**
1642  * Notify controller that VBUS is powered, called by whatever
1643  * detects VBUS sessions
1644  */
1645 static int tegra_vbus_session(struct usb_gadget *gadget, int is_active)
1646 {
1647         struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1648         unsigned long flags;
1649
1650         mutex_lock(&udc->sync_lock);
1651         DBG("%s(%d) turn VBUS state from %s to %s", __func__, __LINE__,
1652                 udc->vbus_active ? "on" : "off", is_active ? "on" : "off");
1653
1654         if (udc->vbus_active && !is_active) {
1655                 /* If cable disconnected, cancel any delayed work */
1656                 cancel_delayed_work_sync(&udc->non_std_charger_work);
1657                 spin_lock_irqsave(&udc->lock, flags);
1658                 /* reset all internal Queues and inform client driver */
1659                 reset_queues(udc);
1660                 /* stop the controller and turn off the clocks */
1661                 dr_controller_stop(udc);
1662                 dr_controller_reset(udc);
1663                 udc->vbus_active = 0;
1664                 udc->usb_state = USB_STATE_DEFAULT;
1665                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_NONE);
1666                 spin_unlock_irqrestore(&udc->lock, flags);
1667                 tegra_usb_phy_power_off(udc->phy);
1668                 tegra_usb_set_charging_current(udc);
1669                 udc->current_limit = 0;
1670                 udc->aca_status = false;
1671         } else if (!udc->vbus_active && is_active) {
1672                 tegra_usb_phy_power_on(udc->phy);
1673                 /* setup the controller in the device mode */
1674                 dr_controller_setup(udc);
1675                 /* setup EP0 for setup packet */
1676                 ep0_setup(udc);
1677                 /* initialize the USB and EP states */
1678                 udc->usb_state = USB_STATE_ATTACHED;
1679                 udc->ep0_state = WAIT_FOR_SETUP;
1680                 udc->ep0_dir = 0;
1681                 udc->vbus_active = 1;
1682                 tegra_detect_cable_type(udc);
1683                 /* start the controller if USB host detected */
1684                 if ((udc->connect_type == CONNECT_TYPE_SDP) ||
1685                     (udc->connect_type == CONNECT_TYPE_CDP) ||
1686                     (udc->connect_type == CONNECT_TYPE_DCP_MAXIM) ||
1687                     (udc->connect_type == CONNECT_TYPE_ACA_NV_CHARGER) ||
1688                     (udc->connect_type == CONNECT_TYPE_ACA_RID_B) ||
1689                     (udc->connect_type == CONNECT_TYPE_ACA_RID_C))
1690                         dr_controller_run(udc);
1691         } else if (udc->vbus_active && is_active && udc->support_aca_rid) {
1692                 /* handle rid_b -> rid_c */
1693                 /* rid_c/rid_b -> vbus */
1694                 /* vbus -> rid_c/rid_b */
1695
1696                 /* If MAXIM do not call cable_detect. resets vbus */
1697                 if (udc->connect_type != CONNECT_TYPE_DCP_MAXIM)
1698                         tegra_detect_cable_type(udc);
1699         }
1700         mutex_unlock(&udc->sync_lock);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * Constrain controller's VBUS power usage.
1707  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1708  * reporting how much power the device may consume. For example, this
1709  * could affect how quickly batteries are recharged.
1710  *
1711  * Returns zero on success, else negative errno.
1712  */
1713 static int tegra_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1714 {
1715         struct tegra_udc *udc;
1716
1717         udc = container_of(gadget, struct tegra_udc, gadget);
1718
1719         if (udc->connect_type == CONNECT_TYPE_DCP_MAXIM ||
1720                 udc->connect_type == CONNECT_TYPE_ACA_RID_B ||
1721                 udc->connect_type == CONNECT_TYPE_ACA_RID_C)
1722                 return 0;
1723
1724         /* Some hosts during booting first supply vbus and then
1725            send setup packets after x seconds. In this case we detect
1726            as non-standard. Handle this case by setting to SDP */
1727         if (udc->connect_type != CONNECT_TYPE_NONE
1728                 && udc->connect_type != CONNECT_TYPE_SDP
1729                 && udc->connect_type != CONNECT_TYPE_CDP
1730                 && udc->connect_type != CONNECT_TYPE_ACA_NV_CHARGER)
1731                 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1732
1733         /* Avoid unnecessary work if there is no change in current limit */
1734         if (udc->current_limit != mA) {
1735                 udc->current_limit = mA;
1736                 schedule_work(&udc->current_work);
1737         }
1738
1739         if (udc->transceiver)
1740                 return usb_phy_set_power(udc->transceiver, mA);
1741         return -ENOTSUPP;
1742 }
1743
1744 /**
1745  * Change Data+ pullup status
1746  * this func is used by usb_gadget_connect/disconnect
1747  */
1748 static int tegra_pullup(struct usb_gadget *gadget, int is_on)
1749 {
1750         struct tegra_udc *udc;
1751         u32 tmp;
1752         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
1753
1754         udc = container_of(gadget, struct tegra_udc, gadget);
1755         udc->softconnect = (is_on != 0);
1756         if (udc->transceiver && udc->transceiver->state !=
1757                         OTG_STATE_B_PERIPHERAL)
1758                         return 0;
1759
1760         /* set interrupt latency to 125 uS (1 uFrame) */
1761         tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
1762         tmp &= ~USB_CMD_ITC;
1763         tmp |= USB_CMD_ITC_1_MICRO_FRM;
1764         if (can_pullup(udc)) {
1765                 udc_writel(udc, tmp | USB_CMD_RUN_STOP, USB_CMD_REG_OFFSET);
1766                 /*
1767                  * We cannot tell difference between a SDP and non-standard
1768                  * charger (which has D+/D- line floating) based on line status
1769                  * at the time VBUS is detected.
1770                  *
1771                  * We can schedule a 4s delayed work and verify it is an
1772                  * non-standard charger if no setup packet is received after
1773                  * enumeration started.
1774                  */
1775                 if (udc->charging_supported &&
1776                         ((udc->connect_type == CONNECT_TYPE_SDP) ||
1777                         (udc->connect_type == CONNECT_TYPE_CDP)))
1778                         schedule_delayed_work(&udc->non_std_charger_work,
1779                                 msecs_to_jiffies(NON_STD_CHARGER_DET_TIME_MS));
1780         } else {
1781                 cancel_delayed_work(&udc->non_std_charger_work);
1782                 udc_writel(udc, (tmp & ~USB_CMD_RUN_STOP), USB_CMD_REG_OFFSET);
1783         }
1784
1785         DBG("%s(%d) END\n", __func__, __LINE__);
1786         return 0;
1787 }
1788
1789 /* Release udc structures */
1790 static void tegra_udc_release(struct device *dev)
1791 {
1792         struct usb_gadget *gadget = dev_to_usb_gadget(dev);
1793         struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1794
1795         complete(udc->done);
1796         usb_phy_shutdown(get_usb_phy(udc->phy));
1797         kfree(udc);
1798 }
1799
1800 static int tegra_udc_start(struct usb_gadget *g,
1801                 struct usb_gadget_driver *driver);
1802 static int tegra_udc_stop(struct usb_gadget *g,
1803                 struct usb_gadget_driver *driver);
1804 /* defined in gadget.h */
1805 static const struct usb_gadget_ops tegra_gadget_ops = {
1806         .get_frame = tegra_get_frame,
1807 #ifndef CONFIG_USB_ANDROID
1808         .wakeup = tegra_wakeup,
1809 #endif
1810         .set_selfpowered = tegra_set_selfpowered,
1811         .vbus_session = tegra_vbus_session,
1812         .vbus_draw = tegra_vbus_draw,
1813         .pullup = tegra_pullup,
1814         .udc_start = tegra_udc_start,
1815         .udc_stop = tegra_udc_stop,
1816 };
1817
1818 /**
1819  * Set protocol stall on ep0, protocol stall will automatically be cleared
1820  * on new transaction.
1821  */
1822 static void ep0stall(struct tegra_udc *udc)
1823 {
1824         u32 tmp;
1825
1826         /* must set tx and rx to stall at the same time */
1827         tmp = udc_readl(udc, EP_CONTROL_REG_OFFSET);
1828         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1829         udc_writel(udc, tmp, EP_CONTROL_REG_OFFSET);
1830         udc->ep0_state = WAIT_FOR_SETUP;
1831         udc->ep0_dir = 0;
1832 }
1833
1834 /* Prime a status phase for ep0 */
1835 static int ep0_prime_status(struct tegra_udc *udc, int direction)
1836 {
1837         struct tegra_req *req = udc->status_req;
1838         struct tegra_ep *ep;
1839
1840         if (direction == EP_DIR_IN)
1841                 udc->ep0_dir = USB_DIR_IN;
1842         else
1843                 udc->ep0_dir = USB_DIR_OUT;
1844
1845         ep = &udc->eps[0];
1846         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1847
1848         req->ep = ep;
1849         req->req.length = 0;
1850         req->req.status = -EINPROGRESS;
1851         req->req.actual = 0;
1852         req->req.complete = NULL;
1853         req->dtd_count = 0;
1854
1855         if (tegra_req_to_dtd(req, GFP_ATOMIC) == 0)
1856                 tegra_queue_td(ep, req);
1857         else
1858                 return -ENOMEM;
1859
1860         list_add_tail(&req->queue, &ep->queue);
1861
1862         return 0;
1863 }
1864
1865 static void udc_reset_ep_queue(struct tegra_udc *udc, u8 pipe)
1866 {
1867         struct tegra_ep *ep = get_ep_by_pipe(udc, pipe);
1868
1869         if (ep->name[0])
1870                 nuke(ep, -ESHUTDOWN);
1871 }
1872
1873 /* ch9 Set address */
1874 static void ch9setaddress(struct tegra_udc *udc, u16 value, u16 index,
1875                 u16 length)
1876 {
1877         /* Save the new address to device struct */
1878         udc->device_address = (u8) value;
1879         /* Update usb state */
1880         udc->usb_state = USB_STATE_ADDRESS;
1881         /* Status phase */
1882         if (ep0_prime_status(udc, EP_DIR_IN))
1883                 ep0stall(udc);
1884 }
1885
1886 /* ch9 Get status */
1887 static void ch9getstatus(struct tegra_udc *udc, u8 request_type, u16 value,
1888                 u16 index, u16 length)
1889 {
1890         u16 tmp = 0;            /* Status, cpu endian */
1891         struct tegra_req *req;
1892         struct tegra_ep *ep;
1893
1894         ep = &udc->eps[0];
1895
1896         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1897                 /* Get device status */
1898                 if (udc->selfpowered)
1899                         tmp = 1 << USB_DEVICE_SELF_POWERED;
1900                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1901         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1902                 /* Get interface status
1903                  * We don't have interface information in udc driver */
1904                 tmp = 0;
1905         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1906                 /* Get endpoint status */
1907                 struct tegra_ep *target_ep;
1908
1909                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1910
1911                 /* stall if endpoint doesn't exist */
1912                 if (!target_ep->desc)
1913                         goto stall;
1914                 tmp = dr_ep_get_stall(udc, ep_index(target_ep),
1915                                 ep_is_in(target_ep)) << USB_ENDPOINT_HALT;
1916         }
1917
1918         udc->ep0_dir = USB_DIR_IN;
1919         /* Borrow the per device status_req */
1920         req = udc->status_req;
1921         /* Fill in the reqest structure */
1922         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1923         req->ep = ep;
1924         req->req.length = 2;
1925         req->req.status = -EINPROGRESS;
1926         req->req.actual = 0;
1927         req->req.complete = NULL;
1928         req->dtd_count = 0;
1929
1930         /* map virtual address to hardware */
1931         if (req->req.dma == DMA_ADDR_INVALID) {
1932                 DEFINE_DMA_ATTRS(attrs);
1933                 struct device *dev = ep->udc->gadget.dev.parent;
1934                 size_t orig = req->req.length;
1935                 size_t ext = orig + AHB_PREFETCH_BUFFER;
1936                 enum dma_data_direction dir =
1937                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1938
1939                 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1940                 req->req.dma = dma_map_single_attrs(dev, req->req.buf, ext, dir,
1941                                                     &attrs);
1942                 if (dma_mapping_error(dev, req->req.dma))
1943                         return;
1944
1945                 dma_sync_single_for_device(dev, req->req.dma, orig, dir);
1946
1947                 req->mapped = 1;
1948         } else {
1949                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1950                                         req->req.dma, req->req.length,
1951                                         ep_is_in(ep)
1952                                                 ? DMA_TO_DEVICE
1953                                                 : DMA_FROM_DEVICE);
1954                 req->mapped = 0;
1955         }
1956
1957         /* prime the data phase */
1958         if ((tegra_req_to_dtd(req, GFP_ATOMIC) == 0))
1959                 tegra_queue_td(ep, req);
1960         else                    /* no mem */
1961                 goto stall;
1962
1963         list_add_tail(&req->queue, &ep->queue);
1964         udc->ep0_state = DATA_STATE_XMIT;
1965         return;
1966 stall:
1967         ep0stall(udc);
1968 }
1969
1970 static void udc_test_mode(struct tegra_udc *udc, u32 test_mode)
1971 {
1972         struct tegra_req *req = NULL;
1973         struct tegra_ep *ep;
1974         u32 portsc, bitmask;
1975         unsigned long timeout;
1976
1977         /* Ack the ep0 IN */
1978         if (ep0_prime_status(udc, EP_DIR_IN))
1979                 ep0stall(udc);
1980
1981         /* get the ep0 */
1982         ep = &udc->eps[0];
1983         bitmask = ep_is_in(ep)
1984                 ? (1 << (ep_index(ep) + 16))
1985                 : (1 << (ep_index(ep)));
1986
1987         timeout = jiffies + HZ;
1988         /* Wait until ep0 IN endpoint txfr is complete */
1989         while (!(udc_readl(udc, EP_COMPLETE_REG_OFFSET) & bitmask)) {
1990                 if (time_after(jiffies, timeout)) {
1991                         pr_err("Timeout for Ep0 IN Ack\n");
1992                         break;
1993                 }
1994                 cpu_relax();
1995         }
1996
1997         switch (test_mode << PORTSCX_PTC_BIT_POS) {
1998         case PORTSCX_PTC_JSTATE:
1999                 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
2000                 schedule_work(&udc->current_work);
2001                 VDBG("TEST_J\n");
2002                 break;
2003         case PORTSCX_PTC_KSTATE:
2004                 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
2005                 schedule_work(&udc->current_work);
2006                 VDBG("TEST_K\n");
2007                 break;
2008         case PORTSCX_PTC_SEQNAK:
2009                 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
2010                 schedule_work(&udc->current_work);
2011                 VDBG("TEST_SE0_NAK\n");
2012                 break;
2013         case PORTSCX_PTC_PACKET:
2014                 VDBG("TEST_PACKET\n");
2015
2016                 /* get the ep and configure for IN direction */
2017                 ep = &udc->eps[0];
2018                 udc->ep0_dir = USB_DIR_IN;
2019
2020                 /* Initialize ep0 status request structure */
2021                 req = container_of(tegra_alloc_request(NULL, GFP_ATOMIC),
2022                                 struct tegra_req, req);
2023                 /* allocate a small amount of memory to get valid address */
2024                 req->req.buf = kmalloc(sizeof(tegra_udc_test_packet),
2025                                         GFP_ATOMIC);
2026                 req->req.dma = virt_to_phys(req->req.buf);
2027
2028                 /* Fill in the reqest structure */
2029                 memcpy(req->req.buf, tegra_udc_test_packet,
2030                                         sizeof(tegra_udc_test_packet));
2031                 req->ep = ep;
2032                 req->req.length = sizeof(tegra_udc_test_packet);
2033                 req->req.status = -EINPROGRESS;
2034                 req->req.actual = 0;
2035                 req->req.complete = NULL;
2036                 req->dtd_count = 0;
2037                 req->mapped = 0;
2038
2039                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
2040                                         req->req.dma, req->req.length,
2041                                         ep_is_in(ep)
2042                                                 ? DMA_TO_DEVICE
2043                                                 : DMA_FROM_DEVICE);
2044
2045                 /* prime the data phase */
2046                 if ((tegra_req_to_dtd(req, GFP_ATOMIC) == 0))
2047                         tegra_queue_td(ep, req);
2048                 else                    /* no mem */
2049                         goto stall;
2050
2051                 list_add_tail(&req->queue, &ep->queue);
2052                 udc->ep0_state = DATA_STATE_XMIT;
2053                 break;
2054         case PORTSCX_PTC_FORCE_EN:
2055                 VDBG("TEST_FORCE_EN\n");
2056                 break;
2057         default:
2058                 ERR("udc unknown test mode[%d]!\n", test_mode);
2059                 goto stall;
2060         }
2061
2062         /* read the portsc register */
2063         portsc = udc_readl(udc, PORTSCX_REG_OFFSET);
2064         /* set the test mode selector */
2065         portsc |= test_mode << PORTSCX_PTC_BIT_POS;
2066         udc_writel(udc, portsc, PORTSCX_REG_OFFSET);
2067
2068         /*
2069          * The device must have its power cycled to exit test mode.
2070          * See USB 2.0 spec, section 9.4.9 for test modes operation
2071          * in "Set Feature".
2072          * See USB 2.0 spec, section 7.1.20 for test modes.
2073          */
2074         pr_info("udc entering the test mode, power cycle to exit test mode\n");
2075         return;
2076 stall:
2077         ep0stall(udc);
2078         if (req) {
2079                 kfree(req->req.buf);
2080                 tegra_free_request(NULL, &req->req);
2081         }
2082 }
2083
2084 static void setup_received_irq(struct tegra_udc *udc,
2085                 struct usb_ctrlrequest *setup)
2086 {
2087         u16 wValue = le16_to_cpu(setup->wValue);
2088         u16 wIndex = le16_to_cpu(setup->wIndex);
2089         u16 wLength = le16_to_cpu(setup->wLength);
2090
2091         udc_reset_ep_queue(udc, 0);
2092
2093         /* We process some stardard setup requests here */
2094         switch (setup->bRequest) {
2095         case USB_REQ_GET_STATUS:
2096                 /* Data+Status phase from udc */
2097                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2098                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
2099                         break;
2100                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
2101                 return;
2102
2103         case USB_REQ_SET_ADDRESS:
2104                 /* Status phase from udc */
2105                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2106                                                 | USB_RECIP_DEVICE))
2107                         break;
2108                 /* This delay is necessary for some windows drivers to
2109                  * properly recognize the device */
2110                 mdelay(1);
2111                 ch9setaddress(udc, wValue, wIndex, wLength);
2112                 return;
2113
2114         case USB_REQ_CLEAR_FEATURE:
2115         case USB_REQ_SET_FEATURE:
2116                 /* Status phase from udc */
2117         {
2118                 int rc = -EOPNOTSUPP;
2119
2120                 if (setup->bRequestType == USB_RECIP_DEVICE &&
2121                                  wValue == USB_DEVICE_TEST_MODE) {
2122                         /*
2123                          * If the feature selector is TEST_MODE, then the most
2124                          * significant byte of wIndex is used to specify the
2125                          * specific test mode and the lower byte of wIndex must
2126                          * be zero.
2127                          */
2128                         udc_test_mode(udc, wIndex >> 8);
2129                         return;
2130
2131                 } else if ((setup->bRequestType &
2132                                 (USB_RECIP_MASK | USB_TYPE_MASK)) ==
2133                                 (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2134                         int pipe = get_pipe_by_windex(wIndex);
2135                         struct tegra_ep *ep;
2136
2137                         if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
2138                                 break;
2139                         ep = get_ep_by_pipe(udc, pipe);
2140
2141                         spin_unlock(&udc->lock);
2142                         rc = tegra_ep_set_halt(&ep->ep,
2143                                         (setup->bRequest == USB_REQ_SET_FEATURE)
2144                                                 ? 1 : 0);
2145                         spin_lock(&udc->lock);
2146
2147                 } else if ((setup->bRequestType & (USB_RECIP_MASK
2148                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2149                                 | USB_TYPE_STANDARD)) {
2150                         /* Note: The driver has not include OTG support yet.
2151                          * This will be set when OTG support is added */
2152                         if (!gadget_is_otg(&udc->gadget))
2153                                 break;
2154                         else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
2155                                 udc->gadget.b_hnp_enable = 1;
2156                         else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2157                                 udc->gadget.a_hnp_support = 1;
2158                         else if (setup->bRequest ==
2159                                         USB_DEVICE_A_ALT_HNP_SUPPORT)
2160                                 udc->gadget.a_alt_hnp_support = 1;
2161                         else
2162                                 break;
2163                         rc = 0;
2164                 } else
2165                         break;
2166
2167                 if (rc == 0) {
2168                         if (ep0_prime_status(udc, EP_DIR_IN))
2169                                 ep0stall(udc);
2170                 }
2171                 return;
2172         }
2173
2174         default:
2175                 break;
2176         }
2177
2178         /* Requests handled by gadget */
2179         if (wLength) {
2180                 /* Data phase from gadget, status phase from udc */
2181                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2182                                 ?  USB_DIR_IN : USB_DIR_OUT;
2183                 spin_unlock(&udc->lock);
2184                 if (udc->driver && udc->driver->setup(&udc->gadget,
2185                                 &udc->local_setup_buff) < 0)
2186                         ep0stall(udc);
2187                 spin_lock(&udc->lock);
2188                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
2189                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
2190         } else {
2191                 /* No data phase, IN status from gadget */
2192                 udc->ep0_dir = USB_DIR_IN;
2193                 spin_unlock(&udc->lock);
2194                 if (udc->driver && udc->driver->setup(&udc->gadget,
2195                                 &udc->local_setup_buff) < 0)
2196                         ep0stall(udc);
2197                 spin_lock(&udc->lock);
2198                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
2199         }
2200 }
2201
2202 /* Process request for Data or Status phase of ep0
2203  * prime status phase if needed */
2204 static void ep0_req_complete(struct tegra_udc *udc, struct tegra_ep *ep0,
2205                 struct tegra_req *req)
2206 {
2207         if (udc->usb_state == USB_STATE_ADDRESS) {
2208                 /* Set the new address */
2209                 u32 new_address = (u32) udc->device_address;
2210                 udc_writel(udc, new_address << USB_DEVICE_ADDRESS_BIT_POS,
2211                                 USB_DEVICE_ADDR_REG_OFFSET);
2212         }
2213
2214         done(ep0, req, 0);
2215
2216         switch (udc->ep0_state) {
2217         case DATA_STATE_XMIT:
2218                 /* receive status phase */
2219                 if (ep0_prime_status(udc, EP_DIR_OUT))
2220                         ep0stall(udc);
2221                 break;
2222         case DATA_STATE_RECV:
2223                 /* send status phase */
2224                 if (ep0_prime_status(udc, EP_DIR_IN))
2225                         ep0stall(udc);
2226                 break;
2227         case WAIT_FOR_OUT_STATUS:
2228                 udc->ep0_state = WAIT_FOR_SETUP;
2229                 break;
2230         case WAIT_FOR_SETUP:
2231                 ERR("Unexpect ep0 packets\n");
2232                 break;
2233         default:
2234                 ep0stall(udc);
2235                 break;
2236         }
2237 }
2238
2239 /* Tripwire mechanism to ensure a setup packet payload is extracted without
2240  * being corrupted by another incoming setup packet */
2241 static void tripwire_handler(struct tegra_udc *udc, u8 ep_num, u8 *buffer_ptr)
2242 {
2243         u32 temp;
2244         struct ep_queue_head *qh;
2245
2246         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
2247
2248         /* Clear bit in ENDPTSETUPSTAT */
2249         temp = udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET);
2250         udc_writel(udc, temp | (1 << ep_num), EP_SETUP_STATUS_REG_OFFSET);
2251
2252         /* while a hazard exists when setup package arrives */
2253         do {
2254                 /* Set Setup Tripwire */
2255                 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
2256                 udc_writel(udc, temp | USB_CMD_SUTW, USB_CMD_REG_OFFSET);
2257
2258                 /* Copy the setup packet to local buffer */
2259                 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
2260         } while (!(udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_SUTW));
2261
2262         /* Clear Setup Tripwire */
2263         temp = udc_readl(udc, USB_CMD_REG_OFFSET);
2264         udc_writel(udc, temp & ~USB_CMD_SUTW, USB_CMD_REG_OFFSET);
2265 }
2266
2267 /* process-ep_req(): free the completed Tds for this req */
2268 static int process_ep_req(struct tegra_udc *udc, int pipe,
2269                 struct tegra_req *curr_req)
2270 {
2271         struct ep_td_struct *curr_td;
2272         int     td_complete, actual, remaining_length, j, tmp;
2273         int     status = 0;
2274         int     errors = 0;
2275         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
2276         int direction = pipe % 2;
2277
2278         curr_td = curr_req->head;
2279         td_complete = 0;
2280         actual = curr_req->req.length;
2281
2282         for (j = 0; j < curr_req->dtd_count; j++) {
2283                 /* Fence read for coherency of AHB master intiated writes */
2284                 if (udc->fence_read)
2285                         readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
2286
2287                 dma_sync_single_for_cpu(udc->gadget.dev.parent, curr_td->td_dma,
2288                                 sizeof(struct ep_td_struct), DMA_FROM_DEVICE);
2289
2290                 remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
2291                                         & DTD_PACKET_SIZE)
2292                                 >> DTD_LENGTH_BIT_POS;
2293                 actual -= remaining_length;
2294                 errors = le32_to_cpu(curr_td->size_ioc_sts);
2295                 if (errors & DTD_ERROR_MASK) {
2296                         if (errors & DTD_STATUS_HALTED) {
2297                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
2298                                 /* Clear the errors and Halt condition */
2299                                 tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
2300                                 tmp &= ~errors;
2301                                 curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
2302                                 status = -EPIPE;
2303                                 /* FIXME: continue with next queued TD? */
2304
2305                                 break;
2306                         }
2307                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
2308                                 VDBG("Transfer overflow");
2309                                 status = -EPROTO;
2310                                 break;
2311                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
2312                                 VDBG("ISO error");
2313                                 status = -EILSEQ;
2314                                 break;
2315                         } else
2316                                 ERR("Unknown error has occurred (0x%x)!\n",
2317                                         errors);
2318
2319                 } else if (le32_to_cpu(curr_td->size_ioc_sts)
2320                                 & DTD_STATUS_ACTIVE) {
2321                         VDBG("Request not complete");
2322                         status = REQ_UNCOMPLETE;
2323                         return status;
2324                 } else if (remaining_length) {
2325                         if (direction) {
2326                                 VDBG("Transmit dTD remaining length not zero");
2327                                 status = -EPROTO;
2328                                 break;
2329                         } else {
2330                                 td_complete++;
2331                                 break;
2332                         }
2333                 } else {
2334                         td_complete++;
2335                         VDBG("dTD transmitted successful");
2336                 }
2337
2338                 if (j != curr_req->dtd_count - 1)
2339                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
2340         }
2341
2342         if (status)
2343                 return status;
2344
2345         curr_req->req.actual = actual;
2346
2347         return 0;
2348 }
2349
2350 /* Process a DTD completion interrupt */
2351 static void dtd_complete_irq(struct tegra_udc *udc)
2352 {
2353         u32 bit_pos;
2354         int i, ep_num, direction, bit_mask, status;
2355         struct tegra_ep *curr_ep;
2356         struct tegra_req *curr_req, *temp_req;
2357
2358         /* Clear the bits in the register */
2359         bit_pos = udc_readl(udc, EP_COMPLETE_REG_OFFSET);
2360         udc_writel(udc, bit_pos, EP_COMPLETE_REG_OFFSET);
2361
2362         if (!bit_pos)
2363                 return;
2364
2365         for (i = 0; i < udc->max_ep; i++) {
2366                 ep_num = i >> 1;
2367                 direction = i % 2;
2368
2369                 bit_mask = 1 << (ep_num + 16 * direction);
2370
2371                 if (!(bit_pos & bit_mask))
2372                         continue;
2373
2374                 curr_ep = get_ep_by_pipe(udc, i);
2375
2376                 /* If the ep is configured */
2377                 if (curr_ep->name[0] == '\0') {
2378                         WARNING("Invalid EP?");
2379                         continue;
2380                 }
2381
2382                 /* process the req queue until an uncomplete request */
2383                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
2384                                 queue) {
2385                         status = process_ep_req(udc, i, curr_req);
2386
2387                         VDBG("status of process_ep_req= %d, ep = %d",
2388                                         status, ep_num);
2389                         if (status == REQ_UNCOMPLETE)
2390                                 break;
2391                         /* write back status to req */
2392                         curr_req->req.status = status;
2393
2394                         if (ep_num == 0) {
2395                                 ep0_req_complete(udc, curr_ep, curr_req);
2396                                 break;
2397                         } else
2398                                 done(curr_ep, curr_req, status);
2399                 }
2400         }
2401 }
2402
2403 /* Process a port change interrupt */
2404 static void port_change_irq(struct tegra_udc *udc)
2405 {
2406         u32 speed;
2407         unsigned int port_control_reg_offset;
2408
2409         if (udc->has_hostpc)
2410                 port_control_reg_offset = USB_HOSTPCX_DEVLC_REG_OFFSET;
2411         else
2412                 port_control_reg_offset = PORTSCX_REG_OFFSET;
2413
2414         /* Bus resetting is finished */
2415         if (!(udc_readl(udc, port_control_reg_offset) & PORTSCX_PORT_RESET)) {
2416                 /* Get the speed */
2417                 speed = (udc_readl(udc, port_control_reg_offset)
2418                                 & PORTSCX_PORT_SPEED_MASK);
2419                 if (speed == PORTSCX_PORT_SPEED_HIGH)
2420                         udc->gadget.speed = USB_SPEED_HIGH;
2421                 else if (speed == PORTSCX_PORT_SPEED_FULL)
2422                         udc->gadget.speed = USB_SPEED_FULL;
2423                 else if (speed == PORTSCX_PORT_SPEED_LOW)
2424                         udc->gadget.speed = USB_SPEED_LOW;
2425                 else
2426                         udc->gadget.speed = USB_SPEED_UNKNOWN;
2427         }
2428
2429         /* Update USB state */
2430         if (!udc->resume_state)
2431                 udc->usb_state = USB_STATE_DEFAULT;
2432 }
2433
2434 /* Process suspend interrupt */
2435 static void suspend_irq(struct tegra_udc *udc)
2436 {
2437         udc->resume_state = udc->usb_state;
2438         udc->usb_state = USB_STATE_SUSPENDED;
2439
2440         /* report suspend to the driver, serial.c does not support this */
2441         if (udc->driver && udc->driver->suspend)
2442                 udc->driver->suspend(&udc->gadget);
2443 }
2444
2445 static void bus_resume(struct tegra_udc *udc)
2446 {
2447         udc->usb_state = udc->resume_state;
2448         udc->resume_state = 0;
2449
2450         /* report resume to the driver, serial.c does not support this */
2451         if (udc->driver && udc->driver->resume)
2452                 udc->driver->resume(&udc->gadget);
2453 }
2454
2455 /* Clear up all ep queues */
2456 static int reset_queues(struct tegra_udc *udc)
2457 {
2458         u8 pipe;
2459
2460         for (pipe = 0; pipe < udc->max_pipes; pipe++)
2461                 udc_reset_ep_queue(udc, pipe);
2462
2463         /* report disconnect; the driver is already quiesced */
2464         spin_unlock(&udc->lock);
2465         if (udc->driver && udc->driver->disconnect)
2466                 udc->driver->disconnect(&udc->gadget);
2467         spin_lock(&udc->lock);
2468
2469         return 0;
2470 }
2471
2472 /* Process reset interrupt */
2473 static void reset_irq(struct tegra_udc *udc)
2474 {
2475         u32 temp;
2476         unsigned long timeout;
2477
2478         /* Clear the device address */
2479         temp = udc_readl(udc, USB_DEVICE_ADDR_REG_OFFSET);
2480         udc_writel(udc, temp & ~USB_DEVICE_ADDRESS_MASK,
2481                                 USB_DEVICE_ADDR_REG_OFFSET);
2482
2483         udc->device_address = 0;
2484
2485         /* Clear usb state */
2486         udc->resume_state = 0;
2487         udc->ep0_dir = 0;
2488         udc->ep0_state = WAIT_FOR_SETUP;
2489         udc->remote_wakeup = 0; /* default to 0 on reset */
2490         udc->gadget.b_hnp_enable = 0;
2491         udc->gadget.a_hnp_support = 0;
2492         udc->gadget.a_alt_hnp_support = 0;
2493
2494         /* Clear all the setup token semaphores */
2495         temp = udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET);
2496         udc_writel(udc, temp, EP_SETUP_STATUS_REG_OFFSET);
2497
2498         /* Clear all the endpoint complete status bits */
2499         temp = udc_readl(udc, EP_COMPLETE_REG_OFFSET);
2500         udc_writel(udc, temp, EP_COMPLETE_REG_OFFSET);
2501
2502         timeout = jiffies + 100;
2503         while (udc_readl(udc, EP_PRIME_REG_OFFSET)) {
2504                 /* Wait until all endptprime bits cleared */
2505                 if (time_after(jiffies, timeout)) {
2506                         ERR("Timeout for reset\n");
2507                         break;
2508                 }
2509                 cpu_relax();
2510         }
2511
2512         /* Write 1s to the flush register */
2513         udc_writel(udc, 0xffffffff, EPFLUSH_REG_OFFSET);
2514
2515         /* When the bus reset is seen on Tegra, the PORTSCX_PORT_RESET bit
2516          * is not set. Reset all the queues, include XD, dTD, EP queue
2517          * head and TR Queue */
2518         VDBG("Bus reset");
2519         reset_queues(udc);
2520         udc->usb_state = USB_STATE_DEFAULT;
2521 }
2522
2523 static void tegra_udc_set_current_limit_work(struct work_struct *work)
2524 {
2525         struct tegra_udc *udc = container_of(work, struct tegra_udc,
2526                                                 current_work);
2527         tegra_usb_set_charging_current(udc);
2528 }
2529
2530 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
2531 static void tegra_udc_set_cpu_freq_normal(unsigned long data)
2532 {
2533         set_cpufreq_normal_flag = 1;
2534         schedule_work(&the_udc->boost_cpufreq_work);
2535 }
2536
2537 static void tegra_udc_boost_cpu_frequency_work(struct work_struct *work)
2538 {
2539         if (set_cpufreq_normal_flag) {
2540                 pm_qos_update_request(&boost_cpu_freq_req,
2541                                         PM_QOS_DEFAULT_VALUE);
2542                 boost_cpufreq_work_flag = 1;
2543                 set_cpufreq_normal_flag = 0;
2544                 DBG("%s(%d) set CPU frequency to normal\n", __func__,
2545                                                         __LINE__);
2546                 return ;
2547         }
2548
2549         /* If CPU frequency is not boosted earlier boost it, and modify
2550          * timer expiry time to 2sec */
2551         if (boost_cpufreq_work_flag) {
2552                 if (boost_enable)
2553                         pm_qos_update_request(
2554                                 &boost_cpu_freq_req,
2555                                 (s32)(CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
2556                                       * 1000));
2557                 boost_cpufreq_work_flag = 0;
2558                 DBG("%s(%d) boost CPU frequency\n", __func__, __LINE__);
2559         }
2560         mod_timer(&boost_timer, jiffies + msecs_to_jiffies(2000));
2561 }
2562 #endif
2563
2564 static void tegra_udc_irq_work(struct work_struct *irq_work)
2565 {
2566         struct tegra_udc *udc = container_of(irq_work, struct tegra_udc,
2567                                                  irq_work);
2568         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2569
2570         /* Check whether cable is connected*/
2571         if (vbus_enabled(udc))
2572                 tegra_vbus_session(&udc->gadget, 1);
2573         else
2574                 tegra_vbus_session(&udc->gadget, 0);
2575
2576         DBG("%s(%d) END\n", __func__, __LINE__);
2577 }
2578
2579 /*
2580  * When VBUS is detected we already know it is DCP/SDP/CDP devices if it is a
2581  * standard device. If we did not receive EP0 setup packet, we can assume it
2582  * as a non-standard charger.
2583  */
2584 static void tegra_udc_non_std_charger_detect_work(struct work_struct *work)
2585 {
2586         struct tegra_udc *udc = container_of(work, struct tegra_udc,
2587                                         non_std_charger_work.work);
2588         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2589
2590         tegra_udc_set_charger_type(udc, CONNECT_TYPE_NON_STANDARD_CHARGER);
2591         tegra_usb_set_charging_current(udc);
2592
2593         DBG("%s(%d) END\n", __func__, __LINE__);
2594 }
2595
2596 /* Restart device controller in the OTG mode on VBUS detection */
2597 static void tegra_udc_restart(struct tegra_udc *udc)
2598 {
2599         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2600
2601         /* setup the controller in the device mode */
2602         dr_controller_setup(udc);
2603         /* setup EP0 for setup packet */
2604         ep0_setup(udc);
2605         udc->vbus_active = 1;
2606         /* start the controller */
2607         dr_controller_run(udc);
2608         /* initialize the USB and EP states */
2609         udc->usb_state = USB_STATE_ATTACHED;
2610         udc->ep0_state = WAIT_FOR_SETUP;
2611         udc->ep0_dir = 0;
2612
2613         DBG("%s(%d) END\n", __func__, __LINE__);
2614 }
2615
2616 /* USB device controller interrupt handler */
2617 static irqreturn_t tegra_udc_irq(int irq, void *_udc)
2618 {
2619         struct tegra_udc *udc = _udc;
2620         u32 irq_src, temp;
2621         irqreturn_t status = IRQ_NONE;
2622         unsigned long flags;
2623
2624         spin_lock_irqsave(&udc->lock, flags);
2625
2626         if (!udc->transceiver) {
2627                 if (tegra_platform_is_fpga()) {
2628                         temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
2629                         /* write back the register to clear the interrupt */
2630                         udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
2631                         if (temp & USB_SYS_VBUS_ASESSION_CHANGED)
2632                                 schedule_work(&udc->irq_work);
2633                         status = IRQ_HANDLED;
2634                 } else {
2635                         temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
2636                         /* write back the register to clear the interrupt */
2637                         udc_writel(udc, temp, VBUS_WAKEUP_REG_OFFSET);
2638                         if (temp & USB_SYS_VBUS_WAKEUP_INT_STATUS)
2639                                 schedule_work(&udc->irq_work);
2640                         status = IRQ_HANDLED;
2641                 }
2642         }
2643
2644         /* Disable ISR for OTG host mode */
2645         if (udc->stopped)
2646                 goto done;
2647
2648         /* Fence read for coherency of AHB master intiated writes */
2649         if (udc->fence_read)
2650                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
2651
2652         irq_src = udc_readl(udc, USB_STS_REG_OFFSET) &
2653                                 udc_readl(udc, USB_INTR_REG_OFFSET);
2654
2655         if (irq_src == 0)
2656                 goto done;
2657
2658         /* Clear notification bits */
2659         udc_writel(udc, irq_src, USB_STS_REG_OFFSET);
2660
2661         /* Need to resume? */
2662         if (udc->usb_state == USB_STATE_SUSPENDED)
2663                 if (!(udc_readl(udc, PORTSCX_REG_OFFSET)
2664                                 & PORTSCX_PORT_SUSPEND))
2665                         bus_resume(udc);
2666
2667         /* USB Interrupt */
2668         if (irq_src & USB_STS_INT) {
2669                 VDBG("Packet int");
2670                 /* Setup package, we only support ep0 as control ep */
2671                 if (udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET) &
2672                                 EP_SETUP_STATUS_EP0) {
2673                         /* Setup packet received, we are connected to host
2674                          * and not to charger. Cancel any delayed work */
2675                         cancel_delayed_work(&udc->non_std_charger_work);
2676                         tripwire_handler(udc, 0,
2677                                         (u8 *) (&udc->local_setup_buff));
2678                         setup_received_irq(udc, &udc->local_setup_buff);
2679                         status = IRQ_HANDLED;
2680                 }
2681
2682                 /* completion of dtd */
2683                 if (udc_readl(udc, EP_COMPLETE_REG_OFFSET)) {
2684                         dtd_complete_irq(udc);
2685                         status = IRQ_HANDLED;
2686                 }
2687         }
2688
2689         /* SOF (for ISO transfer) */
2690         if (irq_src & USB_STS_SOF)
2691                 status = IRQ_HANDLED;
2692
2693         /* Port Change */
2694         if (irq_src & USB_STS_PORT_CHANGE) {
2695                 port_change_irq(udc);
2696                 status = IRQ_HANDLED;
2697         }
2698
2699         /* Reset Received */
2700         if (irq_src & USB_STS_RESET) {
2701                 reset_irq(udc);
2702                 status = IRQ_HANDLED;
2703         }
2704
2705         /* Sleep Enable (Suspend) */
2706         if (irq_src & USB_STS_SUSPEND) {
2707                 suspend_irq(udc);
2708                 status = IRQ_HANDLED;
2709         }
2710
2711         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR))
2712                 VDBG("Error IRQ %x", irq_src);
2713
2714 done:
2715         spin_unlock_irqrestore(&udc->lock, flags);
2716         return status;
2717 }
2718
2719 /**
2720  * Hook to gadget drivers
2721  * Called by initialization code of gadget drivers
2722  */
2723 static int tegra_udc_start(struct usb_gadget *g,
2724                 struct usb_gadget_driver *driver)
2725 {
2726         struct tegra_udc *udc = the_udc;
2727         unsigned long flags = 0;
2728         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2729
2730         /* lock is needed but whether should use this lock or another */
2731         spin_lock_irqsave(&udc->lock, flags);
2732
2733         driver->driver.bus = NULL;
2734         /* hook up the driver */
2735         udc->driver = driver;
2736         spin_unlock_irqrestore(&udc->lock, flags);
2737
2738         /* Enable DR IRQ reg and Set usbcmd reg  Run bit */
2739         if (vbus_enabled(udc) && !(udc->transceiver
2740                         && udc->transceiver->state != OTG_STATE_B_PERIPHERAL))
2741                 tegra_vbus_session(&udc->gadget, 1);
2742
2743         printk(KERN_INFO "%s: bind to driver %s\n",
2744                         udc->gadget.name, driver->driver.name);
2745
2746         DBG("%s(%d) END\n", __func__, __LINE__);
2747         return 0;
2748 }
2749
2750 /* Disconnect from gadget driver */
2751 static int tegra_udc_stop(struct usb_gadget *g,
2752                 struct usb_gadget_driver *driver)
2753 {
2754         struct tegra_udc *udc = the_udc;
2755         struct tegra_ep *loop_ep;
2756         unsigned long flags;
2757
2758         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2759
2760         tegra_vbus_session(&udc->gadget, 0);
2761
2762         /* stand operation */
2763         spin_lock_irqsave(&udc->lock, flags);
2764         udc->gadget.speed = USB_SPEED_UNKNOWN;
2765         nuke(&udc->eps[0], -ESHUTDOWN);
2766         list_for_each_entry(loop_ep, &udc->gadget.ep_list,
2767                         ep.ep_list)
2768                 nuke(loop_ep, -ESHUTDOWN);
2769         spin_unlock_irqrestore(&udc->lock, flags);
2770
2771         udc->gadget.dev.driver = NULL;
2772         udc->driver = NULL;
2773
2774         if (driver)
2775                 DBG("%s(%d) unregistered gadget driver '%s'\n",
2776                          __func__, __LINE__, driver->driver.name);
2777
2778         DBG("%s(%d) END\n", __func__, __LINE__);
2779
2780         return 0;
2781 }
2782
2783
2784 /* Internal structure setup functions */
2785 static int tegra_udc_setup_qh(struct tegra_udc *udc)
2786 {
2787         u32 dccparams;
2788         size_t size;
2789         struct resource *res;
2790
2791         /* Read Device Controller Capability Parameters register */
2792         dccparams = udc_readl(udc, DCCPARAMS_REG_OFFSET);
2793         if (!(dccparams & DCCPARAMS_DC)) {
2794                 ERR("This SOC doesn't support device role\n");
2795                 return -ENODEV;
2796         }
2797
2798         /* Get max device endpoints */
2799         /* DEN is bidirectional ep number, max_ep doubles the number */
2800         udc->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2801
2802         udc->eps = kzalloc(sizeof(struct tegra_ep) * udc->max_ep, GFP_KERNEL);
2803         if (!udc->eps) {
2804                 ERR("malloc tegra_ep failed\n");
2805                 return -1;
2806         }
2807
2808         /* Setup hardware queue heads */
2809         size = udc->max_ep * sizeof(struct ep_queue_head);
2810         udc->ep_qh = (struct ep_queue_head *)((u8 *)(udc->regs) + QH_OFFSET);
2811         res = platform_get_resource(udc->pdev, IORESOURCE_MEM, 0);
2812         if (!res) {
2813                 ERR("resource request failed\n");
2814                 kfree(udc->eps);
2815                 return -ENODEV;
2816         }
2817         udc->ep_qh_dma = res->start + QH_OFFSET;
2818         udc->ep_qh_size = size;
2819
2820         /* Initialize ep0 status request structure */
2821         /* FIXME: tegra_alloc_request() ignores ep argument */
2822         udc->status_req = container_of(tegra_alloc_request(NULL, GFP_KERNEL),
2823                         struct tegra_req, req);
2824         /* Allocate a small amount of memory to get valid address */
2825         udc->status_req->req.buf = dma_alloc_coherent(&udc->pdev->dev,
2826                                 STATUS_BUFFER_SIZE, &udc->status_req->req.dma,
2827                                 GFP_KERNEL);
2828         if (!udc->status_req->req.buf) {
2829                 ERR("alloc status_req buffer failed\n");
2830                 kfree(udc->eps);
2831                 return -ENOMEM;
2832         }
2833
2834         udc->resume_state = USB_STATE_NOTATTACHED;
2835         udc->usb_state = USB_STATE_POWERED;
2836         udc->ep0_dir = 0;
2837         udc->remote_wakeup = 0; /* default to 0 on reset */
2838
2839         return 0;
2840 }
2841
2842 /**
2843  * Setup the tegra_ep struct for eps
2844  * Link tegra_ep->ep to gadget->ep_list
2845  * ep0out is not used so do nothing here
2846  * ep0in should be taken care
2847  */
2848 static int __init struct_ep_setup(struct tegra_udc *udc, unsigned char index,
2849                 char *name, int link)
2850 {
2851         struct tegra_ep *ep = &udc->eps[index];
2852
2853         ep->udc = udc;
2854         strcpy(ep->name, name);
2855         ep->ep.name = ep->name;
2856
2857         ep->ep.ops = &tegra_ep_ops;
2858         ep->stopped = 0;
2859
2860         /* for ep0: maxP defined in desc
2861          * for other eps, maxP is set by epautoconfig() called by gadget layer
2862          */
2863         ep->ep.maxpacket = (unsigned short) ~0;
2864
2865         /* the queue lists any req for this ep */
2866         INIT_LIST_HEAD(&ep->queue);
2867
2868         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2869         if (link)
2870                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2871         ep->gadget = &udc->gadget;
2872         ep->qh = &udc->ep_qh[index];
2873
2874         return 0;
2875 }
2876
2877 static int __init tegra_udc_ep_setup(struct tegra_udc *udc)
2878 {
2879         /* initialize EP0 descriptor */
2880         static const struct usb_endpoint_descriptor tegra_ep0_desc = {
2881                 .bLength =              USB_DT_ENDPOINT_SIZE,
2882                 .bDescriptorType =      USB_DT_ENDPOINT,
2883                 .bEndpointAddress = 0,
2884                 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2885                 .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
2886         };
2887         int i;
2888
2889         /* setup QH and epctrl for ep0 */
2890         ep0_setup(udc);
2891
2892         /* setup udc->eps[] for ep0 */
2893         struct_ep_setup(udc, 0, "ep0", 0);
2894         /* for ep0: the desc defined here;
2895          * for other eps, gadget layer called ep_enable with defined desc
2896          */
2897         udc->eps[0].desc = &tegra_ep0_desc;
2898         udc->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2899
2900         /* setup the udc->eps[] for non-control endpoints and link
2901          * to gadget.ep_list */
2902         for (i = 1; i < (int)(udc->max_ep / 2); i++) {
2903                 char name[14];
2904
2905                 sprintf(name, "ep%dout", i);
2906                 struct_ep_setup(udc, i * 2, name, 1);
2907                 sprintf(name, "ep%din", i);
2908                 struct_ep_setup(udc, i * 2 + 1, name, 1);
2909         }
2910
2911         return 0;
2912 }
2913
2914 static struct tegra_usb_platform_data *tegra_udc_dt_parse_pdata(
2915                 struct platform_device *pdev)
2916 {
2917         struct tegra_usb_platform_data *pdata;
2918         struct device_node *np = pdev->dev.of_node;
2919
2920         if (!np)
2921                 return NULL;
2922
2923         pdata = devm_kzalloc(&pdev->dev, sizeof(struct tegra_usb_platform_data),
2924                         GFP_KERNEL);
2925         if (!pdata) {
2926                 dev_err(&pdev->dev, "Can't allocate platform data\n");
2927                 return ERR_PTR(-ENOMEM);
2928         }
2929
2930         pdata->port_otg = of_property_read_bool(np, "nvidia,port-otg");
2931         pdata->support_pmu_vbus =
2932                 of_property_read_bool(np, "nvidia,enable-pmu-vbus-detection");
2933         pdata->u_data.dev.charging_supported =
2934                 of_property_read_bool(np, "nvidia,charging-supported");
2935         pdata->u_data.dev.is_xhci =
2936                 of_property_read_bool(np, "nvidia,enable-xhci-host");
2937
2938         of_property_read_u32(np, "nvidia,dcp-current-limit-ma",
2939                                 &pdata->u_data.dev.dcp_current_limit_ma);
2940         of_property_read_u32(np, "nvidia,qc2-current-limit-ma",
2941                                 &pdata->u_data.dev.qc2_current_limit_ma);
2942         of_property_read_u32(np, "nvidia,qc2-input-voltage",
2943                                 &pdata->qc2_voltage);
2944         of_property_read_u32(np, "nvidia,id-detection-type",
2945                                 &pdata->id_det_type);
2946
2947         DBG("%s(%d) DT parsing done\n", __func__, __LINE__);
2948         return pdata;
2949 }
2950
2951 static struct tegra_udc_soc_data tegra_soc_config = {
2952         .utmi = {
2953                 .hssync_start_delay = 0,
2954                 .elastic_limit = 16,
2955                 .idle_wait_delay = 17,
2956                 .term_range_adj = 6,
2957                 .xcvr_setup = 8,
2958                 .xcvr_lsfslew = 2,
2959                 .xcvr_lsrslew = 2,
2960                 .xcvr_setup_offset = 0,
2961                 .xcvr_use_fuses = 1,
2962         },
2963         .has_hostpc = true,
2964         .unaligned_dma_buf_supported = false,
2965         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
2966         .op_mode = TEGRA_USB_OPMODE_DEVICE,
2967 };
2968
2969 static struct tegra_udc_soc_data tegra21x_soc_config = {
2970         .utmi = {
2971                 .hssync_start_delay = 0,
2972                 .elastic_limit = 16,
2973                 .idle_wait_delay = 17,
2974                 .term_range_adj = 6,
2975                 .xcvr_setup = 8,
2976                 .xcvr_lsfslew = 2,
2977                 .xcvr_lsrslew = 2,
2978                 .xcvr_setup_offset = 0,
2979                 .xcvr_use_fuses = 0,
2980         },
2981         .has_hostpc = true,
2982         .unaligned_dma_buf_supported = false,
2983         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
2984         .op_mode = TEGRA_USB_OPMODE_DEVICE,
2985 };
2986
2987 static struct of_device_id tegra_udc_of_match[] = {
2988         {.compatible = "nvidia,tegra210-udc", .data = &tegra21x_soc_config, },
2989         {.compatible = "nvidia,tegra132-udc", .data = &tegra_soc_config, },
2990         {.compatible = "nvidia,tegra124-udc", .data = &tegra_soc_config, },
2991         { /* termination */ },
2992 };
2993 MODULE_DEVICE_TABLE(of, tegra_udc_of_match);
2994
2995 /* Driver probe function
2996  * all intialization operations implemented here except enabling usb_intr reg
2997  * board setup should have been done in the platform code
2998  */
2999 static int __init tegra_udc_probe(struct platform_device *pdev)
3000 {
3001         struct tegra_udc *udc;
3002         struct resource *res;
3003         struct tegra_usb_platform_data *pdata;
3004         const struct of_device_id *match;
3005         struct tegra_udc_soc_data *soc_data;
3006         struct tegra_usb_dev_mode_data *dev_pdata;
3007         unsigned char xcvr_setup_offset;
3008
3009         int err = -ENODEV;
3010         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3011
3012 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
3013         if (tegra_bonded_out_dev(BOND_OUT_USBD))
3014                 return -ENODEV;
3015 #endif
3016
3017         the_udc = udc = devm_kzalloc(&pdev->dev,
3018                                 sizeof(struct tegra_udc), GFP_KERNEL);
3019         if (udc == NULL) {
3020                 ERR("malloc udc failed\n");
3021                 return -ENOMEM;
3022         }
3023
3024         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3025         if (!res) {
3026                 err = -ENXIO;
3027                 ERR("failed to get platform resources\n");
3028                 goto err_kfree;
3029         }
3030
3031         if (!request_mem_region(res->start, res->end - res->start + 1,
3032                                 driver_name)) {
3033                 ERR("request mem region failed\n");
3034                 err = -EBUSY;
3035                 goto err_kfree;
3036         }
3037
3038         udc->regs = ioremap(res->start, resource_size(res));
3039         if (!udc->regs) {
3040                 err = -ENOMEM;
3041                 ERR("failed to map mem region\n");
3042                 goto err_rel_mem_region;
3043         }
3044
3045         udc->irq = platform_get_irq(pdev, 0);
3046         if (!udc->irq) {
3047                 err = -ENODEV;
3048                 ERR("failed to get platform irq resources\n");
3049                 goto err_iounmap;
3050         }
3051
3052         err = request_irq(udc->irq, tegra_udc_irq,
3053                                 IRQF_SHARED | IRQF_TRIGGER_HIGH,
3054                                 driver_name, udc);
3055         if (err) {
3056                 ERR("cannot request irq %d err %d\n", udc->irq, err);
3057                 goto err_iounmap;
3058         }
3059
3060         if (pdev->dev.of_node) {
3061                 match = of_match_device(of_match_ptr(tegra_udc_of_match),
3062                                 &pdev->dev);
3063                 if (!match) {
3064                         dev_err(&pdev->dev, "Error: No device match found\n");
3065                         return -ENODEV;
3066                 }
3067
3068                 soc_data = (struct tegra_udc_soc_data *)match->data;
3069                 pdata = tegra_udc_dt_parse_pdata(pdev);
3070                 udc->support_aca_nv_cable =
3071                                 of_property_read_bool(pdev->dev.of_node,
3072                                         "nvidia,enable-aca-nv-charger-detection");
3073                 udc->support_aca_rid =
3074                                 of_property_read_bool(pdev->dev.of_node,
3075                                         "nvidia,enable-aca-rid-detection");
3076                 pdata->has_hostpc = soc_data->has_hostpc;
3077                 pdata->unaligned_dma_buf_supported =
3078                         soc_data->unaligned_dma_buf_supported;
3079                 pdata->phy_intf = soc_data->phy_intf;
3080                 pdata->op_mode = soc_data->op_mode;
3081                 pdata->u_cfg.utmi = soc_data->utmi;
3082
3083                 /* Note:  setup_offset is actually a signed char value*/
3084                 if (!of_property_read_u8(pdev->dev.of_node,
3085                                 "nvidia,xcvr-setup-offset",
3086                                 &xcvr_setup_offset))
3087                         pdata->u_cfg.utmi.xcvr_setup_offset =
3088                                 (signed char)xcvr_setup_offset;
3089
3090                 dev_pdata = dev_get_platdata(&pdev->dev);
3091                 if (dev_pdata)
3092                         pdata->u_data.dev.is_xhci = dev_pdata->is_xhci;
3093
3094                 pdev->dev.platform_data = pdata;
3095         }
3096
3097         pdata = dev_get_platdata(&pdev->dev);
3098         if (pdata) {
3099                 /*Disable fence read if H/W support is disabled*/
3100                 if (pdata->unaligned_dma_buf_supported)
3101                         udc->fence_read = false;
3102                 else
3103                         udc->fence_read = true;
3104
3105                 udc->charging_supported = pdata->u_data.dev.charging_supported;
3106                 udc->qc2_voltage = pdata->qc2_voltage;
3107
3108                 udc->qc2_current_limit =
3109                         pdata->u_data.dev.qc2_current_limit_ma * 1000;
3110
3111                 DBG("%s: QC2 voltage = %d, current = %d\n",
3112                         __func__,
3113                         udc->qc2_voltage,
3114                         udc->qc2_current_limit);
3115
3116                 if (pdata->u_data.dev.dcp_current_limit_ma)
3117                         udc->dcp_current_limit =
3118                                 pdata->u_data.dev.dcp_current_limit_ma * 1000;
3119                 else
3120                         udc->dcp_current_limit =
3121                                 USB_CHARGING_DCP_CURRENT_LIMIT_UA;
3122         } else {
3123                 dev_err(&pdev->dev, "failed to get platform_data\n");
3124                 err = -ENODATA;
3125                 goto err_irq;
3126         }
3127
3128         udc->phy = tegra_usb_phy_open(pdev);
3129         if (IS_ERR(udc->phy)) {
3130                 dev_err(&pdev->dev, "failed to open USB phy\n");
3131                 err = -ENXIO;
3132                 goto err_irq;
3133         }
3134
3135         err = tegra_usb_phy_power_on(udc->phy);
3136         if (err) {
3137                 dev_err(&pdev->dev, "failed to power on the phy\n");
3138                 goto err_phy;
3139         }
3140
3141         err = usb_phy_init(get_usb_phy(udc->phy));
3142         if (err) {
3143                 dev_err(&pdev->dev, "failed to init the phy\n");
3144                 goto err_phy;
3145         }
3146         spin_lock_init(&udc->lock);
3147         mutex_init(&udc->sync_lock);
3148         udc->stopped = 1;
3149         udc->pdev = pdev;
3150         udc->has_hostpc = pdata->has_hostpc;
3151         udc->support_pmu_vbus = pdata->support_pmu_vbus;
3152         udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3153         platform_set_drvdata(pdev, udc);
3154
3155         /* Initialize the udc structure including QH members */
3156         err = tegra_udc_setup_qh(udc);
3157         if (err) {
3158                 dev_err(&pdev->dev, "failed to setup udc QH\n");
3159                 goto err_phy;
3160         }
3161
3162         /* Initialize usb hw reg except for regs for EP,
3163          * leave usbintr reg untouched */
3164         err = dr_controller_setup(udc);
3165         if (err) {
3166                 dev_err(&pdev->dev, "failed to setup udc controller\n");
3167                 goto err_phy;
3168         }
3169
3170         /* Setup gadget structure */
3171         udc->gadget.ops = &tegra_gadget_ops;
3172         udc->gadget.max_speed = USB_SPEED_HIGH;
3173         udc->gadget.ep0 = &udc->eps[0].ep;
3174         INIT_LIST_HEAD(&udc->gadget.ep_list);
3175         udc->gadget.speed = USB_SPEED_UNKNOWN;
3176         udc->gadget.name = driver_name;
3177
3178         err = tegra_udc_ep_setup(udc);
3179         if (err) {
3180                 dev_err(&pdev->dev, "failed to setup end points\n");
3181                 goto err_phy;
3182         }
3183
3184         /* Use dma_pool for TD management */
3185         udc->td_pool = dma_pool_create("udc_td", &pdev->dev,
3186                         sizeof(struct ep_td_struct),
3187                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
3188         if (!udc->td_pool) {
3189                 err = -ENOMEM;
3190                 goto err_phy;
3191         }
3192
3193         err = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
3194                 tegra_udc_release);
3195         if (err)
3196                 goto err_del_udc;
3197 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
3198         boost_cpufreq_work_flag = 1;
3199         ep_queue_request_count = 0;
3200         INIT_WORK(&udc->boost_cpufreq_work,
3201                                         tegra_udc_boost_cpu_frequency_work);
3202         pm_qos_add_request(&boost_cpu_freq_req, PM_QOS_CPU_FREQ_MIN,
3203                                         PM_QOS_DEFAULT_VALUE);
3204         setup_timer(&boost_timer, tegra_udc_set_cpu_freq_normal, 0);
3205 #endif
3206
3207         /* External connector */
3208         udc->edev = kzalloc(sizeof(struct extcon_dev), GFP_KERNEL);
3209         if (!udc->edev) {
3210                 dev_err(&pdev->dev, "failed to allocate memory for extcon\n");
3211                 err = -ENOMEM;
3212                 goto err_del_udc;
3213         }
3214
3215         udc->edev->name = driver_name;
3216         udc->edev->supported_cable = (const char **) tegra_udc_extcon_cable;
3217         udc->edev->dev.parent = &pdev->dev;
3218         err = extcon_dev_register(udc->edev);
3219         if (err) {
3220                 dev_err(&pdev->dev, "failed to register extcon device\n");
3221                 kfree(udc->edev);
3222                 udc->edev = NULL;
3223         }
3224
3225         if (udc->support_pmu_vbus) {
3226                 if (pdev->dev.of_node) {
3227                         udc->vbus_extcon_dev = extcon_get_extcon_dev_by_cable(
3228                                         &pdev->dev, "vbus");
3229                 } else if (pdata->vbus_extcon_dev_name) {
3230                         udc->vbus_extcon_dev =
3231                                 extcon_get_extcon_dev(pdata->vbus_extcon_dev_name);
3232                 }
3233         }
3234
3235         if (udc->support_aca_nv_cable) {
3236                 if (pdev->dev.of_node)
3237                         udc->aca_nv_extcon_cable =
3238                                 extcon_get_extcon_cable(&pdev->dev, "aca-nv");
3239                 if (IS_ERR(udc->aca_nv_extcon_cable)) {
3240                         dev_err(&pdev->dev,
3241                                         "failed to get aca-nv extcon cable\n");
3242                         err = -EPROBE_DEFER;
3243                 } else
3244                         udc->aca_nv_extcon_dev =
3245                                 udc->aca_nv_extcon_cable->edev;
3246         }
3247
3248         if (udc->support_aca_rid && pdev->dev.of_node) {
3249                 udc->aca_rid_b_ecable =
3250                         extcon_get_extcon_cable(&pdev->dev, "aca-rb");
3251                 if (IS_ERR(udc->aca_rid_b_ecable)) {
3252                         dev_err(&pdev->dev,
3253                                 "failed to get aca-rid-b extcon cable\n");
3254                         err = -EPROBE_DEFER;
3255                         goto err_del_udc;
3256                 }
3257
3258                 udc->aca_rid_c_ecable =
3259                         extcon_get_extcon_cable(&pdev->dev, "aca-rc");
3260                 if (IS_ERR(udc->aca_rid_c_ecable)) {
3261                         dev_err(&pdev->dev,
3262                                 "failed to get aca-rid-c extcon cable\n");
3263                         err = -EPROBE_DEFER;
3264                         goto err_del_udc;
3265                 }
3266         }
3267
3268         /* Create work for controlling clocks to the phy if otg is disabled */
3269         INIT_WORK(&udc->irq_work, tegra_udc_irq_work);
3270         INIT_DELAYED_WORK(&udc->non_std_charger_work,
3271                         tegra_udc_non_std_charger_detect_work);
3272         INIT_WORK(&udc->current_work, tegra_udc_set_current_limit_work);
3273         /* Get the regulator for drawing the vbus current in udc driver */
3274         udc->vbus_reg = regulator_get(&pdev->dev, "usb_bat_chg");
3275         if (IS_ERR(udc->vbus_reg)) {
3276                 dev_info(&pdev->dev,
3277                         "usb_bat_chg regulator not registered:"
3278                                 " USB charging will not be enabled\n");
3279                 udc->vbus_reg = NULL;
3280         }
3281
3282         if (pdata->port_otg)
3283                 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
3284
3285         if (IS_ERR_OR_NULL(udc->transceiver))
3286                 udc->transceiver = NULL;
3287
3288         if (udc->transceiver) {
3289                 dr_controller_stop(udc);
3290                 dr_controller_reset(udc);
3291                 tegra_usb_phy_power_off(udc->phy);
3292                 udc->vbus_active = 0;
3293                 udc->usb_state = USB_STATE_DEFAULT;
3294                 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
3295         }
3296
3297         DBG("%s(%d) END\n", __func__, __LINE__);
3298         return 0;
3299
3300 err_del_udc:
3301         dma_pool_destroy(udc->td_pool);
3302
3303 err_phy:
3304         usb_phy_shutdown(get_usb_phy(udc->phy));
3305
3306 err_irq:
3307         free_irq(udc->irq, udc);
3308
3309 err_iounmap:
3310         iounmap(udc->regs);
3311
3312 err_rel_mem_region:
3313         release_mem_region(res->start, res->end - res->start + 1);
3314
3315 err_kfree:
3316         return err;
3317 }
3318
3319 /* Driver removal function
3320  * Free resources and finish pending transactions
3321  */
3322 static int __exit tegra_udc_remove(struct platform_device *pdev)
3323 {
3324         struct tegra_udc *udc = platform_get_drvdata(pdev);
3325         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3326
3327         DECLARE_COMPLETION(done);
3328
3329         if (!udc)
3330                 return -ENODEV;
3331         if (!res) {
3332                 ERR("resource request failed\n");
3333                 return -ENODEV;
3334         }
3335
3336         if (udc->edev != NULL) {
3337                 extcon_dev_unregister(udc->edev);
3338                 kfree(udc->edev);
3339         }
3340
3341         udc->done = &done;
3342         usb_del_gadget_udc(&udc->gadget);
3343
3344         cancel_delayed_work(&udc->non_std_charger_work);
3345         cancel_work_sync(&udc->irq_work);
3346 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
3347         cancel_work_sync(&udc->boost_cpufreq_work);
3348         pm_qos_remove_request(&boost_cpu_freq_req);
3349         del_timer(&boost_timer);
3350 #endif
3351
3352         if (udc->vbus_reg)
3353                 regulator_put(udc->vbus_reg);
3354
3355         if (udc->transceiver)
3356                 otg_set_peripheral(udc->transceiver->otg, NULL);
3357
3358         /* Free allocated memory */
3359         dma_free_coherent(&pdev->dev, STATUS_BUFFER_SIZE,
3360                                 udc->status_req->req.buf,
3361                                 udc->status_req->req.dma);
3362         kfree(udc->status_req);
3363         kfree(udc->eps);
3364
3365         dma_pool_destroy(udc->td_pool);
3366         free_irq(udc->irq, udc);
3367         iounmap(udc->regs);
3368         release_mem_region(res->start, res->end - res->start + 1);
3369
3370         mutex_destroy(&udc->sync_lock);
3371         /* Free udc -- wait for the release() finished */
3372         wait_for_completion(&done);
3373
3374         return 0;
3375 }
3376
3377 #ifdef CONFIG_PM
3378 static int tegra_udc_prepare(struct device *dev)
3379 {
3380         struct tegra_udc *udc = dev_get_drvdata(dev);
3381         u32 temp;
3382         int index;
3383         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3384
3385         if (udc->support_pmu_vbus) {
3386                 if (udc->vbus_extcon_dev != NULL &&
3387                         extcon_get_cable_state(udc->vbus_extcon_dev, "USB"))
3388                         udc->vbus_in_lp0 = true;
3389         } else {
3390                 temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
3391                 if (temp & USB_SYS_VBUS_STATUS)
3392                         udc->vbus_in_lp0 = true;
3393         }
3394
3395         if (udc->support_aca_nv_cable && udc->aca_nv_extcon_cable) {
3396                 index = udc->aca_nv_extcon_cable->cable_index;
3397                 if (extcon_get_cable_state_(udc->aca_nv_extcon_dev, index))
3398                         udc->vbus_in_lp0 = true;
3399         }
3400
3401         if (udc->support_aca_rid && udc->aca_rid_b_ecable) {
3402                 index = udc->aca_rid_b_ecable->cable_index;
3403                 if (extcon_get_cable_state_(udc->aca_rid_b_ecable->edev,
3404                                                 index))
3405                         udc->vbus_in_lp0 = true;
3406         }
3407
3408         if (udc->support_aca_rid && udc->aca_rid_c_ecable) {
3409                 index = udc->aca_rid_c_ecable->cable_index;
3410                 if (extcon_get_cable_state_(udc->aca_rid_c_ecable->edev,
3411                                                 index))
3412                         udc->vbus_in_lp0 = true;
3413         }
3414         /* During driver resume sometimes connect_type_lp0 is
3415            set to NONE, which means task is finished incomplete,
3416            in this case retain the value */
3417         if (udc->connect_type_lp0 == CONNECT_TYPE_NONE)
3418                 udc->connect_type_lp0 = udc->connect_type;
3419
3420         dev_info(dev, "%s: lp0_connect_type = %d\n", __func__,
3421                 udc->connect_type_lp0);
3422
3423         DBG("%s(%d) END\n", __func__, __LINE__);
3424         return 0;
3425 }
3426
3427 static void tegra_udc_complete(struct device *dev)
3428 {
3429         struct tegra_udc *udc = dev_get_drvdata(dev);
3430
3431         /* vbus_in_lp0 flag is and should be cleared in resume callback,
3432            we clear the flag here in case system suspend is aborted after
3433            prepare callback is done but before running suspend callback */
3434         udc->vbus_in_lp0 = false;
3435 }
3436
3437 static int tegra_udc_suspend(struct device *dev)
3438 {
3439         struct tegra_udc *udc = dev_get_drvdata(dev);
3440         unsigned long flags;
3441
3442         int err = 0;
3443         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3444
3445         /* If the controller is in otg mode, return */
3446         if (udc->transceiver)
3447                 return 0;
3448
3449         if (udc->irq) {
3450                 err = enable_irq_wake(udc->irq);
3451                 if (err < 0)
3452                         dev_err(dev,
3453                         "Couldn't enable USB udc mode wakeup,"
3454                         " irq=%d, error=%d\n", udc->irq, err);
3455         }
3456
3457         if (udc->vbus_active) {
3458                 spin_lock_irqsave(&udc->lock, flags);
3459                 /* Reset all internal Queues and inform client driver */
3460                 reset_queues(udc);
3461                 udc->vbus_active = 0;
3462                 udc->usb_state = USB_STATE_DEFAULT;
3463                 spin_unlock_irqrestore(&udc->lock, flags);
3464         }
3465         /* Stop the controller and turn off the clocks */
3466         dr_controller_stop(udc);
3467
3468         tegra_usb_phy_power_off(udc->phy);
3469
3470         DBG("%s(%d) END\n", __func__, __LINE__);
3471         return 0;
3472 }
3473
3474 static int tegra_udc_resume(struct device *dev)
3475 {
3476         struct tegra_udc *udc = dev_get_drvdata(dev);
3477         u32 temp;
3478
3479         int err = 0, index;
3480         DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3481
3482         udc->vbus_in_lp0 = false;
3483
3484         /* Set Current limit to 0 if charger is disconnected in LP0 */
3485         if (udc->vbus_reg != NULL) {
3486                 if (udc->support_aca_nv_cable && udc->aca_nv_extcon_cable &&
3487                         udc->connect_type_lp0 == CONNECT_TYPE_ACA_NV_CHARGER) {
3488                         index = udc->aca_nv_extcon_cable->cable_index;
3489                         if ((udc->connect_type_lp0 != CONNECT_TYPE_NONE) &&
3490                                 !extcon_get_cable_state_(udc->aca_nv_extcon_dev,
3491                                                                 index)) {
3492                                 tegra_udc_set_extcon_state(udc);
3493                                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3494                                 regulator_set_current_limit(udc->vbus_reg,
3495                                                                 0, 0);
3496                         }
3497                 } else if (udc->support_aca_rid && udc->aca_rid_b_ecable &&
3498                         udc->connect_type_lp0 == CONNECT_TYPE_ACA_RID_B) {
3499                         index = udc->aca_rid_b_ecable->cable_index;
3500                         if ((udc->connect_type_lp0 == CONNECT_TYPE_ACA_RID_B) &&
3501                                 !extcon_get_cable_state_(
3502                                         udc->aca_rid_b_ecable->edev, index)) {
3503                                 tegra_udc_set_extcon_state(udc);
3504                                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3505                                 regulator_set_current_limit(udc->vbus_reg,
3506                                                                 0, 0);
3507                         }
3508                 } else if (udc->support_aca_rid && udc->aca_rid_c_ecable &&
3509                         udc->connect_type_lp0 == CONNECT_TYPE_ACA_RID_C) {
3510                         index = udc->aca_rid_c_ecable->cable_index;
3511                         if ((udc->connect_type_lp0 != CONNECT_TYPE_ACA_RID_C) &&
3512                                 !extcon_get_cable_state_(
3513                                         udc->aca_rid_c_ecable->edev, index)) {
3514                                 tegra_udc_set_extcon_state(udc);
3515                                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3516                                 regulator_set_current_limit(udc->vbus_reg,
3517                                                                 0, 0);
3518                         }
3519                 } else if (udc->support_pmu_vbus) {
3520                         dev_info(dev, "%s: state (%d, %d)\n", __func__,
3521                                udc->connect_type_lp0,
3522                                udc->vbus_extcon_dev != NULL ?
3523                                 extcon_get_cable_state(udc->vbus_extcon_dev,
3524                                                                 "USB") : -1);
3525                         if ((udc->connect_type_lp0 != CONNECT_TYPE_NONE) &&
3526                                 udc->vbus_extcon_dev != NULL &&
3527                                 !extcon_get_cable_state(udc->vbus_extcon_dev,
3528                                                                 "USB")) {
3529                                 tegra_udc_set_extcon_state(udc);
3530                                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3531                                 regulator_set_current_limit(udc->vbus_reg,
3532                                                                          0, 0);
3533                         }
3534                 } else {
3535                         temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
3536                         if ((udc->connect_type_lp0 != CONNECT_TYPE_NONE) &&
3537                                         !(temp & USB_SYS_VBUS_STATUS)) {
3538                                 tegra_udc_set_extcon_state(udc);
3539                                 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3540                                 regulator_set_current_limit(udc->vbus_reg,
3541                                                                          0, 0);
3542                         }
3543                 }
3544         }
3545
3546         if (udc->transceiver)
3547                 return 0;
3548
3549         if (udc->irq) {
3550                 err = disable_irq_wake(udc->irq);
3551                 if (err < 0)
3552                         dev_err(dev,
3553                                 "Couldn't disable USB udc mode wakeup, "
3554                                 "irq=%d, error=%d\n", udc->irq, err);
3555         }
3556
3557         tegra_usb_phy_power_on(udc->phy);
3558         tegra_udc_restart(udc);
3559
3560         /* Power down the phy if cable is not connected */
3561         if (!vbus_enabled(udc)) {
3562                 udc->vbus_active = 0;
3563                 tegra_usb_phy_power_off(udc->phy);
3564         }
3565
3566         DBG("%s(%d) END\n", __func__, __LINE__);
3567         return 0;
3568 }
3569
3570 static const struct dev_pm_ops tegra_udc_pm_ops = {
3571         .prepare = tegra_udc_prepare,
3572         .complete = tegra_udc_complete,
3573         .suspend = tegra_udc_suspend,
3574         .resume = tegra_udc_resume,
3575 };
3576 #endif /* CONFIG_PM */
3577
3578 static struct platform_driver tegra_udc_driver = {
3579         .remove  = __exit_p(tegra_udc_remove),
3580         .driver  = {
3581                 .name = (char *)driver_name,
3582                 .owner = THIS_MODULE,
3583                 .of_match_table = of_match_ptr(tegra_udc_of_match),
3584 #ifdef CONFIG_PM
3585                 .pm = &tegra_udc_pm_ops,
3586 #endif
3587         },
3588 };
3589
3590 static int __init udc_init(void)
3591 {
3592         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
3593         return platform_driver_probe(&tegra_udc_driver, tegra_udc_probe);
3594 }
3595 module_init(udc_init);
3596 static void __exit udc_exit(void)
3597 {
3598         platform_driver_unregister(&tegra_udc_driver);
3599         printk(KERN_WARNING "%s unregistered\n", driver_desc);
3600 }
3601 module_exit(udc_exit);
3602
3603 MODULE_DESCRIPTION(DRIVER_DESC);
3604 MODULE_AUTHOR(DRIVER_AUTHOR);
3605 MODULE_LICENSE("GPL");
3606 MODULE_ALIAS("platform:tegra-udc");