drivers/video/tegra/dc/hdmi.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/fb.h>
  24 #include <linux/gpio.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/mutex.h>
  29 #ifdef CONFIG_SWITCH
  30 #include <linux/switch.h>
  31 #endif
  32 #include <linux/debugfs.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/device.h>
  35 #include <linux/export.h>
  36 #include <linux/clk/tegra.h>
  37
  38 #include <mach/dc.h>
  39 #include <mach/fb.h>
  40 #include <linux/nvhost.h>
  41 #include <mach/hdmi-audio.h>
  42
  43 #include <video/tegrafb.h>
  44
  45 #include "dc_reg.h"
  46 #include "dc_priv.h"
  47 #include "hdmi_reg.h"
  48 #include "hdmi.h"
  49 #include "hdmi_state_machine.h"
  50 #include "edid.h"
  51 #include "nvhdcp.h"
  52 #include <linux/of.h>
  53 #include <linux/of_address.h>
  54
  55 /* datasheet claims this will always be 216MHz */
  56 #define HDMI_AUDIOCLK_FREQ              216000000
  57
  58 #define HDMI_REKEY_DEFAULT              56
  59
  60 #define HDMI_ELD_VER_INDEX                      0
  61 #define HDMI_ELD_RESERVED1_INDEX                1
  62 #define HDMI_ELD_BASELINE_LEN_INDEX             2
  63 #define HDMI_ELD_RESERVED2_INDEX                3
  64 #define HDMI_ELD_CEA_VER_MNL_INDEX              4
  65 #define HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX         5
  66 #define HDMI_ELD_AUD_SYNC_DELAY_INDEX           6
  67 #define HDMI_ELD_SPK_ALLOC_INDEX                7
  68 #define HDMI_ELD_PORT_ID_INDEX                  8  /*  8 to 15  */
  69 #define HDMI_ELD_MANF_NAME_INDEX                16 /* 16 to 17 */
  70 #define HDMI_ELD_PRODUCT_CODE_INDEX             18 /* 18 to 19 */
  71 #define HDMI_ELD_MONITOR_NAME_INDEX             20 /* 20 to 20 + MNL - 1 */
  72 #define HDMI_ELD_BUF_SIZE                       96
  73
  74 /* According to HDA ELD spec, the maxmimum baseline
  75  * eld size for tye 2 ELD_Ver encoding (which is
  76  * what this code supports) is 80 bytes.
  77  */
  78 #define MAX_BASELINE_ELD_SIZE                   80
  79
  80 /* These two values need to be cross checked in case of
  81      addition/removal from tegra_dc_hdmi_aspect_ratios[] */
  82 #define TEGRA_DC_HDMI_MIN_ASPECT_RATIO_PERCENT  80
  83 #define TEGRA_DC_HDMI_MAX_ASPECT_RATIO_PERCENT  320
  84
  85 struct tegra_dc_hdmi_data *dc_hdmi;
  86
  87 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
  88 const struct tmds_config tmds_config[] = {
  89         { /* 480p modes */
  90         .pclk = 27000000,
  91         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  92                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
  93                 SOR_PLL_TX_REG_LOAD(0),
  94         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
  95         .pe_current = 0x00000000,
  96         .drive_current = 0x0a0a0a0a,
  97         },
  98         { /* 720p modes */
  99         .pclk = 74250000,
 100         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 101                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 102                 SOR_PLL_TX_REG_LOAD(0),
 103         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 104         .pe_current = 0x0a0a0a0a,
 105         .drive_current = 0x0a0a0a0a,
 106         },
 107         { /* 1080p modes */
 108         .pclk = INT_MAX,
 109         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 110                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(3) |
 111                 SOR_PLL_TX_REG_LOAD(0),
 112         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 113         .pe_current = 0x0a0a0a0a,
 114         .drive_current = 0x0a0a0a0a,
 115         },
 116 };
 117 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
 118 const struct tmds_config tmds_config[] = {
 119         { /* 480p modes */
 120         .pclk = 27000000,
 121         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 122                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
 123                 SOR_PLL_TX_REG_LOAD(3),
 124         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 125         .pe_current = 0x00000000,
 126         .drive_current = 0x0f0f0f0f,
 127         },
 128         { /* 720p modes */
 129         .pclk = 74250000,
 130         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 131                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 132                 SOR_PLL_TX_REG_LOAD(3),
 133         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 134         .pe_current = 0x0c0c0c0c,
 135         .drive_current = 0x0f0f0f0f,
 136         },
 137         { /* 1080p modes */
 138         .pclk = INT_MAX,
 139         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 140                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 141                 SOR_PLL_TX_REG_LOAD(3),
 142         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 143         .pe_current = 0x0c0c0c0c,
 144         .drive_current = 0x0f0f0f0f,
 145         },
 146 };
 147 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
 148 const struct tmds_config tmds_config[] = {
 149         { /* 480p/576p / 25.2MHz/27MHz modes */
 150         .pclk = 27000000,
 151         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 152                 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT,
 153         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 154         .pe_current = 0x00000000,
 155         .drive_current = 0x1a1a1a1a,
 156         .peak_current = 0x00000000,
 157         },
 158         { /* 720p / 74.25MHz modes */
 159         .pclk = 74250000,
 160         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 161                 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT,
 162         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 163         .pe_current = 0x0f0f0f0f,
 164         .drive_current = 0x1a1a1a1a,
 165         .peak_current = 0x00000000,
 166         },
 167         { /* 1080p / 148.5MHz modes */
 168         .pclk = 148500000,
 169         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 170                 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT,
 171         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 172         .pe_current = 0x0a0a0a0a,
 173         .drive_current = 0x1f1f1f1f,
 174         .peak_current = 0x00000000,
 175         },
 176         { /* 225/297MHz modes */
 177         .pclk = INT_MAX,
 178         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 179                 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT,
 180         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 181                 | SOR_PLL_TMDS_TERM_ENABLE,
 182         .pe_current = 0x00000000,
 183         .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */
 184         .peak_current = 0x040f0f0f,
 185         /* Alternative settings:
 186         .drive_current = 0x2c333333,
 187         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(6)
 188                 | SOR_PLL_TMDS_TERM_ENABLE,
 189         */
 190         },
 191 };
 192 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
 193 const struct tmds_config tmds_config[] = {
 194         { /* 480p/576p / 25.2MHz/27MHz modes */
 195         .version = MKDEV(1, 0),
 196         .pclk = 27000000,
 197         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 198                 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT,
 199         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 200         .pe_current = 0x00000000,
 201         .drive_current = 0x1a1a1a1a,
 202         .peak_current = 0x00000000,
 203         .pad_ctls0_mask    = 0xfffff0ff,
 204         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 205         },
 206         { /* 720p / 74.25MHz modes */
 207         .version = MKDEV(1, 0),
 208         .pclk = 74250000,
 209         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 210                 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT,
 211         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 212         .pe_current = 0x0f0f0f0f,
 213         .drive_current = 0x1a1a1a1a,
 214         .peak_current = 0x00000000,
 215         .pad_ctls0_mask    = 0xfffff0ff,
 216         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 217         },
 218         { /* 1080p / 148.5MHz modes */
 219         .version = MKDEV(1, 0),
 220         .pclk = 148500000,
 221         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 222                 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT,
 223         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 224         .pe_current = 0x0a0a0a0a,
 225         .drive_current = 0x1f1f1f1f,
 226         .peak_current = 0x00000000,
 227         .pad_ctls0_mask    = 0xfffff0ff,
 228         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 229         },
 230         { /* 225/297MHz modes */
 231         .version = MKDEV(1, 0),
 232         .pclk = INT_MAX,
 233         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 234                 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT,
 235         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 236                 | SOR_PLL_TMDS_TERM_ENABLE,
 237         .pe_current = 0x00000000,
 238         .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */
 239         .peak_current = 0x040f0f0f,
 240         .pad_ctls0_mask    = 0xfffff0ff,
 241         .pad_ctls0_setting = 0x00000600, /* BG_VREF_LEVEL */
 242         },
 243 };
 244 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
 245 const struct tmds_config tmds_config[] = {
 246         { /* 480p modes */
 247         .pclk = 27000000,
 248         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 249                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x0) |
 250                 SOR_PLL_TX_REG_LOAD(0),
 251         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 252                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 253         .pe_current = 0x0,
 254         .drive_current = 0x1f1f1f1f,
 255         .peak_current = 0x0,
 256         },
 257         { /* 720p modes */
 258         .pclk = 74250000,
 259         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 260                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x1) |
 261                 SOR_PLL_TX_REG_LOAD(0),
 262         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 263                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 264         .pe_current = 0x0,
 265         .drive_current = 0x20202020,
 266         .peak_current = 0x0,
 267         },
 268         { /* 1080p modes */
 269         .pclk = INT_MAX,
 270         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 271                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x3) |
 272                 SOR_PLL_TX_REG_LOAD(0),
 273         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 274                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 275         .pe_current = 0x0,
 276         .drive_current = 0x22222222,
 277         .peak_current = 0x04040404,
 278         },
 279 };
 280 #else
 281 #warning tmds_config needs to be defined for your arch
 282 #endif
 283
 284 struct tegra_hdmi_audio_config {
 285         unsigned pix_clock;
 286         unsigned n;
 287         unsigned cts;
 288         unsigned aval;
 289 };
 290
 291
 292 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 293         {25200000,      4096,   25200,  24000},
 294         {27000000,      4096,   27000,  24000},
 295         {74250000,      4096,   74250,  24000},
 296         {148500000,     4096,   148500, 24000},
 297         {241500000,     4096,   241500, 24000},
 298         {297000000,     3072,   222750, 24000},
 299         {0,             0,      0},
 300 };
 301
 302 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
 303         {25200000,      5880,   26250,  25000},
 304         {27000000,      5880,   28125,  25000},
 305         {74250000,      4704,   61875,  20000},
 306         {148500000,     4704,   123750, 20000},
 307         {241500000,     4704,   201250, 20000},
 308         {297000000,     4704,   247500, 20000},
 309         {0,             0,      0},
 310 };
 311
 312 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 313         {25200000,      6144,   25200,  24000},
 314         {27000000,      6144,   27000,  24000},
 315         {74250000,      6144,   74250,  24000},
 316         {148500000,     6144,   148500, 24000},
 317         {241500000,     5632,   221375, 22000},
 318         {297000000,     5120,   247500, 24000},
 319         {0,             0,      0},
 320 };
 321
 322 const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
 323         {25200000,      11760,  26250,  25000},
 324         {27000000,      11760,  28125,  25000},
 325         {74250000,      9408,   61875,  20000},
 326         {148500000,     9408,   123750, 20000},
 327         {241500000,     9408,   201250, 20000},
 328         {297000000,     9408,   247500, 20000},
 329         {0,             0,      0},
 330 };
 331
 332 const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
 333         {25200000,      12288,  25200,  24000},
 334         {27000000,      12288,  27000,  24000},
 335         {74250000,      12288,  74250,  24000},
 336         {148500000,     12288,  148500, 24000},
 337         {241500000,     11264,  221375, 22000},
 338         {297000000,     10240,  247500, 24000},
 339         {0,             0,      0},
 340 };
 341
 342 const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
 343         {25200000,      23520,  26250,  25000},
 344         {27000000,      23520,  28125,  25000},
 345         {74250000,      18816,  61875,  20000},
 346         {148500000,     18816,  123750, 20000},
 347         {241500000,     18816,  201250, 20000},
 348         {297000000,     18816,  247500, 20000},
 349         {0,             0,      0},
 350 };
 351
 352 const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
 353         {25200000,      24576,  25200,  24000},
 354         {27000000,      24576,  27000,  24000},
 355         {74250000,      24576,  74250,  24000},
 356         {148500000,     24576,  148500, 24000},
 357         {241500000,     22528,  221375, 22000},
 358         {297000000,     20480,  247500, 24000},
 359         {0,             0,      0},
 360 };
 361
 362 static const struct tegra_hdmi_audio_config
 363 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
 364 {
 365         const struct tegra_hdmi_audio_config *table;
 366
 367         switch (audio_freq) {
 368         case AUDIO_FREQ_32K:
 369                 table = tegra_hdmi_audio_32k;
 370                 break;
 371         case AUDIO_FREQ_44_1K:
 372                 table = tegra_hdmi_audio_44_1k;
 373                 break;
 374         case AUDIO_FREQ_48K:
 375                 table = tegra_hdmi_audio_48k;
 376                 break;
 377         case AUDIO_FREQ_88_2K:
 378                 table = tegra_hdmi_audio_88_2k;
 379                 break;
 380         case AUDIO_FREQ_96K:
 381                 table = tegra_hdmi_audio_96k;
 382                 break;
 383         case AUDIO_FREQ_176_4K:
 384                 table = tegra_hdmi_audio_176_4k;
 385                 break;
 386         case AUDIO_FREQ_192K:
 387                 table = tegra_hdmi_audio_192k;
 388                 break;
 389         default:
 390                 return NULL;
 391         }
 392
 393         while (table->pix_clock) {
 394                 if (table->pix_clock > (pix_clock/100*99) &&
 395                 table->pix_clock < (pix_clock/100*101) &&
 396                 table->pix_clock >= 1000)
 397                         return table;
 398                 table++;
 399         }
 400
 401         return NULL;
 402 }
 403
 404
 405 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 406                                              unsigned long reg)
 407 {
 408         unsigned long ret;
 409         ret = readl(hdmi->base + reg * 4);
 410         trace_display_readl(hdmi->dc, ret, hdmi->base + reg * 4);
 411         return ret;
 412 }
 413
 414 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 415                                      unsigned long val, unsigned long reg)
 416 {
 417         trace_display_writel(hdmi->dc, val, hdmi->base + reg * 4);
 418         writel(val, hdmi->base + reg * 4);
 419 }
 420
 421 static inline int tegra_hdmi_writel_eld_buf(struct tegra_dc_hdmi_data *hdmi,
 422                                             const u8 *buf,
 423                                             size_t buf_entries, size_t index,
 424                                             void __iomem *eld_buf_addr)
 425 {
 426         size_t end_index = index + buf_entries;
 427         do {
 428                 unsigned long val = (index << 8) | *buf;
 429
 430                 trace_display_writel(hdmi->dc, val, eld_buf_addr);
 431                 writel(val, eld_buf_addr);
 432                 index++;
 433                 buf++;
 434         } while (index < end_index);
 435         /* outer for loop that uses this will increment index by 1 */
 436         return index - 1;
 437 }
 438
 439 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 440                                          unsigned long reg, unsigned long clr,
 441                                          unsigned long set)
 442 {
 443         unsigned long val = tegra_hdmi_readl(hdmi, reg);
 444         val &= ~clr;
 445         val |= set;
 446         tegra_hdmi_writel(hdmi, val, reg);
 447 }
 448
 449 #ifdef CONFIG_DEBUG_FS
 450 static int dbg_hdmi_show(struct seq_file *m, void *unused)
 451 {
 452         struct tegra_dc_hdmi_data *hdmi = m->private;
 453
 454         /* If gated quitely return */
 455         if (!tegra_dc_is_powered(hdmi->dc))
 456                 return 0;
 457
 458 #define DUMP_REG(a) do {                                                \
 459                 seq_printf(m, "%-32s\t%03x\t%08lx\n",                   \
 460                        #a, a, tegra_hdmi_readl(hdmi, a));               \
 461         } while (0)
 462
 463         tegra_dc_io_start(hdmi->dc);
 464         clk_prepare_enable(hdmi->clk);
 465
 466         DUMP_REG(HDMI_CTXSW);
 467         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 468         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 469         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 470         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 471         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 472         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 473         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 474         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 475         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 476         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 477         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 478         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 479         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 480         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 481         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 482         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 483         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 484         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 485         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 486         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 487         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 488         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 489         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 490         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 491         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 492         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 493         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 494         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 495         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 496         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 497         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 498         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 499         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 500         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 501         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 502         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 503         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 504         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 505         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 506         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 507         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 508         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 509         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 510         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 511         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 512         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 513         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 514         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 515         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 516         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 517         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 518         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 519         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 520         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 521         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 522         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 523         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 524         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 525         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 526         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 527         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 528         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 529         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 530         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 531         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 532         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 533         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 534         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 535         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 536         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 537         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 538         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 539         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 540         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 541         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 542         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 543         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 544         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 545         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 546         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 547         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 548         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
 549         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 550         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 551         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 552         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 553         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
 554         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
 555         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
 556         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
 557         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
 558         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
 559         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
 560         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
 561         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
 562         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
 563         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
 564         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
 565         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
 566         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
 567         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
 568         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
 569         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
 570         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
 571         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
 572         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
 573         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
 574         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
 575         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
 576         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
 577         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
 578         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
 579         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
 580         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
 581         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
 582         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
 583         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
 584         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
 585         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
 586         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
 587         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
 588         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
 589         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 590         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
 591         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
 592         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
 593         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
 594         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
 595         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
 596         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
 597         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
 598         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
 599         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
 600         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
 601         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
 602         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
 603         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
 604         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
 605         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
 606         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
 607         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
 608         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
 609         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
 610         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
 611         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
 612         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
 613         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
 614         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
 615         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
 616         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
 617         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
 618         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
 619         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
 620 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 621         DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 622 #endif
 623 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC) && !defined(CONFIG_ARCH_TEGRA_11x_SOC)
 624         DUMP_REG(HDMI_NV_PDISP_SOR_PAD_CTLS0);
 625         DUMP_REG(HDMI_NV_PDISP_SOR_PAD_CTLS1);
 626         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL);
 627         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS);
 628         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER);
 629         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW);
 630         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH);
 631         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW);
 632         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH);
 633         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW);
 634         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH);
 635         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW);
 636         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH);
 637 #endif
 638
 639 #undef DUMP_REG
 640
 641         clk_disable_unprepare(hdmi->clk);
 642         tegra_dc_io_end(hdmi->dc);
 643
 644         return 0;
 645 }
 646
 647 static int dbg_hdmi_show_open(struct inode *inode, struct file *file)
 648 {
 649         return single_open(file, dbg_hdmi_show, inode->i_private);
 650 }
 651
 652 static const struct file_operations dbg_hdmi_show_fops = {
 653         .open           = dbg_hdmi_show_open,
 654         .read           = seq_read,
 655         .llseek         = seq_lseek,
 656         .release        = single_release,
 657 };
 658
 659 static int dbg_hotplug_show(struct seq_file *m, void *unused)
 660 {
 661         struct tegra_dc_hdmi_data *hdmi = m->private;
 662         struct tegra_dc *dc = hdmi->dc;
 663
 664         if (WARN_ON(!hdmi || !dc || !dc->out))
 665                 return -EINVAL;
 666
 667         seq_put_decimal_ll(m, '\0', dc->out->hotplug_state);
 668         seq_putc(m, '\n');
 669         return 0;
 670 }
 671
 672 static int dbg_hotplug_open(struct inode *inode, struct file *file)
 673 {
 674         return single_open(file, dbg_hotplug_show, inode->i_private);
 675 }
 676
 677 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
 678         size_t len, loff_t *pos)
 679 {
 680         struct seq_file *m = file->private_data; /* single_open() initialized */
 681         struct tegra_dc_hdmi_data *hdmi = m->private;
 682         struct tegra_dc *dc = hdmi->dc;
 683         int ret;
 684         long new_state;
 685
 686         if (WARN_ON(!hdmi || !dc || !dc->out))
 687                 return -EINVAL;
 688
 689         ret = kstrtol_from_user(addr, len, 10, &new_state);
 690         if (ret < 0)
 691                 return ret;
 692
 693         if (dc->out->hotplug_state == 0 && new_state != 0) {
 694                 /* was 0, now -1 or 1.
 695                  * we are overriding the hpd GPIO, so ignore the interrupt. */
 696                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
 697
 698                 disable_irq(gpio_irq);
 699         } else if (dc->out->hotplug_state != 0 && new_state == 0) {
 700                 /* was -1 or 1, and now 0
 701                  * restore the interrupt for hpd GPIO. */
 702                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
 703
 704                 enable_irq(gpio_irq);
 705         }
 706
 707         dc->out->hotplug_state = new_state;
 708
 709         hdmi_state_machine_set_pending_hpd();
 710
 711         return len;
 712 }
 713
 714 static const struct file_operations dbg_hotplug_fops = {
 715         .open           = dbg_hotplug_open,
 716         .read           = seq_read,
 717         .write          = dbg_hotplug_write,
 718         .llseek         = seq_lseek,
 719         .release        = single_release,
 720 };
 721
 722 static struct dentry *hdmidir;
 723
 724 static void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
 725 {
 726         struct dentry *retval;
 727
 728         hdmidir = debugfs_create_dir("tegra_hdmi", NULL);
 729         if (!hdmidir)
 730                 return;
 731         retval = debugfs_create_file("regs", S_IRUGO, hdmidir, hdmi,
 732                 &dbg_hdmi_show_fops);
 733         if (!retval)
 734                 goto free_out;
 735         retval = debugfs_create_file("hotplug", S_IRUGO, hdmidir, hdmi,
 736                 &dbg_hotplug_fops);
 737         if (!retval)
 738                 goto free_out;
 739         return;
 740 free_out:
 741         debugfs_remove_recursive(hdmidir);
 742         hdmidir = NULL;
 743         return;
 744 }
 745 #else
 746 static inline void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
 747 { }
 748 #endif
 749
 750 #define PIXCLOCK_TOLERANCE      200
 751
 752 static int tegra_dc_calc_clock_per_frame(const struct fb_videomode *mode)
 753 {
 754         return (mode->left_margin + mode->xres +
 755                 mode->right_margin + mode->hsync_len) *
 756                (mode->upper_margin + mode->yres +
 757                 mode->lower_margin + mode->vsync_len);
 758 }
 759
 760 static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,
 761                                         const struct fb_videomode *mode)
 762 {
 763         unsigned max_pixclock = tegra_dc_get_out_max_pixclock(dc);
 764         if (max_pixclock) {
 765                 /* this might look counter-intuitive,
 766                  * but pixclock's unit is picos(not Khz)
 767                  */
 768                 return mode->pixclock >= max_pixclock;
 769         } else {
 770                 return true;
 771         }
 772 }
 773
 774 static bool tegra_dc_check_constraint(const struct fb_videomode *mode)
 775 {
 776         return mode->hsync_len > 1 && mode->vsync_len > 1 &&
 777                 mode->lower_margin + mode->vsync_len + mode->upper_margin > 1 &&
 778                 mode->xres >= 16 && mode->yres >= 16;
 779 }
 780
 781 /* adjusts pixclock to fit audio table */
 782 static bool tegra_dc_hdmi_adjust_pixclock(const struct tegra_dc *dc,
 783                                         struct fb_videomode *mode)
 784 {
 785         const struct tegra_hdmi_audio_config *cfg = tegra_hdmi_audio_44_1k;
 786         unsigned pclk;
 787
 788         if (!mode->pixclock)
 789                 return false;
 790
 791         pclk = PICOS2KHZ(mode->pixclock) * 1000;
 792
 793         /* look on 44.1k audio table, if mode's pixel clock is within 1%, then
 794          * use the pixel clock from the audio table.*/
 795         while (cfg->pix_clock) {
 796                 if (cfg->pix_clock > (pclk / 100 * 99) &&
 797                         cfg->pix_clock < (pclk / 100 * 101) &&
 798                         cfg->pix_clock >= 1000) {
 799                         mode->pixclock = KHZ2PICOS(cfg->pix_clock / 1000);
 800                         return true;
 801                 }
 802                 cfg++;
 803         }
 804         return false;
 805 }
 806
 807 bool tegra_dc_hdmi_mode_filter(const struct tegra_dc *dc,
 808                                         struct fb_videomode *mode)
 809 {
 810         long total_clocks;
 811
 812 #ifndef CONFIG_ARCH_TEGRA_12x_SOC
 813         if (mode->vmode & FB_VMODE_INTERLACED)
 814                 return false;
 815 #endif
 816
 817         /* Ignore modes with a 0 pixel clock */
 818         if (!mode->pixclock)
 819                 return false;
 820
 821 #ifdef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
 822                 if (PICOS2KHZ(mode->pixclock) > 74250)
 823                         return false;
 824 #endif
 825
 826 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 827         /* Display B max is 4096 */
 828         if (mode->xres > 4096)
 829                 return false;
 830 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 831         if (mode->xres > 2560)
 832                 return false;
 833 #else
 834         /* don't filter any modes due to width - probably not what you want */
 835 #endif
 836
 837         tegra_dc_hdmi_adjust_pixclock(dc, mode);
 838
 839         /* Check if the mode's pixel clock is more than the max rate*/
 840         if (!tegra_dc_hdmi_valid_pixclock(dc, mode))
 841                 return false;
 842
 843         /* Work around for modes that fail the constrait:
 844          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1 */
 845         if (mode->lower_margin == 1) {
 846                 mode->lower_margin++;
 847                 mode->upper_margin--;
 848         }
 849
 850         /* even after fix-ups the mode still isn't supported */
 851         if (!tegra_dc_check_constraint(mode))
 852                 return false;
 853
 854         mode->flag |= FB_MODE_IS_DETAILED;
 855         total_clocks = tegra_dc_calc_clock_per_frame(mode);
 856         mode->refresh = total_clocks ?
 857                 (PICOS2KHZ(mode->pixclock) * 1000) / total_clocks : 0;
 858
 859         return true;
 860 }
 861
 862 /* used by tegra_dc_probe() to detect hpd/hdmi status at boot */
 863 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 864 {
 865         /* trigger an edid read by the hdmi state machine */
 866         hdmi_state_machine_set_pending_hpd();
 867
 868         return tegra_dc_hpd(dc);
 869 }
 870
 871 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 872 {
 873         struct tegra_dc *dc = ptr;
 874         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 875
 876         pr_info("%s: start\n", __func__);
 877         rt_mutex_lock(&hdmi->suspend_lock);
 878         if (!hdmi->suspended)
 879                 hdmi_state_machine_set_pending_hpd();
 880         rt_mutex_unlock(&hdmi->suspend_lock);
 881         pr_info("%s: end\n", __func__);
 882         return IRQ_HANDLED;
 883 }
 884
 885 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 886 {
 887         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 888
 889         tegra_nvhdcp_suspend(hdmi->nvhdcp);
 890
 891         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
 892                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
 893                 int ret;
 894
 895                 ret = enable_irq_wake(wake_irq);
 896                 if (ret < 0) {
 897                         dev_err(&dc->ndev->dev,
 898                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
 899                         __func__, wake_irq, ret);
 900                 }
 901         }
 902
 903         rt_mutex_lock(&hdmi->suspend_lock);
 904         hdmi->suspended = true;
 905         rt_mutex_unlock(&hdmi->suspend_lock);
 906
 907 }
 908
 909 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
 910 {
 911         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 912
 913         rt_mutex_lock(&hdmi->suspend_lock);
 914         hdmi->suspended = false;
 915         hdmi_state_machine_set_pending_hpd();
 916         rt_mutex_unlock(&hdmi->suspend_lock);
 917
 918         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
 919                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
 920
 921         tegra_nvhdcp_resume(hdmi->nvhdcp);
 922 }
 923
 924 #ifdef CONFIG_SWITCH
 925 static ssize_t underscan_show(struct device *dev,
 926                                 struct device_attribute *attr, char *buf)
 927 {
 928         struct tegra_dc_hdmi_data *hdmi =
 929                         container_of(dev_get_drvdata(dev), struct tegra_dc_hdmi_data, hpd_switch);
 930
 931         if (hdmi->edid)
 932                 return sprintf(buf, "%d\n", tegra_edid_underscan_supported(hdmi->edid));
 933         else
 934                 return 0;
 935 }
 936
 937 static DEVICE_ATTR(underscan, S_IRUGO, underscan_show, NULL);
 938
 939 static ssize_t hdmi_audio_show(struct device *dev,
 940                                 struct device_attribute *attr, char *buf)
 941 {
 942         struct tegra_dc_hdmi_data *hdmi =
 943                         container_of(dev_get_drvdata(dev),
 944                                    struct tegra_dc_hdmi_data, audio_switch);
 945
 946         if (hdmi->edid)
 947                 return sprintf(buf, "%d\n",
 948                                    tegra_edid_audio_supported(hdmi->edid));
 949         else
 950                 return 0;
 951 }
 952
 953 static DEVICE_ATTR(hdmi_audio, S_IRUGO, hdmi_audio_show, NULL);
 954 #endif
 955
 956
 957 static int tegra_dc_hdmi_i2c_xfer(struct tegra_dc *dc, struct i2c_msg *msgs,
 958         int num)
 959 {
 960         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 961
 962         return i2c_transfer(hdmi->i2c_info.client->adapter, msgs, num);
 963 }
 964
 965 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 966 {
 967         struct tegra_dc_hdmi_data *hdmi;
 968         struct resource *res;
 969         struct resource hdmi_res;
 970         struct resource *base_res;
 971         int ret;
 972         void __iomem *base;
 973         struct clk *clk = NULL;
 974         struct clk *disp1_clk = NULL;
 975         struct clk *disp2_clk = NULL;
 976         struct tegra_hdmi_out *hdmi_out = NULL;
 977         struct i2c_adapter *adapter = NULL;
 978         int err;
 979         struct device_node *np = dc->ndev->dev.of_node;
 980 #ifdef CONFIG_USE_OF
 981         struct device_node *np_hdmi =
 982                 of_find_node_by_path("/host1x/hdmi");
 983 #else
 984         struct device_node *np_hdmi = NULL;
 985 #endif
 986         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 987         if (!hdmi)
 988                 return -ENOMEM;
 989         if (np) {
 990                 if (np_hdmi && of_device_is_available(np_hdmi)) {
 991                         of_address_to_resource(np_hdmi, 0, &hdmi_res);
 992                         res = &hdmi_res;
 993                 } else {
 994                         err = -EINVAL;
 995                         goto err_free_hdmi;
 996                 }
 997         } else {
 998                 res = platform_get_resource_byname(dc->ndev,
 999                         IORESOURCE_MEM, "hdmi_regs");
1000         }
1001         if (!res) {
1002                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
1003                 err = -ENOENT;
1004                 goto err_free_hdmi;
1005         }
1006
1007         base_res = request_mem_region(res->start,
1008                 resource_size(res), dc->ndev->name);
1009         if (!base_res) {
1010                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
1011                 err = -EBUSY;
1012                 goto err_free_hdmi;
1013         }
1014
1015         base = ioremap(res->start, resource_size(res));
1016         if (!base) {
1017                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
1018                 err = -EBUSY;
1019                 goto err_release_resource_reg;
1020         }
1021
1022         clk = clk_get(&dc->ndev->dev, "hdmi");
1023         if (IS_ERR_OR_NULL(clk)) {
1024                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
1025                 err = -ENOENT;
1026                 goto err_iounmap_reg;
1027         }
1028
1029         disp1_clk = clk_get_sys("tegradc.0", NULL);
1030         if (IS_ERR_OR_NULL(disp1_clk)) {
1031                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
1032                 err = -ENOENT;
1033                 goto err_put_clock;
1034         }
1035
1036         disp2_clk = clk_get_sys("tegradc.1", NULL);
1037         if (IS_ERR_OR_NULL(disp2_clk)) {
1038                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
1039                 err = -ENOENT;
1040                 goto err_put_clock;
1041         }
1042
1043 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1044         hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
1045         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
1046                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
1047                 err = -ENOENT;
1048                 goto err_put_clock;
1049         }
1050
1051         hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
1052         if (IS_ERR_OR_NULL(hdmi->hda2codec_clk)) {
1053                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2codec clock\n");
1054                 err = -ENOENT;
1055                 goto err_put_clock;
1056         }
1057
1058         hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
1059         if (IS_ERR_OR_NULL(hdmi->hda2hdmi_clk)) {
1060                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2hdmi clock\n");
1061                 err = -ENOENT;
1062                 goto err_put_clock;
1063         }
1064 #endif
1065
1066         /* Get the pointer of board file settings */
1067         hdmi_out = dc->pdata->default_out->hdmi_out;
1068         if (hdmi_out)
1069                 memcpy(&hdmi->info, hdmi_out, sizeof(hdmi->info));
1070
1071         hdmi->edid = tegra_edid_create(dc, tegra_dc_hdmi_i2c_xfer);
1072         if (IS_ERR_OR_NULL(hdmi->edid)) {
1073                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
1074                 err = PTR_ERR(hdmi->edid);
1075                 goto err_put_clock;
1076         }
1077         tegra_dc_set_edid(dc, hdmi->edid);
1078
1079         adapter = i2c_get_adapter(dc->out->dcc_bus);
1080         if (!adapter) {
1081                 pr_err("can't get adpater for bus %d\n", dc->out->dcc_bus);
1082                 err = -EBUSY;
1083                 goto err_put_clock;
1084         }
1085
1086         hdmi->i2c_info.board.addr = 0x50;
1087         hdmi->i2c_info.board.platform_data = hdmi;
1088         strlcpy(hdmi->i2c_info.board.type, "tegra_hdmi",
1089                 sizeof(hdmi->i2c_info.board.type));
1090
1091         hdmi->i2c_info.client = i2c_new_device(adapter, &hdmi->i2c_info.board);
1092         i2c_put_adapter(adapter);
1093
1094         if (!hdmi->i2c_info.client) {
1095                 pr_err("can't create new device\n");
1096                 err = -EBUSY;
1097                 goto err_put_clock;
1098         }
1099
1100 #ifdef CONFIG_TEGRA_NVHDCP
1101         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
1102                         dc->out->ddc_bus);
1103         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1104                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
1105                 err = PTR_ERR(hdmi->nvhdcp);
1106                 goto err_edid_destroy;
1107         }
1108 #else
1109         hdmi->nvhdcp = NULL;
1110 #endif
1111         hdmi_state_machine_init(hdmi);
1112
1113         hdmi->dc = dc;
1114         hdmi->base = base;
1115         hdmi->base_res = base_res;
1116         hdmi->clk = clk;
1117         hdmi->disp1_clk = disp1_clk;
1118         hdmi->disp2_clk = disp2_clk;
1119         hdmi->suspended = false;
1120         hdmi->eld_retrieved = false;
1121         hdmi->clk_enabled = false;
1122         hdmi->audio_freq = 44100;
1123         hdmi->audio_source = AUTO;
1124         rt_mutex_init(&hdmi->suspend_lock);
1125
1126 #ifdef CONFIG_SWITCH
1127         hdmi->hpd_switch.name = "hdmi";
1128         ret = switch_dev_register(&hdmi->hpd_switch);
1129
1130         if (!ret)
1131                 ret = device_create_file(hdmi->hpd_switch.dev,
1132                         &dev_attr_underscan);
1133         BUG_ON(ret != 0);
1134
1135         hdmi->audio_switch.name = "hdmi_audio";
1136         ret = switch_dev_register(&hdmi->audio_switch);
1137
1138         if (!ret)
1139                 ret = device_create_file(hdmi->audio_switch.dev,
1140                         &dev_attr_hdmi_audio);
1141         BUG_ON(ret != 0);
1142 #endif
1143
1144         dc->out->depth = 24;
1145
1146         tegra_dc_set_outdata(dc, hdmi);
1147
1148         dc_hdmi = hdmi;
1149         /* boards can select default content protection policy */
1150         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND)
1151                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1152                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
1153         else
1154                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1155                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
1156
1157         tegra_dc_hdmi_debug_create(hdmi);
1158
1159         err = gpio_request(dc->out->hotplug_gpio, "hdmi_hpd");
1160         if (err < 0) {
1161                 dev_err(&dc->ndev->dev, "hdmi: hpd gpio_request failed\n");
1162                 goto err_nvhdcp_destroy;
1163         }
1164
1165         gpio_direction_input(dc->out->hotplug_gpio);
1166
1167         /* TODO: support non-hotplug */
1168         ret = request_threaded_irq(gpio_to_irq(dc->out->hotplug_gpio),
1169                 NULL, tegra_dc_hdmi_irq,
1170                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1171                 dev_name(&dc->ndev->dev), dc);
1172
1173         if (ret) {
1174                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed - %d\n",
1175                         gpio_to_irq(dc->out->hotplug_gpio), ret);
1176                 err = -EBUSY;
1177                 goto err_gpio_free;
1178         }
1179
1180         return 0;
1181
1182 err_gpio_free:
1183         gpio_free(dc->out->hotplug_gpio);
1184 err_nvhdcp_destroy:
1185         if (hdmi->nvhdcp)
1186                 tegra_nvhdcp_destroy(hdmi->nvhdcp);
1187 #ifdef CONFIG_TEGRA_NVHDCP
1188 err_edid_destroy:
1189 #endif
1190         tegra_edid_destroy(hdmi->edid);
1191 err_put_clock:
1192 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1193         if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
1194                 clk_put(hdmi->hda2hdmi_clk);
1195         if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
1196                 clk_put(hdmi->hda2codec_clk);
1197         if (!IS_ERR_OR_NULL(hdmi->hda_clk))
1198                 clk_put(hdmi->hda_clk);
1199 #endif
1200         if (!IS_ERR_OR_NULL(disp2_clk))
1201                 clk_put(disp2_clk);
1202         if (!IS_ERR_OR_NULL(disp1_clk))
1203                 clk_put(disp1_clk);
1204         if (!IS_ERR_OR_NULL(clk))
1205                 clk_put(clk);
1206 err_iounmap_reg:
1207         iounmap(base);
1208 err_release_resource_reg:
1209         release_resource(base_res);
1210 err_free_hdmi:
1211         kfree(hdmi);
1212         return err;
1213 }
1214
1215 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1216 {
1217         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1218
1219         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1220         hdmi_state_machine_shutdown();
1221
1222         i2c_release_client(hdmi->i2c_info.client);
1223 #ifdef CONFIG_SWITCH
1224         switch_dev_unregister(&hdmi->hpd_switch);
1225         switch_dev_unregister(&hdmi->audio_switch);
1226 #endif
1227         iounmap(hdmi->base);
1228         release_resource(hdmi->base_res);
1229 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1230         clk_put(hdmi->hda2hdmi_clk);
1231         clk_put(hdmi->hda2codec_clk);
1232         clk_put(hdmi->hda_clk);
1233 #endif
1234         clk_put(hdmi->clk);
1235         clk_put(hdmi->disp1_clk);
1236         clk_put(hdmi->disp2_clk);
1237         tegra_edid_destroy(hdmi->edid);
1238         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1239
1240         kfree(hdmi);
1241
1242 }
1243
1244 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
1245 {
1246         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1247         int i;
1248         unsigned freqs[] = {
1249                 32000,
1250                 44100,
1251                 48000,
1252                 88200,
1253                 96000,
1254                 176400,
1255                 192000,
1256         };
1257
1258         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
1259                 unsigned f = freqs[i];
1260                 unsigned eight_half;
1261                 unsigned delta;;
1262
1263                 if (f > 96000)
1264                         delta = 2;
1265                 else if (f > 48000)
1266                         delta = 6;
1267                 else
1268                         delta = 9;
1269
1270                 if (!f)
1271                         eight_half = 0;
1272                 else
1273                         eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
1274                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
1275                                   AUDIO_FS_HIGH(eight_half + delta),
1276                                   HDMI_NV_PDISP_AUDIO_FS(i));
1277         }
1278 }
1279
1280 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1281 static void tegra_dc_hdmi_setup_eld_buff(struct tegra_dc *dc)
1282 {
1283         size_t i;
1284         u8 tmp;
1285         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1286         void __iomem *eld_buf_addr;
1287         int baseline_eld_len = (HDMI_ELD_MONITOR_NAME_INDEX -
1288                                 HDMI_ELD_CEA_VER_MNL_INDEX +
1289                                 hdmi->eld.mnl +
1290                                 (3 * hdmi->eld.sad_count));
1291         u8 baseline_eld_len_val;
1292
1293         eld_buf_addr = hdmi->base + HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0 * 4;
1294
1295         /* the baseline_eld_len needs to be written as a
1296          * multiple of DWORDS (4 bytes).
1297          */
1298         BUG_ON(baseline_eld_len > MAX_BASELINE_ELD_SIZE);
1299         baseline_eld_len_val = DIV_ROUND_UP(baseline_eld_len, 4);
1300
1301         /* program ELD stuff.  we must write all bytes of the
1302          * ELD buffer.  when hda_eld.c tries to read it back,
1303          * it's query of the size returns not how many valid
1304          * were written, but the entire size, and will try to
1305          * read all the bytes in the buffer.  it will fail
1306          * if any invalid bytes are read back, so we have to
1307          * fill the entire buffer with something, even if it's
1308          * just zeroes.
1309          */
1310         for (i = 0; i < HDMI_ELD_BUF_SIZE; i++) {
1311                 switch (i) {
1312                 case HDMI_ELD_VER_INDEX:
1313                         tmp = (hdmi->eld.eld_ver << 3);
1314                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1315                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1316                         break;
1317                 case HDMI_ELD_RESERVED1_INDEX:
1318                 case HDMI_ELD_RESERVED2_INDEX:
1319                         /* must write a dummy byte or else hda_eld.c
1320                          * will get an error when it tries to read a
1321                          * complete eld buffer
1322                          */
1323                         tegra_hdmi_writel(hdmi, (i << 8),
1324                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1325                         break;
1326                 case HDMI_ELD_BASELINE_LEN_INDEX:
1327                         tegra_hdmi_writel(hdmi, (i << 8) | baseline_eld_len_val,
1328                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1329                         break;
1330                 case HDMI_ELD_CEA_VER_MNL_INDEX:
1331                         tmp = (hdmi->eld.cea_edid_ver << 5);
1332                         tmp |= (hdmi->eld.mnl & 0x1f);
1333                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1334                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1335                         break;
1336                 case HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX:
1337                         tmp = (hdmi->eld.sad_count << 4);
1338                         tmp |= (hdmi->eld.conn_type & 0xC);
1339                         tmp |= (hdmi->eld.support_ai & 0x2);
1340                         tmp |= (hdmi->eld.support_hdcp & 0x1);
1341                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1342                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1343                         break;
1344                 case HDMI_ELD_AUD_SYNC_DELAY_INDEX:
1345                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.aud_synch_delay),
1346                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1347                         break;
1348                 case HDMI_ELD_SPK_ALLOC_INDEX:
1349                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.spk_alloc),
1350                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1351                         break;
1352                 case HDMI_ELD_PORT_ID_INDEX:
1353                         i = tegra_hdmi_writel_eld_buf(hdmi, hdmi->eld.port_id,
1354                                                       8, i, eld_buf_addr);
1355                         break;
1356                 case HDMI_ELD_MANF_NAME_INDEX:
1357                         i = tegra_hdmi_writel_eld_buf(hdmi,
1358                                                       hdmi->eld.manufacture_id,
1359                                                       2, i, eld_buf_addr);
1360                         break;
1361                 case HDMI_ELD_PRODUCT_CODE_INDEX:
1362                         i = tegra_hdmi_writel_eld_buf(hdmi,
1363                                                       hdmi->eld.product_id,
1364                                                       2, i, eld_buf_addr);
1365                         break;
1366                 case HDMI_ELD_MONITOR_NAME_INDEX:
1367                         /* write the eld.mnl bytes of the monitor name,
1368                          * followed immediately the short audio descriptor bytes
1369                          */
1370                         i = tegra_hdmi_writel_eld_buf(hdmi,
1371                                                       hdmi->eld.monitor_name,
1372                                                       hdmi->eld.mnl, i,
1373                                                       eld_buf_addr) + 1;
1374                         i = tegra_hdmi_writel_eld_buf(hdmi, hdmi->eld.sad,
1375                                                       hdmi->eld.sad_count * 3,
1376                                                       i, eld_buf_addr);
1377                         break;
1378                 default:
1379                         tegra_hdmi_writel(hdmi, (i << 8),
1380                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1381                 }
1382         }
1383
1384         /* set presence and valid bit  */
1385         tegra_hdmi_writel(hdmi, 3, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1386 }
1387 #endif
1388
1389 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
1390                                         unsigned audio_source)
1391 {
1392         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1393         const struct tegra_hdmi_audio_config *config;
1394         unsigned long audio_n;
1395 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1396         unsigned long reg_addr = 0;
1397 #endif
1398         unsigned a_source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
1399
1400         if (HDA == audio_source)
1401                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
1402         else if (SPDIF == audio_source)
1403                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
1404
1405 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1406         if (hdmi->audio_inject_null)
1407                 a_source |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1408
1409         tegra_hdmi_writel(hdmi,a_source,
1410                           HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1411         tegra_hdmi_writel(hdmi,
1412                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1413                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
1414                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1415 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1416         tegra_hdmi_writel(hdmi, (1 << HDMI_AUDIO_HBR_ENABLE_SHIFT) |
1417            tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0),
1418            HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0);
1419 #endif
1420 #else
1421         tegra_hdmi_writel(hdmi,
1422                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1423                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
1424                           a_source,
1425                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1426 #endif
1427         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
1428         if (!config) {
1429                 dev_err(&dc->ndev->dev,
1430                         "hdmi: can't set audio to %d at %d pix_clock",
1431                         audio_freq, dc->mode.pclk);
1432                 return -EINVAL;
1433         }
1434
1435         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
1436
1437         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
1438                 AUDIO_N_VALUE(config->n - 1);
1439         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1440
1441         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
1442                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1443
1444         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
1445                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1446
1447         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
1448                           SPARE_CTS_RESET_VAL(1),
1449                           HDMI_NV_PDISP_HDMI_SPARE);
1450
1451         audio_n &= ~AUDIO_N_RESETF;
1452         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1453
1454 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1455         switch (audio_freq) {
1456         case AUDIO_FREQ_32K:
1457                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0;
1458                 break;
1459         case AUDIO_FREQ_44_1K:
1460                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0;
1461                 break;
1462         case AUDIO_FREQ_48K:
1463                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0;
1464                 break;
1465         case AUDIO_FREQ_88_2K:
1466                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0;
1467                 break;
1468         case AUDIO_FREQ_96K:
1469                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0;
1470                 break;
1471         case AUDIO_FREQ_176_4K:
1472                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0;
1473                 break;
1474         case AUDIO_FREQ_192K:
1475                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0;
1476                 break;
1477         }
1478
1479         tegra_hdmi_writel(hdmi, config->aval, reg_addr);
1480 #endif
1481         tegra_dc_hdmi_setup_audio_fs_tables(dc);
1482
1483         return 0;
1484 }
1485
1486 int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source)
1487 {
1488         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1489
1490         if (!hdmi)
1491                 return -EAGAIN;
1492
1493         /* check for know freq */
1494         if (AUDIO_FREQ_32K == audio_freq ||
1495                 AUDIO_FREQ_44_1K== audio_freq ||
1496                 AUDIO_FREQ_48K== audio_freq ||
1497                 AUDIO_FREQ_88_2K== audio_freq ||
1498                 AUDIO_FREQ_96K== audio_freq ||
1499                 AUDIO_FREQ_176_4K== audio_freq ||
1500                 AUDIO_FREQ_192K== audio_freq) {
1501                 /* If we can program HDMI, then proceed */
1502                 if (hdmi->clk_enabled) {
1503                         tegra_dc_io_start(hdmi->dc);
1504                         tegra_dc_hdmi_setup_audio(hdmi->dc, audio_freq,audio_source);
1505                         tegra_dc_io_end(hdmi->dc);
1506                 }
1507
1508                 /* Store it for using it in enable */
1509                 hdmi->audio_freq = audio_freq;
1510                 hdmi->audio_source = audio_source;
1511         }
1512         else
1513                 return -EINVAL;
1514
1515         return 0;
1516 }
1517 EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1518
1519 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1520 int tegra_hdmi_audio_null_sample_inject(bool on)
1521 {
1522         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1523         unsigned int val = 0;
1524
1525         if (!hdmi)
1526                 return -EAGAIN;
1527
1528         if (hdmi->audio_inject_null != on) {
1529                 hdmi->audio_inject_null = on;
1530                 if (hdmi->clk_enabled) {
1531                         val = tegra_hdmi_readl(hdmi,
1532                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1533                         val &= ~AUDIO_CNTRL0_INJECT_NULLSMPL;
1534                         if (on)
1535                                 val |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1536                         tegra_hdmi_writel(hdmi,val,
1537                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1538                 }
1539         }
1540
1541         return 0;
1542 }
1543 EXPORT_SYMBOL(tegra_hdmi_audio_null_sample_inject);
1544
1545 int tegra_hdmi_setup_hda_presence()
1546 {
1547         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1548
1549         if (!hdmi)
1550                 return -EAGAIN;
1551
1552         if (hdmi->clk_enabled && hdmi->eld_retrieved) {
1553                 /* If HDA_PRESENCE is already set reset it */
1554                 tegra_dc_unpowergate_locked(hdmi->dc);
1555                 if (tegra_hdmi_readl(hdmi,
1556                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
1557                         tegra_hdmi_writel(hdmi, 0,
1558                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1559
1560                 tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
1561                 tegra_dc_powergate_locked(hdmi->dc);
1562                 return 0;
1563         }
1564         return -ENODEV;
1565
1566 }
1567 EXPORT_SYMBOL(tegra_hdmi_setup_hda_presence);
1568 #endif
1569
1570 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
1571                                          u8 type, u8 version, void *data, int len)
1572 {
1573         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1574         u32 subpack[2];  /* extra byte for zero padding of subpack */
1575         int i;
1576         u8 csum;
1577
1578         /* first byte of data is the checksum */
1579         csum = type + version + len - 1;
1580         for (i = 1; i < len; i++)
1581                 csum +=((u8 *)data)[i];
1582         ((u8 *)data)[0] = 0x100 - csum;
1583
1584         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
1585                           INFOFRAME_HEADER_VERSION(version) |
1586                           INFOFRAME_HEADER_LEN(len - 1),
1587                           header_reg);
1588
1589         /* The audio inforame only has one set of subpack registers.  The hdmi
1590          * block pads the rest of the data as per the spec so we have to fixup
1591          * the length before filling in the subpacks.
1592          */
1593         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
1594                 len = 6;
1595
1596         /* each subpack 7 bytes devided into:
1597          *   subpack_low - bytes 0 - 3
1598          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
1599          */
1600         for (i = 0; i < len; i++) {
1601                 int subpack_idx = i % 7;
1602
1603                 if (subpack_idx == 0)
1604                         memset(subpack, 0x0, sizeof(subpack));
1605
1606                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
1607
1608                 if (subpack_idx == 6 || (i + 1 == len)) {
1609                         int reg = header_reg + 1 + (i / 7) * 2;
1610
1611                         tegra_hdmi_writel(hdmi, subpack[0], reg);
1612                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
1613                 }
1614         }
1615 }
1616
1617 static int tegra_dc_find_cea_vic(const struct tegra_dc_mode *mode)
1618 {
1619         struct fb_videomode m;
1620         unsigned i;
1621         unsigned best = 0;
1622
1623         tegra_dc_to_fb_videomode(&m, mode);
1624
1625         m.vmode &= ~FB_VMODE_STEREO_MASK; /* stereo modes have the same VICs */
1626
1627         for (i = 1; i < CEA_MODEDB_SIZE; i++) {
1628                 const struct fb_videomode *curr = &cea_modes[i];
1629
1630                 if (!fb_mode_is_equal(&m, curr))
1631                         continue;
1632
1633                 if (!best)
1634                         best = i;
1635                 /* if either flag is set, then match is required */
1636                 if (curr->flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9)) {
1637                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1638                                 best = i;
1639                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1640                                 best = i;
1641                 } else {
1642                         best = i;
1643                 }
1644         }
1645         return best;
1646 }
1647
1648 static int tegra_dc_find_hdmi_vic(const struct tegra_dc_mode *mode)
1649 {
1650         struct fb_videomode m;
1651         unsigned i;
1652
1653         tegra_dc_to_fb_videomode(&m, mode);
1654
1655         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1656                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1657
1658                 if (fb_mode_is_equal(&m, curr))
1659                         return i;
1660         }
1661         return 0;
1662 }
1663
1664 static void tegra_dc_hdmi_disable_generic_infoframe(struct tegra_dc *dc)
1665 {
1666         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1667         u32 val;
1668
1669         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1670         val &= ~GENERIC_CTRL_ENABLE;
1671         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1672 }
1673
1674 /* return 1 if generic infoframe is used, 0 if not used */
1675 static int tegra_dc_hdmi_setup_hdmi_vic_infoframe(struct tegra_dc *dc, bool dvi)
1676 {
1677         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1678         struct hdmi_extres_infoframe extres;
1679         int hdmi_vic;
1680         u32 val;
1681
1682         if (dvi)
1683                 return 0;
1684         hdmi_vic = tegra_dc_find_hdmi_vic(&dc->mode);
1685         if (hdmi_vic <= 0)
1686                 return 0;
1687
1688         memset(&extres, 0x0, sizeof(extres));
1689
1690         extres.csum = 0;
1691         extres.regid0 = 0x03;
1692         extres.regid1 = 0x0c;
1693         extres.regid2 = 0x00;
1694         extres.hdmi_video_format = 1; /* Extended Resolution Format */
1695         extres.hdmi_vic = hdmi_vic;
1696
1697         tegra_dc_hdmi_write_infopack(dc,
1698                 HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1699                 HDMI_INFOFRAME_TYPE_VENDOR, HDMI_VENDOR_VERSION,
1700                 &extres, 6);
1701         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1702         val |= GENERIC_CTRL_ENABLE;
1703         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1704         return 1;
1705 }
1706
1707 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
1708 {
1709         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1710         struct hdmi_avi_infoframe avi;
1711         unsigned int blender_reg;
1712
1713         if (dvi) {
1714                 tegra_hdmi_writel(hdmi, 0x0,
1715                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1716                 return;
1717         }
1718
1719         memset(&avi, 0x0, sizeof(avi));
1720
1721         /* Indicate active format info is valid. */
1722         avi.a = 1;
1723         avi.r = HDMI_AVI_R_SAME;
1724
1725 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
1726         blender_reg = DC_DISP_BORDER_COLOR;
1727 #else
1728         blender_reg = DC_DISP_BLEND_BACKGROUND_COLOR;
1729 #endif
1730
1731         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
1732                 tegra_dc_writel(dc, 0x00101010, blender_reg);
1733         else
1734                 tegra_dc_writel(dc, 0x00000000, blender_reg);
1735
1736         avi.vic = tegra_dc_find_cea_vic(&dc->mode);
1737         avi.m = dc->mode.avi_m;
1738         if (tegra_edid_underscan_supported(hdmi->edid))
1739                 avi.s = HDMI_AVI_S_UNDERSCAN;
1740         dev_dbg(&dc->ndev->dev, "HDMI AVI vic=%d m=%d\n", avi.vic, avi.m);
1741         avi.s = HDMI_AVI_S_UNDERSCAN;
1742
1743         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
1744                                      HDMI_INFOFRAME_TYPE_AVI,
1745                                      HDMI_AVI_VERSION,
1746                                      &avi, sizeof(avi));
1747
1748         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1749                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1750 }
1751
1752 static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
1753 {
1754         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1755         struct hdmi_stereo_infoframe stereo;
1756         u32 val;
1757
1758         WARN(!dc->mode.stereo_mode,
1759                 "function assumes 3D/stereo mode is disabled\n");
1760
1761         memset(&stereo, 0x0, sizeof(stereo));
1762
1763         stereo.regid0 = 0x03;
1764         stereo.regid1 = 0x0c;
1765         stereo.regid2 = 0x00;
1766         stereo.hdmi_video_format = 2; /* 3D_Structure present */
1767 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1768         stereo._3d_structure = 0; /* frame packing */
1769 #else
1770         stereo._3d_structure = 8; /* side-by-side (half) */
1771         stereo._3d_ext_data = 0; /* something which fits into 00XX bit req */
1772 #endif
1773
1774         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1775                                         HDMI_INFOFRAME_TYPE_VENDOR,
1776                                         HDMI_VENDOR_VERSION,
1777                                         &stereo, 6);
1778
1779         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1780         val |= GENERIC_CTRL_ENABLE;
1781
1782         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1783 }
1784
1785 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
1786 {
1787         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1788         struct hdmi_audio_infoframe audio;
1789
1790         if (dvi) {
1791                 tegra_hdmi_writel(hdmi, 0x0,
1792                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1793                 return;
1794         }
1795
1796         memset(&audio, 0x0, sizeof(audio));
1797
1798         audio.cc = HDMI_AUDIO_CC_2;
1799         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
1800                                      HDMI_INFOFRAME_TYPE_AUDIO,
1801                                      HDMI_AUDIO_VERSION,
1802                                      &audio, sizeof(audio));
1803
1804         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1805                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1806 }
1807
1808 static void tegra_dc_hdmi_setup_tmds(struct tegra_dc_hdmi_data *hdmi,
1809                 const struct tmds_config *tc)
1810 {
1811 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1812         u32 val;
1813 #endif
1814
1815         tegra_hdmi_writel(hdmi, tc->pll0, HDMI_NV_PDISP_SOR_PLL0);
1816         tegra_hdmi_writel(hdmi, tc->pll1, HDMI_NV_PDISP_SOR_PLL1);
1817
1818         tegra_hdmi_writel(hdmi, tc->pe_current, HDMI_NV_PDISP_PE_CURRENT);
1819
1820 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1821         tegra_hdmi_writel(hdmi, tc->drive_current,
1822                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1823         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1824         val |= DRIVE_CURRENT_FUSE_OVERRIDE_T11x;
1825         if (MAJOR(tc->version) >= 1) {
1826                 val &= tc->pad_ctls0_mask;
1827                 val |= tc->pad_ctls0_setting;
1828         }
1829         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1830
1831         tegra_hdmi_writel(hdmi, tc->peak_current,
1832                 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1833 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
1834         tegra_hdmi_writel(hdmi, tc->drive_current,
1835                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1836         tegra_hdmi_writel(hdmi, 0x800034bb, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1837
1838         tegra_hdmi_writel(hdmi, tc->peak_current,
1839                 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1840 #else
1841         tegra_hdmi_writel(hdmi, tc->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE,
1842                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1843 #endif
1844 }
1845
1846 void tegra_dc_hdmi_setup_audio_and_infoframes(struct tegra_dc *dc)
1847 {
1848         int rekey;
1849         int err;
1850         u32 val;
1851         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1852
1853         if (!hdmi->dvi) {
1854                 err = tegra_dc_hdmi_setup_audio(dc, hdmi->audio_freq,
1855                         hdmi->audio_source);
1856
1857                 if (err < 0)
1858                         hdmi->dvi = true;
1859         }
1860
1861 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1862         tegra_dc_hdmi_setup_eld_buff(dc);
1863 #endif
1864
1865         rekey = HDMI_REKEY_DEFAULT;
1866         val = HDMI_CTRL_REKEY(rekey);
1867         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
1868                                         dc->mode.h_back_porch +
1869                                         dc->mode.h_front_porch -
1870                                         rekey - 18) / 32);
1871         if (!hdmi->dvi)
1872                 val |= HDMI_CTRL_ENABLE;
1873         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
1874
1875         if (hdmi->dvi)
1876                 tegra_hdmi_writel(hdmi, 0x0,
1877                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1878         else
1879                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
1880                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1881
1882         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
1883
1884         if (dc->mode.stereo_mode)
1885                 tegra_dc_hdmi_setup_stereo_infoframe(dc);
1886         else if (!tegra_dc_hdmi_setup_hdmi_vic_infoframe(dc, hdmi->dvi))
1887                 tegra_dc_hdmi_disable_generic_infoframe(dc);
1888
1889         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
1890 }
1891
1892 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1893 {
1894         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1895         int pulse_start;
1896         int dispclk_div_8_2;
1897         int retries;
1898         unsigned long val;
1899         unsigned i;
1900         const struct tmds_config *tmds_ptr;
1901         size_t tmds_len;
1902         bool edid_read;
1903
1904         /* enable power, clocks, resets, etc. */
1905
1906         /* The upstream DC needs to be clocked for accesses to HDMI to not
1907          * hard lock the system.  Because we don't know if HDMI is connected
1908          * to disp1 or disp2 we need to enable both until we set the DC mux.
1909          */
1910         clk_prepare_enable(hdmi->disp1_clk);
1911         clk_prepare_enable(hdmi->disp2_clk);
1912
1913 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1914         /* Enabling HDA clocks before asserting HDA PD and ELDV bits */
1915         clk_prepare_enable(hdmi->hda_clk);
1916         clk_prepare_enable(hdmi->hda2codec_clk);
1917         clk_prepare_enable(hdmi->hda2hdmi_clk);
1918 #endif
1919
1920         /* Reseting HDMI clock would cause visible display reset during boot
1921          * if bootloader set an image already. Skip such operation if HDMI
1922          * is already running on desired clock rate.
1923          */
1924         if (clk_get_rate(hdmi->clk) == dc->mode.pclk) {
1925                 pr_info("%s: HDMI clock already configured to "
1926                         "target frequency, skipping clk setup.\n", __func__);
1927                 clk_prepare_enable(hdmi->clk);
1928         } else {
1929                 tegra_dc_setup_clk(dc, hdmi->clk);
1930                 clk_set_rate(hdmi->clk, dc->mode.pclk);
1931
1932                 clk_prepare_enable(hdmi->clk);
1933                 tegra_periph_reset_assert(hdmi->clk);
1934                 mdelay(1);
1935                 tegra_periph_reset_deassert(hdmi->clk);
1936         }
1937
1938         /* TODO: copy HDCP keys from KFUSE to HDMI */
1939
1940         /* Program display timing registers: handled by dc */
1941
1942         /* program HDMI registers and SOR sequencer */
1943
1944         tegra_dc_io_start(dc);
1945         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
1946
1947         dc->out->depth = 24;
1948         dc->out->dither = TEGRA_DC_DISABLE_DITHER;
1949         tegra_dc_set_color_control(dc);
1950
1951         /* video_preamble uses h_pulse2 */
1952         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
1953                 dc->mode.h_back_porch - 10;
1954         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1955         tegra_dc_writel(dc,
1956                         PULSE_MODE_NORMAL |
1957                         PULSE_POLARITY_HIGH |
1958                         PULSE_QUAL_VACTIVE |
1959                         PULSE_LAST_END_A,
1960                         DC_DISP_H_PULSE2_CONTROL);
1961         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
1962                   DC_DISP_H_PULSE2_POSITION_A);
1963
1964         tegra_hdmi_writel(hdmi,
1965                           VSYNC_WINDOW_END(0x210) |
1966                           VSYNC_WINDOW_START(0x200) |
1967                           VSYNC_WINDOW_ENABLE,
1968                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1969
1970         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
1971                 tegra_hdmi_writel(hdmi,
1972                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
1973                                   ARM_VIDEO_RANGE_FULL,
1974                                   HDMI_NV_PDISP_INPUT_CONTROL);
1975         else
1976                 tegra_hdmi_writel(hdmi,
1977                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
1978                                   ARM_VIDEO_RANGE_LIMITED,
1979                                   HDMI_NV_PDISP_INPUT_CONTROL);
1980
1981         clk_disable_unprepare(hdmi->disp1_clk);
1982         clk_disable_unprepare(hdmi->disp2_clk);
1983
1984         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1985         tegra_hdmi_writel(hdmi,
1986                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1987                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
1988                           HDMI_NV_PDISP_SOR_REFCLK);
1989
1990         hdmi->clk_enabled = true;
1991
1992         edid_read = hdmi->eld_retrieved;
1993         /* on first boot, we haven't read EDID yet so
1994          * we don't know what to setup yet.  we'll
1995          * call audio and infoframes setup in hdmi worker
1996          * after EDID has been read.
1997          */
1998         if (edid_read) {
1999                 /* after boot, this is called by hwc via ioctl
2000                  * blank/unblank, which is done after EDID has
2001                  * been read.
2002                  */
2003                 tegra_dc_hdmi_setup_audio_and_infoframes(dc);
2004         }
2005
2006         /* Set tmds config. Set it to custom values provided in board file;
2007          * otherwise, set it to default values. */
2008         if (hdmi->info.tmds_config && hdmi->info.n_tmds_config) {
2009                 tmds_ptr = hdmi->info.tmds_config;
2010                 tmds_len = hdmi->info.n_tmds_config;
2011         } else {
2012                 tmds_ptr = tmds_config;
2013                 tmds_len = ARRAY_SIZE(tmds_config);
2014         }
2015
2016         for (i = 0; i < tmds_len && tmds_ptr[i].pclk < dc->mode.pclk; i++)
2017                 ;
2018         if (i < tmds_len) {
2019                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[i]);
2020         } else {
2021                 dev_warn(&dc->ndev->dev,
2022                         "pixel clock %u not present on TMDS table.\n",
2023                         dc->mode.pclk);
2024                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[tmds_len - 1]);
2025         }
2026
2027         /* enable SOR */
2028         tegra_hdmi_writel(hdmi,
2029                           SOR_SEQ_CTL_PU_PC(0) |
2030                           SOR_SEQ_PU_PC_ALT(0) |
2031                           SOR_SEQ_PD_PC(8) |
2032                           SOR_SEQ_PD_PC_ALT(8),
2033                           HDMI_NV_PDISP_SOR_SEQ_CTL);
2034
2035         val = SOR_SEQ_INST_WAIT_TIME(1) |
2036                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
2037                 SOR_SEQ_INST_HALT |
2038                 SOR_SEQ_INST_PIN_A_LOW |
2039                 SOR_SEQ_INST_PIN_B_LOW |
2040                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
2041
2042         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
2043         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
2044
2045         val = 0x1c800;
2046         val &= ~SOR_CSTM_ROTCLK(~0);
2047         val |= SOR_CSTM_ROTCLK(2);
2048         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
2049
2050         /* Putting display into STOP MODE will reset display which is undesired
2051          * if bootloader has already initialized display with image.
2052          */
2053         if (!hdmi->dc->initialized) {
2054                 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP,
2055                                 DC_CMD_DISPLAY_COMMAND);
2056                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2057                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2058         } else {
2059                 pr_info("%s: DC already initialized, skip putting HDMI "
2060                         "to STOP mode.\n", __func__);
2061         }
2062
2063         /* start SOR */
2064         tegra_hdmi_writel(hdmi,
2065                           SOR_PWR_NORMAL_STATE_PU |
2066                           SOR_PWR_NORMAL_START_NORMAL |
2067                           SOR_PWR_SAFE_STATE_PD |
2068                           SOR_PWR_SETTING_NEW_TRIGGER,
2069                           HDMI_NV_PDISP_SOR_PWR);
2070         tegra_hdmi_writel(hdmi,
2071                           SOR_PWR_NORMAL_STATE_PU |
2072                           SOR_PWR_NORMAL_START_NORMAL |
2073                           SOR_PWR_SAFE_STATE_PD |
2074                           SOR_PWR_SETTING_NEW_DONE,
2075                           HDMI_NV_PDISP_SOR_PWR);
2076
2077         retries = 1000;
2078         do {
2079                 BUG_ON(--retries < 0);
2080                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
2081         } while (val & SOR_PWR_SETTING_NEW_PENDING);
2082
2083         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
2084                 SOR_STATE_ASY_OWNER_HEAD0 |
2085                 SOR_STATE_ASY_SUBOWNER_BOTH |
2086                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
2087                 SOR_STATE_ASY_DEPOL_POS;
2088
2089         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
2090                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
2091         else
2092                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
2093
2094         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
2095                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
2096         else
2097                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
2098
2099         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
2100
2101         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
2102         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
2103
2104         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2105         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
2106         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
2107                           HDMI_NV_PDISP_SOR_STATE1);
2108         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2109
2110         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
2111
2112         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2113                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
2114                         DC_CMD_DISPLAY_POWER_CONTROL);
2115
2116         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
2117         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2118         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2119
2120         /* we are called at boot when the actual connection state
2121          * isn't known, and other times (like fb_blank, which
2122          * does a disable followed by an enable) when it is.
2123          * don't just assume a connection but check hpd.
2124          */
2125         tegra_nvhdcp_set_plug(hdmi->nvhdcp, tegra_dc_hpd(dc));
2126         tegra_dc_io_end(dc);
2127 }
2128
2129 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2130 {
2131         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2132
2133         /*
2134          * set DC to STOP mode
2135          */
2136         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2137         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2138         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2139
2140         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
2141
2142 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2143         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2144         /* sleep 1ms before disabling clocks to ensure HDA gets the interrupt */
2145         msleep(1);
2146         clk_disable_unprepare(hdmi->hda2hdmi_clk);
2147         clk_disable_unprepare(hdmi->hda2codec_clk);
2148         clk_disable_unprepare(hdmi->hda_clk);
2149 #endif
2150         tegra_periph_reset_assert(hdmi->clk);
2151         hdmi->clk_enabled = false;
2152         clk_disable_unprepare(hdmi->clk);
2153         tegra_dvfs_set_rate(hdmi->clk, 0);
2154 }
2155
2156
2157 /* To determine the best parent clock rate for a nominal HDMI pixel clock
2158  * rate for T124 host1x display controller
2159  * o inputs:
2160  *  - dc: pointer to the display controller
2161  *  - parent_clk: pointer to the parent clock
2162  *  - pclk: rate of nominal HDMI pixel clock in Hz
2163  * o outputs:
2164  *  - return: best parent clock rate in Hz
2165  */
2166 static unsigned long  tegra12x_hdmi_determine_parent(
2167         struct tegra_dc *dc, struct clk *parent_clk, int pclk)
2168 {
2169         /* T124 hdmi pclk:
2170          *   parentClk = pclk * m  (m=1,1.5,2,2.5,...,128.5)
2171          *   (refclk * n) = pclk * m  (n=1,1.5,2,2.5,...,128.5)
2172          *     (no half resolutions for m due to uneven out duty cycle)
2173          *   (refclk * N / 2) = pclk * m  (N=2,3,4,...,257)
2174          *   m = (refclk / 2 * N) / pclk  (m=1,2,3,...,128)
2175          *     looking for N to make m whole number
2176          */
2177         int  n, m;
2178         int  b, fr, f;
2179
2180         /* following parameters should come from parent clock */
2181         const int  ref  = 12000000;   /* reference clock to parent */
2182         const int  pmax = 600000000;  /* max freq of parent clock */
2183         const int  pmin = 200000000;  /* min freq of parent clock */
2184
2185         b = 0;
2186         fr = 1000;
2187         for (n = 4; (ref / 2 * n) <= pmax; n++) {
2188                 if ((ref / 2 * n) < pmin)  /* too low */
2189                         continue;
2190                 m = DIV_ROUND_UP((ref / 2 * n), (pclk / 1000));
2191                 if (m <= 1700)  /* for 2 <= m */
2192                         continue;
2193                 f = m % 1000;  /* fractional parts */
2194                 f = (0 == f) ? f : (1000 - f);  /* round-up */
2195                 if (0 == f) {  /* exact match */
2196                         b = n;
2197                         fr = f;
2198                         break;
2199                 } else if (f < fr) {
2200                         b = n;
2201                         fr = f;
2202                 }
2203         }
2204
2205         return (unsigned long)(ref / 2 * b);
2206 }
2207
2208
2209 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
2210 {
2211         unsigned long rate;
2212         struct clk *parent_clk = clk_get_sys(NULL,
2213                 dc->out->parent_clk ? : "pll_d_out0");
2214 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2215         struct clk *base_clk = clk_get_parent(parent_clk);
2216 #endif
2217         if (clk != dc->clk) {
2218 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2219                 clk_set_rate(base_clk, dc->mode.pclk);
2220
2221                 if (clk_get_parent(clk) != parent_clk)
2222                         clk_set_parent(clk, parent_clk);
2223
2224                 clk_set_rate(clk, dc->mode.pclk / 4);
2225 #else
2226                 rate = 100000000;
2227                 clk_set_rate(parent_clk, rate);
2228                 if (clk_get_parent(clk) != parent_clk)
2229                         clk_set_parent(clk, parent_clk);
2230                 clk_set_rate(clk,  rate / 4);
2231 #endif
2232         }
2233
2234         /*
2235          * Providing dynamic frequency rate setting for T20/T30 HDMI.
2236          * The required rate needs to be setup at 4x multiplier,
2237          * as out0 is 1/2 of the actual PLL output.
2238          */
2239 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2240         rate = tegra12x_hdmi_determine_parent(dc, parent_clk, dc->mode.pclk);
2241 #else
2242         rate = dc->mode.pclk * 2;
2243         while (rate < 500000000)
2244                 rate *= 2;
2245 #endif
2246 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2247         if (rate != clk_get_rate(base_clk))
2248                 clk_set_rate(base_clk, rate);
2249 #else
2250         if (rate != clk_get_rate(parent_clk))
2251                 clk_set_rate(parent_clk, rate);
2252 #endif
2253         if (clk_get_parent(clk) != parent_clk)
2254                 clk_set_parent(clk, parent_clk);
2255
2256         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2257 }
2258
2259 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
2260         .init = tegra_dc_hdmi_init,
2261         .destroy = tegra_dc_hdmi_destroy,
2262         .enable = tegra_dc_hdmi_enable,
2263         .disable = tegra_dc_hdmi_disable,
2264         .detect = tegra_dc_hdmi_detect,
2265         .suspend = tegra_dc_hdmi_suspend,
2266         .resume = tegra_dc_hdmi_resume,
2267         .mode_filter = tegra_dc_hdmi_mode_filter,
2268         .setup_clk = tegra_dc_hdmi_setup_clk,
2269 };
2270
2271 struct tegra_dc *tegra_dc_hdmi_get_dc(struct tegra_dc_hdmi_data *hdmi)
2272 {
2273         return hdmi ? hdmi->dc : NULL;
2274 }