2 * drivers/misc/tegra-profiler/hrt.c
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/sched.h>
20 #include <linux/hrtimer.h>
21 #include <linux/slab.h>
22 #include <linux/cpu.h>
23 #include <linux/ptrace.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/nsproxy.h>
27 #include <clocksource/arm_arch_timer.h>
29 #include <asm/cputype.h>
30 #include <asm/irq_regs.h>
31 #include <asm/arch_timer.h>
33 #include <linux/tegra_profiler.h>
40 #include "power_clk.h"
44 static struct quadd_hrt_ctx hrt;
47 read_all_sources(struct pt_regs *regs, struct task_struct *task);
49 struct hrt_event_value {
54 static inline u32 get_task_state(struct task_struct *task)
56 return (u32)(task->state | task->exit_state);
59 static enum hrtimer_restart hrtimer_handler(struct hrtimer *hrtimer)
63 regs = get_irq_regs();
65 if (!atomic_read(&hrt.active))
66 return HRTIMER_NORESTART;
68 qm_debug_handler_sample(regs);
71 read_all_sources(regs, NULL);
73 hrtimer_forward_now(hrtimer, ns_to_ktime(hrt.sample_period));
74 qm_debug_timer_forward(regs, hrt.sample_period);
76 return HRTIMER_RESTART;
79 static void start_hrtimer(struct quadd_cpu_context *cpu_ctx)
81 u64 period = hrt.sample_period;
83 __hrtimer_start_range_ns(&cpu_ctx->hrtimer,
84 ns_to_ktime(period), 0,
85 HRTIMER_MODE_REL_PINNED, 0);
86 qm_debug_timer_start(NULL, period);
89 static void cancel_hrtimer(struct quadd_cpu_context *cpu_ctx)
91 hrtimer_cancel(&cpu_ctx->hrtimer);
92 qm_debug_timer_cancel();
95 static void init_hrtimer(struct quadd_cpu_context *cpu_ctx)
97 hrtimer_init(&cpu_ctx->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
98 cpu_ctx->hrtimer.function = hrtimer_handler;
101 static inline u64 get_posix_clock_monotonic_time(void)
105 do_posix_clock_monotonic_gettime(&ts);
106 return timespec_to_ns(&ts);
109 static inline u64 get_arch_time(struct timecounter *tc)
112 const struct cyclecounter *cc = tc->cc;
114 value = cc->read(cc);
115 return cyclecounter_cyc2ns(cc, value);
118 u64 quadd_get_time(void)
120 struct timecounter *tc = hrt.tc;
122 return (tc && hrt.use_arch_timer) ?
124 get_posix_clock_monotonic_time();
128 __put_sample(struct quadd_record_data *data,
129 struct quadd_iovec *vec,
130 int vec_count, int cpu_id)
133 struct quadd_comm_data_interface *comm = hrt.quadd_ctx->comm;
135 err = comm->put_sample(data, vec, vec_count, cpu_id);
137 atomic64_inc(&hrt.skipped_samples);
139 atomic64_inc(&hrt.counter_samples);
143 quadd_put_sample_this_cpu(struct quadd_record_data *data,
144 struct quadd_iovec *vec, int vec_count)
146 __put_sample(data, vec, vec_count, -1);
150 quadd_put_sample(struct quadd_record_data *data,
151 struct quadd_iovec *vec, int vec_count)
153 __put_sample(data, vec, vec_count, 0);
156 static void put_header(void)
159 int nr_events = 0, max_events = QUADD_MAX_COUNTERS;
160 int events[QUADD_MAX_COUNTERS];
161 struct quadd_record_data record;
162 struct quadd_header_data *hdr = &record.hdr;
163 struct quadd_parameters *param = &hrt.quadd_ctx->param;
164 unsigned int extra = param->reserved[QUADD_PARAM_IDX_EXTRA];
165 struct quadd_iovec vec;
166 struct quadd_ctx *ctx = hrt.quadd_ctx;
167 struct quadd_event_source_interface *pmu = ctx->pmu;
168 struct quadd_event_source_interface *pl310 = ctx->pl310;
170 record.record_type = QUADD_RECORD_TYPE_HEADER;
172 hdr->magic = QUADD_HEADER_MAGIC;
173 hdr->version = QUADD_SAMPLES_VERSION;
175 hdr->backtrace = param->backtrace;
176 hdr->use_freq = param->use_freq;
177 hdr->system_wide = param->system_wide;
179 /* TODO: dynamically */
180 #ifdef QM_DEBUG_SAMPLES_ENABLE
181 hdr->debug_samples = 1;
183 hdr->debug_samples = 0;
186 hdr->freq = param->freq;
187 hdr->ma_freq = param->ma_freq;
188 hdr->power_rate_freq = param->power_rate_freq;
190 hdr->power_rate = hdr->power_rate_freq > 0 ? 1 : 0;
191 hdr->get_mmap = (extra & QUADD_PARAM_EXTRA_GET_MMAP) ? 1 : 0;
194 hdr->extra_length = 0;
196 if (hdr->backtrace) {
197 struct quadd_unw_methods *um = &hrt.um;
199 hdr->reserved |= um->fp ? QUADD_HDR_BT_FP : 0;
200 hdr->reserved |= um->ut ? QUADD_HDR_BT_UT : 0;
201 hdr->reserved |= um->ut_ce ? QUADD_HDR_BT_UT_CE : 0;
202 hdr->reserved |= um->dwarf ? QUADD_HDR_BT_DWARF : 0;
205 if (hrt.use_arch_timer)
206 hdr->reserved |= QUADD_HDR_USE_ARCH_TIMER;
208 if (hrt.get_stack_offset)
209 hdr->reserved |= QUADD_HDR_STACK_OFFSET;
212 nr_events += pmu->get_current_events(events, max_events);
215 nr_events += pl310->get_current_events(events + nr_events,
216 max_events - nr_events);
218 hdr->nr_events = nr_events;
221 vec.len = nr_events * sizeof(events[0]);
223 for_each_possible_cpu(cpu_id)
224 __put_sample(&record, &vec, 1, cpu_id);
228 put_sched_sample(struct task_struct *task, int is_sched_in)
230 unsigned int cpu, flags;
231 struct quadd_record_data record;
232 struct quadd_sched_data *s = &record.sched;
234 record.record_type = QUADD_RECORD_TYPE_SCHED;
236 cpu = quadd_get_processor_id(NULL, &flags);
238 s->lp_mode = (flags & QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP) ? 1 : 0;
240 s->sched_in = is_sched_in ? 1 : 0;
241 s->time = quadd_get_time();
246 s->data[QUADD_SCHED_IDX_TASK_STATE] = get_task_state(task);
247 s->data[QUADD_SCHED_IDX_RESERVED] = 0;
249 quadd_put_sample_this_cpu(&record, NULL, 0);
252 static int get_sample_data(struct quadd_sample_data *sample,
253 struct pt_regs *regs,
254 struct task_struct *task)
256 unsigned int cpu, flags;
257 struct quadd_ctx *quadd_ctx = hrt.quadd_ctx;
259 cpu = quadd_get_processor_id(regs, &flags);
263 (flags & QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP) ? 1 : 0;
264 sample->thumb_mode = (flags & QUADD_CPUMODE_THUMB) ? 1 : 0;
265 sample->user_mode = user_mode(regs) ? 1 : 0;
267 /* For security reasons, hide IPs from the kernel space. */
268 if (!sample->user_mode && !quadd_ctx->collect_kernel_ips)
271 sample->ip = instruction_pointer(regs);
273 sample->time = quadd_get_time();
274 sample->reserved = 0;
275 sample->pid = task->pid;
276 sample->in_interrupt = in_interrupt() ? 1 : 0;
281 static int read_source(struct quadd_event_source_interface *source,
282 struct pt_regs *regs,
283 struct hrt_event_value *events_vals,
287 u32 prev_val, val, res_val;
288 struct event_data events[QUADD_MAX_COUNTERS];
293 max_events = min_t(int, max_events, QUADD_MAX_COUNTERS);
294 nr_events = source->read(events, max_events);
296 for (i = 0; i < nr_events; i++) {
297 struct event_data *s = &events[i];
299 prev_val = s->prev_val;
303 res_val = val - prev_val;
305 res_val = QUADD_U32_MAX - prev_val + val;
307 if (s->event_source == QUADD_EVENT_SOURCE_PL310) {
308 int nr_active = atomic_read(&hrt.nr_active_all_core);
310 res_val /= nr_active;
313 events_vals[i].event_id = s->event_id;
314 events_vals[i].value = res_val;
321 get_stack_offset(struct task_struct *task,
322 struct pt_regs *regs,
323 struct quadd_callchain *cc)
326 struct vm_area_struct *vma;
327 struct mm_struct *mm = task->mm;
332 sp = cc->nr > 0 ? cc->curr_sp :
333 quadd_user_stack_pointer(regs);
335 vma = find_vma(mm, sp);
339 return vma->vm_end - sp;
343 read_all_sources(struct pt_regs *regs, struct task_struct *task)
345 u32 state, extra_data = 0, urcs = 0;
346 int i, vec_idx = 0, bt_size = 0;
347 int nr_events = 0, nr_positive_events = 0;
348 struct pt_regs *user_regs;
349 struct quadd_iovec vec[6];
350 struct hrt_event_value events[QUADD_MAX_COUNTERS];
351 u32 events_extra[QUADD_MAX_COUNTERS];
353 struct quadd_record_data record_data;
354 struct quadd_sample_data *s = &record_data.sample;
356 struct quadd_ctx *ctx = hrt.quadd_ctx;
357 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
358 struct quadd_callchain *cc = &cpu_ctx->cc;
363 if (atomic_read(&cpu_ctx->nr_active) == 0)
369 if (task_is_dead(task))
373 if (!task_nsproxy(task)) {
379 if (ctx->pmu && ctx->pmu_info.active)
380 nr_events += read_source(ctx->pmu, regs,
381 events, QUADD_MAX_COUNTERS);
383 if (ctx->pl310 && ctx->pl310_info.active)
384 nr_events += read_source(ctx->pl310, regs,
386 QUADD_MAX_COUNTERS - nr_events);
394 user_regs = current_pt_regs();
396 if (get_sample_data(s, regs, task))
399 vec[vec_idx].base = &extra_data;
400 vec[vec_idx].len = sizeof(extra_data);
411 if (ctx->param.backtrace) {
414 bt_size = quadd_get_user_callchain(user_regs, cc, ctx, task);
416 if (!bt_size && !user_mode(regs)) {
417 unsigned long pc = instruction_pointer(user_regs);
421 cc->cs_64 = compat_user_mode(user_regs) ? 0 : 1;
425 bt_size += quadd_callchain_store(cc, pc,
426 QUADD_UNW_TYPE_KCTX);
430 int ip_size = cc->cs_64 ? sizeof(u64) : sizeof(u32);
431 int nr_types = DIV_ROUND_UP(bt_size, 8);
433 vec[vec_idx].base = cc->cs_64 ?
434 (void *)cc->ip_64 : (void *)cc->ip_32;
435 vec[vec_idx].len = bt_size * ip_size;
438 vec[vec_idx].base = cc->types;
439 vec[vec_idx].len = nr_types * sizeof(cc->types[0]);
443 extra_data |= QUADD_SED_IP64;
446 urcs |= (cc->urc_fp & QUADD_SAMPLE_URC_MASK) <<
447 QUADD_SAMPLE_URC_SHIFT_FP;
448 urcs |= (cc->urc_ut & QUADD_SAMPLE_URC_MASK) <<
449 QUADD_SAMPLE_URC_SHIFT_UT;
450 urcs |= (cc->urc_dwarf & QUADD_SAMPLE_URC_MASK) <<
451 QUADD_SAMPLE_URC_SHIFT_DWARF;
453 s->reserved |= QUADD_SAMPLE_RES_URCS_ENABLED;
455 vec[vec_idx].base = &urcs;
456 vec[vec_idx].len = sizeof(urcs);
459 s->callchain_nr = bt_size;
461 if (hrt.get_stack_offset) {
462 long offset = get_stack_offset(task, user_regs, cc);
464 u32 off = offset >> 2;
465 off = min_t(u32, off, 0xffff);
466 extra_data |= off << QUADD_SED_STACK_OFFSET_SHIFT;
470 record_data.record_type = QUADD_RECORD_TYPE_SAMPLE;
473 for (i = 0; i < nr_events; i++) {
474 u32 value = events[i].value;
476 s->events_flags |= 1 << i;
477 events_extra[nr_positive_events++] = value;
481 if (nr_positive_events == 0)
484 vec[vec_idx].base = events_extra;
485 vec[vec_idx].len = nr_positive_events * sizeof(events_extra[0]);
488 state = get_task_state(task);
491 vec[vec_idx].base = &state;
492 vec[vec_idx].len = sizeof(state);
498 quadd_put_sample_this_cpu(&record_data, vec, vec_idx);
502 is_profile_process(struct task_struct *task)
505 pid_t pid, profile_pid;
506 struct quadd_ctx *ctx = hrt.quadd_ctx;
513 for (i = 0; i < ctx->param.nr_pids; i++) {
514 profile_pid = ctx->param.pids[i];
515 if (profile_pid == pid)
522 add_active_thread(struct quadd_cpu_context *cpu_ctx, pid_t pid, pid_t tgid)
524 struct quadd_thread_data *t_data = &cpu_ctx->active_thread;
526 if (t_data->pid > 0 ||
527 atomic_read(&cpu_ctx->nr_active) > 0) {
528 pr_warn_once("Warning for thread: %d\n", (int)pid);
537 static int remove_active_thread(struct quadd_cpu_context *cpu_ctx, pid_t pid)
539 struct quadd_thread_data *t_data = &cpu_ctx->active_thread;
544 if (t_data->pid == pid) {
550 pr_warn_once("Warning for thread: %d\n", (int)pid);
554 void __quadd_task_sched_in(struct task_struct *prev,
555 struct task_struct *task)
557 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
558 struct quadd_ctx *ctx = hrt.quadd_ctx;
559 struct event_data events[QUADD_MAX_COUNTERS];
560 /* static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 2); */
562 if (likely(!atomic_read(&hrt.active)))
565 if (__ratelimit(&ratelimit_state))
566 pr_info("sch_in, cpu: %d, prev: %u (%u) \t--> curr: %u (%u)\n",
567 smp_processor_id(), (unsigned int)prev->pid,
568 (unsigned int)prev->tgid, (unsigned int)task->pid,
569 (unsigned int)task->tgid);
572 if (is_profile_process(task)) {
573 put_sched_sample(task, 1);
575 add_active_thread(cpu_ctx, task->pid, task->tgid);
576 atomic_inc(&cpu_ctx->nr_active);
578 if (atomic_read(&cpu_ctx->nr_active) == 1) {
583 ctx->pl310->read(events, 1);
585 start_hrtimer(cpu_ctx);
586 atomic_inc(&hrt.nr_active_all_core);
591 void __quadd_task_sched_out(struct task_struct *prev,
592 struct task_struct *next)
595 struct pt_regs *user_regs;
596 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
597 struct quadd_ctx *ctx = hrt.quadd_ctx;
598 /* static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 2); */
600 if (likely(!atomic_read(&hrt.active)))
603 if (__ratelimit(&ratelimit_state))
604 pr_info("sch_out: cpu: %d, prev: %u (%u) \t--> next: %u (%u)\n",
605 smp_processor_id(), (unsigned int)prev->pid,
606 (unsigned int)prev->tgid, (unsigned int)next->pid,
607 (unsigned int)next->tgid);
610 if (is_profile_process(prev)) {
611 user_regs = task_pt_regs(prev);
613 read_all_sources(user_regs, prev);
615 n = remove_active_thread(cpu_ctx, prev->pid);
616 atomic_sub(n, &cpu_ctx->nr_active);
618 if (n && atomic_read(&cpu_ctx->nr_active) == 0) {
619 cancel_hrtimer(cpu_ctx);
620 atomic_dec(&hrt.nr_active_all_core);
626 put_sched_sample(prev, 0);
630 void __quadd_event_mmap(struct vm_area_struct *vma)
632 struct quadd_parameters *param;
634 if (likely(!atomic_read(&hrt.active)))
637 if (!is_profile_process(current))
640 param = &hrt.quadd_ctx->param;
641 quadd_process_mmap(vma, param->pids[0]);
644 static void reset_cpu_ctx(void)
647 struct quadd_cpu_context *cpu_ctx;
648 struct quadd_thread_data *t_data;
650 for (cpu_id = 0; cpu_id < nr_cpu_ids; cpu_id++) {
651 cpu_ctx = per_cpu_ptr(hrt.cpu_ctx, cpu_id);
652 t_data = &cpu_ctx->active_thread;
654 atomic_set(&cpu_ctx->nr_active, 0);
661 int quadd_hrt_start(void)
667 struct quadd_ctx *ctx = hrt.quadd_ctx;
668 struct quadd_parameters *param = &ctx->param;
670 freq = ctx->param.freq;
671 freq = max_t(long, QUADD_HRT_MIN_FREQ, freq);
672 period = NSEC_PER_SEC / freq;
673 hrt.sample_period = period;
675 if (ctx->param.ma_freq > 0)
676 hrt.ma_period = MSEC_PER_SEC / ctx->param.ma_freq;
680 atomic64_set(&hrt.counter_samples, 0);
681 atomic64_set(&hrt.skipped_samples, 0);
685 extra = param->reserved[QUADD_PARAM_IDX_EXTRA];
687 if (param->backtrace) {
688 struct quadd_unw_methods *um = &hrt.um;
690 um->fp = extra & QUADD_PARAM_EXTRA_BT_FP ? 1 : 0;
691 um->ut = extra & QUADD_PARAM_EXTRA_BT_UT ? 1 : 0;
692 um->ut_ce = extra & QUADD_PARAM_EXTRA_BT_UT_CE ? 1 : 0;
693 um->dwarf = extra & QUADD_PARAM_EXTRA_BT_DWARF ? 1 : 0;
695 pr_info("unw methods: fp/ut/ut_ce/dwarf: %u/%u/%u/%u\n",
696 um->fp, um->ut, um->ut_ce, um->dwarf);
699 if (hrt.tc && (extra & QUADD_PARAM_EXTRA_USE_ARCH_TIMER))
700 hrt.use_arch_timer = 1;
702 hrt.use_arch_timer = 0;
704 pr_info("timer: %s\n", hrt.use_arch_timer ? "arch" : "monotonic clock");
706 hrt.get_stack_offset =
707 (extra & QUADD_PARAM_EXTRA_STACK_OFFSET) ? 1 : 0;
711 if (extra & QUADD_PARAM_EXTRA_GET_MMAP) {
712 err = quadd_get_current_mmap(param->pids[0]);
714 pr_err("error: quadd_get_current_mmap\n");
722 quadd_ma_start(&hrt);
724 atomic_set(&hrt.active, 1);
726 pr_info("Start hrt: freq/period: %ld/%llu\n", freq, period);
730 void quadd_hrt_stop(void)
732 struct quadd_ctx *ctx = hrt.quadd_ctx;
734 pr_info("Stop hrt, samples all/skipped: %llu/%llu\n",
735 atomic64_read(&hrt.counter_samples),
736 atomic64_read(&hrt.skipped_samples));
743 atomic_set(&hrt.active, 0);
745 atomic64_set(&hrt.counter_samples, 0);
746 atomic64_set(&hrt.skipped_samples, 0);
748 /* reset_cpu_ctx(); */
751 void quadd_hrt_deinit(void)
753 if (atomic_read(&hrt.active))
756 free_percpu(hrt.cpu_ctx);
759 void quadd_hrt_get_state(struct quadd_module_state *state)
761 state->nr_all_samples = atomic64_read(&hrt.counter_samples);
762 state->nr_skipped_samples = atomic64_read(&hrt.skipped_samples);
765 static void init_arch_timer(void)
767 u32 cntkctl = arch_timer_get_cntkctl();
769 if (cntkctl & ARCH_TIMER_USR_VCT_ACCESS_EN)
770 hrt.tc = arch_timer_get_timecounter();
775 struct quadd_hrt_ctx *quadd_hrt_init(struct quadd_ctx *ctx)
780 struct quadd_cpu_context *cpu_ctx;
783 atomic_set(&hrt.active, 0);
785 freq = ctx->param.freq;
786 freq = max_t(long, QUADD_HRT_MIN_FREQ, freq);
787 period = NSEC_PER_SEC / freq;
788 hrt.sample_period = period;
790 if (ctx->param.ma_freq > 0)
791 hrt.ma_period = MSEC_PER_SEC / ctx->param.ma_freq;
795 atomic64_set(&hrt.counter_samples, 0);
798 hrt.cpu_ctx = alloc_percpu(struct quadd_cpu_context);
800 return ERR_PTR(-ENOMEM);
802 for_each_possible_cpu(cpu_id) {
803 cpu_ctx = per_cpu_ptr(hrt.cpu_ctx, cpu_id);
805 atomic_set(&cpu_ctx->nr_active, 0);
807 cpu_ctx->active_thread.pid = -1;
808 cpu_ctx->active_thread.tgid = -1;
810 cpu_ctx->cc.hrt = &hrt;
812 init_hrtimer(cpu_ctx);