drivers/video/tegra/dc/dsi.c

   1 /*
   2  * drivers/video/tegra/dc/dsi.c
   3  *
   4  * Copyright (c) 2011-2014, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/export.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/nvhost.h>
  32 #include <linux/lcm.h>
  33 #include <linux/gcd.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-soc.h>
  38 #include <linux/nvhost.h>
  39 #include <linux/of_address.h>
  40
  41 #include <mach/dc.h>
  42 #include <mach/fb.h>
  43 #include <mach/csi.h>
  44
  45 #include "dc_reg.h"
  46 #include "dc_priv.h"
  47 #include "dev.h"
  48 #include "dsi_regs.h"
  49 #include "dsi.h"
  50 #include "mipi_cal.h"
  51
  52 /* HACK! This needs to come from DT */
  53 #include "../../../../arch/arm/mach-tegra/iomap.h"
  54
  55 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
  56 #define DSIB_MODE_ENABLE                0x2
  57
  58 /* Only enabling for T124 for now; causes issues for other chips */
  59 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
  60 #define DSI_USE_SYNC_POINTS 1
  61 #else
  62 #define DSI_USE_SYNC_POINTS 0
  63 #endif
  64
  65 #define S_TO_MS(x)                      (1000 * (x))
  66 #define MS_TO_US(x)                     (1000 * (x))
  67
  68 #define DSI_MODULE_NOT_INIT             0x0
  69 #define DSI_MODULE_INIT                 0x1
  70
  71 #define DSI_LPHS_NOT_INIT               0x0
  72 #define DSI_LPHS_IN_LP_MODE             0x1
  73 #define DSI_LPHS_IN_HS_MODE             0x2
  74
  75 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
  76 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
  77 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
  78
  79 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
  80 #define DSI_DRIVEN_MODE_DC              0x1
  81 #define DSI_DRIVEN_MODE_HOST            0x2
  82
  83 #define DSI_PHYCLK_OUT_DIS              0x0
  84 #define DSI_PHYCLK_OUT_EN               0x1
  85
  86 #define DSI_PHYCLK_NOT_INIT             0x0
  87 #define DSI_PHYCLK_CONTINUOUS           0x1
  88 #define DSI_PHYCLK_TX_ONLY              0x2
  89
  90 #define DSI_CLK_BURST_NOT_INIT          0x0
  91 #define DSI_CLK_BURST_NONE_BURST        0x1
  92 #define DSI_CLK_BURST_BURST_MODE        0x2
  93
  94 #define DSI_DC_STREAM_DISABLE           0x0
  95 #define DSI_DC_STREAM_ENABLE            0x1
  96
  97 #define DSI_LP_OP_NOT_INIT              0x0
  98 #define DSI_LP_OP_WRITE                 0x1
  99 #define DSI_LP_OP_READ                  0x2
 100
 101 #define DSI_HOST_IDLE_PERIOD            1000
 102 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
 103
 104 static bool enable_read_debug;
 105 module_param(enable_read_debug, bool, 0644);
 106 MODULE_PARM_DESC(enable_read_debug,
 107                 "Enable to print read fifo and return packet type");
 108
 109 bool tegra_dsi_enable_read_debug(struct tegra_dc_dsi_data *dsi)
 110 {
 111         enable_read_debug = true;
 112         return enable_read_debug;
 113 }
 114
 115 bool tegra_dsi_disable_read_debug(struct tegra_dc_dsi_data *dsi)
 116 {
 117         enable_read_debug = false;
 118         return enable_read_debug;
 119 }
 120
 121 /* source of video data */
 122 enum {
 123         TEGRA_DSI_DRIVEN_BY_DC,
 124         TEGRA_DSI_DRIVEN_BY_HOST,
 125 };
 126
 127 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
 128         DSI_PKT_SEQ_0_LO,
 129         DSI_PKT_SEQ_0_HI,
 130         DSI_PKT_SEQ_1_LO,
 131         DSI_PKT_SEQ_1_HI,
 132         DSI_PKT_SEQ_2_LO,
 133         DSI_PKT_SEQ_2_HI,
 134         DSI_PKT_SEQ_3_LO,
 135         DSI_PKT_SEQ_3_HI,
 136         DSI_PKT_SEQ_4_LO,
 137         DSI_PKT_SEQ_4_HI,
 138         DSI_PKT_SEQ_5_LO,
 139         DSI_PKT_SEQ_5_HI,
 140 };
 141
 142 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
 143         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 144         0,
 145         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 146         0,
 147         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 148         0,
 149         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 150         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 151         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 152         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 153         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 154         0,
 155         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 156         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 157         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 158         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 159 };
 160
 161 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
 162         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 163         0,
 164         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 165         0,
 166         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 167         0,
 168         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 169         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 170         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 172         0,
 173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 174         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 175         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 176 };
 177
 178 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
 179         PKT_ID0(CMD_VS) | PKT_LEN0(0),
 180         0,
 181         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 182         0,
 183         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 184         0,
 185         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 186         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 187         0,
 188         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 189         0,
 190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 191         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 192         0,
 193 };
 194
 195 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
 196         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 197         0,
 198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 199         0,
 200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 201         0,
 202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 203         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 204         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 206         0,
 207         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 208         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 209         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 210 };
 211
 212 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
 213         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 214         0,
 215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 216         0,
 217         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 218         0,
 219         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 220         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 221         0,
 222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 223         0,
 224         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 225         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 226         0,
 227 };
 228
 229 const u32 dsi_pkt_seq_video_non_burst_no_eot[NUMOF_PKT_SEQ] = {
 230         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 231         0,
 232         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 233         0,
 234         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 235         0,
 236         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 237                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 238         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 239         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 240         0,
 241         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 242                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 243         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 244 };
 245
 246 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
 247         0,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 254                 PKT_LEN1(7) | PKT_LP,
 255         0,
 256         0,
 257         0,
 258         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 259                 PKT_LEN1(7) | PKT_LP,
 260         0,
 261 };
 262
 263 const u32 init_reg[] = {
 264         DSI_INT_ENABLE,
 265         DSI_INT_STATUS,
 266         DSI_INT_MASK,
 267         DSI_INIT_SEQ_DATA_0,
 268         DSI_INIT_SEQ_DATA_1,
 269         DSI_INIT_SEQ_DATA_2,
 270         DSI_INIT_SEQ_DATA_3,
 271         DSI_INIT_SEQ_DATA_4,
 272         DSI_INIT_SEQ_DATA_5,
 273         DSI_INIT_SEQ_DATA_6,
 274         DSI_INIT_SEQ_DATA_7,
 275         DSI_DCS_CMDS,
 276         DSI_PKT_SEQ_0_LO,
 277         DSI_PKT_SEQ_1_LO,
 278         DSI_PKT_SEQ_2_LO,
 279         DSI_PKT_SEQ_3_LO,
 280         DSI_PKT_SEQ_4_LO,
 281         DSI_PKT_SEQ_5_LO,
 282         DSI_PKT_SEQ_0_HI,
 283         DSI_PKT_SEQ_1_HI,
 284         DSI_PKT_SEQ_2_HI,
 285         DSI_PKT_SEQ_3_HI,
 286         DSI_PKT_SEQ_4_HI,
 287         DSI_PKT_SEQ_5_HI,
 288         DSI_CONTROL,
 289         DSI_HOST_DSI_CONTROL,
 290         DSI_PAD_CONTROL,
 291         DSI_PAD_CONTROL_CD,
 292         DSI_SOL_DELAY,
 293         DSI_MAX_THRESHOLD,
 294         DSI_TRIGGER,
 295         DSI_TX_CRC,
 296         DSI_INIT_SEQ_CONTROL,
 297         DSI_PKT_LEN_0_1,
 298         DSI_PKT_LEN_2_3,
 299         DSI_PKT_LEN_4_5,
 300         DSI_PKT_LEN_6_7,
 301 };
 302
 303 const u32 init_reg_vs1_ext[] = {
 304         DSI_PAD_CONTROL_0_VS1,
 305         DSI_PAD_CONTROL_CD_VS1,
 306         DSI_PAD_CD_STATUS_VS1,
 307         DSI_PAD_CONTROL_1_VS1,
 308         DSI_PAD_CONTROL_2_VS1,
 309         DSI_PAD_CONTROL_3_VS1,
 310         DSI_PAD_CONTROL_4_VS1,
 311         DSI_GANGED_MODE_CONTROL,
 312         DSI_GANGED_MODE_START,
 313         DSI_GANGED_MODE_SIZE,
 314 };
 315
 316 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
 317 static int tegra_dsi_host_resume(struct tegra_dc *dc);
 318 static void tegra_dc_dsi_idle_work(struct work_struct *work);
 319 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
 320                                      struct tegra_dc_dsi_data *dsi,
 321                                      int no_of_frames);
 322
 323 unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
 324                                                         u32 reg, int index)
 325 {
 326         unsigned long ret;
 327
 328         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 329         ret = readl(dsi->base[index] + reg * 4);
 330         trace_display_readl(dsi->dc, ret, dsi->base[index] + reg * 4);
 331         return ret;
 332 }
 333 EXPORT_SYMBOL(tegra_dsi_controller_readl);
 334
 335 void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
 336                                                 u32 val, u32 reg, int index)
 337 {
 338         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 339         trace_display_writel(dsi->dc, val, dsi->base[index] + reg * 4);
 340         writel(val, dsi->base[index] + reg * 4);
 341 }
 342 EXPORT_SYMBOL(tegra_dsi_controller_writel);
 343
 344 unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 345 {
 346         unsigned long ret;
 347         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 348         ret = readl(dsi->base[DSI_INSTANCE_0] + reg * 4);
 349         trace_display_readl(dsi->dc, ret, dsi->base[DSI_INSTANCE_0] + reg * 4);
 350         return ret;
 351 }
 352 EXPORT_SYMBOL(tegra_dsi_readl);
 353
 354 void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 355 {
 356         int  i = 0;
 357         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 358         for (i = 0; i < dsi->max_instances; i++) {
 359                 trace_display_writel(dsi->dc, val, dsi->base[i] + reg * 4);
 360                 writel(val, dsi->base[i] + reg * 4);
 361         }
 362 }
 363 EXPORT_SYMBOL(tegra_dsi_writel);
 364
 365 inline void tegra_dsi_reset_deassert(struct tegra_dc_dsi_data *dsi)
 366 {
 367         int i = 0;
 368         for (i = 0; i < dsi->max_instances; i++)
 369                 tegra_periph_reset_deassert(dsi->dsi_clk[i]);
 370 }
 371
 372 inline void tegra_dsi_reset_assert(struct tegra_dc_dsi_data *dsi)
 373 {
 374         int i = 0;
 375         for (i = 0; i < dsi->max_instances; i++)
 376                 tegra_periph_reset_assert(dsi->dsi_clk[i]);
 377 }
 378
 379 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi);
 380 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi);
 381
 382 void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
 383 {
 384         int i = 0;
 385         for (i = 0; i < dsi->max_instances; i++) {
 386                 clk_prepare_enable(dsi->dsi_clk[i]);
 387                 udelay(800);
 388         }
 389 }
 390
 391 void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
 392 {
 393         int i = 0;
 394         for (i = 0; i < dsi->max_instances; i++) {
 395                 clk_disable_unprepare(dsi->dsi_clk[i]);
 396                 udelay(800);
 397         }
 398 }
 399
 400 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi)
 401 {
 402         int i = 0;
 403         for (i = 0; i < dsi->max_instances; i++) {
 404                 clk_prepare_enable(dsi->dsi_lp_clk[i]);
 405                 udelay(800);
 406         }
 407 }
 408
 409 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi)
 410 {
 411         int i = 0;
 412         for (i = 0; i < dsi->max_instances; i++) {
 413                 clk_disable_unprepare(dsi->dsi_lp_clk[i]);
 414                 udelay(800);
 415         }
 416 }
 417
 418 static void tegra_dsi_setup_clk(struct tegra_dc *dc,
 419         struct tegra_dc_dsi_data *dsi)
 420 {
 421         int i = 0;
 422         for (i = 0; i < dsi->max_instances; i++) {
 423                 tegra_dc_setup_clk(dc, dsi->dsi_clk[i]);
 424                 mdelay(3);
 425         }
 426 }
 427
 428 static void __maybe_unused tegra_dsi_syncpt_reset(
 429                                 struct tegra_dc_dsi_data *dsi)
 430 {
 431         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
 432         /* stabilization delay */
 433         udelay(300);
 434         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
 435         /* stabilization delay */
 436         udelay(300);
 437 }
 438
 439 static int __maybe_unused tegra_dsi_syncpt
 440         (struct tegra_dc_dsi_data *dsi, u8 link_id)
 441 {
 442         u32 val;
 443         int ret = 0;
 444
 445         if (!nvhost_syncpt_read_ext_check(dsi->dc->ndev, dsi->syncpt_id, &val))
 446                 dsi->syncpt_val = val;
 447
 448         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
 449                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
 450         tegra_dsi_controller_writel(dsi, val, DSI_INCR_SYNCPT, link_id);
 451
 452         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
 453                 dsi->syncpt_val + 1, (u32)MAX_SCHEDULE_TIMEOUT, NULL, NULL);
 454         if (ret < 0) {
 455                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
 456                 goto fail;
 457         }
 458
 459         (dsi->syncpt_val)++;
 460         return 0;
 461 fail:
 462         return ret;
 463 }
 464
 465 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
 466 {
 467         u32 dsi_clock_rate_khz;
 468
 469         switch (dsi->info.video_burst_mode) {
 470         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
 471         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
 472         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
 473         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
 474                 /* Calculate DSI HS clock rate for DSI burst mode */
 475                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
 476                                         dsi->shift_clk_div.mul /
 477                                         dsi->shift_clk_div.div;
 478                 break;
 479         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
 480         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
 481         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
 482         default:
 483                 /* Clock rate is default DSI clock rate for non-burst mode */
 484                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
 485                 break;
 486         }
 487
 488         return dsi_clock_rate_khz;
 489 }
 490
 491 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
 492 {
 493         u32 dsi_clock_rate_khz;
 494
 495         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 496                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
 497                         dsi_clock_rate_khz =
 498                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
 499                 else
 500                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
 501         else
 502                 if (lp_op == DSI_LP_OP_READ)
 503                         dsi_clock_rate_khz =
 504                                 dsi->info.lp_read_cmd_mode_freq_khz;
 505                 else
 506                         dsi_clock_rate_khz =
 507                                 dsi->info.lp_cmd_mode_freq_khz;
 508
 509         return dsi_clock_rate_khz;
 510 }
 511
 512 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
 513                                                 struct tegra_dc_dsi_data *dsi)
 514 {
 515         struct tegra_dc_shift_clk_div shift_clk_div;
 516         struct tegra_dc_shift_clk_div max_shift_clk_div;
 517         struct tegra_dc_shift_clk_div delta_shift_clk_div;
 518         u32 temp_lcm;
 519         u32 burst_width;
 520         u32 burst_width_max;
 521         u32 temp_gcd;
 522         u32 default_hs_clk_mhz =
 523                 DIV_ROUND_CLOSEST(dsi->default_hs_clk_khz, 1000);
 524         u32 max_panel_freq_mhz =
 525                 DIV_ROUND_CLOSEST(dsi->info.max_panel_freq_khz, 1000);
 526
 527         /* Get the real value of default shift_clk_div. default_shift_clk_div
 528          * holds the real value of shift_clk_div.
 529          */
 530         shift_clk_div = dsi->default_shift_clk_div;
 531
 532         /* Calculate shift_clk_div which can match the video_burst_mode. */
 533         if (dsi->info.video_burst_mode >=
 534                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
 535                 if (max_panel_freq_mhz >= default_hs_clk_mhz) {
 536                         /* formula:
 537                          * dsi->info.max_panel_freq_khz * shift_clk_div /
 538                          * dsi->default_hs_clk_khz
 539                          */
 540                         max_shift_clk_div.mul = max_panel_freq_mhz *
 541                                                 shift_clk_div.mul;
 542                         max_shift_clk_div.div = default_hs_clk_mhz *
 543                                                 shift_clk_div.div;
 544                 } else {
 545                         max_shift_clk_div = shift_clk_div;
 546                 }
 547
 548                 burst_width = dsi->info.video_burst_mode
 549                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 550                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
 551                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 552
 553                 /* formula:
 554                  * (max_shift_clk_div - shift_clk_div) *
 555                  * burst_width / burst_width_max
 556                  */
 557                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
 558                 delta_shift_clk_div.mul = (temp_lcm / max_shift_clk_div.div *
 559                                         max_shift_clk_div.mul -
 560                                         temp_lcm / shift_clk_div.div *
 561                                         shift_clk_div.mul) *
 562                                         burst_width;
 563                 delta_shift_clk_div.div = temp_lcm * burst_width_max;
 564
 565                 /* formula:
 566                  * shift_clk_div + delta_shift_clk_div
 567                  */
 568                 temp_lcm = lcm(shift_clk_div.div, delta_shift_clk_div.div);
 569                 shift_clk_div.mul = temp_lcm / shift_clk_div.div *
 570                                 shift_clk_div.mul +
 571                                 temp_lcm / delta_shift_clk_div.div *
 572                                 delta_shift_clk_div.mul;
 573                 shift_clk_div.div = temp_lcm;
 574
 575                 /* crunch shift clk numerator and denominator */
 576                 temp_gcd = gcd(shift_clk_div.mul, shift_clk_div.div);
 577                 shift_clk_div.mul /= temp_gcd;
 578                 shift_clk_div.div /= temp_gcd;
 579         }
 580
 581         return shift_clk_div;
 582 }
 583
 584 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
 585                                         struct tegra_dc_dsi_data *dsi)
 586 {
 587         u32 h_width_pixels;
 588         u32 h_act_corr = 0;
 589         u32 hfp_corr = 0;
 590         u32 temp = 0;
 591
 592         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 593                         dc->mode.h_sync_width + dc->mode.h_active;
 594
 595         if (WARN(!dsi->info.n_data_lanes, "dsi n_data_lanes is 0\n"))
 596                 return;
 597
 598         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
 599                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
 600                 if (temp) {
 601                         h_act_corr = dsi->info.n_data_lanes - temp;
 602                         h_width_pixels += h_act_corr;
 603                 }
 604         }
 605
 606         temp = h_width_pixels % dsi->info.n_data_lanes;
 607         if (temp) {
 608                 hfp_corr = dsi->info.n_data_lanes - temp;
 609                 h_width_pixels += hfp_corr;
 610         }
 611
 612         while (1) {
 613                 if (WARN(!dsi->pixel_scaler_div, "dsi pixel_scaler_div is 0"))
 614                         temp = 0;
 615                 else
 616                         temp = (h_width_pixels * dsi->pixel_scaler_mul /
 617                                 dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
 618                 if (temp) {
 619                         hfp_corr += dsi->info.n_data_lanes;
 620                         h_width_pixels += dsi->info.n_data_lanes;
 621                 }
 622                 else
 623                         break;
 624         }
 625
 626         dc->mode.h_front_porch += hfp_corr;
 627         dc->mode.h_active += h_act_corr;
 628 }
 629
 630 static void tegra_dsi_init_sw(struct tegra_dc *dc,
 631                         struct tegra_dc_dsi_data *dsi)
 632 {
 633         u32 h_width_pixels;
 634         u32 v_width_lines;
 635         u32 pixel_clk_hz;
 636         u32 byte_clk_hz;
 637         u32 plld_clk_mhz;
 638         u8 n_data_lanes;
 639
 640         switch (dsi->info.pixel_format) {
 641         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
 642                 /* 2 bytes per pixel */
 643                 dsi->pixel_scaler_mul = 2;
 644                 dsi->pixel_scaler_div = 1;
 645                 break;
 646         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
 647                 /* 2.25 bytes per pixel */
 648                 dsi->pixel_scaler_mul = 9;
 649                 dsi->pixel_scaler_div = 4;
 650                 break;
 651         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
 652         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
 653                 /* 3 bytes per pixel */
 654                 dsi->pixel_scaler_mul = 3;
 655                 dsi->pixel_scaler_div = 1;
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         dsi->ulpm = false;
 662         dsi->enabled = false;
 663         dsi->clk_ref = false;
 664
 665         n_data_lanes = dsi->info.n_data_lanes;
 666         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
 667                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
 668                 n_data_lanes /= 2;
 669
 670         dsi->dsi_control_val =
 671                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
 672                         DSI_CONTROL_NUM_DATA_LANES(n_data_lanes - 1) |
 673                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
 674                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
 675
 676         if (dsi->info.ganged_type)
 677                 tegra_dsi_pix_correction(dc, dsi);
 678
 679         /* Below we are going to calculate dsi and dc clock rate.
 680          * Calcuate the horizontal and vertical width.
 681          */
 682         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 683                         dc->mode.h_sync_width + dc->mode.h_active;
 684
 685         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
 686                         dc->mode.v_sync_width + dc->mode.v_active;
 687
 688         /* Calculate minimum required pixel rate. */
 689         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
 690         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
 691                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
 692                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
 693                                 "should be larger than rated refresh rate.\n");
 694                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
 695                                                 dsi->info.rated_refresh_rate;
 696         }
 697
 698         /* Calculate minimum byte rate on DSI interface. */
 699         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
 700                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
 701
 702         /* Round up to multiple of mega hz. */
 703         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
 704                                                                 1000000);
 705
 706         /* Calculate default real shift_clk_div. */
 707         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
 708                                         dsi->pixel_scaler_mul;
 709         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
 710                                         dsi->info.n_data_lanes;
 711
 712         /* Calculate default DSI hs clock. DSI interface is double data rate.
 713          * Data is transferred on both rising and falling edge of clk, div by 2
 714          * to get the actual clock rate.
 715          */
 716         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
 717
 718         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
 719                                         dsi->default_shift_clk_div.div) /
 720                                         (2 * dsi->default_shift_clk_div.mul);
 721
 722         /* Get the actual shift_clk_div and clock rates. */
 723         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
 724         dsi->target_lp_clk_khz =
 725                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
 726         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
 727
 728         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
 729                                         dsi->target_hs_clk_khz);
 730
 731 #if DSI_USE_SYNC_POINTS
 732         dsi->syncpt_id = NVSYNCPT_DSI;
 733 #endif
 734
 735         /*
 736          * Force video clock to be continuous mode if
 737          * enable_hs_clock_on_lp_cmd_mode is set
 738          */
 739         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 740                 if (dsi->info.video_clock_mode !=
 741                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
 742                         dev_warn(&dc->ndev->dev,
 743                                 "Force clock continuous mode\n");
 744
 745                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
 746         }
 747
 748         atomic_set(&dsi->host_ref, 0);
 749         dsi->host_suspended = false;
 750         mutex_init(&dsi->host_lock);
 751         init_completion(&dc->out->user_vblank_comp);
 752         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
 753         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
 754 }
 755
 756 #define SELECT_T_PHY(platform_t_phy_ps, default_phy, clk_ps, hw_inc) ( \
 757 (platform_t_phy_ps) ? ( \
 758 ((DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)) < 0 ? 0 : \
 759 (DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)))) : \
 760 ((default_phy) < 0 ? 0 : (default_phy)))
 761
 762 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
 763                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 764 {
 765         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 766                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 767                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 768
 769         phy_timing_clk->t_clktrail = SELECT_T_PHY(
 770                 dsi->info.phy_timing.t_clktrail_ns * 1000,
 771                 T_CLKTRAIL_DEFAULT(clk_ps), clk_ps, T_CLKTRAIL_HW_INC);
 772
 773         phy_timing_clk->t_clkpost = SELECT_T_PHY(
 774                 dsi->info.phy_timing.t_clkpost_ns * 1000,
 775                 T_CLKPOST_DEFAULT(clk_ps), clk_ps, T_CLKPOST_HW_INC);
 776
 777         phy_timing_clk->t_clkzero = SELECT_T_PHY(
 778                 dsi->info.phy_timing.t_clkzero_ns * 1000,
 779                 T_CLKZERO_DEFAULT(clk_ps), clk_ps, T_CLKZERO_HW_INC);
 780
 781         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
 782                 dsi->info.phy_timing.t_clkprepare_ns * 1000,
 783                 T_CLKPREPARE_DEFAULT(clk_ps), clk_ps, T_CLKPREPARE_HW_INC);
 784
 785         phy_timing_clk->t_clkpre = SELECT_T_PHY(
 786                 dsi->info.phy_timing.t_clkpre_ns * 1000,
 787                 T_CLKPRE_DEFAULT, clk_ps, T_CLKPRE_HW_INC);
 788 }
 789
 790 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
 791                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 792 {
 793         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 794                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 795                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 796
 797         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
 798                 dsi->info.phy_timing.t_hsdexit_ns * 1000,
 799                 T_HSEXIT_DEFAULT(clk_ps), clk_ps, T_HSEXIT_HW_INC);
 800
 801         phy_timing_clk->t_hstrail = SELECT_T_PHY(
 802                 dsi->info.phy_timing.t_hstrail_ns * 1000,
 803                 T_HSTRAIL_DEFAULT(clk_ps), clk_ps, T_HSTRAIL_HW_INC);
 804
 805         phy_timing_clk->t_datzero = SELECT_T_PHY(
 806                 dsi->info.phy_timing.t_datzero_ns * 1000,
 807                 T_DATZERO_DEFAULT(clk_ps), clk_ps, T_DATZERO_HW_INC);
 808
 809         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
 810                 dsi->info.phy_timing.t_hsprepare_ns * 1000,
 811                 T_HSPREPARE_DEFAULT(clk_ps), clk_ps, T_HSPREPARE_HW_INC);
 812 }
 813
 814 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
 815                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 816 {
 817         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 818                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 819                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 820 }
 821
 822 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
 823                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 824 {
 825         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 826                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 827                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 828
 829         phy_timing_clk->t_taget = SELECT_T_PHY(
 830                 dsi->info.phy_timing.t_taget_ns * 1000,
 831                 T_TAGET_DEFAULT(clk_ps), clk_ps, T_TAGET_HW_INC);
 832
 833         phy_timing_clk->t_tasure = SELECT_T_PHY(
 834                 dsi->info.phy_timing.t_tasure_ns * 1000,
 835                 T_TASURE_DEFAULT(clk_ps), clk_ps, T_TASURE_HW_INC);
 836
 837         phy_timing_clk->t_tago = SELECT_T_PHY(
 838                 dsi->info.phy_timing.t_tago_ns * 1000,
 839                 T_TAGO_DEFAULT(clk_ps), clk_ps, T_TAGO_HW_INC);
 840 }
 841
 842 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
 843                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 844 {
 845         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 846                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 847                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 848
 849         phy_timing_clk->t_wakeup = SELECT_T_PHY(
 850                 dsi->info.phy_timing.t_wakeup_ns * 1000,
 851                 T_WAKEUP_DEFAULT, clk_ps, T_WAKEUP_HW_INC);
 852 }
 853
 854 #undef SELECT_T_PHY
 855
 856 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
 857                                 struct dsi_phy_timing_inclk *phy_timing_clk,
 858                                 u32 clk_ps, u8 lphs)
 859 {
 860         if (tegra_platform_is_fpga() && !(dsi->info.ganged_type)) {
 861                 clk_ps = (1000 * 1000 * 1000) / (dsi->info.fpga_freq_khz ?
 862                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
 863         }
 864
 865         if (lphs == DSI_LPHS_IN_HS_MODE) {
 866                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ps);
 867                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ps);
 868         } else {
 869                 /* default is LP mode */
 870                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ps);
 871                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ps);
 872                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ps);
 873                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 874                         tegra_dsi_get_clk_phy_timing(dsi,
 875                                         phy_timing_clk, clk_ps);
 876         }
 877 }
 878
 879 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
 880                                 struct dsi_phy_timing_inclk *phy_timing,
 881                                 u32 clk_ps, u8 lphs)
 882 {
 883         int err = 0;
 884
 885 #define CHECK_RANGE(val, min, max) ( \
 886                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
 887                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 888
 889         if (tegra_platform_is_fpga())
 890                 clk_ps = dsi->info.fpga_freq_khz ?
 891                         ((1000 * 1000 * 1000) / dsi->info.fpga_freq_khz) :
 892                         DEFAULT_FPGA_FREQ_KHZ;
 893
 894         err = CHECK_RANGE(
 895         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 896                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC),
 897                         MIPI_T_TLPX_PS_MIN, MIPI_T_TLPX_PS_MAX);
 898         if (err < 0) {
 899                 dev_warn(&dsi->dc->ndev->dev,
 900                         "dsi: Tlpx mipi range violated\n");
 901                 goto fail;
 902         }
 903
 904         if (lphs == DSI_LPHS_IN_HS_MODE) {
 905                 err = CHECK_RANGE(
 906                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 907                         phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC),
 908                         MIPI_T_HSEXIT_PS_MIN, MIPI_T_HSEXIT_PS_MAX);
 909                 if (err < 0) {
 910                         dev_warn(&dsi->dc->ndev->dev,
 911                                 "dsi: HsExit mipi range violated\n");
 912                         goto fail;
 913                 }
 914
 915                 err = CHECK_RANGE(
 916                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 917                         phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC),
 918                         MIPI_T_HSTRAIL_PS_MIN(clk_ps), MIPI_T_HSTRAIL_PS_MAX);
 919                 if (err < 0) {
 920                         dev_warn(&dsi->dc->ndev->dev,
 921                                 "dsi: HsTrail mipi range violated\n");
 922                         goto fail;
 923                 }
 924
 925                 err = CHECK_RANGE(
 926                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 927                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 928                         MIPI_T_HSZERO_PS_MIN, MIPI_T_HSZERO_PS_MAX);
 929                 if (err < 0) {
 930                         dev_warn(&dsi->dc->ndev->dev,
 931                                 "dsi: HsZero mipi range violated\n");
 932                         goto fail;
 933                 }
 934
 935                 err = CHECK_RANGE(
 936                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 937                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC),
 938                         MIPI_T_HSPREPARE_PS_MIN(clk_ps),
 939                         MIPI_T_HSPREPARE_PS_MAX(clk_ps));
 940                 if (err < 0) {
 941                         dev_warn(&dsi->dc->ndev->dev,
 942                                 "dsi: HsPrepare mipi range violated\n");
 943                         goto fail;
 944                 }
 945
 946                 err = CHECK_RANGE(
 947                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 948                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
 949                         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 950                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 951                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MIN(clk_ps),
 952                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MAX);
 953                 if (err < 0) {
 954                         dev_warn(&dsi->dc->ndev->dev,
 955                         "dsi: HsPrepare + HsZero mipi range violated\n");
 956                         goto fail;
 957                 }
 958         } else {
 959                 /* default is LP mode */
 960                 err = CHECK_RANGE(
 961                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 962                         phy_timing->t_wakeup, clk_ps, T_WAKEUP_HW_INC),
 963                         MIPI_T_WAKEUP_PS_MIN, MIPI_T_WAKEUP_PS_MAX);
 964                 if (err < 0) {
 965                         dev_warn(&dsi->dc->ndev->dev,
 966                                 "dsi: WakeUp mipi range violated\n");
 967                         goto fail;
 968                 }
 969
 970                 err = CHECK_RANGE(
 971                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 972                         phy_timing->t_tasure, clk_ps, T_TASURE_HW_INC),
 973                         MIPI_T_TASURE_PS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 974                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)),
 975                         MIPI_T_TASURE_PS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 976                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)));
 977                 if (err < 0) {
 978                         dev_warn(&dsi->dc->ndev->dev,
 979                                 "dsi: TaSure mipi range violated\n");
 980                         goto fail;
 981                 }
 982         }
 983
 984         if (lphs == DSI_LPHS_IN_HS_MODE ||
 985                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 986                 err = CHECK_RANGE(
 987                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 988                         phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC),
 989                         MIPI_T_CLKTRAIL_PS_MIN, MIPI_T_CLKTRAIL_PS_MAX);
 990                 if (err < 0) {
 991                         dev_warn(&dsi->dc->ndev->dev,
 992                                 "dsi: ClkTrail mipi range violated\n");
 993                         goto fail;
 994                 }
 995
 996                 err = CHECK_RANGE(
 997                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 998                         phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC),
 999                         MIPI_T_CLKPOST_PS_MIN(clk_ps), MIPI_T_CLKPOST_PS_MAX);
1000                 if (err < 0) {
1001                         dev_warn(&dsi->dc->ndev->dev,
1002                                 "dsi: ClkPost mipi range violated\n");
1003                         goto fail;
1004                 }
1005
1006                 err = CHECK_RANGE(
1007                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1008                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1009                         MIPI_T_CLKZERO_PS_MIN, MIPI_T_CLKZERO_PS_MAX);
1010                 if (err < 0) {
1011                         dev_warn(&dsi->dc->ndev->dev,
1012                                 "dsi: ClkZero mipi range violated\n");
1013                         goto fail;
1014                 }
1015
1016                 err = CHECK_RANGE(
1017                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1018                         phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC),
1019                         MIPI_T_CLKPREPARE_PS_MIN, MIPI_T_CLKPREPARE_PS_MAX);
1020                 if (err < 0) {
1021                         dev_warn(&dsi->dc->ndev->dev,
1022                                 "dsi: ClkPrepare mipi range violated\n");
1023                         goto fail;
1024                 }
1025
1026                 err = CHECK_RANGE(
1027                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1028                         phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC),
1029                         MIPI_T_CLKPRE_PS_MIN, MIPI_T_CLKPRE_PS_MAX);
1030                 if (err < 0) {
1031                         dev_warn(&dsi->dc->ndev->dev,
1032                                 "dsi: ClkPre mipi range violated\n");
1033                         goto fail;
1034                 }
1035
1036                 err = CHECK_RANGE(
1037                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1038                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1039                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1040                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1041                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MIN,
1042                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MAX);
1043                 if (err < 0) {
1044                         dev_warn(&dsi->dc->ndev->dev,
1045                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1046                         goto fail;
1047                 }
1048         }
1049 fail:
1050 #undef CHECK_RANGE
1051         return err;
1052 }
1053
1054 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1055                                 struct dsi_phy_timing_inclk *phy_timing,
1056                                 u32 clk_ps, u8 lphs)
1057 {
1058         u32 hs_t_phy_ps = 0;
1059         u32 clk_t_phy_ps = 0;
1060         u32 t_phy_ps;
1061         u32 h_blank_ps;
1062         struct tegra_dc_mode *modes;
1063         u32 t_pix_ps;
1064         int err = 0;
1065
1066         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1067                 goto fail;
1068
1069         if (dsi->info.video_data_type ==
1070                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1071                 dsi->info.video_burst_mode <=
1072                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1073                 goto fail;
1074
1075         modes = dsi->dc->out->modes;
1076         t_pix_ps = clk_ps * BITS_PER_BYTE *
1077                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1078
1079         hs_t_phy_ps =
1080                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1081                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1082                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1083                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1084                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1085                 phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
1086                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1087                 phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC) +
1088                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1089                 phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC) +
1090                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1091                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC);
1092
1093         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1094                 clk_t_phy_ps =
1095                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1096                 phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC) +
1097                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1098                 phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC) +
1099                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1100                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC) +
1101                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1102                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1103                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1104                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1105                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1106                 phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC) +
1107                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1108                 phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC);
1109
1110                 /* clk_pre overlaps LP-11 hs mode start sequence */
1111                 hs_t_phy_ps -= DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1112                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC);
1113         }
1114
1115         h_blank_ps = t_pix_ps * (modes->h_sync_width + modes->h_back_porch +
1116                                                 modes->h_front_porch);
1117
1118         /* Extra tlpx and byte cycle required by dsi HW */
1119         t_phy_ps = dsi->info.n_data_lanes * (hs_t_phy_ps + clk_t_phy_ps +
1120                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1121                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1122                 clk_ps * BITS_PER_BYTE);
1123
1124         if (h_blank_ps < t_phy_ps) {
1125                 err = -EINVAL;
1126                 dev_WARN(&dsi->dc->ndev->dev,
1127                         "dsi: Hblank is smaller than HS phy timing: %u pix\n",
1128                                         (t_phy_ps - h_blank_ps) / t_pix_ps);
1129                 goto fail;
1130         }
1131
1132         return 0;
1133 fail:
1134         return err;
1135 }
1136
1137 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1138                                 struct dsi_phy_timing_inclk *phy_timing,
1139                                 u32 clk_ps, u8 lphs)
1140 {
1141         int err = 0;
1142
1143         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ps, lphs);
1144         if (err < 0) {
1145                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1146                 goto fail;
1147         }
1148
1149         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ps, lphs);
1150         if (err < 0) {
1151                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1152                 goto fail;
1153         }
1154
1155         /* TODO: add more contraints */
1156 fail:
1157         return err;
1158 }
1159
1160 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1161 {
1162         u32 val;
1163         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1164
1165         tegra_dsi_get_phy_timing
1166                 (dsi, &phy_timing, dsi->current_bit_clk_ps, lphs);
1167
1168         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1169                                         dsi->current_bit_clk_ps, lphs);
1170
1171         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1172                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1173                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1174                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1175                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1176
1177                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1178                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1179                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1180                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1181
1182                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1183                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1184                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1185
1186                 phy_timing.t_taget += T_TAGET_HW_INC;
1187                 phy_timing.t_tasure += T_TASURE_HW_INC;
1188                 phy_timing.t_tago += T_TAGO_HW_INC;
1189         }
1190         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1191                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1192                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1193                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1194         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1195
1196         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1197                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1198                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1199                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1200         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1201
1202         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1203                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1204                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1205         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1206
1207         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1208                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1209                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1210         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1211
1212         dsi->phy_timing = phy_timing;
1213 }
1214
1215 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1216                                 struct tegra_dc_dsi_data *dsi)
1217 {
1218         u32 dsi_to_pixel_clk_ratio;
1219         u32 temp;
1220         u32 temp1;
1221         u32 mipi_clk_adj_kHz = 0;
1222         u32 sol_delay;
1223         struct tegra_dc_mode *dc_modes = &dc->mode;
1224
1225         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1226         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1227                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1228
1229         /* Convert Fdsi to byte format */
1230         dsi_to_pixel_clk_ratio *= 1000/8;
1231
1232         /* Multiplying by 1000 so that we don't loose the fraction part */
1233         temp = dc_modes->h_active * 1000;
1234         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1235                         dc_modes->h_sync_width;
1236
1237         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1238                         temp * dsi->pixel_scaler_mul /
1239                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1240
1241         /* Do rounding on sol delay */
1242         sol_delay = (sol_delay + 1000 - 1)/1000;
1243
1244         /* TODO:
1245          * 1. find out the correct sol fifo depth to use
1246          * 2. verify with hw about the clamping function
1247          */
1248         if (sol_delay > (480 * 4)) {
1249                 sol_delay = (480 * 4);
1250                 mipi_clk_adj_kHz = sol_delay +
1251                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1252                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1253
1254                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1255
1256                 mipi_clk_adj_kHz *= 4;
1257         }
1258
1259         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1260
1261         return sol_delay;
1262 }
1263
1264 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1265                                 struct tegra_dc_dsi_data *dsi)
1266 {
1267         u32 sol_delay;
1268         u32 internal_delay;
1269         u32 h_width_byte_clk;
1270         u32 h_width_pixels;
1271         u32 h_width_ganged_byte_clk;
1272         u8 n_data_lanes_this_cont = 0;
1273         u8 n_data_lanes_ganged = 0;
1274
1275         if (!(dsi->info.ganged_type)) {
1276                 if (dsi->info.video_burst_mode ==
1277                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1278                         dsi->info.video_burst_mode ==
1279                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1280 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1281                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1282                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1283 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1284                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1285                 } else {
1286                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1287                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1288                 }
1289         } else {
1290 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1291 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1292 #define FIFO_WR_PIX_CLK_DELAY 2
1293 #define FIFO_RD_BYTE_CLK_DELAY 6
1294 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1295                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1296                                 FIFO_WR_PIX_CLK_DELAY)
1297
1298                 internal_delay = DIV_ROUND_UP(
1299                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1300                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1301                                 + FIFO_RD_BYTE_CLK_DELAY;
1302
1303                 h_width_pixels = dc->mode.h_sync_width +
1304                                         dc->mode.h_back_porch +
1305                                         dc->mode.h_active +
1306                                         dc->mode.h_front_porch;
1307
1308                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1309                                         dsi->pixel_scaler_mul,
1310                                         dsi->pixel_scaler_div *
1311                                         dsi->info.n_data_lanes);
1312
1313                 if (dsi->info.ganged_type ==
1314                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1315                         dsi->info.ganged_type ==
1316                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1317                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1318                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1319                 }
1320
1321                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1322                                         n_data_lanes_this_cont *
1323                                         h_width_byte_clk,
1324                                         n_data_lanes_ganged);
1325
1326                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1327                                                         internal_delay;
1328                 sol_delay = (dsi->info.video_data_type ==
1329                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1330                                 sol_delay + 20 : sol_delay;
1331
1332 #undef SOL_TO_VALID_PIX_CLK_DELAY
1333 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1334 #undef FIFO_WR_PIX_CLK_DELAY
1335 #undef FIFO_RD_BYTE_CLK_DELAY
1336 #undef TOT_INTERNAL_PIX_DELAY
1337         }
1338
1339         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1340                                                 DSI_SOL_DELAY);
1341 }
1342
1343 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1344 {
1345         u32 val;
1346         u32 bytes_per_frame;
1347         u32 timeout = 0;
1348
1349         /* TODO: verify the following equation */
1350         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1351                                                 (dsi->info.refresh_rate * 8);
1352         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1353         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1354
1355         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1356                         DSI_TIMEOUT_0_HTX_TO(timeout);
1357         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1358
1359         if (dsi->info.panel_reset_timeout_msec)
1360                 timeout = (dsi->info.panel_reset_timeout_msec * 1000 * 1000 *
1361                                          1000) / dsi->current_bit_clk_ps;
1362         else
1363                 timeout = DSI_PR_TO_VALUE;
1364
1365         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1366                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1367         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1368
1369         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1370                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1371                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1372                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1373         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1374 }
1375
1376 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1377                                                 struct tegra_dc_dsi_data *dsi)
1378 {
1379         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1380         u32 hact_pkt_len_pix = 0;
1381         u32 hact_pkt_len_bytes = 0;
1382         u32 hfp_pkt_len_bytes = 0;
1383         u32 pix_per_line_orig = 0;
1384         u32 pix_per_line = 0;
1385         u32 val = 0;
1386         int i = 0;
1387
1388 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1389 #define HEADER_OVERHEAD 16
1390
1391         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1392                         dc->mode.h_active + dc->mode.h_front_porch;
1393
1394         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1395                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1396         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1397
1398         switch (dsi->info.ganged_type) {
1399         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT: /* fall through */
1400         case TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD: /* fall through */
1401                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1402                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1403                 break;
1404         default:
1405                 dev_err(&dc->ndev->dev, "dsi: invalid ganged type\n");
1406         }
1407
1408         for (i = 0; i < dsi->max_instances; i++) {
1409                 hact_pkt_len_bytes = hact_pkt_len_pix *
1410                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1411                 hfp_pkt_len_bytes = pix_per_line *
1412                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1413                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1414
1415                 val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1416                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1417                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_2_3, i);
1418
1419                 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1420                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1421                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_4_5, i);
1422
1423                 hact_pkt_len_pix =
1424                         hact_pkt_len_pix_orig - hact_pkt_len_pix;
1425                 pix_per_line = pix_per_line_orig - pix_per_line;
1426         }
1427
1428         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1429                 DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1430         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1431
1432 #undef HEADER_OVERHEAD
1433 }
1434
1435 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1436                                                 struct tegra_dc_dsi_data *dsi)
1437 {
1438         u32 val;
1439         u32 hact_pkt_len;
1440         u32 hsa_pkt_len;
1441         u32 hbp_pkt_len;
1442         u32 hfp_pkt_len;
1443
1444         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1445                                                         dsi->pixel_scaler_div;
1446         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1447                                                         dsi->pixel_scaler_div;
1448         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1449                                                         dsi->pixel_scaler_div;
1450         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1451                                                         dsi->pixel_scaler_div;
1452
1453         if (dsi->info.video_burst_mode !=
1454                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1455                 hbp_pkt_len += hsa_pkt_len;
1456
1457         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1458         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1459         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1460
1461         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1462                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1463         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1464
1465         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1466                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1467         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1468
1469         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1470                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1471         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1472
1473         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1474         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1475 }
1476
1477 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1478                                                 struct tegra_dc_dsi_data *dsi)
1479 {
1480         unsigned long   val;
1481         unsigned long   act_bytes;
1482
1483         if (dsi->info.ganged_type) {
1484                 act_bytes = DIV_ROUND_UP(dc->mode.h_active, 2);
1485                 act_bytes = (act_bytes) * dsi->pixel_scaler_mul /
1486                                 dsi->pixel_scaler_div + 1;
1487         } else {
1488                 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1489                                 dsi->pixel_scaler_div + 1;
1490         }
1491         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1492         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1493
1494         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1495         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1496
1497         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1498         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1499
1500         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1501         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1502 }
1503
1504 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1505                                 struct tegra_dc_dsi_data *dsi)
1506 {
1507         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1508                 return;
1509
1510         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1511                 if (dsi->info.ganged_type)
1512                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1513                 else
1514                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1515         } else {
1516                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1517         }
1518 }
1519
1520 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1521                                 struct tegra_dc_dsi_data *dsi)
1522 {
1523         const u32 *pkt_seq;
1524         u32 rgb_info;
1525         u32 pkt_seq_3_5_rgb_lo;
1526         u32 pkt_seq_3_5_rgb_hi;
1527         u32     val;
1528         u32 reg;
1529         u8  i;
1530
1531         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1532                 return;
1533
1534         switch (dsi->info.pixel_format) {
1535         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1536                 rgb_info = CMD_RGB_16BPP;
1537                 break;
1538         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1539                 rgb_info = CMD_RGB_18BPP;
1540                 break;
1541         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1542                 rgb_info = CMD_RGB_18BPPNP;
1543                 break;
1544         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1545         default:
1546                 rgb_info = CMD_RGB_24BPP;
1547                 break;
1548         }
1549
1550         pkt_seq_3_5_rgb_lo = 0;
1551         pkt_seq_3_5_rgb_hi = 0;
1552         if (dsi->info.pkt_seq)
1553                 pkt_seq = dsi->info.pkt_seq;
1554         else if (dsi->info.video_data_type ==
1555                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1556                         pkt_seq = dsi_pkt_seq_cmd_mode;
1557         } else {
1558                 switch (dsi->info.video_burst_mode) {
1559                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1560                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1561                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1562                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1563                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1564                         pkt_seq_3_5_rgb_lo =
1565                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1566                         if (!dsi->info.no_pkt_seq_eot)
1567                                 pkt_seq = dsi_pkt_seq_video_burst;
1568                         else
1569                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1570                         break;
1571                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1572                         pkt_seq_3_5_rgb_hi =
1573                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1574                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1575                         break;
1576                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1577                 default:
1578                         if (dsi->info.ganged_type) {
1579                                 pkt_seq_3_5_rgb_lo =
1580                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1581                                 pkt_seq =
1582                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1583                         } else {
1584                                 pkt_seq_3_5_rgb_lo =
1585                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1586                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1587                         }
1588
1589                         /* Simulator does not support EOT packet yet */
1590                         if (tegra_cpu_is_asim())
1591                                 pkt_seq = dsi_pkt_seq_video_non_burst_no_eot;
1592                         break;
1593                 }
1594         }
1595
1596         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1597                 val = pkt_seq[i];
1598                 reg = dsi_pkt_seq_reg[i];
1599                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1600                         val |= pkt_seq_3_5_rgb_lo;
1601                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1602                         val |= pkt_seq_3_5_rgb_hi;
1603                 tegra_dsi_writel(dsi, val, reg);
1604         }
1605 }
1606
1607 static void tegra_dsi_reset_underflow_overflow
1608                                 (struct tegra_dc_dsi_data *dsi)
1609 {
1610         u32 val;
1611
1612         val = tegra_dsi_readl(dsi, DSI_STATUS);
1613         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1614         if (val) {
1615                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1616                         dev_warn(&dsi->dc->ndev->dev,
1617                                 "dsi: video fifo overflow. Resetting flag\n");
1618                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1619                         dev_warn(&dsi->dc->ndev->dev,
1620                                 "dsi: video fifo underflow. Resetting flag\n");
1621                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1622                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1623                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1624                 udelay(5);
1625         }
1626 }
1627
1628 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1629 {
1630         u32 trigger;
1631         u32 val;
1632         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1633         struct tegra_dc_mode mode = dsi->dc->mode;
1634         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1635                                 mode.v_active + mode.v_front_porch;
1636         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1637         u32 timeout_cnt = 0;
1638
1639 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1640 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1641
1642         val = tegra_dsi_readl(dsi, DSI_STATUS);
1643         while (!(val & DSI_STATUS_IDLE(0x1))) {
1644                 cpu_relax();
1645                 udelay(line_period);
1646                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1647                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1648                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1649                         break;
1650                 }
1651         }
1652
1653         tegra_dsi_writel(dsi,
1654                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1655                 DSI_POWER_CONTROL);
1656         /* stabilization delay */
1657         udelay(300);
1658
1659         tegra_dsi_writel(dsi,
1660                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1661                 DSI_POWER_CONTROL);
1662         /* stabilization delay */
1663         udelay(300);
1664
1665         /* dsi HW does not clear host trigger bit automatically
1666          * on dsi interface disable if host fifo is empty or in mid
1667          * of host transmission
1668          */
1669         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1670         if (trigger)
1671                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1672
1673 #undef DSI_IDLE_TIMEOUT
1674 }
1675
1676 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1677                                         struct tegra_dc_dsi_data *dsi)
1678 {
1679         tegra_dc_get(dc);
1680
1681         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1682         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1683         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1684         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1685
1686         tegra_dc_put(dc);
1687
1688         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1689 }
1690
1691 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1692  * whichever happens to occur first
1693  */
1694 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1695                                 struct tegra_dc_dsi_data *dsi,
1696                                 u32 timeout_n_frames)
1697 {
1698         long timeout;
1699         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1700         struct tegra_dc_mode mode = dc->mode;
1701         u32 line_period = DIV_ROUND_UP(
1702                                 MS_TO_US(frame_period),
1703                                 mode.v_sync_width + mode.v_back_porch +
1704                                 mode.v_active + mode.v_front_porch);
1705
1706         if (timeout_n_frames < 2)
1707                 dev_WARN(&dc->ndev->dev,
1708                 "dsi: to stop at next frame give at least 2 frame delay\n");
1709
1710         timeout = tegra_dc_wait_for_frame_end(dc, timeout_n_frames *
1711                 frame_period);
1712
1713         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1714         udelay(mode.v_ref_to_sync * line_period);
1715
1716         return timeout;
1717 }
1718
1719 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1720                                                 struct tegra_dc_dsi_data *dsi,
1721                                                 u32 timeout_n_frames)
1722 {
1723         tegra_dsi_stop_dc_stream(dc, dsi);
1724
1725         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1726
1727         tegra_dsi_soft_reset(dsi);
1728
1729         tegra_dsi_reset_underflow_overflow(dsi);
1730 }
1731
1732 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1733 {
1734         int err;
1735
1736         /* convert to spio */
1737         err = gpio_request(gpio, "temp_request");
1738         if (err < 0) {
1739                 dev_err(&dsi->dc->ndev->dev,
1740                         "dsi: %s: gpio request failed %d\n", __func__, err);
1741                 return;
1742         }
1743         gpio_free(gpio);
1744 }
1745
1746 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1747                                         struct tegra_dc_dsi_data *dsi)
1748 {
1749         u32 val;
1750
1751         tegra_dc_get(dc);
1752         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
1753
1754         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1755
1756         /* TODO: clean up */
1757         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1758                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1759                         DC_CMD_DISPLAY_POWER_CONTROL);
1760
1761         /* Configure one-shot mode or continuous mode */
1762         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1763                 /* disable LSPI/LCD_DE output */
1764                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1765                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1766
1767                 /* enable MSF & set MSF polarity */
1768                 val = MSF_ENABLE | MSF_LSPI;
1769                 if (!dsi->info.te_polarity_low)
1770                         val |= MSF_POLARITY_HIGH;
1771                 else
1772                         val |= MSF_POLARITY_LOW;
1773                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1774
1775                 /* set non-continuous mode */
1776                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1777                                                 DC_CMD_DISPLAY_COMMAND);
1778
1779                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1780                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1781
1782                 if (dsi->info.te_gpio)
1783                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1784         } else {
1785                 /* set continuous mode */
1786                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1787                                                 DC_CMD_DISPLAY_COMMAND);
1788                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1789                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1790         }
1791
1792         tegra_dc_put(dc);
1793
1794         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1795 }
1796
1797 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1798                                 struct tegra_dc_dsi_data *dsi)
1799 {
1800         u32 shift_clk_div_register;
1801         u32 val;
1802
1803         /* formula: (dsi->shift_clk_div - 1) * 2 */
1804         shift_clk_div_register = DIV_ROUND_CLOSEST(
1805                                 ((dsi->shift_clk_div.mul -
1806                                 dsi->shift_clk_div.div) * 2),
1807                                 dsi->shift_clk_div.div);
1808
1809         if (tegra_platform_is_fpga()) {
1810                 shift_clk_div_register = 1;
1811                 if (dsi->info.ganged_type)
1812                         shift_clk_div_register = 0;
1813         }
1814
1815         tegra_dc_get(dc);
1816
1817         val = PIXEL_CLK_DIVIDER_PCD1 |
1818                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1819
1820         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1821          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1822          * After 2us delay, write the target values to it. */
1823 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_11x_SOC)
1824         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1825         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1826         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1827
1828         udelay(2);
1829 #endif
1830
1831         /* TODO: find out if PCD3 option is required */
1832         val = PIXEL_CLK_DIVIDER_PCD1 |
1833                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1834
1835         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1836
1837         tegra_dc_put(dc);
1838 }
1839
1840 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1841                         struct tegra_dc_dsi_data *dsi, u32 clk)
1842 {
1843         u32 rm;
1844         u32 pclk_khz;
1845
1846         /* Round up to MHz */
1847         rm = clk % 1000;
1848         if (rm != 0)
1849                 clk -= rm;
1850
1851         /* Set up pixel clock */
1852         pclk_khz = (clk * dsi->shift_clk_div.div) /
1853                                 dsi->shift_clk_div.mul;
1854
1855         dc->mode.pclk = pclk_khz * 1000;
1856
1857         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1858         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1859
1860         /* TODO: Define one shot work delay in board file. */
1861         /* Since for one-shot mode, refresh rate is usually set larger than
1862          * expected refresh rate, it needs at least 3 frame period. Less
1863          * delay one shot work is, more powering saving we have. */
1864         dc->one_shot_delay_ms = 4 *
1865                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1866
1867         tegra_dsi_setup_clk(dc, dsi);
1868         tegra_dsi_reset_deassert(dsi);
1869
1870         dsi->current_dsi_clk_khz =
1871                         clk_get_rate(dsi->dsi_clk[0]) / 1000;
1872         dsi->current_bit_clk_ps =  DIV_ROUND_CLOSEST((1000 * 1000 * 1000),
1873                                         (dsi->current_dsi_clk_khz * 2));
1874 }
1875
1876 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1877 {
1878         u32 val;
1879
1880         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1881         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1882
1883         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1884                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1885                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1886         } else {
1887                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1888                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1889         }
1890         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1891
1892         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1893         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1894         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1895         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1896
1897         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1898 }
1899
1900 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1901 {
1902         u32 val;
1903         tegra_dsi_hs_clk_out_enable(dsi);
1904
1905         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1906         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1907         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1908         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1909 }
1910
1911 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1912                                                 struct tegra_dc_dsi_data *dsi)
1913 {
1914         u32 val;
1915
1916         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1917                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1918
1919         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1920         /* stabilization delay */
1921         udelay(300);
1922
1923         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1924         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1925         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1926         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1927
1928         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1929         /* stabilization delay */
1930         udelay(300);
1931
1932         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1933         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1934 }
1935
1936 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1937 {
1938         u32 dsi_control;
1939         u32 host_dsi_control;
1940         u32 max_threshold;
1941
1942         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1943         host_dsi_control = HOST_DSI_CTRL_COMMON |
1944                         HOST_DSI_CTRL_HOST_DRIVEN |
1945                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1946         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1947
1948         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1949         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1950         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1951
1952         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1953         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1954         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1955 }
1956
1957 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1958                                                 u8 driven_mode)
1959 {
1960         u32 dsi_control;
1961         u32 host_dsi_control;
1962         u32 max_threshold;
1963         u32 dcs_cmd;
1964
1965         dsi_control = dsi->dsi_control_val;
1966         host_dsi_control = HOST_DSI_CTRL_COMMON;
1967         max_threshold = 0;
1968         dcs_cmd = 0;
1969
1970         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1971                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1972                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1973                 max_threshold =
1974                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1975                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1976         } else {
1977                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1978                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1979                 max_threshold =
1980                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1981                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1982
1983                 if (dsi->info.video_data_type ==
1984                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1985                         dsi_control |= DSI_CTRL_CMD_MODE;
1986                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1987                                 DSI_WRITE_MEMORY_START)|
1988                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1989                                 DSI_WRITE_MEMORY_CONTINUE);
1990                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1991                 } else {
1992                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1993                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1994                 }
1995         }
1996
1997         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1998         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1999         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2000         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2001 }
2002
2003 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
2004 {
2005         u32 val;
2006
2007         if (dsi->info.controller_vs == DSI_VS_1) {
2008                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2009                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2010                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2011                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2012                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2013                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2014                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
2015                                                 (TEGRA_DSI_PAD_DISABLE) |
2016                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2017                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
2018                                                 (TEGRA_DSI_PAD_DISABLE);
2019                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2020         } else {
2021                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2022                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2023                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2024                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2025                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2026                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
2027                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
2028                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2029         }
2030 }
2031
2032 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
2033 {
2034         u32 val;
2035
2036         if (dsi->info.controller_vs == DSI_VS_1) {
2037                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2038                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2039                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2040                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2041                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2042                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2043                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2044                                                 TEGRA_DSI_PAD_ENABLE) |
2045                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2046                                                 TEGRA_DSI_PAD_ENABLE) |
2047                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2048                                                 TEGRA_DSI_PAD_ENABLE);
2049                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2050         } else {
2051                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2052                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2053                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2054                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2055                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2056                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2057                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2058                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2059         }
2060 }
2061
2062 static void __maybe_unused
2063 tegra_dsi_mipi_calibration_status(struct tegra_dc_dsi_data *dsi)
2064 {
2065         u32 val = 0;
2066         u32 timeout = 0;
2067         /* Start calibration */
2068         val = tegra_mipi_cal_read(dsi->mipi_cal,
2069                 MIPI_CAL_MIPI_CAL_CTRL_0);
2070         val |= (MIPI_CAL_STARTCAL(0x1));
2071         tegra_mipi_cal_write(dsi->mipi_cal, val,
2072                 MIPI_CAL_MIPI_CAL_CTRL_0);
2073
2074         for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2075                         timeout; timeout -= 100) {
2076                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2077                 MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2078                 if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2079                         (val & MIPI_AUTO_CAL_DONE(0x1))) {
2080                                 dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2081                                 break;
2082                 }
2083                 usleep_range(10, 100);
2084         }
2085         if (timeout <= 0)
2086                 dev_info(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2087 }
2088
2089 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
2090 static void tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
2091 {
2092         u32 val;
2093         struct clk *clk72mhz = NULL;
2094
2095         clk72mhz = clk_get_sys("clk72mhz", NULL);
2096         if (IS_ERR_OR_NULL(clk72mhz)) {
2097                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2098                 return;
2099         }
2100         clk_prepare_enable(clk72mhz);
2101
2102         /* Calibration settings begin */
2103         val = tegra_mipi_cal_read(dsi->mipi_cal,
2104                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2105         val &= ~PAD_DRIV_UP_REF(0x7);
2106         val |= PAD_DRIV_UP_REF(0x3);
2107         tegra_mipi_cal_write(dsi->mipi_cal, val,
2108                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2109         /*Bug 1445912: override tap delay for panel-a-1200-1920-7-0 */
2110         if (dsi->info.boardinfo.platform_boardid == BOARD_P1761 &&
2111                 dsi->info.boardinfo.display_boardversion == 1) {
2112                 val = (DSI_PAD_OUTADJ3(0x4) | DSI_PAD_OUTADJ2(0x4) |
2113                    DSI_PAD_OUTADJ1(0x4) | DSI_PAD_OUTADJ0(0x4));
2114                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_1_VS1);
2115         }
2116
2117         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2118                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2119                 DSI_PAD_OUTADJCLK(0x0));
2120         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2121
2122         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2123         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2124                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2125         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2126
2127         /* Calibrate DSI 0 */
2128         if (dsi->info.ganged_type ||
2129                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2130                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2131                         MIPI_CAL_SELDSIA(0x1) |
2132                         MIPI_CAL_HSPDOSDSIA(0x0) |
2133                         MIPI_CAL_HSPUOSDSIA(0x0) |
2134                         MIPI_CAL_TERMOSDSIA(0x0);
2135                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2136                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2137                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2138                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2139
2140                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2141                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2142                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2143                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2144                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2145                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2146                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2147
2148                 /* Deselect PAD C */
2149                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2150                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2151                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2152                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2153                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2154
2155                 /* Deselect PAD D */
2156                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2157                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2158                 val &= ~(MIPI_CAL_SELDSID(0x1));
2159                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2160                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2161
2162                 val = MIPI_CAL_NOISE_FLT(0xa) |
2163                           MIPI_CAL_PRESCALE(0x2) |
2164                           MIPI_CAL_CLKEN_OVR(0x1) |
2165                           MIPI_CAL_AUTOCAL_EN(0x0);
2166                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2167                         MIPI_CAL_MIPI_CAL_CTRL_0);
2168
2169                 tegra_dsi_mipi_calibration_status(dsi);
2170         }
2171         /* Calibrate DSI 1 */
2172         if (dsi->info.ganged_type ||
2173                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2174                 val = MIPI_CAL_OVERIDEC(0x0) |
2175                         MIPI_CAL_SELC(0x1) |
2176                         MIPI_CAL_HSPDOSC(0x0) |
2177                         MIPI_CAL_HSPUOSC(0x0) |
2178                         MIPI_CAL_TERMOSC(0x0);
2179                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2180                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2181                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2182                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2183
2184                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2185                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2186                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2187                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2188                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2189                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2190                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2191
2192                 /* Deselect PAD A */
2193                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2194                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2195                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2196                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2197                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2198
2199                 /* Deselect PAD B */
2200                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2201                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2202                 val &= ~(MIPI_CAL_SELDSID(0x1));
2203                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2204                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2205
2206                 val = MIPI_CAL_NOISE_FLT(0xa) |
2207                           MIPI_CAL_PRESCALE(0x2) |
2208                           MIPI_CAL_CLKEN_OVR(0x1) |
2209                           MIPI_CAL_AUTOCAL_EN(0x0);
2210                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2211                         MIPI_CAL_MIPI_CAL_CTRL_0);
2212
2213                 tegra_dsi_mipi_calibration_status(dsi);
2214         }
2215
2216         clk_disable_unprepare(clk72mhz);
2217 }
2218 #endif
2219
2220 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2221 void tegra_dsi_mipi_calibration_14x(struct tegra_dc_dsi_data *dsi)
2222 {
2223         u32 val;
2224         struct clk *clk72mhz = NULL;
2225
2226         clk72mhz = clk_get_sys("clk72mhz", NULL);
2227         if (IS_ERR_OR_NULL(clk72mhz)) {
2228                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2229                 return;
2230         }
2231         clk_prepare_enable(clk72mhz);
2232
2233         tegra_mipi_cal_write(dsi->mipi_cal,
2234                         PAD_DRIV_DN_REF(0x2),
2235                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2236
2237         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2238                      DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1));
2239         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2240
2241         val = (DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2242         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2243
2244         val = MIPI_CAL_HSCLKPDOSDSIA(0x2) |
2245                 MIPI_CAL_HSCLKPUOSDSIA(0x2);
2246         tegra_mipi_cal_write(dsi->mipi_cal, val,
2247                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2248         tegra_mipi_cal_write(dsi->mipi_cal, val,
2249                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2250
2251         val = MIPI_CAL_OVERIDEDSIA(0x0) |
2252                 MIPI_CAL_SELDSIA(0x1) |
2253                 MIPI_CAL_HSPDOSDSIA(0x0) |
2254                 MIPI_CAL_HSPUOSDSIA(0x0) |
2255                 MIPI_CAL_TERMOSDSIA(0x0);
2256         tegra_mipi_cal_write(dsi->mipi_cal, val,
2257                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2258         tegra_mipi_cal_write(dsi->mipi_cal, val,
2259                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2260
2261         val = MIPI_CAL_NOISE_FLT(0xa) |
2262                   MIPI_CAL_PRESCALE(0x2) |
2263                   MIPI_CAL_CLKEN_OVR(0x1) |
2264                   MIPI_CAL_AUTOCAL_EN(0x0);
2265         tegra_mipi_cal_write(dsi->mipi_cal, val,
2266                 MIPI_CAL_MIPI_CAL_CTRL_0);
2267
2268         tegra_dsi_mipi_calibration_status(dsi);
2269
2270         clk_disable_unprepare(clk72mhz);
2271 }
2272 #endif
2273
2274 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2275 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2276 {
2277         u32 val;
2278         /* Calibration settings begin */
2279         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2280                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2281                 DSI_PAD_OUTADJCLK(0x0));
2282         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2283
2284         /* Calibrate DSI 0 */
2285         if (dsi->info.ganged_type ||
2286                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2287                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2288                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2289                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2290                         MIPI_CAL_SELDSIA(0x1) |
2291                         MIPI_CAL_HSPDOSDSIA(0x0) |
2292                         MIPI_CAL_HSPUOSDSIA(0x4) |
2293                         MIPI_CAL_TERMOSDSIA(0x5);
2294                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2295                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2296                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2297                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2298
2299                 /* Deselect PAD C */
2300                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2301                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2302                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2303                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2304                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2305
2306                 /* Deselect PAD D */
2307                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2308                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2309                 val &= ~(MIPI_CAL_SELDSID(0x1));
2310                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2311                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2312
2313                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2314                         MIPI_CAL_MIPI_CAL_CTRL_0);
2315                 val = MIPI_CAL_NOISE_FLT(0xa) |
2316                           MIPI_CAL_PRESCALE(0x2) |
2317                           MIPI_CAL_CLKEN_OVR(0x1) |
2318                           MIPI_CAL_AUTOCAL_EN(0x0);
2319                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2320                         MIPI_CAL_MIPI_CAL_CTRL_0);
2321
2322                 tegra_dsi_mipi_calibration_status(dsi);
2323         }
2324
2325         /* Calibrate DSI 1 */
2326         if (dsi->info.ganged_type ||
2327                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2328                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2329                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2330                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2331                         MIPI_CAL_SELDSIC(0x1) |
2332                         MIPI_CAL_HSPDOSDSIC(0x0) |
2333                         MIPI_CAL_HSPUOSDSIC(0x4) |
2334                         MIPI_CAL_TERMOSDSIC(0x5);
2335                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2336                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2337                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2338                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2339
2340                 /* Deselect PAD A */
2341                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2342                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2343                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2344                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2345                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2346
2347                 /* Deselect PAD B */
2348                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2349                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2350                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2351                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2352                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2353
2354                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2355                         MIPI_CAL_MIPI_CAL_CTRL_0);
2356                 val = MIPI_CAL_NOISE_FLT(0xa) |
2357                           MIPI_CAL_PRESCALE(0x2) |
2358                           MIPI_CAL_CLKEN_OVR(0x1) |
2359                           MIPI_CAL_AUTOCAL_EN(0x0);
2360                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2361                         MIPI_CAL_MIPI_CAL_CTRL_0);
2362
2363                 tegra_dsi_mipi_calibration_status(dsi);
2364         }
2365 }
2366 #endif
2367 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2368 {
2369         if (!dsi->ulpm)
2370                 tegra_dsi_pad_enable(dsi);
2371         else
2372                 tegra_dsi_pad_disable(dsi);
2373
2374         if (dsi->info.controller_vs == DSI_VS_1) {
2375
2376                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2377
2378                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2379
2380                 tegra_mipi_cal_write(dsi->mipi_cal,
2381                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2382                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2383                 tegra_mipi_cal_write(dsi->mipi_cal,
2384                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2385                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2386 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2387                 tegra_dsi_mipi_calibration_11x(dsi);
2388 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
2389                 tegra_dsi_mipi_calibration_14x(dsi);
2390 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2391                 tegra_dsi_mipi_calibration_12x(dsi);
2392 #endif
2393                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2394         } else {
2395 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2396                 u32 val = 0;
2397
2398                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2399                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2400                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2401                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2402                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2403                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2404
2405                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2406                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2407                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2408                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2409                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2410
2411                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2412
2413                 val = MIPI_CAL_TERMOSA(0x4);
2414                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2415
2416                 val = MIPI_CAL_TERMOSB(0x4);
2417                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2418
2419                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2420                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2421
2422                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2423                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2424
2425                 val = PAD_CIL_PDVREG(0x0);
2426                 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2427 #endif
2428         }
2429 }
2430
2431 static void tegra_dsi_panelB_enable(void)
2432 {
2433         unsigned int val;
2434
2435         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2436         val |= DSIB_MODE_ENABLE;
2437         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2438 }
2439
2440 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2441                                 struct tegra_dc_dsi_data *dsi)
2442 {
2443         u32 i;
2444         int err = 0;
2445
2446         if (dsi->avdd_dsi_csi)
2447                 err = regulator_enable(dsi->avdd_dsi_csi);
2448         if (WARN(err, "unable to enable regulator"))
2449                 return err;
2450         /* stablization delay */
2451         mdelay(50);
2452         /* Enable DSI clocks */
2453         tegra_dsi_clk_enable(dsi);
2454         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2455
2456         /* Stop DC stream before configuring DSI registers
2457          * to avoid visible glitches on panel during transition
2458          * from bootloader to kernel driver
2459          */
2460         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2461
2462         tegra_dsi_writel(dsi,
2463                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2464                 DSI_POWER_CONTROL);
2465         /* stabilization delay */
2466         udelay(300);
2467
2468         if (dsi->info.dsi_instance || dsi->info.ganged_type)
2469                 tegra_dsi_panelB_enable();
2470
2471         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2472
2473         /* Initialize DSI registers */
2474         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2475                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2476         if (dsi->info.controller_vs == DSI_VS_1) {
2477                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2478                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2479         }
2480
2481         tegra_dsi_pad_calibration(dsi);
2482
2483         tegra_dsi_writel(dsi,
2484                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2485                 DSI_POWER_CONTROL);
2486         /* stabilization delay */
2487         udelay(300);
2488
2489         dsi->status.init = DSI_MODULE_INIT;
2490         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2491         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2492         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2493         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2494         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2495         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2496         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2497         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2498
2499         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
2500                 tegra_dsi_syncpt_reset(dsi);
2501
2502         return 0;
2503 }
2504
2505 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2506                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2507 {
2508         int err;
2509
2510         if (dsi->status.init != DSI_MODULE_INIT) {
2511                 err = -EPERM;
2512                 goto fail;
2513         }
2514
2515         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2516                         dsi->status.lp_op == lp_op)
2517                 goto success;
2518
2519         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2520                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2521
2522         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2523         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2524                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2525                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2526
2527         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2528         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2529                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2530                 tegra_dsi_set_timeout(dsi);
2531         }
2532
2533         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2534
2535         tegra_dsi_set_control_reg_lp(dsi);
2536
2537         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2538                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2539                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2540
2541         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2542         dsi->status.lp_op = lp_op;
2543         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2544 success:
2545         err = 0;
2546 fail:
2547         return err;
2548 }
2549
2550 static void tegra_dsi_ganged(struct tegra_dc *dc,
2551                                 struct tegra_dc_dsi_data *dsi)
2552 {
2553         u32 low_width = 0;
2554         u32 high_width = 0;
2555         u32 h_active = dc->out->modes->h_active;
2556         u32 val = 0;
2557
2558         if (dsi->info.controller_vs < DSI_VS_1) {
2559                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2560                 "supported with current controller version\n");
2561                 return;
2562         }
2563
2564         if (dsi->info.ganged_type ==
2565                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2566                 /* DSI 0 */
2567                 tegra_dsi_controller_writel(dsi,
2568                         DSI_GANGED_MODE_START_POINTER(0),
2569                         DSI_GANGED_MODE_START, DSI_INSTANCE_0);
2570                 /* DSI 1 */
2571                 tegra_dsi_controller_writel(dsi,
2572                         DSI_GANGED_MODE_START_POINTER(h_active / 2),
2573                         DSI_GANGED_MODE_START, DSI_INSTANCE_1);
2574
2575                 low_width = DIV_ROUND_UP(h_active, 2);
2576                 high_width = h_active - low_width;
2577                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2578                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2579
2580         } else if (dsi->info.ganged_type ==
2581                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2582                 /* DSI 0 */
2583                 tegra_dsi_controller_writel(dsi,
2584                         DSI_GANGED_MODE_START_POINTER(0),
2585                         DSI_GANGED_MODE_START, DSI_INSTANCE_0);
2586                 /* DSI 1 */
2587                 tegra_dsi_controller_writel(dsi,
2588                         DSI_GANGED_MODE_START_POINTER(1),
2589                         DSI_GANGED_MODE_START, DSI_INSTANCE_1);
2590
2591                 low_width = 0x1;
2592                 high_width = 0x1;
2593                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2594                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2595         }
2596
2597         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2598
2599         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2600                                                 DSI_GANGED_MODE_CONTROL);
2601 }
2602
2603 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2604                                         struct tegra_dc_dsi_data *dsi,
2605                                         u8 driven_mode)
2606 {
2607         int err;
2608
2609         if (dsi->status.init != DSI_MODULE_INIT) {
2610                 err = -EPERM;
2611                 goto fail;
2612         }
2613
2614         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2615                 dsi->driven_mode == driven_mode)
2616                 goto success;
2617
2618         dsi->driven_mode = driven_mode;
2619
2620         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2621                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2622
2623         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2624                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2625                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2626
2627         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2628                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2629                 tegra_dsi_set_timeout(dsi);
2630         }
2631
2632         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2633
2634         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2635                 tegra_dsi_set_pkt_seq(dc, dsi);
2636                 tegra_dsi_set_pkt_length(dc, dsi);
2637                 tegra_dsi_set_sol_delay(dc, dsi);
2638                 tegra_dsi_set_dc_clk(dc, dsi);
2639         }
2640
2641         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2642
2643         if (dsi->info.ganged_type)
2644                 tegra_dsi_ganged(dc, dsi);
2645
2646         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2647                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2648                 tegra_dsi_hs_clk_out_enable(dsi);
2649
2650         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2651 success:
2652         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2653         err = 0;
2654 fail:
2655         return err;
2656 }
2657
2658 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2659 {
2660         u32 timeout = 0;
2661         bool retVal = true;
2662
2663         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2664                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2665                         tegra_dsi_controller_readl(dsi,
2666                                         DSI_TRIGGER, link_id))) {
2667                         retVal = false;
2668                         break;
2669                 }
2670                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2671                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2672         }
2673
2674         return retVal;
2675 }
2676
2677 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2678 {
2679         u32 timeout = 0;
2680         bool retVal = true;
2681
2682         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2683                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2684                         tegra_dsi_controller_readl(dsi,
2685                                         DSI_HOST_DSI_CONTROL, link_id))) {
2686                         retVal = false;
2687                         break;
2688                 }
2689                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2690                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2691         }
2692
2693         return retVal;
2694 }
2695
2696 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2697 {
2698         int err = 0;
2699
2700         if (tegra_dsi_write_busy(dsi, link_id)) {
2701                 err = -EBUSY;
2702                 dev_err(&dsi->dc->ndev->dev,
2703                         "DSI trigger bit already set\n");
2704                 goto fail;
2705         }
2706
2707         if (tegra_dsi_read_busy(dsi, link_id)) {
2708                 err = -EBUSY;
2709                 dev_err(&dsi->dc->ndev->dev,
2710                         "DSI immediate bta bit already set\n");
2711                 goto fail;
2712         }
2713 fail:
2714         return (err < 0 ? true : false);
2715 }
2716
2717 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2718 {
2719         u32 val;
2720
2721         val = tegra_dsi_readl(dsi, DSI_STATUS);
2722         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2723         if (val) {
2724                 dev_warn(&dsi->dc->ndev->dev,
2725                         "DSI read count not zero, resetting\n");
2726                 tegra_dsi_soft_reset(dsi);
2727         }
2728 }
2729
2730 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2731                                                 struct tegra_dc_dsi_data *dsi,
2732                                                 struct tegra_dc *dc,
2733                                                 u8 lp_op)
2734 {
2735         struct dsi_status *init_status = NULL;
2736         int err;
2737
2738         if (dsi->status.init != DSI_MODULE_INIT ||
2739                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2740                 err = -EPERM;
2741                 goto fail;
2742         }
2743
2744         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2745         if (!init_status)
2746                 return ERR_PTR(-ENOMEM);
2747
2748         *init_status = dsi->status;
2749
2750         if (dsi->info.hs_cmd_mode_supported) {
2751                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2752                                 TEGRA_DSI_DRIVEN_BY_HOST);
2753                 if (err < 0) {
2754                         dev_err(&dc->ndev->dev,
2755                         "Switch to HS host mode failed\n");
2756                         goto fail;
2757                 }
2758
2759                 goto success;
2760         }
2761
2762         if (dsi->status.lp_op != lp_op) {
2763                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2764                 if (err < 0) {
2765                         dev_err(&dc->ndev->dev,
2766                         "DSI failed to go to LP mode\n");
2767                         goto fail;
2768                 }
2769         }
2770 success:
2771         return init_status;
2772 fail:
2773         kfree(init_status);
2774         return ERR_PTR(err);
2775 }
2776
2777 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2778                                 struct tegra_dc *dc,
2779                                 struct tegra_dc_dsi_data *dsi,
2780                                 u8 lp_op)
2781 {
2782         int i = 0;
2783         int err = 0;
2784         struct dsi_status *init_status;
2785         bool restart_dc_stream = false;
2786
2787         if (dsi->status.init != DSI_MODULE_INIT ||
2788                 dsi->ulpm) {
2789                 err = -EPERM;
2790                 goto fail;
2791         }
2792
2793         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2794                 restart_dc_stream = true;
2795                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2796         }
2797
2798         for (i = 0; i < dsi->max_instances; i++) {
2799                 if (tegra_dsi_host_busy(dsi, i)) {
2800                         tegra_dsi_soft_reset(dsi);
2801                         if (tegra_dsi_host_busy(dsi, i)) {
2802                                 err = -EBUSY;
2803                                 dev_err(&dc->ndev->dev, "DSI host busy\n");
2804                                 goto fail;
2805                         }
2806                 }
2807         }
2808
2809         if (lp_op == DSI_LP_OP_READ)
2810                 tegra_dsi_reset_read_count(dsi);
2811
2812         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2813                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2814                 if (err < 0) {
2815                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2816                         goto fail;
2817                 }
2818         }
2819
2820         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2821                                         (dsi, dc, lp_op);
2822         if (IS_ERR_OR_NULL(init_status)) {
2823                 err = PTR_ERR(init_status);
2824                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2825                 goto fail;
2826         }
2827
2828         if (restart_dc_stream)
2829                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2830
2831         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
2832                 if (atomic_read(&dsi_syncpt_rst))
2833                         tegra_dsi_syncpt_reset(dsi);
2834
2835         return init_status;
2836 fail:
2837         return ERR_PTR(err);
2838 }
2839
2840 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2841                                 struct tegra_dc_dsi_data *dsi,
2842                                 struct dsi_status *init_status)
2843 {
2844         int err = 0;
2845
2846         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2847                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2848                 if (err < 0) {
2849                         dev_err(&dc->ndev->dev,
2850                                 "Failed to config LP mode\n");
2851                         goto fail;
2852                 }
2853                 goto success;
2854         }
2855
2856         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2857                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2858                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2859                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2860                 if (err < 0) {
2861                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2862                         goto fail;
2863                 }
2864         }
2865
2866         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2867                 tegra_dsi_start_dc_stream(dc, dsi);
2868 success:
2869 fail:
2870         kfree(init_status);
2871         return err;
2872 }
2873
2874 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi, u8 link_id)
2875 {
2876         int status = 0;
2877
2878         if (tegra_dsi_controller_readl(dsi, DSI_TRIGGER, link_id)) {
2879                 status = -EBUSY;
2880                 goto fail;
2881         }
2882
2883         tegra_dsi_controller_writel(dsi,
2884                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
2885                                 DSI_TRIGGER, link_id);
2886
2887         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
2888                 status = tegra_dsi_syncpt(dsi, link_id);
2889                 if (status < 0) {
2890                         dev_err(&dsi->dc->ndev->dev,
2891                                 "DSI syncpt for host trigger failed\n");
2892                         goto fail;
2893                 }
2894         } else {
2895                 if (tegra_dsi_write_busy(dsi, link_id)) {
2896                         status = -EBUSY;
2897                         dev_err(&dsi->dc->ndev->dev,
2898                                 "Timeout waiting on write completion\n");
2899                 }
2900         }
2901
2902 fail:
2903         return status;
2904 }
2905
2906 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2907                                         struct tegra_dsi_cmd *cmd)
2908 {
2909         u8 virtual_channel;
2910         u32 val;
2911         int err;
2912         u8 *pdata = cmd->pdata;
2913         u8 data_id = cmd->data_id;
2914         u16 data_len = cmd->sp_len_dly.data_len;
2915
2916         err = 0;
2917
2918         if (!dsi->info.ganged_type && cmd->link_id == TEGRA_DSI_LINK1) {
2919                 dev_err(&dsi->dc->ndev->dev, "DSI invalid command\n");
2920                 return -EINVAL;
2921         }
2922
2923         virtual_channel = dsi->info.virtual_channel <<
2924                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2925
2926         /* always use hw for ecc */
2927         val = (virtual_channel | data_id) << 0 |
2928                         data_len << 8;
2929         tegra_dsi_controller_writel(dsi, val, DSI_WR_DATA, cmd->link_id);
2930
2931         /* if pdata != NULL, pkt type is long pkt */
2932         if (pdata != NULL) {
2933                 while (data_len) {
2934                         if (data_len >= 4) {
2935                                 val = ((u32 *) pdata)[0];
2936                                 data_len -= 4;
2937                                 pdata += 4;
2938                         } else {
2939                                 val = 0;
2940                                 memcpy(&val, pdata, data_len);
2941                                 pdata += data_len;
2942                                 data_len = 0;
2943                         }
2944                         tegra_dsi_controller_writel(dsi, val,
2945                                 DSI_WR_DATA, cmd->link_id);
2946                 }
2947         }
2948
2949         if (cmd->cmd_type != TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
2950                 err = tegra_dsi_host_trigger(dsi, cmd->link_id);
2951                 if (err < 0)
2952                         dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2953         }
2954
2955         return err;
2956 }
2957
2958 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2959 {
2960         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2961
2962         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2963                 atomic_inc(&dsi->host_ref);
2964                 tegra_dsi_host_resume(dc);
2965         }
2966 }
2967
2968 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2969 {
2970         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2971
2972         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2973                 atomic_dec(&dsi->host_ref);
2974
2975                 if (!atomic_read(&dsi->host_ref) &&
2976                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2977                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2978         }
2979 }
2980
2981 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2982 {
2983         struct tegra_dc_dsi_data *dsi = container_of(
2984                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2985
2986         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2987                 tegra_dsi_host_suspend(dsi->dc);
2988 }
2989
2990 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2991                         struct tegra_dc_dsi_data *dsi,
2992                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
2993 {
2994         int err = 0;
2995         struct dsi_status *init_status;
2996
2997         init_status = tegra_dsi_prepare_host_transmission(
2998                                 dc, dsi, DSI_LP_OP_WRITE);
2999         if (IS_ERR_OR_NULL(init_status)) {
3000                 err = PTR_ERR(init_status);
3001                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3002                 goto fail;
3003         }
3004
3005         err = _tegra_dsi_write_data(dsi, cmd);
3006         mdelay(delay_ms);
3007 fail:
3008         err = tegra_dsi_restore_state(dc, dsi, init_status);
3009         if (err < 0)
3010                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3011
3012         return err;
3013 }
3014
3015 int tegra_dsi_write_data(struct tegra_dc *dc,
3016                         struct tegra_dc_dsi_data *dsi,
3017                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3018 {
3019         int err;
3020
3021         tegra_dc_io_start(dc);
3022         tegra_dc_dsi_hold_host(dc);
3023
3024         err = tegra_dsi_write_data_nosync(dc, dsi, cmd, delay_ms);
3025
3026         tegra_dc_dsi_release_host(dc);
3027         tegra_dc_io_end(dc);
3028
3029         return err;
3030 }
3031
3032 EXPORT_SYMBOL(tegra_dsi_write_data);
3033
3034 int tegra_dsi_start_host_cmd_v_blank_video(struct tegra_dc_dsi_data *dsi,
3035         struct tegra_dsi_cmd *cmd)
3036 {
3037         struct tegra_dc *dc = dsi->dc;
3038         int err = 0;
3039         u32 val;
3040
3041         if (!dsi->enabled) {
3042                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3043                 return -EINVAL;
3044         }
3045
3046         tegra_dc_io_start(dc);
3047         tegra_dc_dsi_hold_host(dc);
3048         val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3049         tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3050         _tegra_dsi_write_data(dsi, cmd);
3051         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3052                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3053                                 TEGRA_DSI_DRIVEN_BY_DC);
3054                 if (err < 0) {
3055                         dev_err(&dc->ndev->dev,
3056                                 "dsi: not able to set to hs mode\n");
3057                         goto fail;
3058                 }
3059         }
3060         tegra_dsi_start_dc_stream(dc, dsi);
3061         tegra_dsi_wait_frame_end(dc, dsi, 2);
3062  fail:
3063         tegra_dc_dsi_release_host(dc);
3064         tegra_dc_io_end(dc);
3065
3066         return err;
3067 }
3068 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_video);
3069
3070 int tegra_dsi_end_host_cmd_v_blank_video(struct tegra_dc *dc,
3071                                         struct tegra_dc_dsi_data *dsi)
3072 {
3073         if (!dsi->enabled) {
3074                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3075                 return -EINVAL;
3076         }
3077
3078         tegra_dc_io_start(dc);
3079         tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3080         tegra_dc_io_end(dc);
3081
3082         return 0;
3083 }
3084 EXPORT_SYMBOL(tegra_dsi_end_host_cmd_v_blank_video);
3085
3086 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3087                                         struct tegra_dc_dsi_data *dsi,
3088                                         struct tegra_dsi_cmd *cmd,
3089                                         u32 n_cmd)
3090 {
3091 #define DEFAULT_DELAY_MS 1
3092         u32 i;
3093         int err;
3094         u8 delay_ms;
3095
3096         err = 0;
3097         for (i = 0; i < n_cmd; i++) {
3098                 struct tegra_dsi_cmd *cur_cmd;
3099                 cur_cmd = &cmd[i];
3100
3101                 /*
3102                  * Some Panels need reset midway in the command sequence.
3103                  */
3104                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
3105                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
3106                                        cur_cmd->data_id);
3107                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
3108                         mdelay(cur_cmd->sp_len_dly.delay_ms);
3109                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
3110                                 tegra_dsi_send_dc_frames(dc,
3111                                                 dsi,
3112                                                 cur_cmd->sp_len_dly.frame_cnt);
3113                 } else if (cur_cmd->cmd_type ==
3114                                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3115                         tegra_dsi_start_host_cmd_v_blank_video(dsi, cur_cmd);
3116                         tegra_dsi_end_host_cmd_v_blank_video(dc, dsi);
3117                 } else {
3118                         delay_ms = DEFAULT_DELAY_MS;
3119                         if ((i + 1 < n_cmd) &&
3120                                 (cmd[i + 1].cmd_type == TEGRA_DSI_DELAY_MS)) {
3121                                 delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
3122                                 i++;
3123                         }
3124                         err = tegra_dsi_write_data_nosync(dc, dsi,
3125                                                         cur_cmd, delay_ms);
3126                         if (err < 0)
3127                                 break;
3128                 }
3129         }
3130         return err;
3131 #undef DEFAULT_DELAY_MS
3132 }
3133
3134 static u8 tegra_dsi_ecc(u32 header)
3135 {
3136         char ecc_parity[24] = {
3137                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
3138                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
3139                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
3140         };
3141         u8 ecc_byte;
3142         int i;
3143
3144         ecc_byte = 0;
3145         for (i = 0; i < 24; i++)
3146                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
3147
3148         return ecc_byte;
3149 }
3150
3151 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
3152 {
3153         u16 byte_cnt;
3154         u8 bit_cnt;
3155         char curr_byte;
3156         u16 crc = 0xFFFF;
3157         u16 poly = 0x8408;
3158
3159         if (data_len > 0) {
3160                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
3161                         curr_byte = pdata[byte_cnt];
3162                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
3163                                 if (((crc & 0x0001 ) ^
3164                                         (curr_byte & 0x0001)) > 0)
3165                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
3166                                 else
3167                                         crc = (crc >> 1) & 0x7FFF;
3168
3169                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
3170                         }
3171                 }
3172         }
3173         return crc;
3174 }
3175
3176 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
3177                                                 struct tegra_dsi_cmd *cmd)
3178 {
3179         u8 virtual_channel;
3180         u32 val;
3181         u16 data_len = cmd->sp_len_dly.data_len;
3182         u8 seq_ctrl_reg = 0;
3183
3184         virtual_channel = dsi->info.virtual_channel <<
3185                                 DSI_VIR_CHANNEL_BIT_POSITION;
3186
3187         val = (virtual_channel | cmd->data_id) << 0 |
3188                 data_len << 8;
3189
3190         val |= tegra_dsi_ecc(val) << 24;
3191
3192         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
3193
3194         /* if pdata != NULL, pkt type is long pkt */
3195         if (cmd->pdata != NULL) {
3196                 u8 *pdata;
3197                 u8 *pdata_mem;
3198                 /* allocate memory for pdata + 2 bytes checksum */
3199                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
3200                 if (!pdata_mem) {
3201                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
3202                         tegra_dsi_soft_reset(dsi);
3203                         return -ENOMEM;
3204                 }
3205
3206                 memcpy(pdata_mem, cmd->pdata, data_len);
3207                 pdata = pdata_mem;
3208                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
3209
3210                 /* data_len = length of pdata + 2 byte checksum */
3211                 data_len += 2;
3212
3213                 while (data_len) {
3214                         if (data_len >= 4) {
3215                                 val = ((u32 *) pdata)[0];
3216                                 data_len -= 4;
3217                                 pdata += 4;
3218                         } else {
3219                                 val = 0;
3220                                 memcpy(&val, pdata, data_len);
3221                                 pdata += data_len;
3222                                 data_len = 0;
3223                         }
3224                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
3225                                                         seq_ctrl_reg++);
3226                 }
3227                 kfree(pdata_mem);
3228         }
3229
3230         return 0;
3231 }
3232
3233 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
3234                                                 struct tegra_dsi_cmd *cmd)
3235 {
3236 #define PKT_HEADER_LEN_BYTE     4
3237 #define CHECKSUM_LEN_BYTE       2
3238
3239         int err = 0;
3240         u32 val;
3241         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
3242         struct tegra_dc *dc = dsi->dc;
3243
3244         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
3245                 return -EINVAL;
3246
3247         mutex_lock(&dsi->lock);
3248         tegra_dc_io_start(dc);
3249         tegra_dc_dsi_hold_host(dc);
3250
3251 #if DSI_USE_SYNC_POINTS
3252         atomic_set(&dsi_syncpt_rst, 1);
3253 #endif
3254
3255         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
3256         if (err < 0) {
3257                 dev_err(&dsi->dc->ndev->dev,
3258                         "dsi: dcs pkt seq ctrl init failed\n");
3259                 goto fail;
3260         }
3261
3262         if (cmd->pdata) {
3263                 u16 data_len = cmd->sp_len_dly.data_len;
3264                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
3265         }
3266
3267         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
3268                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
3269                                                 TEGRA_DSI_ENABLE);
3270         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
3271
3272 fail:
3273         tegra_dc_dsi_release_host(dc);
3274         tegra_dc_io_end(dc);
3275         mutex_unlock(&dsi->lock);
3276         return err;
3277
3278 #undef PKT_HEADER_LEN_BYTE
3279 #undef CHECKSUM_LEN_BYTE
3280 }
3281 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
3282
3283 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi)
3284 {
3285         struct tegra_dc *dc = dsi->dc;
3286         u32 cnt;
3287
3288         mutex_lock(&dsi->lock);
3289         tegra_dc_io_start(dc);
3290         tegra_dc_dsi_hold_host(dc);
3291
3292         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3293                 if (atomic_read(&dsi_syncpt_rst)) {
3294                         tegra_dsi_wait_frame_end(dc, dsi, 2);
3295                         tegra_dsi_syncpt_reset(dsi);
3296                         atomic_set(&dsi_syncpt_rst, 0);
3297                 }
3298
3299         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
3300
3301         /* clear seq data registers */
3302         for (cnt = 0; cnt < 8; cnt++)
3303                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
3304
3305         tegra_dc_dsi_release_host(dc);
3306         tegra_dc_io_end(dc);
3307
3308         mutex_unlock(&dsi->lock);
3309 }
3310 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
3311
3312 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3313 {
3314         u32 val;
3315         int err = 0;
3316
3317         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3318         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
3319         tegra_dsi_controller_writel(dsi, val,
3320                                 DSI_HOST_DSI_CONTROL, TEGRA_DSI_LINK0);
3321
3322         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3323                 err = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3324                 if (err < 0) {
3325                         dev_err(&dsi->dc->ndev->dev,
3326                                 "DSI syncpt for bta failed\n");
3327                 }
3328         } else {
3329                 if (tegra_dsi_read_busy(dsi, TEGRA_DSI_LINK0)) {
3330                         err = -EBUSY;
3331                         dev_err(&dsi->dc->ndev->dev,
3332                                 "Timeout wating on read completion\n");
3333                 }
3334         }
3335
3336         return err;
3337 }
3338
3339 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
3340                                         u32 rd_fifo_cnt, u8 *read_fifo)
3341 {
3342         int err;
3343         u32 payload_size;
3344
3345         payload_size = 0;
3346         err = 0;
3347
3348         switch (read_fifo[0]) {
3349         case DSI_ESCAPE_CMD:
3350                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
3351                 break;
3352         case DSI_ACK_NO_ERR:
3353                 dev_info(&dc->ndev->dev,
3354                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
3355                 return err;
3356         default:
3357                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3358                 break;
3359         }
3360
3361         switch (read_fifo[4] & 0xff) {
3362         case GEN_LONG_RD_RES:
3363                 /* Fall through */
3364         case DCS_LONG_RD_RES:
3365                 payload_size = (read_fifo[5] |
3366                                 (read_fifo[6] << 8)) & 0xFFFF;
3367                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3368                                 "payload_size[0x%x]\n", payload_size);
3369                 break;
3370         case GEN_1_BYTE_SHORT_RD_RES:
3371                 /* Fall through */
3372         case DCS_1_BYTE_SHORT_RD_RES:
3373                 payload_size = 1;
3374                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3375                         "payload_size[0x%x]\n", payload_size);
3376                 break;
3377         case GEN_2_BYTE_SHORT_RD_RES:
3378                 /* Fall through */
3379         case DCS_2_BYTE_SHORT_RD_RES:
3380                 payload_size = 2;
3381                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3382                         "payload_size[0x%x]\n", payload_size);
3383                 break;
3384         case ACK_ERR_RES:
3385                 payload_size = 2;
3386                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3387                         "Packet payload_size[0x%x]\n", payload_size);
3388                 break;
3389         default:
3390                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3391                 err = -EINVAL;
3392                 break;
3393         }
3394         return err;
3395 }
3396
3397 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3398                         struct tegra_dc_dsi_data *dsi,
3399                         u8 *read_fifo)
3400 {
3401         u32 val;
3402         u32 i;
3403         u32 poll_time = 0;
3404         u32 rd_fifo_cnt;
3405         int err = 0;
3406         u8 *read_fifo_cp = read_fifo;
3407
3408         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3409                 mdelay(1);
3410                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3411                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3412                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3413                         dev_err(&dc->ndev->dev,
3414                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3415                         break;
3416                 }
3417                 poll_time++;
3418         }
3419
3420         if (rd_fifo_cnt == 0) {
3421                 dev_info(&dc->ndev->dev,
3422                         "DSI RD_FIFO_CNT is zero\n");
3423                 err = -EINVAL;
3424                 goto fail;
3425         }
3426
3427         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3428                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3429                 dev_warn(&dc->ndev->dev,
3430                         "DSI overflow/underflow error\n");
3431         }
3432
3433         /* Read data from FIFO */
3434         for (i = 0; i < rd_fifo_cnt; i++) {
3435                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3436                 if (enable_read_debug)
3437                         dev_info(&dc->ndev->dev,
3438                         "Read data[%d]: 0x%x\n", i, val);
3439                 memcpy(read_fifo, &val, 4);
3440                 read_fifo += 4;
3441         }
3442
3443         /* Make sure all the data is read from the FIFO */
3444         val = tegra_dsi_readl(dsi, DSI_STATUS);
3445         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3446         if (val)
3447                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3448                 " even after reading FIFO_RD_CNT words from read fifo\n");
3449
3450         if (enable_read_debug) {
3451                 err =
3452                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3453                 if (err < 0)
3454                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3455         }
3456 fail:
3457         return err;
3458 }
3459
3460 int tegra_dsi_read_data(struct tegra_dc *dc,
3461                                 struct tegra_dc_dsi_data *dsi,
3462                                 u16 max_ret_payload_size,
3463                                 u8 panel_reg_addr, u8 *read_data)
3464 {
3465         int err = 0;
3466         struct dsi_status *init_status;
3467         static struct tegra_dsi_cmd temp_cmd;
3468
3469         if (!dsi->enabled) {
3470                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3471                 return -EINVAL;
3472         }
3473         tegra_dc_dsi_hold_host(dc);
3474         mutex_lock(&dsi->lock);
3475         tegra_dc_io_start(dc);
3476         clk_prepare_enable(dsi->dsi_fixed_clk);
3477         tegra_dsi_lp_clk_enable(dsi);
3478         init_status = tegra_dsi_prepare_host_transmission(
3479                                 dc, dsi, DSI_LP_OP_WRITE);
3480         if (IS_ERR_OR_NULL(init_status)) {
3481                 err = PTR_ERR(init_status);
3482                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3483                 goto fail;
3484         }
3485
3486         /* Set max return payload size in words */
3487         temp_cmd.data_id = dsi_command_max_return_pkt_size;
3488         temp_cmd.sp_len_dly.data_len = max_ret_payload_size;
3489         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3490         if (err < 0) {
3491                 dev_err(&dc->ndev->dev,
3492                                 "DSI write failed\n");
3493                 goto fail;
3494         }
3495
3496         /* DCS to read given panel register */
3497         temp_cmd.data_id = dsi_command_dcs_read_with_no_params;
3498         temp_cmd.sp_len_dly.sp.data0 = panel_reg_addr;
3499         temp_cmd.sp_len_dly.sp.data1 = 0;
3500         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3501         if (err < 0) {
3502                 dev_err(&dc->ndev->dev,
3503                                 "DSI write failed\n");
3504                 goto fail;
3505         }
3506
3507         tegra_dsi_reset_read_count(dsi);
3508
3509         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3510                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3511                 if (err < 0) {
3512                         dev_err(&dc->ndev->dev,
3513                         "DSI failed to go to LP read mode\n");
3514                         goto fail;
3515                 }
3516         }
3517
3518         err = tegra_dsi_bta(dsi);
3519         if (err < 0) {
3520                 dev_err(&dc->ndev->dev,
3521                         "DSI IMM BTA timeout\n");
3522                 goto fail;
3523         }
3524
3525         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3526         if (err < 0) {
3527                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3528                 goto fail;
3529         }
3530 fail:
3531         err = tegra_dsi_restore_state(dc, dsi, init_status);
3532         if (err < 0)
3533                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3534         tegra_dsi_lp_clk_disable(dsi);
3535         clk_disable_unprepare(dsi->dsi_fixed_clk);
3536         tegra_dc_io_end(dc);
3537         mutex_unlock(&dsi->lock);
3538         tegra_dc_dsi_release_host(dc);
3539         return err;
3540 }
3541 EXPORT_SYMBOL(tegra_dsi_read_data);
3542
3543 static const char * const error_sanity[] = {
3544                 "SoT Error",
3545                 "SoT Sync Error",
3546                 "EoT Sync Error",
3547                 "Escape Mode Entry Comand Error",
3548                 "Low-Power Transmit Sync Error",
3549                 "HS Receive Timeout Error",
3550                 "False Control Error",
3551                 "Reserved",
3552                 "ECC Error,Single Bit",
3553                 "ECC Error, Multi Bit",
3554                 "Checksum Error",
3555                 "DSI Data Type Not recognized",
3556                 "DSI VC ID Invalid",
3557                 "DSI Protocol Violation",
3558                 "Reserved",
3559                 "Reserved",
3560 };
3561
3562 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3563                                 struct tegra_dc_dsi_data *dsi,
3564                                 struct sanity_status *san)
3565 {
3566         int err = 0;
3567         u32 flagset[16];
3568         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3569         struct dsi_status *init_status;
3570         static struct tegra_dsi_cmd dsi_nop_cmd =
3571                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3572
3573         if (!dsi->enabled) {
3574                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3575                 return -EINVAL;
3576         }
3577         tegra_dc_dsi_hold_host(dc);
3578         tegra_dc_io_start(dc);
3579         clk_prepare_enable(dsi->dsi_fixed_clk);
3580         tegra_dsi_lp_clk_enable(dsi);
3581         memset(flagset, 0, sizeof(flagset));
3582         init_status = tegra_dsi_prepare_host_transmission(
3583                                 dc, dsi, DSI_LP_OP_WRITE);
3584         if (IS_ERR_OR_NULL(init_status)) {
3585                 err = PTR_ERR(init_status);
3586                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3587                 goto fail;
3588         }
3589
3590         err = _tegra_dsi_write_data(dsi, &dsi_nop_cmd);
3591         if (err < 0) {
3592                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3593                 goto fail;
3594         }
3595
3596         tegra_dsi_reset_read_count(dsi);
3597
3598         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3599                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3600                 if (err < 0) {
3601                         dev_err(&dc->ndev->dev,
3602                         "DSI failed to go to LP read mode\n");
3603                         goto fail;
3604                 }
3605         }
3606
3607         err = tegra_dsi_bta(dsi);
3608         if (err < 0) {
3609                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3610                 goto fail;
3611         }
3612
3613         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3614         if (err < 0) {
3615                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3616                 goto fail;
3617         }
3618
3619         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3620                 if (read_fifo[4] == ACK_ERR_RES) {
3621                         u16 payload = read_fifo[5] | (read_fifo[6] << 8);
3622                         int i = 0;
3623                         for (; payload; payload >>= 1, i++) {
3624                                 if (payload & 1) {
3625                                         flagset[i] = 0x01;
3626                                         if (enable_read_debug)
3627                                                 dev_info(&dc->ndev->dev,
3628                                                         " %s => error flag number %d\n",
3629                                                         error_sanity[i], i);
3630                                 }
3631                         }
3632                         if (san != NULL) {
3633                                 san->sot_error = flagset[0];
3634                                 san->sot_sync_error = flagset[1];
3635                                 san->eot_sync_error = flagset[2];
3636                                 san->escape_mode_entry_comand_error =
3637                                                 flagset[3];
3638                                 san->low_power_transmit_sync_error = flagset[4];
3639                                 san->hs_receive_timeout_error = flagset[5];
3640                                 san->false_control_error = flagset[6];
3641                                 san->reserved1 = flagset[7];
3642                                 san->ecc_error_single_bit = flagset[8];
3643                                 san->ecc_error_multi_bit = flagset[9];
3644                                 san->checksum_error = flagset[10];
3645                                 san->dsi_data_type_not_recognized = flagset[11];
3646                                 san->dsi_vc_id_invalid = flagset[12];
3647                                 san->dsi_protocol_violation = flagset[13];
3648                                 san->reserved2 = flagset[14];
3649                                 san->reserved3 = flagset[15];
3650                         }
3651                 }
3652                 dev_warn(&dc->ndev->dev,
3653                         "Ack no error trigger message not received\n");
3654                 err = -EAGAIN;
3655         }
3656
3657 fail:
3658         err = tegra_dsi_restore_state(dc, dsi, init_status);
3659         if (err < 0)
3660                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3661         tegra_dsi_lp_clk_disable(dsi);
3662         clk_disable_unprepare(dsi->dsi_fixed_clk);
3663         tegra_dc_io_end(dc);
3664         tegra_dc_dsi_release_host(dc);
3665         return err;
3666 }
3667 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3668
3669 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3670 {
3671         u32 val;
3672         int ret = 0;
3673
3674         if (dsi->info.ulpm_not_supported)
3675                 return 0;
3676
3677         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3678                 if (atomic_read(&dsi_syncpt_rst))
3679                         tegra_dsi_syncpt_reset(dsi);
3680
3681         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3682         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3683         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3684         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3685
3686         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3687                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3688                 if (ret < 0) {
3689                         dev_err(&dsi->dc->ndev->dev,
3690                                 "DSI syncpt for ulpm enter failed\n");
3691                         return ret;
3692                 }
3693         } else {
3694                 /* TODO: Find exact delay required */
3695                 mdelay(10);
3696         }
3697         dsi->ulpm = true;
3698
3699         return ret;
3700 }
3701
3702 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3703 {
3704         u32 val;
3705         int ret = 0;
3706
3707         if (dsi->info.ulpm_not_supported)
3708                 return 0;
3709
3710         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3711                 if (atomic_read(&dsi_syncpt_rst))
3712                         tegra_dsi_syncpt_reset(dsi);
3713
3714         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3715         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3716         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3717         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3718
3719         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3720                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3721                 if (ret < 0) {
3722                         dev_err(&dsi->dc->ndev->dev,
3723                                 "DSI syncpt for ulpm exit failed\n");
3724                         return ret;
3725                 }
3726         } else {
3727                 /* TODO: Find exact delay required */
3728                 mdelay(10);
3729         }
3730         dsi->ulpm = false;
3731
3732         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3733         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3734         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3735         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3736
3737         return ret;
3738 }
3739
3740 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3741                                      struct tegra_dc_dsi_data *dsi,
3742                                      int no_of_frames)
3743 {
3744         int err;
3745         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3746         u8 lp_op = dsi->status.lp_op;
3747         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3748
3749         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3750                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3751                                 TEGRA_DSI_DRIVEN_BY_DC);
3752                 if (err < 0) {
3753                         dev_err(&dc->ndev->dev,
3754                                 "Switch to HS host mode failed\n");
3755                         return;
3756                 }
3757         }
3758
3759         /*
3760          * Some panels need DC frames be sent under certain
3761          * conditions. We are working on the right fix for this
3762          * requirement, while using this current fix.
3763          */
3764         tegra_dsi_start_dc_stream(dc, dsi);
3765
3766         /*
3767          * Send frames in Continuous or One-shot mode.
3768          */
3769         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3770                 /* FIX ME: tegra_dc_blank() implicitly takes lock */
3771                 int flag = mutex_is_locked(&dc->lock);
3772                 if (flag)
3773                         mutex_unlock(&dc->lock);
3774                 while (no_of_frames--)
3775                         tegra_dc_blank(dc, BLANK_ALL);
3776                 if (flag)
3777                         mutex_lock(&dc->lock);
3778         } else
3779                 mdelay(no_of_frames * frame_period);
3780
3781         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3782
3783         if (switch_to_lp) {
3784                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3785                 if (err < 0)
3786                         dev_err(&dc->ndev->dev,
3787                                 "DSI failed to go to LP mode\n");
3788         }
3789 }
3790
3791 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
3792 {
3793         int err = 0;
3794
3795         if (dsi->avdd_dsi_csi)
3796                 err = regulator_enable(dsi->avdd_dsi_csi);
3797         WARN(err, "unable to enable regulator");
3798
3799         dsi->status.init = DSI_MODULE_INIT;
3800         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3801         dsi->status.driven = DSI_DRIVEN_MODE_DC;
3802         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3803         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
3804         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3805         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
3806
3807         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
3808                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
3809         else
3810                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
3811
3812         if (!(dsi->info.ganged_type)) {
3813                 if (dsi->info.video_burst_mode ==
3814                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
3815                         dsi->info.video_burst_mode ==
3816                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
3817                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
3818                 else
3819                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
3820         }
3821
3822         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
3823                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
3824         else
3825                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
3826
3827         tegra_dsi_clk_enable(dsi);
3828
3829         dsi->enabled = true;
3830 }
3831
3832 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
3833 {
3834         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3835         int err = 0;
3836
3837         mutex_lock(&dsi->lock);
3838         tegra_dc_io_start(dc);
3839
3840         /*
3841          * Do not program this panel as the bootloader as has already
3842          * initialized it. This avoids periods of blanking during boot.
3843          */
3844         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
3845                 tegra_dsi_setup_initialized_panel(dsi);
3846                 goto fail;
3847         }
3848
3849         /* Stop DC stream before configuring DSI registers
3850          * to avoid visible glitches on panel during transition
3851          * from bootloader to kernel driver
3852          */
3853         tegra_dsi_stop_dc_stream(dc, dsi);
3854
3855         if (dsi->enabled) {
3856                 if (dsi->ulpm) {
3857                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3858                                 dev_err(&dc->ndev->dev,
3859                                         "DSI failed to exit ulpm\n");
3860                                 goto fail;
3861                         }
3862                 }
3863
3864                 if (dsi->info.panel_reset) {
3865                         /*
3866                          * Certain panels need dc frames be sent before
3867                          * waking panel.
3868                          */
3869                         if (dsi->info.panel_send_dc_frames)
3870                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3871
3872                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3873                                                         dsi->info.dsi_init_cmd,
3874                                                         dsi->info.n_init_cmd);
3875                         if (err < 0) {
3876                                 dev_err(&dc->ndev->dev,
3877                                 "dsi: error sending dsi init cmd\n");
3878                                 goto fail;
3879                         }
3880                 } else if (dsi->info.dsi_late_resume_cmd) {
3881                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3882                                                 dsi->info.dsi_late_resume_cmd,
3883                                                 dsi->info.n_late_resume_cmd);
3884                         if (err < 0) {
3885                                 dev_err(&dc->ndev->dev,
3886                                 "dsi: error sending late resume cmd\n");
3887                                 goto fail;
3888                         }
3889                 }
3890         } else {
3891                 err = tegra_dsi_init_hw(dc, dsi);
3892                 if (err < 0) {
3893                         dev_err(&dc->ndev->dev,
3894                                 "dsi: not able to init dsi hardware\n");
3895                         goto fail;
3896                 }
3897
3898                 if (dsi->ulpm) {
3899                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3900                                 dev_err(&dc->ndev->dev,
3901                                         "DSI failed to enter ulpm\n");
3902                                 goto fail;
3903                         }
3904
3905                         tegra_dsi_pad_enable(dsi);
3906
3907                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3908                                 dev_err(&dc->ndev->dev,
3909                                         "DSI failed to exit ulpm\n");
3910                                 goto fail;
3911                         }
3912                 }
3913
3914                 /*
3915                  * Certain panels need dc frames be sent before
3916                  * waking panel.
3917                  */
3918                 if (dsi->info.panel_send_dc_frames)
3919                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3920
3921                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3922                 if (err < 0) {
3923                         dev_err(&dc->ndev->dev,
3924                                 "dsi: not able to set to lp mode\n");
3925                         goto fail;
3926                 }
3927
3928                 if (dsi->info.lp00_pre_panel_wakeup)
3929                         tegra_dsi_pad_disable(dsi);
3930
3931                 dsi->enabled = true;
3932         }
3933
3934         if (dsi->out_ops && dsi->out_ops->enable)
3935                 dsi->out_ops->enable(dsi);
3936 fail:
3937         tegra_dc_io_end(dc);
3938         mutex_unlock(&dsi->lock);
3939 }
3940
3941 static void tegra_dc_dsi_postpoweron(struct tegra_dc *dc)
3942 {
3943         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3944         int err = 0;
3945
3946         /*
3947          * Do not configure. Use bootloader configuration.
3948          * This avoids periods of blanking during boot.
3949          */
3950         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
3951                 return;
3952
3953         mutex_lock(&dsi->lock);
3954         tegra_dc_io_start(dc);
3955
3956         if (dsi->enabled) {
3957                 if (dsi->info.lp00_pre_panel_wakeup)
3958                         tegra_dsi_pad_enable(dsi);
3959
3960                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3961                                                         dsi->info.n_init_cmd);
3962                 if (err < 0) {
3963                         dev_err(&dc->ndev->dev,
3964                                 "dsi: error while sending dsi init cmd\n");
3965                         goto fail;
3966                 }
3967
3968                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3969                                 TEGRA_DSI_DRIVEN_BY_DC);
3970                 if (err < 0) {
3971                         dev_err(&dc->ndev->dev,
3972                                 "dsi: not able to set to hs mode\n");
3973                         goto fail;
3974                 }
3975
3976                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3977                         tegra_dsi_start_dc_stream(dc, dsi);
3978
3979                 dsi->host_suspended = false;
3980         }
3981 fail:
3982         tegra_dc_io_end(dc);
3983         mutex_unlock(&dsi->lock);
3984 }
3985
3986 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3987 {
3988         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3989
3990 #ifdef CONFIG_DEBUG_FS
3991         tegra_dc_dsi_debug_create(dsi);
3992 #endif
3993
3994         if (dsi->info.dsi2lvds_bridge_enable)
3995                 dsi->out_ops = &tegra_dsi2lvds_ops;
3996         else if (dsi->info.dsi2edp_bridge_enable)
3997                 dsi->out_ops = &tegra_dsi2edp_ops;
3998         else
3999                 dsi->out_ops = NULL;
4000
4001         if (dsi->out_ops && dsi->out_ops->init)
4002                 dsi->out_ops->init(dsi);
4003
4004         tegra_dsi_init_sw(dc, dsi);
4005 }
4006
4007 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
4008                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
4009 {
4010         u16 i;
4011         u16 len;
4012
4013         memcpy(dst, src, sizeof(*dst) * n_cmd);
4014
4015         for (i = 0; i < n_cmd; i++)
4016                 if (src[i].pdata) {
4017                         len = sizeof(*src[i].pdata) *
4018                                         src[i].sp_len_dly.data_len;
4019                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
4020                         if (!dst[i].pdata)
4021                                 goto free_cmd_pdata;
4022                         memcpy(dst[i].pdata, src[i].pdata, len);
4023                 }
4024
4025         return 0;
4026
4027 free_cmd_pdata:
4028         while (i--)
4029                 if (dst[i].pdata)
4030                         kfree(dst[i].pdata);
4031         return -ENOMEM;
4032 }
4033
4034 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
4035                                                 struct tegra_dsi_out *p_dsi)
4036 {
4037         struct tegra_dsi_cmd *p_init_cmd;
4038         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
4039         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
4040         struct tegra_dsi_cmd *p_suspend_cmd;
4041         int err = 0;
4042
4043         if (dsi->info.n_data_lanes > MAX_DSI_DATA_LANES)
4044                 return -EINVAL;
4045
4046         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
4047                                 p_dsi->n_init_cmd, GFP_KERNEL);
4048         if (!p_init_cmd)
4049                 return -ENOMEM;
4050
4051         if (p_dsi->dsi_early_suspend_cmd) {
4052                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
4053                                         p_dsi->n_early_suspend_cmd,
4054                                         GFP_KERNEL);
4055                 if (!p_early_suspend_cmd) {
4056                         err = -ENOMEM;
4057                         goto err_free_init_cmd;
4058                 }
4059         }
4060
4061         if (p_dsi->dsi_late_resume_cmd) {
4062                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
4063                                         p_dsi->n_late_resume_cmd,
4064                                         GFP_KERNEL);
4065                 if (!p_late_resume_cmd) {
4066                         err = -ENOMEM;
4067                         goto err_free_p_early_suspend_cmd;
4068                 }
4069         }
4070
4071         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
4072                                 GFP_KERNEL);
4073         if (!p_suspend_cmd) {
4074                 err = -ENOMEM;
4075                 goto err_free_p_late_resume_cmd;
4076         }
4077
4078         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
4079
4080         /* Copy panel init cmd */
4081         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
4082                                                 p_init_cmd, p_dsi->n_init_cmd);
4083         if (err < 0)
4084                 goto err_free;
4085         dsi->info.dsi_init_cmd = p_init_cmd;
4086
4087         /* Copy panel early suspend cmd */
4088         if (p_dsi->dsi_early_suspend_cmd) {
4089                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
4090                                         p_early_suspend_cmd,
4091                                         p_dsi->n_early_suspend_cmd);
4092                 if (err < 0)
4093                         goto err_free;
4094                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
4095         }
4096
4097         /* Copy panel late resume cmd */
4098         if (p_dsi->dsi_late_resume_cmd) {
4099                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
4100                                                 p_late_resume_cmd,
4101                                                 p_dsi->n_late_resume_cmd);
4102                 if (err < 0)
4103                         goto err_free;
4104                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
4105         }
4106
4107         /* Copy panel suspend cmd */
4108         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
4109                                         p_dsi->n_suspend_cmd);
4110         if (err < 0)
4111                 goto err_free;
4112         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
4113
4114         if (!dsi->info.panel_reset_timeout_msec)
4115                 dsi->info.panel_reset_timeout_msec =
4116                                                 DEFAULT_PANEL_RESET_TIMEOUT;
4117         if (!dsi->info.panel_buffer_size_byte)
4118                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
4119
4120         if (!dsi->info.max_panel_freq_khz) {
4121                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
4122
4123                 if (dsi->info.video_burst_mode >
4124                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
4125                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
4126                                         "is not set for DSI burst mode.\n");
4127                         dsi->info.video_burst_mode =
4128                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
4129                 }
4130         }
4131
4132         if (!dsi->info.lp_cmd_mode_freq_khz)
4133                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
4134
4135         if (!dsi->info.lp_read_cmd_mode_freq_khz)
4136                 dsi->info.lp_read_cmd_mode_freq_khz =
4137                         dsi->info.lp_cmd_mode_freq_khz;
4138
4139         /* host mode is for testing only */
4140         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4141         return 0;
4142
4143 err_free:
4144         kfree(p_suspend_cmd);
4145 err_free_p_late_resume_cmd:
4146         kfree(p_late_resume_cmd);
4147 err_free_p_early_suspend_cmd:
4148         kfree(p_early_suspend_cmd);
4149 err_free_init_cmd:
4150         kfree(p_init_cmd);
4151         return err;
4152 }
4153
4154 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
4155 {
4156         struct tegra_dc_dsi_data *dsi;
4157         struct resource *res;
4158         struct resource *base_res;
4159         struct resource dsi_res;
4160         void __iomem *base;
4161         struct clk *dc_clk = NULL;
4162         struct clk *dsi_clk;
4163         struct clk *dsi_fixed_clk = NULL;
4164         struct clk *dsi_lp_clk = NULL;
4165         struct tegra_dsi_out *dsi_pdata;
4166         int err = 0, i;
4167         char *ganged_reg_name[2] = {"ganged_dsia_regs", "ganged_dsib_regs"};
4168         char *dsi_clk_name[2] = {"dsia", "dsib"};
4169         char *dsi_lp_clk_name[2] = {"dsialp", "dsiblp"};
4170         struct device_node *np = dc->ndev->dev.of_node;
4171 #ifdef CONFIG_USE_OF
4172         struct device_node *np_dsi =
4173                 of_find_node_by_path("/host1x/dsi");
4174 #else
4175         struct device_node *np_dsi = NULL;
4176 #endif
4177         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4178         if (!dsi) {
4179                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
4180                 return -ENOMEM;
4181         }
4182
4183         dsi->max_instances = dc->out->dsi->ganged_type ? MAX_DSI_INSTANCE : 1;
4184         for (i = 0; i < dsi->max_instances; i++) {
4185                 if (np) {
4186                         if (np_dsi && of_device_is_available(np_dsi)) {
4187                                 of_address_to_resource(np_dsi, i, &dsi_res);
4188                                 res = &dsi_res;
4189                         } else {
4190                                 err = -EINVAL;
4191                                 goto err_free_dsi;
4192                         }
4193                 } else {
4194                         res = platform_get_resource_byname(dc->ndev,
4195                                         IORESOURCE_MEM,
4196                                         dc->out->dsi->ganged_type ?
4197                                         ganged_reg_name[i] : "dsi_regs");
4198                 }
4199                 if (!res) {
4200                         dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
4201                         err = -ENOENT;
4202                         goto err_free_dsi;
4203                 }
4204
4205                 base_res = request_mem_region(res->start, resource_size(res),
4206                                         dc->ndev->name);
4207                 if (!base_res) {
4208                         dev_err(&dc->ndev->dev,
4209                                 "dsi: request_mem_region failed\n");
4210                         err = -EBUSY;
4211                         goto err_free_dsi;
4212                 }
4213
4214                 base = ioremap(res->start, resource_size(res));
4215                 if (!base) {
4216                         dev_err(&dc->ndev->dev,
4217                                 "dsi: registers can't be mapped\n");
4218                         err = -EBUSY;
4219                         goto err_release_regs;
4220                 }
4221
4222                 dsi_pdata = dc->pdata->default_out->dsi;
4223                 if (!dsi_pdata) {
4224                         dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
4225                         goto err_release_regs;
4226                 }
4227
4228                 dsi_clk = dsi->info.dsi_instance ?
4229                                 clk_get(&dc->ndev->dev,
4230                                 dsi_clk_name[DSI_INSTANCE_1]) :
4231                                 clk_get(&dc->ndev->dev, dsi_clk_name[i]);
4232                 dsi_lp_clk = dsi->info.dsi_instance ?
4233                                 clk_get(&dc->ndev->dev,
4234                                 dsi_lp_clk_name[DSI_INSTANCE_1]) :
4235                                 clk_get(&dc->ndev->dev, dsi_lp_clk_name[i]);
4236
4237                 if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_lp_clk)) {
4238                         dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
4239                         err = -EBUSY;
4240                         goto err_dsi_clk_put;
4241                 }
4242
4243                 dsi->base[i] = base;
4244                 dsi->base_res[i] = base_res;
4245                 dsi->dsi_clk[i] = dsi_clk;
4246                 dsi->dsi_lp_clk[i] = dsi_lp_clk;
4247         }
4248
4249         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
4250
4251         if (IS_ERR_OR_NULL(dsi_fixed_clk)) {
4252                 dev_err(&dc->ndev->dev, "dsi: can't get fixed clock\n");
4253                 err = -EBUSY;
4254                 goto err_release_regs;
4255         }
4256
4257         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
4258         if (IS_ERR_OR_NULL(dc_clk)) {
4259                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
4260                         dev_name(&dc->ndev->dev));
4261                 err = -EBUSY;
4262                 goto err_dsi_fixed_clk_put;
4263         }
4264
4265         mutex_init(&dsi->lock);
4266         dsi->dc = dc;
4267         dsi->dc_clk = dc_clk;
4268         dsi->dsi_fixed_clk = dsi_fixed_clk;
4269
4270         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
4271         if (err < 0)
4272                 goto err_dc_clk_put;
4273
4274         tegra_dc_set_outdata(dc, dsi);
4275         __tegra_dc_dsi_init(dc);
4276
4277         return 0;
4278
4279 err_dc_clk_put:
4280         clk_put(dc_clk);
4281 err_dsi_fixed_clk_put:
4282         clk_put(dsi_fixed_clk);
4283 err_dsi_clk_put:
4284         for (i = 0; i < dsi->max_instances; i++) {
4285                 clk_put(dsi->dsi_lp_clk[i]);
4286                 clk_put(dsi->dsi_clk[i]);
4287         }
4288 err_release_regs:
4289         for (i = 0; i < dsi->max_instances; i++)
4290                 release_resource(dsi->base_res[i]);
4291 err_free_dsi:
4292         kfree(dsi);
4293
4294         return err;
4295 }
4296
4297 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
4298 {
4299         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4300         u16 i;
4301         u32 val;
4302
4303         mutex_lock(&dsi->lock);
4304         tegra_dc_io_start(dc);
4305
4306         if (dsi->out_ops && dsi->out_ops->destroy)
4307                 dsi->out_ops->destroy(dsi);
4308
4309         /* free up the pdata */
4310         for (i = 0; i < dsi->info.n_init_cmd; i++) {
4311                 if (dsi->info.dsi_init_cmd[i].pdata)
4312                         kfree(dsi->info.dsi_init_cmd[i].pdata);
4313         }
4314         kfree(dsi->info.dsi_init_cmd);
4315
4316         /* Disable dc stream */
4317         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4318                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4319
4320         /* Disable dsi phy clock */
4321         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
4322                 tegra_dsi_hs_clk_out_disable(dc, dsi);
4323
4324         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4325         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4326
4327         for (i = 0; i < dsi->max_instances; i++) {
4328                 iounmap(dsi->base[i]);
4329                 release_resource(dsi->base_res[i]);
4330         }
4331         clk_put(dsi->dc_clk);
4332         for (i = 0; i < dsi->max_instances; i++)
4333                 clk_put(dsi->dsi_clk[i]);
4334
4335         tegra_dc_io_end(dc);
4336         mutex_unlock(&dsi->lock);
4337         mutex_destroy(&dsi->lock);
4338         kfree(dsi);
4339 }
4340
4341 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4342                                                         u32 settings)
4343 {
4344         struct clk *parent_clk = NULL;
4345         struct clk *base_clk = NULL;
4346         int i = 0;
4347
4348         for (i = 0; i < dsi->max_instances; i++) {
4349                 parent_clk = clk_get_parent(dsi->dsi_clk[i]);
4350                 base_clk = clk_get_parent(parent_clk);
4351
4352 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
4353                 if (dsi->info.dsi_instance)
4354                         tegra_clk_cfg_ex(base_clk,
4355                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
4356                                         settings);
4357                 else
4358                         tegra_clk_cfg_ex(base_clk,
4359                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
4360                                         settings);
4361 #else
4362                 tegra_clk_cfg_ex(base_clk,
4363                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
4364                                 settings);
4365 #endif
4366         }
4367 }
4368
4369 static int tegra_dsi_te_on_off(struct tegra_dc_dsi_data *dsi, bool flag)
4370 {
4371         int ret;
4372
4373         struct tegra_dsi_cmd te_enable[] = {
4374                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4375                                 DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
4376                 DSI_DLY_MS(0),
4377         };
4378
4379         struct tegra_dsi_cmd te_disable[] = {
4380                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4381                                 DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0),
4382                 DSI_DLY_MS(0),
4383         };
4384
4385         if (flag)
4386                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_enable,
4387                                         ARRAY_SIZE(te_enable));
4388         else
4389                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_disable,
4390                                         ARRAY_SIZE(te_disable));
4391
4392         return ret;
4393 }
4394
4395 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4396                                         struct tegra_dc_dsi_data *dsi,
4397                                         u32 suspend_aggr)
4398 {
4399         u32 val = 0;
4400         int err = 0;
4401
4402         switch (suspend_aggr) {
4403         case DSI_HOST_SUSPEND_LV2:
4404                 if (!dsi->ulpm) {
4405                         err = tegra_dsi_enter_ulpm(dsi);
4406                         if (err < 0) {
4407                                 dev_err(&dc->ndev->dev,
4408                                         "DSI failed to enter ulpm\n");
4409                                 goto fail;
4410                         }
4411                 }
4412
4413                 tegra_dsi_pad_disable(dsi);
4414
4415                 /* Suspend core-logic */
4416                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4417                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4418
4419                 /* disable HS logic */
4420                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4421                 val |= DSI_PAD_PDVCLAMP(0x1);
4422                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4423
4424                 /* disable mipi bias pad */
4425                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
4426                 val = tegra_mipi_cal_read(dsi->mipi_cal,
4427                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
4428                 val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
4429                 tegra_mipi_cal_write(dsi->mipi_cal, val,
4430                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
4431                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
4432
4433                 /* fall through */
4434         case DSI_HOST_SUSPEND_LV1:
4435                 /* Disable dsi fast and slow clock */
4436                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4437                 /* fall through */
4438         case DSI_HOST_SUSPEND_LV0:
4439                 /* Disable dsi source clock */
4440                 tegra_dsi_clk_disable(dsi);
4441                 break;
4442         case DSI_NO_SUSPEND:
4443                 break;
4444         default:
4445                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
4446                                                 "is not supported.\n");
4447         }
4448
4449         tegra_dvfs_set_rate(dc->clk, 0);
4450
4451         return 0;
4452 fail:
4453         return err;
4454 }
4455
4456 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
4457                                         struct tegra_dc_dsi_data *dsi,
4458                                         u32 suspend_aggr)
4459 {
4460         u32 val;
4461         int err;
4462
4463         switch (dsi->info.suspend_aggr) {
4464         case DSI_HOST_SUSPEND_LV0:
4465                 tegra_dsi_clk_enable(dsi);
4466                 break;
4467         case DSI_HOST_SUSPEND_LV1:
4468                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4469                 tegra_dsi_clk_enable(dsi);
4470                 break;
4471         case DSI_HOST_SUSPEND_LV2:
4472                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4473                 tegra_dsi_clk_enable(dsi);
4474
4475                 /* enable mipi bias pad */
4476                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
4477                 val = tegra_mipi_cal_read(dsi->mipi_cal,
4478                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
4479                 val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
4480                 tegra_mipi_cal_write(dsi->mipi_cal, val,
4481                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
4482                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
4483
4484                 /* enable HS logic */
4485                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4486                 val &= ~DSI_PAD_PDVCLAMP(0x1);
4487                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4488
4489                 tegra_dsi_writel(dsi,
4490                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
4491                         DSI_POWER_CONTROL);
4492
4493                 if (dsi->ulpm) {
4494                         err = tegra_dsi_enter_ulpm(dsi);
4495                         if (err < 0) {
4496                                 dev_err(&dc->ndev->dev,
4497                                         "DSI failed to enter ulpm\n");
4498                                 goto fail;
4499                         }
4500
4501                         tegra_dsi_pad_enable(dsi);
4502
4503                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4504                                 dev_err(&dc->ndev->dev,
4505                                         "DSI failed to exit ulpm\n");
4506                                 goto fail;
4507                         }
4508                 } else {
4509                         tegra_dsi_pad_enable(dsi);
4510                 }
4511                 break;
4512         case DSI_NO_SUSPEND:
4513                 break;
4514         default:
4515                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
4516                                                 "is not supported.\n");
4517         }
4518
4519         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4520
4521         return 0;
4522 fail:
4523         return err;
4524 }
4525
4526 static int tegra_dsi_host_suspend_trylock(struct tegra_dc *dc,
4527                                         struct tegra_dc_dsi_data *dsi)
4528 {
4529         if (!mutex_trylock(&dc->lp_lock))
4530                 goto fail;
4531         if (!mutex_trylock(&dc->lock))
4532                 goto unlock_one_shot_lp;
4533         if (!mutex_trylock(&dsi->host_lock))
4534                 goto unlock_dc_lock;
4535         if (!mutex_trylock(&dc->one_shot_lock))
4536                 goto unlock_host_lock;
4537
4538         return 1;
4539
4540 unlock_host_lock:
4541         mutex_unlock(&dsi->host_lock);
4542 unlock_dc_lock:
4543         mutex_unlock(&dc->lock);
4544 unlock_one_shot_lp:
4545         mutex_unlock(&dc->lp_lock);
4546 fail:
4547         return 0;
4548 }
4549
4550 static void tegra_dsi_host_suspend_unlock(struct tegra_dc *dc,
4551                                         struct tegra_dc_dsi_data *dsi)
4552 {
4553         mutex_unlock(&dc->one_shot_lock);
4554         mutex_unlock(&dsi->host_lock);
4555         mutex_unlock(&dc->lock);
4556         mutex_unlock(&dc->lp_lock);
4557 }
4558
4559 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
4560 {
4561         int err = 0;
4562         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4563
4564         if (!dsi->enabled)
4565                 return -EINVAL;
4566
4567         while (!tegra_dsi_host_suspend_trylock(dc, dsi))
4568                 cond_resched();
4569
4570         if (dsi->host_suspended || atomic_read(&dsi->host_ref)) {
4571                 tegra_dsi_host_suspend_unlock(dc, dsi);
4572                 return 0;
4573         }
4574
4575         tegra_dc_io_start(dc);
4576
4577         dsi->host_suspended = true;
4578
4579         tegra_dsi_stop_dc_stream(dc, dsi);
4580
4581         tegra_dsi_te_on_off(dsi, false);
4582
4583         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4584         if (err < 0) {
4585                 dev_err(&dc->ndev->dev,
4586                         "DSI host suspend failed\n");
4587                 goto fail;
4588         }
4589
4590         /* Shutting down. Drop any reference to dc clk */
4591         while (tegra_is_clk_enabled(dc->clk))
4592                 tegra_dc_put(dc);
4593
4594         pm_runtime_put_sync(&dc->ndev->dev);
4595 fail:
4596         tegra_dc_io_end(dc);
4597         tegra_dsi_host_suspend_unlock(dc, dsi);
4598         return err;
4599 }
4600
4601 static bool tegra_dc_dsi_osidle(struct tegra_dc *dc)
4602 {
4603         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4604
4605         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4606                 return dsi->host_suspended;
4607         else
4608                 return false;
4609 }
4610
4611 static void tegra_dsi_bl_off(struct backlight_device *bd)
4612 {
4613         if (!bd)
4614                 return;
4615
4616         bd->props.brightness = 0;
4617         backlight_update_status(bd);
4618 }
4619
4620 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
4621                                 struct tegra_dc_dsi_data *dsi)
4622 {
4623         int val = 0;
4624         int err = 0;
4625
4626         if (!dsi->enabled)
4627                 return 0;
4628
4629         cancel_delayed_work(&dsi->idle_work);
4630
4631         tegra_dsi_bl_off(get_backlight_device_by_name(dsi->info.bl_name));
4632
4633         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4634         if (err < 0) {
4635                 dev_err(&dc->ndev->dev,
4636                 "DSI failed to go to LP mode\n");
4637                 goto fail;
4638         }
4639
4640         /* Suspend DSI panel */
4641         err = tegra_dsi_send_panel_cmd(dc, dsi,
4642                         dsi->info.dsi_suspend_cmd,
4643                         dsi->info.n_suspend_cmd);
4644
4645         /*
4646          * Certain panels need dc frames be sent after
4647          * putting panel to sleep.
4648          */
4649         if (dsi->info.panel_send_dc_frames)
4650                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4651
4652         if (err < 0) {
4653                 dev_err(&dc->ndev->dev,
4654                         "dsi: Error sending suspend cmd\n");
4655                 goto fail;
4656         }
4657
4658         if (!dsi->ulpm) {
4659                 err = tegra_dsi_enter_ulpm(dsi);
4660                 if (err < 0) {
4661                         dev_err(&dc->ndev->dev,
4662                                 "DSI failed to enter ulpm\n");
4663                         goto fail;
4664                 }
4665         }
4666
4667         tegra_dsi_pad_disable(dsi);
4668
4669         /* Suspend core-logic */
4670         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4671         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4672
4673         /* Disable dsi fast and slow clock */
4674         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4675
4676         /* Disable dsi source clock */
4677         tegra_dsi_clk_disable(dsi);
4678
4679         dsi->enabled = false;
4680         dsi->host_suspended = true;
4681
4682         return 0;
4683 fail:
4684         return err;
4685 }
4686
4687 static void tegra_dc_dsi_postpoweroff(struct tegra_dc *dc)
4688 {
4689         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4690
4691         if (!dsi->enabled)
4692                 regulator_disable(dsi->avdd_dsi_csi);
4693 }
4694
4695 static int tegra_dsi_host_resume(struct tegra_dc *dc)
4696 {
4697         int err = 0;
4698         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4699
4700         if (!dsi->enabled)
4701                 return -EINVAL;
4702
4703         cancel_delayed_work(&dsi->idle_work);
4704
4705         mutex_lock(&dsi->host_lock);
4706         if (!dsi->host_suspended) {
4707                 mutex_unlock(&dsi->host_lock);
4708                 return 0;
4709         }
4710
4711         tegra_dc_io_start(dc);
4712
4713         pm_runtime_get_sync(&dc->ndev->dev);
4714
4715         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
4716         if (err < 0) {
4717                 dev_err(&dc->ndev->dev,
4718                         "DSI host resume failed\n");
4719                 goto fail;
4720         }
4721
4722         tegra_dsi_te_on_off(dsi, true);
4723
4724         tegra_dsi_start_dc_stream(dc, dsi);
4725         dsi->host_suspended = false;
4726 fail:
4727         tegra_dc_io_end(dc);
4728         mutex_unlock(&dsi->host_lock);
4729         return err;
4730 }
4731
4732 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4733 {
4734         int err;
4735         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4736
4737         if (dsi->host_suspended)
4738                 tegra_dsi_host_resume(dc);
4739
4740         mutex_lock(&dsi->lock);
4741         tegra_dc_io_start(dc);
4742
4743         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4744                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4745
4746         if (dsi->out_ops && dsi->out_ops->disable)
4747                 dsi->out_ops->disable(dsi);
4748
4749         if (dsi->info.power_saving_suspend) {
4750                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4751                         dev_err(&dc->ndev->dev,
4752                                 "DSI failed to enter deep sleep\n");
4753                         goto fail;
4754                 }
4755         } else {
4756                 if (dsi->info.dsi_early_suspend_cmd) {
4757                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4758                                 dsi->info.dsi_early_suspend_cmd,
4759                                 dsi->info.n_early_suspend_cmd);
4760                         if (err < 0) {
4761                                 dev_err(&dc->ndev->dev,
4762                                 "dsi: Error sending early suspend cmd\n");
4763                                 goto fail;
4764                         }
4765                 }
4766
4767                 if (!dsi->ulpm) {
4768                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4769                                 dev_err(&dc->ndev->dev,
4770                                         "DSI failed to enter ulpm\n");
4771                                 goto fail;
4772                         }
4773                 }
4774         }
4775 fail:
4776         mutex_unlock(&dsi->lock);
4777         tegra_dc_io_end(dc);
4778 }
4779
4780 #ifdef CONFIG_PM
4781 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4782 {
4783         struct tegra_dc_dsi_data *dsi;
4784
4785         dsi = tegra_dc_get_outdata(dc);
4786
4787         if (!dsi->enabled)
4788                 return;
4789
4790         if (dsi->host_suspended)
4791                 tegra_dsi_host_resume(dc);
4792
4793         tegra_dc_io_start(dc);
4794         mutex_lock(&dsi->lock);
4795
4796         if (dsi->out_ops && dsi->out_ops->suspend)
4797                 dsi->out_ops->suspend(dsi);
4798
4799         if (!dsi->info.power_saving_suspend) {
4800                 if (dsi->ulpm) {
4801                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4802                                 dev_err(&dc->ndev->dev,
4803                                         "DSI failed to exit ulpm");
4804                                 goto fail;
4805                         }
4806                 }
4807
4808                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4809                         dev_err(&dc->ndev->dev,
4810                                 "DSI failed to enter deep sleep\n");
4811                         goto fail;
4812                 }
4813         }
4814 fail:
4815         mutex_unlock(&dsi->lock);
4816         tegra_dc_io_end(dc);
4817 }
4818
4819 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
4820 {
4821         struct tegra_dc_dsi_data *dsi;
4822
4823         dsi = tegra_dc_get_outdata(dc);
4824
4825         /* No dsi config required since tegra_dc_dsi_enable
4826          * will reconfigure the controller from scratch
4827          */
4828
4829          if (dsi->out_ops && dsi->out_ops->resume)
4830                 dsi->out_ops->resume(dsi);
4831 }
4832 #endif
4833
4834 static int tegra_dc_dsi_init(struct tegra_dc *dc)
4835 {
4836         struct tegra_dc_dsi_data *dsi;
4837         int err = 0;
4838
4839         err = _tegra_dc_dsi_init(dc);
4840         if (err < 0) {
4841                 dev_err(&dc->ndev->dev,
4842                         "dsi: Instance A init failed\n");
4843                 goto err;
4844         }
4845
4846         dsi = tegra_dc_get_outdata(dc);
4847
4848         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
4849         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
4850                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
4851                 err = -ENODEV;
4852                 goto err_reg;
4853         }
4854
4855         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
4856         if (IS_ERR(dsi->mipi_cal)) {
4857                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
4858                 err = PTR_ERR(dsi->mipi_cal);
4859                 goto err_mipi;
4860         }
4861         return 0;
4862 err_mipi:
4863         regulator_put(dsi->avdd_dsi_csi);
4864 err_reg:
4865         _tegra_dc_dsi_destroy(dc);
4866         tegra_dc_set_outdata(dc, NULL);
4867 err:
4868         return err;
4869 }
4870
4871 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4872 {
4873         struct regulator *avdd_dsi_csi;
4874         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4875
4876         avdd_dsi_csi = dsi->avdd_dsi_csi;
4877
4878         _tegra_dc_dsi_destroy(dc);
4879         regulator_put(avdd_dsi_csi);
4880         tegra_mipi_cal_destroy(dc);
4881 }
4882
4883 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
4884 {
4885         unsigned long rate;
4886         struct clk *parent_clk;
4887         struct clk *base_clk;
4888         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4889
4890         /* divide by 1000 to avoid overflow */
4891         dc->mode.pclk /= 1000;
4892         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
4893                                 / dc->shift_clk_div.div;
4894         rate *= 1000;
4895         dc->mode.pclk *= 1000;
4896
4897         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
4898                 goto skip_setup;
4899
4900         if (clk == dc->clk) {
4901                 parent_clk = clk_get_sys(NULL,
4902                                 dc->out->parent_clk ? : "pll_d_out0");
4903                 base_clk = clk_get_parent(parent_clk);
4904         } else {
4905                 if (dc->pdata->default_out->dsi->dsi_instance) {
4906                         parent_clk = clk_get_sys(NULL,
4907                                 dc->out->parent_clk ? : "pll_d2_out0");
4908                         base_clk = clk_get_parent(parent_clk);
4909                 } else {
4910                         parent_clk = clk_get_sys(NULL,
4911                                 dc->out->parent_clk ? : "pll_d_out0");
4912                         base_clk = clk_get_parent(parent_clk);
4913                 }
4914         }
4915         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4916
4917         if (rate != clk_get_rate(base_clk))
4918                 clk_set_rate(base_clk, rate);
4919
4920         if (clk_get_parent(clk) != parent_clk)
4921                 clk_set_parent(clk, parent_clk);
4922
4923 skip_setup:
4924         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4925
4926         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
4927 }
4928
4929 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4930         .init = tegra_dc_dsi_init,
4931         .destroy = tegra_dc_dsi_destroy,
4932         .enable = tegra_dc_dsi_enable,
4933         .postpoweron = tegra_dc_dsi_postpoweron,
4934         .disable = tegra_dc_dsi_disable,
4935         .postpoweroff = tegra_dc_dsi_postpoweroff,
4936         .hold = tegra_dc_dsi_hold_host,
4937         .release = tegra_dc_dsi_release_host,
4938 #ifdef CONFIG_PM
4939         .suspend = tegra_dc_dsi_suspend,
4940         .resume = tegra_dc_dsi_resume,
4941 #endif
4942         .setup_clk = tegra_dc_dsi_setup_clk,
4943         .osidle = tegra_dc_dsi_osidle,
4944 };