2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/i2c.h>
17 #include <linux/gpio.h>
18 #include <linux/mpu.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/nct1008.h>
22 #include <linux/pid_thermal_gov.h>
23 #include <linux/tegra-fuse.h>
24 #include <linux/of_platform.h>
26 #include <mach/pinmux-t12.h>
27 #include <mach/pinmux.h>
28 #include <mach/io_dpd.h>
29 #include <media/camera.h>
30 #include <media/ar0330.h>
31 #include <media/ar0261.h>
32 #include <media/imx135.h>
33 #include <media/imx179.h>
34 #include <media/dw9718.h>
35 #include <media/as364x.h>
36 #include <media/ov5693.h>
37 #include <media/ov7695.h>
38 #include <media/mt9m114.h>
39 #include <media/ad5823.h>
40 #include <media/max77387.h>
42 #include <media/ov4689.h>
43 #include <linux/platform_device.h>
44 #include <media/soc_camera.h>
45 #include <media/soc_camera_platform.h>
46 #include <media/tegra_v4l2_camera.h>
47 #include <linux/generic_adc_thermal.h>
49 #include "cpu-tegra.h"
52 #include "board-common.h"
53 #include "board-ardbeg.h"
54 #include "tegra-board-id.h"
56 #if defined(ARCH_TEGRA_12x_SOC)
57 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
59 I2C_BOARD_INFO("cm32181", 0x48),
64 /* MPU board file definition */
65 static struct mpu_platform_data mpu9250_gyro_data = {
68 /* Located in board_[platformname].h */
69 .orientation = MPU_GYRO_ORIENTATION,
70 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
71 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
72 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
75 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
78 /* Located in board_[platformname].h */
79 .orientation = MPU_GYRO_ORIENTATION_E1762,
80 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
81 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
82 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
85 static struct mpu_platform_data mpu_compass_data = {
86 .orientation = MPU_COMPASS_ORIENTATION,
87 .config = NVI_CONFIG_BOOT_MPU,
90 static struct mpu_platform_data mpu_bmp_pdata = {
91 .config = NVI_CONFIG_BOOT_MPU,
94 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
96 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
97 .platform_data = &mpu9250_gyro_data,
100 /* The actual BMP180 address is 0x77 but because this conflicts
101 * with another device, this address is hacked so Linux will
102 * call the driver. The conflict is technically okay since the
103 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
104 * hard-coded address of 0x77 since it can't be changed anyway.
106 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
107 .platform_data = &mpu_bmp_pdata,
110 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
111 .platform_data = &mpu_compass_data,
115 static void mpuirq_init(void)
118 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
119 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
120 char *gyro_name = MPU_GYRO_NAME;
121 struct board_info board_info;
123 pr_info("*** MPU START *** mpuirq_init...\n");
125 tegra_get_board_info(&board_info);
127 ret = gpio_request(gyro_irq_gpio, gyro_name);
129 pr_err("%s: gpio_request failed %d\n", __func__, ret);
133 ret = gpio_direction_input(gyro_irq_gpio);
135 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
136 gpio_free(gyro_irq_gpio);
139 pr_info("*** MPU END *** mpuirq_init...\n");
141 /* TN8 with diferent Compass address from ardbeg */
142 if (of_machine_is_compatible("nvidia,tn8"))
143 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
145 if (board_info.board_id == BOARD_E1762)
146 inv_mpu9250_i2c0_board_info[0].platform_data =
147 &mpu9250_gyro_data_e1762;
148 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
149 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
150 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
154 * Soc Camera platform driver for testing
156 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
157 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
158 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
160 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
163 /* TODO: probably add clk opertaion here */
164 return 0; /* camera sensor always enabled */
167 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
168 .format_name = "RGB4",
171 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
172 .colorspace = V4L2_COLORSPACE_SRGB,
173 .field = V4L2_FIELD_NONE,
177 .set_capture = ardbeg_soc_camera_set_capture,
180 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
183 .port = TEGRA_CAMERA_PORT_CSI_A,
188 static struct soc_camera_link ardbeg_soc_camera_link = {
189 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
190 .add_device = ardbeg_soc_camera_add,
191 .del_device = ardbeg_soc_camera_del,
192 .module_name = "soc_camera_platform",
193 .priv = &ardbeg_camera_platform_data,
194 .dev_priv = &ardbeg_soc_camera_info,
197 static struct platform_device *ardbeg_pdev;
199 static void ardbeg_soc_camera_release(struct device *dev)
201 soc_camera_platform_release(&ardbeg_pdev);
204 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
206 return soc_camera_platform_add(icd, &ardbeg_pdev,
207 &ardbeg_soc_camera_link,
208 ardbeg_soc_camera_release, 0);
211 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
213 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
216 static struct platform_device ardbeg_soc_camera_device = {
217 .name = "soc-camera-pdrv",
220 .platform_data = &ardbeg_soc_camera_link,
225 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
226 static int ardbeg_imx135_power(struct device *dev, int enable)
231 struct imx135_platform_data ardbeg_imx135_data;
233 static struct i2c_board_info ardbeg_imx135_camera_i2c_device = {
234 I2C_BOARD_INFO("imx135_v4l2", 0x10),
235 .platform_data = &ardbeg_imx135_data,
238 static struct tegra_camera_platform_data ardbeg_imx135_camera_platform_data = {
241 .port = TEGRA_CAMERA_PORT_CSI_A,
246 static struct soc_camera_link imx135_iclink = {
247 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
248 .board_info = &ardbeg_imx135_camera_i2c_device,
249 .module_name = "imx135_v4l2",
251 .power = ardbeg_imx135_power,
252 .priv = &ardbeg_imx135_camera_platform_data,
255 static struct platform_device ardbeg_imx135_soc_camera_device = {
256 .name = "soc-camera-pdrv",
259 .platform_data = &imx135_iclink,
264 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
265 static int ardbeg_ar0261_power(struct device *dev, int enable)
270 struct ar0261_platform_data ardbeg_ar0261_data;
272 static struct i2c_board_info ardbeg_ar0261_camera_i2c_device = {
273 I2C_BOARD_INFO("ar0261_v4l2", 0x36),
274 .platform_data = &ardbeg_ar0261_data,
277 static struct tegra_camera_platform_data ardbeg_ar0261_camera_platform_data = {
280 .port = TEGRA_CAMERA_PORT_CSI_C,
285 static struct soc_camera_link ar0261_iclink = {
286 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
287 .board_info = &ardbeg_ar0261_camera_i2c_device,
288 .module_name = "ar0261_v4l2",
290 .power = ardbeg_ar0261_power,
291 .priv = &ardbeg_ar0261_camera_platform_data,
294 static struct platform_device ardbeg_ar0261_soc_camera_device = {
295 .name = "soc-camera-pdrv",
298 .platform_data = &ar0261_iclink,
303 static struct regulator *ardbeg_vcmvdd;
305 static int ardbeg_get_extra_regulators(void)
307 if (!ardbeg_vcmvdd) {
308 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
309 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
310 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
311 __func__, PTR_ERR(ardbeg_vcmvdd));
312 regulator_put(ardbeg_vcmvdd);
313 ardbeg_vcmvdd = NULL;
321 static struct tegra_io_dpd csia_io = {
323 .io_dpd_reg_index = 0,
327 static struct tegra_io_dpd csib_io = {
329 .io_dpd_reg_index = 0,
333 static struct tegra_io_dpd csie_io = {
335 .io_dpd_reg_index = 1,
339 static int ardbeg_ar0330_front_power_on(struct ar0330_power_rail *pw)
343 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
346 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
347 tegra_io_dpd_disable(&csie_io);
349 gpio_set_value(CAM2_PWDN, 0);
351 err = regulator_enable(pw->iovdd);
353 goto ar0330_front_iovdd_fail;
355 usleep_range(1000, 1100);
356 err = regulator_enable(pw->avdd);
358 goto ar0330_front_avdd_fail;
361 gpio_set_value(CAM2_PWDN, 1);
364 ar0330_front_avdd_fail:
365 regulator_disable(pw->iovdd);
367 ar0330_front_iovdd_fail:
368 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
369 tegra_io_dpd_enable(&csie_io);
370 pr_err("%s failed.\n", __func__);
374 static int ardbeg_ar0330_front_power_off(struct ar0330_power_rail *pw)
376 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
377 /* put CSIE IOs into DPD mode to
378 * save additional power for ardbeg
380 tegra_io_dpd_enable(&csie_io);
384 gpio_set_value(CAM2_PWDN, 0);
388 regulator_disable(pw->iovdd);
389 regulator_disable(pw->avdd);
390 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
391 tegra_io_dpd_enable(&csie_io);
395 struct ar0330_platform_data ardbeg_ar0330_front_data = {
396 .power_on = ardbeg_ar0330_front_power_on,
397 .power_off = ardbeg_ar0330_front_power_off,
398 .dev_name = "ar0330.1",
399 .mclk_name = "mclk2",
402 static int ardbeg_ar0330_power_on(struct ar0330_power_rail *pw)
406 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
409 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
410 tegra_io_dpd_disable(&csia_io);
411 tegra_io_dpd_disable(&csib_io);
413 gpio_set_value(CAM1_PWDN, 0);
415 err = regulator_enable(pw->iovdd);
417 goto ar0330_iovdd_fail;
419 usleep_range(1000, 1100);
420 err = regulator_enable(pw->avdd);
422 goto ar0330_avdd_fail;
425 gpio_set_value(CAM1_PWDN, 1);
429 regulator_disable(pw->iovdd);
432 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
433 tegra_io_dpd_enable(&csia_io);
434 tegra_io_dpd_enable(&csib_io);
435 pr_err("%s failed.\n", __func__);
439 static int ardbeg_ar0330_power_off(struct ar0330_power_rail *pw)
441 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
442 /* put CSIE IOs into DPD mode to
443 * save additional power for ardbeg
445 tegra_io_dpd_enable(&csia_io);
446 tegra_io_dpd_enable(&csib_io);
450 gpio_set_value(CAM1_PWDN, 0);
454 regulator_disable(pw->iovdd);
455 regulator_disable(pw->avdd);
456 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
457 tegra_io_dpd_enable(&csia_io);
458 tegra_io_dpd_enable(&csib_io);
462 struct ar0330_platform_data ardbeg_ar0330_data = {
463 .power_on = ardbeg_ar0330_power_on,
464 .power_off = ardbeg_ar0330_power_off,
465 .dev_name = "ar0330",
468 static int ardbeg_ov4689_power_on(struct ov4689_power_rail *pw)
470 pr_info("%s: ++\n", __func__);
471 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
472 tegra_io_dpd_disable(&csia_io);
473 tegra_io_dpd_disable(&csib_io);
475 gpio_set_value(TEGRA_GPIO_PBB5, 0);
476 usleep_range(10, 20);
477 gpio_set_value(TEGRA_GPIO_PBB5, 1);
478 usleep_range(820, 1000);
483 static int ardbeg_ov4689_power_off(struct ov4689_power_rail *pw)
485 pr_info("%s: ++\n", __func__);
487 gpio_set_value(TEGRA_GPIO_PBB5, 0);
489 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
490 tegra_io_dpd_enable(&csia_io);
491 tegra_io_dpd_enable(&csib_io);
496 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
500 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
503 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
504 tegra_io_dpd_disable(&csie_io);
506 if (ardbeg_get_extra_regulators())
507 goto ardbeg_ar0261_poweron_fail;
509 gpio_set_value(CAM_RSTN, 0);
510 gpio_set_value(CAM_AF_PWDN, 1);
513 err = regulator_enable(ardbeg_vcmvdd);
515 goto ar0261_vcm_fail;
517 err = regulator_enable(pw->dvdd);
519 goto ar0261_dvdd_fail;
521 err = regulator_enable(pw->avdd);
523 goto ar0261_avdd_fail;
525 err = regulator_enable(pw->iovdd);
527 goto ar0261_iovdd_fail;
530 gpio_set_value(CAM2_PWDN, 1);
532 gpio_set_value(CAM_RSTN, 1);
536 regulator_disable(pw->dvdd);
539 regulator_disable(pw->avdd);
542 regulator_disable(ardbeg_vcmvdd);
545 pr_err("%s vcmvdd failed.\n", __func__);
548 ardbeg_ar0261_poweron_fail:
549 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
550 tegra_io_dpd_enable(&csie_io);
551 pr_err("%s failed.\n", __func__);
555 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
557 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
559 /* put CSIE IOs into DPD mode to
560 * save additional power for ardbeg
562 tegra_io_dpd_enable(&csie_io);
566 gpio_set_value(CAM_RSTN, 0);
570 regulator_disable(pw->iovdd);
571 regulator_disable(pw->dvdd);
572 regulator_disable(pw->avdd);
573 regulator_disable(ardbeg_vcmvdd);
574 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
575 tegra_io_dpd_enable(&csie_io);
579 struct ar0261_platform_data ardbeg_ar0261_data = {
580 .power_on = ardbeg_ar0261_power_on,
581 .power_off = ardbeg_ar0261_power_off,
582 .mclk_name = "mclk2",
585 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
588 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
589 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
590 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
591 __func__, PTR_ERR(pw->ext_reg1));
598 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
599 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
600 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
601 __func__, PTR_ERR(pw->ext_reg2));
610 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
614 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
617 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
618 tegra_io_dpd_disable(&csia_io);
619 tegra_io_dpd_disable(&csib_io);
621 if (ardbeg_imx135_get_extra_regulators(pw))
622 goto imx135_poweron_fail;
624 err = regulator_enable(pw->ext_reg1);
626 goto imx135_ext_reg1_fail;
628 err = regulator_enable(pw->ext_reg2);
630 goto imx135_ext_reg2_fail;
633 gpio_set_value(CAM_AF_PWDN, 1);
634 gpio_set_value(CAM1_PWDN, 0);
635 usleep_range(10, 20);
637 err = regulator_enable(pw->avdd);
639 goto imx135_avdd_fail;
641 err = regulator_enable(pw->iovdd);
643 goto imx135_iovdd_fail;
646 gpio_set_value(CAM1_PWDN, 1);
648 usleep_range(300, 310);
654 regulator_disable(pw->avdd);
658 regulator_disable(pw->ext_reg2);
660 imx135_ext_reg2_fail:
662 regulator_disable(pw->ext_reg1);
663 gpio_set_value(CAM_AF_PWDN, 0);
665 imx135_ext_reg1_fail:
667 tegra_io_dpd_enable(&csia_io);
668 tegra_io_dpd_enable(&csib_io);
669 pr_err("%s failed.\n", __func__);
673 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
675 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
676 tegra_io_dpd_enable(&csia_io);
677 tegra_io_dpd_enable(&csib_io);
681 regulator_disable(pw->iovdd);
682 regulator_disable(pw->avdd);
684 regulator_disable(pw->ext_reg1);
685 regulator_disable(pw->ext_reg2);
687 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
688 tegra_io_dpd_enable(&csia_io);
689 tegra_io_dpd_enable(&csib_io);
693 static int ardbeg_imx179_power_on(struct imx179_power_rail *pw)
697 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
700 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
701 tegra_io_dpd_disable(&csia_io);
702 tegra_io_dpd_disable(&csib_io);
704 gpio_set_value(CAM_AF_PWDN, 1);
705 gpio_set_value(CAM_RSTN, 0);
706 gpio_set_value(CAM1_PWDN, 0);
707 usleep_range(10, 20);
709 err = regulator_enable(pw->avdd);
711 goto imx179_avdd_fail;
713 err = regulator_enable(pw->iovdd);
715 goto imx179_iovdd_fail;
717 err = regulator_enable(pw->dvdd);
719 goto imx179_dvdd_fail;
722 gpio_set_value(CAM_RSTN, 1);
724 usleep_range(300, 310);
730 regulator_disable(pw->iovdd);
733 regulator_disable(pw->avdd);
736 tegra_io_dpd_enable(&csia_io);
737 tegra_io_dpd_enable(&csib_io);
738 pr_err("%s failed.\n", __func__);
742 static int ardbeg_imx179_power_off(struct imx179_power_rail *pw)
744 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
745 tegra_io_dpd_enable(&csia_io);
746 tegra_io_dpd_enable(&csib_io);
750 regulator_disable(pw->dvdd);
751 regulator_disable(pw->iovdd);
752 regulator_disable(pw->avdd);
754 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
755 tegra_io_dpd_enable(&csia_io);
756 tegra_io_dpd_enable(&csib_io);
760 struct imx135_platform_data ardbeg_imx135_data = {
769 .power_on = ardbeg_imx135_power_on,
770 .power_off = ardbeg_imx135_power_off,
773 struct imx179_platform_data ardbeg_imx179_data = {
781 .power_on = ardbeg_imx179_power_on,
782 .power_off = ardbeg_imx179_power_off,
785 struct ov4689_platform_data ardbeg_ov4689_data = {
793 .power_on = ardbeg_ov4689_power_on,
794 .power_off = ardbeg_ov4689_power_off,
797 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
800 pr_info("%s\n", __func__);
802 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
805 err = regulator_enable(pw->vdd);
807 goto dw9718_vdd_fail;
809 err = regulator_enable(pw->vdd_i2c);
811 goto dw9718_i2c_fail;
813 err = regulator_enable(pw->vana);
815 goto dw9718_ana_fail;
817 usleep_range(1000, 1020);
819 /* return 1 to skip the in-driver power_on sequence */
820 pr_debug("%s --\n", __func__);
824 regulator_disable(pw->vdd_i2c);
827 regulator_disable(pw->vdd);
830 pr_err("%s FAILED\n", __func__);
834 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
836 pr_info("%s\n", __func__);
838 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
841 regulator_disable(pw->vdd);
842 regulator_disable(pw->vdd_i2c);
843 regulator_disable(pw->vana);
848 static u16 dw9718_devid;
849 static int ardbeg_dw9718_detect(void *buf, size_t size)
851 dw9718_devid = 0x9718;
855 static struct nvc_focus_cap dw9718_cap = {
857 .slew_rate = 0x3A200C,
859 .focus_infinity = 200,
863 static struct dw9718_platform_data ardbeg_dw9718_data = {
864 .cfg = NVC_CFG_NODEV,
867 .dev_name = "focuser",
869 .power_on = ardbeg_dw9718_power_on,
870 .power_off = ardbeg_dw9718_power_off,
871 .detect = ardbeg_dw9718_detect,
874 static struct as364x_platform_data ardbeg_as3648_data = {
877 .max_total_current_mA = 1000,
878 .max_peak_current_mA = 600,
879 .max_torch_current_mA = 600,
880 .vin_low_v_run_mV = 3070,
884 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
885 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
889 .gpio_strobe = CAM_FLASH_STROBE,
892 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
896 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
899 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
900 tegra_io_dpd_disable(&csie_io);
902 gpio_set_value(CAM2_PWDN, 0);
903 usleep_range(1000, 1020);
905 err = regulator_enable(pw->avdd);
907 goto ov7695_avdd_fail;
908 usleep_range(300, 320);
910 err = regulator_enable(pw->iovdd);
912 goto ov7695_iovdd_fail;
913 usleep_range(1000, 1020);
915 gpio_set_value(CAM2_PWDN, 1);
916 usleep_range(1000, 1020);
921 regulator_disable(pw->avdd);
924 gpio_set_value(CAM_RSTN, 0);
925 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
926 tegra_io_dpd_enable(&csie_io);
930 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
932 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
933 /* put CSIE IOs into DPD mode to
934 * save additional power for ardbeg
936 tegra_io_dpd_enable(&csie_io);
939 usleep_range(100, 120);
941 gpio_set_value(CAM2_PWDN, 0);
942 usleep_range(100, 120);
944 regulator_disable(pw->iovdd);
945 usleep_range(100, 120);
947 regulator_disable(pw->avdd);
949 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
950 tegra_io_dpd_enable(&csie_io);
954 struct ov7695_platform_data ardbeg_ov7695_pdata = {
955 .power_on = ardbeg_ov7695_power_on,
956 .power_off = ardbeg_ov7695_power_off,
957 .mclk_name = "mclk2",
960 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
963 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
966 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
967 tegra_io_dpd_disable(&csie_io);
969 gpio_set_value(CAM_RSTN, 0);
970 gpio_set_value(CAM2_PWDN, 1);
971 usleep_range(1000, 1020);
973 err = regulator_enable(pw->iovdd);
975 goto mt9m114_iovdd_fail;
977 err = regulator_enable(pw->avdd);
979 goto mt9m114_avdd_fail;
981 usleep_range(1000, 1020);
982 gpio_set_value(CAM_RSTN, 1);
983 gpio_set_value(CAM2_PWDN, 0);
984 usleep_range(1000, 1020);
986 /* return 1 to skip the in-driver power_on swquence */
990 regulator_disable(pw->iovdd);
993 gpio_set_value(CAM_RSTN, 0);
994 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
995 tegra_io_dpd_enable(&csie_io);
999 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
1001 if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
1002 /* put CSIE IOs into DPD mode to
1003 * save additional power for ardbeg
1005 tegra_io_dpd_enable(&csie_io);
1009 usleep_range(100, 120);
1010 gpio_set_value(CAM_RSTN, 0);
1011 usleep_range(100, 120);
1012 regulator_disable(pw->avdd);
1013 usleep_range(100, 120);
1014 regulator_disable(pw->iovdd);
1016 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1017 tegra_io_dpd_enable(&csie_io);
1021 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
1022 .power_on = ardbeg_mt9m114_power_on,
1023 .power_off = ardbeg_mt9m114_power_off,
1024 .mclk_name = "mclk2",
1028 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
1032 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1035 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
1036 tegra_io_dpd_disable(&csia_io);
1037 tegra_io_dpd_disable(&csib_io);
1039 if (ardbeg_get_extra_regulators())
1040 goto ov5693_poweron_fail;
1042 gpio_set_value(CAM1_PWDN, 0);
1043 usleep_range(10, 20);
1045 err = regulator_enable(pw->avdd);
1047 goto ov5693_avdd_fail;
1049 err = regulator_enable(pw->dovdd);
1051 goto ov5693_iovdd_fail;
1054 gpio_set_value(CAM1_PWDN, 1);
1056 err = regulator_enable(ardbeg_vcmvdd);
1058 goto ov5693_vcmvdd_fail;
1060 usleep_range(1000, 1110);
1065 regulator_disable(pw->dovdd);
1068 regulator_disable(pw->avdd);
1071 gpio_set_value(CAM1_PWDN, 0);
1073 ov5693_poweron_fail:
1074 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1075 tegra_io_dpd_enable(&csia_io);
1076 tegra_io_dpd_enable(&csib_io);
1077 pr_err("%s FAILED\n", __func__);
1081 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
1083 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1084 /* put CSIA/B IOs into DPD mode to
1085 * save additional power for ardbeg
1087 tegra_io_dpd_enable(&csia_io);
1088 tegra_io_dpd_enable(&csib_io);
1092 usleep_range(21, 25);
1093 gpio_set_value(CAM1_PWDN, 0);
1096 regulator_disable(ardbeg_vcmvdd);
1097 regulator_disable(pw->dovdd);
1098 regulator_disable(pw->avdd);
1100 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1101 tegra_io_dpd_enable(&csia_io);
1102 tegra_io_dpd_enable(&csib_io);
1106 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
1107 { OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0, },
1110 #define NV_GUID(a, b, c, d, e, f, g, h) \
1111 ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
1112 (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
1113 (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
1114 (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
1116 static struct nvc_imager_cap ov5693_cap = {
1117 .identifier = "OV5693",
1118 .sensor_nvc_interface = 3,
1119 .pixel_types[0] = 0x101,
1122 .initial_clock_rate_khz = 6000,
1123 .clock_profiles[0] = {
1124 .external_clock_khz = 24000,
1125 .clock_multiplier = 8000000, /* value * 1000000 */
1127 .clock_profiles[1] = {
1128 .external_clock_khz = 0,
1129 .clock_multiplier = 0,
1136 .virtual_channel_id = 0,
1137 .discontinuous_clk_mode = 1,
1138 .cil_threshold_settle = 0,
1139 .min_blank_time_width = 16,
1140 .min_blank_time_height = 16,
1141 .preferred_mode_index = 0,
1143 NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
1145 NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
1146 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1147 .flash_control_enabled = 0,
1148 .adjustable_flash_timing = 0,
1153 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
1154 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
1155 .gpio = ov5693_gpio_pdata,
1156 .power_on = ardbeg_ov5693_power_on,
1157 .power_off = ardbeg_ov5693_power_off,
1158 .dev_name = "ov5693",
1160 .mclk_name = "mclk",
1162 .avdd = "avdd_ov5693",
1169 static int ardbeg_ov5693_front_power_on(struct ov5693_power_rail *pw)
1173 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1176 if (ardbeg_get_extra_regulators())
1177 goto ov5693_front_poweron_fail;
1179 gpio_set_value(CAM2_PWDN, 0);
1180 gpio_set_value(CAM_RSTN, 0);
1181 usleep_range(10, 20);
1183 err = regulator_enable(pw->avdd);
1185 goto ov5693_front_avdd_fail;
1187 err = regulator_enable(pw->dovdd);
1189 goto ov5693_front_iovdd_fail;
1192 gpio_set_value(CAM2_PWDN, 1);
1193 gpio_set_value(CAM_RSTN, 1);
1195 err = regulator_enable(ardbeg_vcmvdd);
1197 goto ov5693_front_vcmvdd_fail;
1199 usleep_range(1000, 1110);
1203 ov5693_front_vcmvdd_fail:
1204 regulator_disable(pw->dovdd);
1206 ov5693_front_iovdd_fail:
1207 regulator_disable(pw->avdd);
1209 ov5693_front_avdd_fail:
1210 gpio_set_value(CAM2_PWDN, 0);
1211 gpio_set_value(CAM_RSTN, 0);
1213 ov5693_front_poweron_fail:
1214 pr_err("%s FAILED\n", __func__);
1218 static int ardbeg_ov5693_front_power_off(struct ov5693_power_rail *pw)
1220 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1224 usleep_range(21, 25);
1225 gpio_set_value(CAM2_PWDN, 0);
1226 gpio_set_value(CAM_RSTN, 0);
1229 regulator_disable(ardbeg_vcmvdd);
1230 regulator_disable(pw->dovdd);
1231 regulator_disable(pw->avdd);
1236 static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
1237 { OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0, },
1238 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
1241 static struct nvc_imager_cap ov5693_front_cap = {
1242 .identifier = "OV5693.1",
1243 .sensor_nvc_interface = 4,
1244 .pixel_types[0] = 0x101,
1247 .initial_clock_rate_khz = 6000,
1248 .clock_profiles[0] = {
1249 .external_clock_khz = 24000,
1250 .clock_multiplier = 8000000, /* value * 1000000 */
1252 .clock_profiles[1] = {
1253 .external_clock_khz = 0,
1254 .clock_multiplier = 0,
1261 .virtual_channel_id = 0,
1262 .discontinuous_clk_mode = 1,
1263 .cil_threshold_settle = 0,
1264 .min_blank_time_width = 16,
1265 .min_blank_time_height = 16,
1266 .preferred_mode_index = 0,
1269 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1270 .flash_control_enabled = 0,
1271 .adjustable_flash_timing = 0,
1275 static struct ov5693_platform_data ardbeg_ov5693_front_pdata = {
1276 .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
1277 .gpio = ov5693_front_gpio_pdata,
1278 .power_on = ardbeg_ov5693_front_power_on,
1279 .power_off = ardbeg_ov5693_front_power_off,
1280 .dev_name = "ov5693.1",
1281 .mclk_name = "mclk2",
1282 .cap = &ov5693_front_cap,
1291 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
1295 pr_info("%s\n", __func__);
1296 gpio_set_value_cansleep(pdata->gpio, 1);
1297 pdata->pwr_dev = AD5823_PWR_DEV_ON;
1302 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
1304 pr_info("%s\n", __func__);
1305 gpio_set_value_cansleep(pdata->gpio, 0);
1306 pdata->pwr_dev = AD5823_PWR_DEV_OFF;
1311 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
1312 .gpio = CAM_AF_PWDN,
1313 .power_on = ardbeg_ad5823_power_on,
1314 .power_off = ardbeg_ad5823_power_off,
1317 static struct camera_data_blob ardbeg_camera_lut[] = {
1318 {"ardbeg_imx135_pdata", &ardbeg_imx135_data},
1319 {"ardbeg_dw9718_pdata", &ardbeg_dw9718_data},
1320 {"ardbeg_ar0261_pdata", &ardbeg_ar0261_data},
1321 {"ardbeg_mt9m114_pdata", &ardbeg_mt9m114_pdata},
1322 {"ardbeg_ov5693_pdata", &ardbeg_ov5693_pdata},
1323 {"ardbeg_ad5823_pdata", &ardbeg_ad5823_pdata},
1324 {"ardbeg_as3648_pdata", &ardbeg_as3648_data},
1325 {"ardbeg_ov7695_pdata", &ardbeg_ov7695_pdata},
1326 {"ardbeg_ov5693f_pdata", &ardbeg_ov5693_front_pdata},
1327 {"ardbeg_ar0330_pdata", &ardbeg_ar0330_data},
1328 {"ardbeg_ar0330_front_pdata", &ardbeg_ar0330_front_data},
1329 {"ardbeg_ov4689_pdata", &ardbeg_ov4689_data},
1333 void __init ardbeg_camera_auxdata(void *data)
1335 struct of_dev_auxdata *aux_lut = data;
1336 while (aux_lut && aux_lut->compatible) {
1337 if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
1338 pr_info("%s: update camera lookup table.\n", __func__);
1339 aux_lut->platform_data = ardbeg_camera_lut;
1345 static int ardbeg_camera_init(void)
1347 struct board_info board_info;
1349 pr_debug("%s: ++\n", __func__);
1350 tegra_get_board_info(&board_info);
1352 /* put CSIA/B/C/D/E IOs into DPD mode to
1353 * save additional power for ardbeg
1355 tegra_io_dpd_enable(&csia_io);
1356 tegra_io_dpd_enable(&csib_io);
1357 tegra_io_dpd_enable(&csie_io);
1359 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
1360 platform_device_register(&ardbeg_soc_camera_device);
1363 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
1364 platform_device_register(&ardbeg_imx135_soc_camera_device);
1367 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
1368 platform_device_register(&ardbeg_ar0261_soc_camera_device);
1373 static struct pid_thermal_gov_params cpu_pid_params = {
1374 .max_err_temp = 4000,
1375 .max_err_gain = 1000,
1380 .up_compensation = 15,
1381 .down_compensation = 15,
1384 static struct thermal_zone_params cpu_tzp = {
1385 .governor_name = "pid_thermal_gov",
1386 .governor_params = &cpu_pid_params,
1389 static struct thermal_zone_params board_tzp = {
1390 .governor_name = "pid_thermal_gov"
1393 static struct throttle_table cpu_throttle_table[] = {
1394 /* CPU_THROT_LOW cannot be used by other than CPU */
1395 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1396 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1397 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1398 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1399 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1400 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1401 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1402 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1403 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1404 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1405 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1406 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1407 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1408 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1409 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1410 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1411 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1412 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1413 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1414 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1415 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1416 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1417 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1418 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1419 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1420 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1421 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1422 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1423 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1424 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1425 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1426 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1427 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1428 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1429 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1430 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1431 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1432 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1433 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1434 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1435 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1436 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1437 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1438 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1439 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1440 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1441 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1442 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1443 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1444 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1445 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1446 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1447 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1448 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1449 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1450 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1451 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1452 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1453 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1454 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1455 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1456 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1457 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1458 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1459 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1460 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1461 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1462 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1463 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1464 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1465 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1466 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1467 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1468 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1469 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1470 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1471 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1472 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1473 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1474 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1475 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1476 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1477 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1478 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1481 static struct balanced_throttle cpu_throttle = {
1482 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1483 .throt_tab = cpu_throttle_table,
1486 static struct throttle_table gpu_throttle_table[] = {
1487 /* CPU_THROT_LOW cannot be used by other than CPU */
1488 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1489 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1490 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1491 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1492 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1493 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1494 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1495 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1496 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1497 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1498 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1499 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1500 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1501 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1502 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1503 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1504 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1505 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1506 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1507 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1508 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1509 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1510 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1511 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1512 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1513 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1514 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1515 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1516 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1517 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1518 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1519 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1520 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1521 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1522 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1523 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1524 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1525 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1526 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1527 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1528 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1529 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1530 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1531 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1532 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1533 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1534 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1535 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1536 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1537 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1538 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1539 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1540 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1541 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1542 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1543 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1544 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1545 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1546 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1547 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1548 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1549 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1550 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1551 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1552 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1553 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1554 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1555 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1556 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1557 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1558 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1559 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1560 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1561 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1562 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1563 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1564 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1565 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1566 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1567 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1568 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1569 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1570 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1571 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1574 static struct balanced_throttle gpu_throttle = {
1575 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1576 .throt_tab = gpu_throttle_table,
1579 /* throttle table that sets all clocks to approximately 50% of their max */
1580 static struct throttle_table emergency_throttle_table[] = {
1581 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1582 { { 1122000, 391000, 288000, 420000, 252000, 396000 } },
1585 static struct balanced_throttle emergency_throttle = {
1586 .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
1587 .throt_tab = emergency_throttle_table,
1590 static int __init ardbeg_balanced_throttle_init(void)
1592 if (of_machine_is_compatible("nvidia,ardbeg") ||
1593 of_machine_is_compatible("nvidia,norrin") ||
1594 of_machine_is_compatible("nvidia,bowmore") ||
1595 of_machine_is_compatible("nvidia,tn8")) {
1597 if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
1598 pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
1599 if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
1600 pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
1601 if (!balanced_throttle_register(&emergency_throttle,
1602 "emergency-balanced"))
1603 pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
1608 late_initcall(ardbeg_balanced_throttle_init);
1610 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1611 static struct thermal_trip_info skin_trips[] = {
1613 .cdev_type = "skin-balanced",
1615 .trip_type = THERMAL_TRIP_PASSIVE,
1616 .upper = THERMAL_NO_LIMIT,
1617 .lower = THERMAL_NO_LIMIT,
1622 static struct therm_est_subdevice skin_devs[] = {
1624 .dev_data = "Tdiode_tegra",
1634 .dev_data = "Tboard_tegra",
1645 static struct therm_est_subdevice tn8ffd_skin_devs[] = {
1647 .dev_data = "Tdiode",
1657 .dev_data = "Tboard",
1668 static struct therm_est_subdevice tn8ffd_t132_skin_devs[] = {
1670 .dev_data = "Tdiode",
1680 .dev_data = "Tboard",
1691 static struct pid_thermal_gov_params skin_pid_params = {
1692 .max_err_temp = 4000,
1693 .max_err_gain = 1000,
1698 .up_compensation = 15,
1699 .down_compensation = 15,
1702 static struct thermal_zone_params skin_tzp = {
1703 .governor_name = "pid_thermal_gov",
1704 .governor_params = &skin_pid_params,
1707 static struct therm_est_data skin_data = {
1708 .num_trips = ARRAY_SIZE(skin_trips),
1709 .trips = skin_trips,
1710 .polling_period = 1100,
1711 .passive_delay = 15000,
1718 static struct throttle_table skin_throttle_table[] = {
1719 /* CPU_THROT_LOW cannot be used by other than CPU */
1720 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1721 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1722 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1723 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1724 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1725 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1726 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1727 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1728 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1729 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1730 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1731 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1732 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1733 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1734 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1735 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1736 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1737 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1738 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1739 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1740 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1741 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1742 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1743 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1744 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1745 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1746 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1747 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1748 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1749 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1750 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1751 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1752 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1753 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1754 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1755 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1756 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1757 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1758 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1759 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1760 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1761 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1762 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1763 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1764 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1765 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1766 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1767 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1768 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1769 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1770 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1771 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1772 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1773 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1774 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1775 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1776 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1777 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1778 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1779 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1780 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1781 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1782 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1783 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1784 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1785 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1786 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1787 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1788 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1789 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1790 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1791 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1792 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1793 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1794 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1795 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1796 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1797 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1798 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1799 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1800 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1801 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1802 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1803 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1806 static struct balanced_throttle skin_throttle = {
1807 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1808 .throt_tab = skin_throttle_table,
1811 static int __init ardbeg_skin_init(void)
1813 struct board_info board_info;
1815 if (of_machine_is_compatible("nvidia,ardbeg") ||
1816 of_machine_is_compatible("nvidia,norrin") ||
1817 of_machine_is_compatible("nvidia,bowmore") ||
1818 of_machine_is_compatible("nvidia,tn8")) {
1820 tegra_get_board_info(&board_info);
1822 if (board_info.board_id == BOARD_P1761 &&
1823 board_info.fab == BOARD_FAB_D) {
1824 skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
1825 skin_data.devs = tn8ffd_t132_skin_devs;
1826 skin_data.toffset = 708;
1827 } else if (board_info.board_id == BOARD_P1761 ||
1828 board_info.board_id == BOARD_E1784 ||
1829 board_info.board_id == BOARD_E1971 ||
1830 board_info.board_id == BOARD_E1991 ||
1831 board_info.board_id == BOARD_E1922) {
1832 skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
1833 skin_data.devs = tn8ffd_skin_devs;
1834 skin_data.toffset = 4034;
1836 skin_data.ndevs = ARRAY_SIZE(skin_devs);
1837 skin_data.devs = skin_devs;
1838 skin_data.toffset = 9793;
1841 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1842 platform_device_register(&tegra_skin_therm_est_device);
1844 if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
1845 pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
1850 late_initcall(ardbeg_skin_init);
1853 static struct nct1008_platform_data ardbeg_nct72_pdata = {
1854 .loc_name = "tegra",
1855 .supported_hwrev = true,
1856 .conv_rate = 0x06, /* 4Hz conversion rate */
1858 .extended_range = true,
1863 .shutdown_limit = 120, /* C */
1864 .passive_delay = 1000,
1868 .cdev_type = "therm_est_activ",
1870 .trip_type = THERMAL_TRIP_ACTIVE,
1872 .upper = THERMAL_NO_LIMIT,
1873 .lower = THERMAL_NO_LIMIT,
1880 .shutdown_limit = 95, /* C */
1881 .passive_delay = 1000,
1885 .cdev_type = "shutdown_warning",
1887 .trip_type = THERMAL_TRIP_PASSIVE,
1888 .upper = THERMAL_NO_LIMIT,
1889 .lower = THERMAL_NO_LIMIT,
1893 .cdev_type = "cpu-balanced",
1895 .trip_type = THERMAL_TRIP_PASSIVE,
1896 .upper = THERMAL_NO_LIMIT,
1897 .lower = THERMAL_NO_LIMIT,
1906 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1907 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
1910 .supported_hwrev = true,
1911 .conv_rate = 0x06, /* 4Hz conversion rate */
1913 .extended_range = true,
1917 .shutdown_limit = 95, /* C */
1922 .shutdown_limit = 85, /* C */
1923 .passive_delay = 10000,
1924 .polling_delay = 1000,
1929 .cdev_type = "skin-balanced",
1931 .trip_type = THERMAL_TRIP_PASSIVE,
1932 .upper = THERMAL_NO_LIMIT,
1933 .lower = THERMAL_NO_LIMIT,
1942 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
1944 I2C_BOARD_INFO("nct72", 0x4c),
1945 .platform_data = &ardbeg_nct72_pdata,
1948 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1950 I2C_BOARD_INFO("nct72", 0x4d),
1951 .platform_data = &ardbeg_nct72_tskin_pdata,
1957 static int ardbeg_nct72_init(void)
1959 int nct72_port = TEGRA_GPIO_PI6;
1962 struct thermal_trip_info *trip_state;
1963 struct board_info board_info;
1965 tegra_get_board_info(&board_info);
1966 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
1967 if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
1968 (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
1969 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit += 20;
1970 for (i = 0; i < ardbeg_nct72_pdata.sensors[EXT].num_trips;
1972 trip_state = &ardbeg_nct72_pdata.sensors[EXT].trips[i];
1973 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
1974 THERMAL_NAME_LENGTH)) {
1975 trip_state->cdev_type = "_none_";
1980 tegra_platform_edp_init(
1981 ardbeg_nct72_pdata.sensors[EXT].trips,
1982 &ardbeg_nct72_pdata.sensors[EXT].num_trips,
1983 12000); /* edp temperature margin */
1984 tegra_add_cpu_vmax_trips(
1985 ardbeg_nct72_pdata.sensors[EXT].trips,
1986 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1987 tegra_add_tgpu_trips(
1988 ardbeg_nct72_pdata.sensors[EXT].trips,
1989 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1991 ardbeg_nct72_pdata.sensors[EXT].trips,
1992 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1993 tegra_add_core_vmax_trips(
1994 ardbeg_nct72_pdata.sensors[EXT].trips,
1995 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1998 /* vmin trips are bound to soctherm on norrin */
1999 if (!(board_info.board_id == BOARD_PM374))
2000 tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
2001 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2003 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
2005 ret = gpio_request(nct72_port, "temp_alert");
2009 ret = gpio_direction_input(nct72_port);
2011 pr_info("%s: calling gpio_free(nct72_port)", __func__);
2012 gpio_free(nct72_port);
2015 /* norrin has thermal sensor on GEN1-I2C i.e. instance 0 */
2016 if (board_info.board_id == BOARD_PM374)
2017 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2018 1); /* only register device[0] */
2019 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
2020 else if (board_info.board_id == BOARD_PM358 ||
2021 board_info.board_id == BOARD_PM359 ||
2022 board_info.board_id == BOARD_PM370 ||
2023 board_info.board_id == BOARD_PM363)
2024 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2025 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2026 else if (board_info.board_id == BOARD_PM375 ||
2027 board_info.board_id == BOARD_PM377) {
2028 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 100;
2029 ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 95;
2030 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2031 1); /* only register device[0] */
2034 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2035 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2040 struct ntc_thermistor_adc_table {
2041 int temp; /* degree C */
2045 static struct ntc_thermistor_adc_table tn8_thermistor_table[] = {
2046 { -40, 2578 }, { -39, 2577 }, { -38, 2576 }, { -37, 2575 },
2047 { -36, 2574 }, { -35, 2573 }, { -34, 2572 }, { -33, 2571 },
2048 { -32, 2569 }, { -31, 2568 }, { -30, 2567 }, { -29, 2565 },
2049 { -28, 2563 }, { -27, 2561 }, { -26, 2559 }, { -25, 2557 },
2050 { -24, 2555 }, { -23, 2553 }, { -22, 2550 }, { -21, 2548 },
2051 { -20, 2545 }, { -19, 2542 }, { -18, 2539 }, { -17, 2536 },
2052 { -16, 2532 }, { -15, 2529 }, { -14, 2525 }, { -13, 2521 },
2053 { -12, 2517 }, { -11, 2512 }, { -10, 2507 }, { -9, 2502 },
2054 { -8, 2497 }, { -7, 2492 }, { -6, 2486 }, { -5, 2480 },
2055 { -4, 2473 }, { -3, 2467 }, { -2, 2460 }, { -1, 2452 },
2056 { 0, 2445 }, { 1, 2437 }, { 2, 2428 }, { 3, 2419 },
2057 { 4, 2410 }, { 5, 2401 }, { 6, 2391 }, { 7, 2380 },
2058 { 8, 2369 }, { 9, 2358 }, { 10, 2346 }, { 11, 2334 },
2059 { 12, 2322 }, { 13, 2308 }, { 14, 2295 }, { 15, 2281 },
2060 { 16, 2266 }, { 17, 2251 }, { 18, 2236 }, { 19, 2219 },
2061 { 20, 2203 }, { 21, 2186 }, { 22, 2168 }, { 23, 2150 },
2062 { 24, 2131 }, { 25, 2112 }, { 26, 2092 }, { 27, 2072 },
2063 { 28, 2052 }, { 29, 2030 }, { 30, 2009 }, { 31, 1987 },
2064 { 32, 1964 }, { 33, 1941 }, { 34, 1918 }, { 35, 1894 },
2065 { 36, 1870 }, { 37, 1845 }, { 38, 1820 }, { 39, 1795 },
2066 { 40, 1769 }, { 41, 1743 }, { 42, 1717 }, { 43, 1691 },
2067 { 44, 1664 }, { 45, 1637 }, { 46, 1610 }, { 47, 1583 },
2068 { 48, 1555 }, { 49, 1528 }, { 50, 1500 }, { 51, 1472 },
2069 { 52, 1445 }, { 53, 1417 }, { 54, 1390 }, { 55, 1362 },
2070 { 56, 1334 }, { 57, 1307 }, { 58, 1280 }, { 59, 1253 },
2071 { 60, 1226 }, { 61, 1199 }, { 62, 1172 }, { 63, 1146 },
2072 { 64, 1120 }, { 65, 1094 }, { 66, 1069 }, { 67, 1044 },
2073 { 68, 1019 }, { 69, 994 }, { 70, 970 }, { 71, 946 },
2074 { 72, 922 }, { 73, 899 }, { 74, 877 }, { 75, 854 },
2075 { 76, 832 }, { 77, 811 }, { 78, 789 }, { 79, 769 },
2076 { 80, 748 }, { 81, 729 }, { 82, 709 }, { 83, 690 },
2077 { 84, 671 }, { 85, 653 }, { 86, 635 }, { 87, 618 },
2078 { 88, 601 }, { 89, 584 }, { 90, 568 }, { 91, 552 },
2079 { 92, 537 }, { 93, 522 }, { 94, 507 }, { 95, 493 },
2080 { 96, 479 }, { 97, 465 }, { 98, 452 }, { 99, 439 },
2081 { 100, 427 }, { 101, 415 }, { 102, 403 }, { 103, 391 },
2082 { 104, 380 }, { 105, 369 }, { 106, 359 }, { 107, 349 },
2083 { 108, 339 }, { 109, 329 }, { 110, 320 }, { 111, 310 },
2084 { 112, 302 }, { 113, 293 }, { 114, 285 }, { 115, 277 },
2085 { 116, 269 }, { 117, 261 }, { 118, 254 }, { 119, 247 },
2086 { 120, 240 }, { 121, 233 }, { 122, 226 }, { 123, 220 },
2087 { 124, 214 }, { 125, 208 },
2090 static struct ntc_thermistor_adc_table *thermistor_table;
2091 static int thermistor_table_size;
2093 static int gadc_thermal_thermistor_adc_to_temp(
2094 struct gadc_thermal_platform_data *pdata, int val, int val2)
2096 int temp = 0, adc_hi, adc_lo;
2099 for (i = 0; i < thermistor_table_size; i++)
2100 if (val >= thermistor_table[i].adc)
2104 temp = thermistor_table[i].temp * 1000;
2105 } else if (i >= (thermistor_table_size - 1)) {
2106 temp = thermistor_table[thermistor_table_size - 1].temp * 1000;
2108 adc_hi = thermistor_table[i - 1].adc;
2109 adc_lo = thermistor_table[i].adc;
2110 temp = thermistor_table[i].temp * 1000;
2111 temp -= ((val - adc_lo) * 1000 / (adc_hi - adc_lo));
2117 #define TDIODE_PRECISION_MULTIPLIER 1000000000LL
2118 #define TDIODE_MIN_TEMP -25000LL
2119 #define TDIODE_MAX_TEMP 125000LL
2121 static int gadc_thermal_tdiode_adc_to_temp(
2122 struct gadc_thermal_platform_data *pdata, int val, int val2)
2125 * Series resistance cancellation using multi-current ADC measurement.
2126 * diode temp = ((adc2 - k * adc1) - (b2 - k * b1)) / (m2 - k * m1)
2127 * - adc1 : ADC raw with current source 400uA
2128 * - m1, b1 : calculated with current source 400uA
2129 * - adc2 : ADC raw with current source 800uA
2130 * - m2, b2 : calculated with current source 800uA
2131 * - k : 2 (= 800uA / 400uA)
2133 const s64 m1 = -0.00571005 * TDIODE_PRECISION_MULTIPLIER;
2134 const s64 b1 = 2524.29891 * TDIODE_PRECISION_MULTIPLIER;
2135 const s64 m2 = -0.005519811 * TDIODE_PRECISION_MULTIPLIER;
2136 const s64 b2 = 2579.354349 * TDIODE_PRECISION_MULTIPLIER;
2137 s64 temp = TDIODE_PRECISION_MULTIPLIER;
2139 temp *= (s64)((val2) - 2 * (val));
2140 temp -= (b2 - 2 * b1);
2141 temp = div64_s64(temp, (m2 - 2 * m1));
2142 temp = min_t(s64, max_t(s64, temp, TDIODE_MIN_TEMP), TDIODE_MAX_TEMP);
2146 static struct gadc_thermal_platform_data gadc_thermal_thermistor_pdata = {
2147 .iio_channel_name = "thermistor",
2148 .tz_name = "Tboard",
2150 .adc_to_temp = gadc_thermal_thermistor_adc_to_temp,
2152 .polling_delay = 15000,
2156 .cdev_type = "therm_est_activ",
2158 .trip_type = THERMAL_TRIP_ACTIVE,
2160 .upper = THERMAL_NO_LIMIT,
2161 .lower = THERMAL_NO_LIMIT,
2168 static struct gadc_thermal_platform_data gadc_thermal_tdiode_pdata = {
2169 .iio_channel_name = "tdiode",
2170 .tz_name = "Tdiode",
2173 .adc_to_temp = gadc_thermal_tdiode_adc_to_temp,
2176 static struct platform_device gadc_thermal_thermistor = {
2177 .name = "generic-adc-thermal",
2180 .platform_data = &gadc_thermal_thermistor_pdata,
2184 static struct platform_device gadc_thermal_tdiode = {
2185 .name = "generic-adc-thermal",
2188 .platform_data = &gadc_thermal_tdiode_pdata,
2192 static struct platform_device *gadc_thermal_devices[] = {
2193 &gadc_thermal_thermistor,
2194 &gadc_thermal_tdiode,
2197 int __init ardbeg_sensors_init(void)
2199 struct board_info board_info;
2200 tegra_get_board_info(&board_info);
2201 /* PM363 and PM359 don't have mpu 9250 mounted */
2202 /* TN8 sensors use Device Tree */
2203 if (board_info.board_id != BOARD_PM363 &&
2204 board_info.board_id != BOARD_PM359 &&
2205 !of_machine_is_compatible("nvidia,tn8") &&
2206 !of_machine_is_compatible("nvidia,bowmore") &&
2207 board_info.board_id != BOARD_PM375 &&
2208 board_info.board_id != BOARD_PM377)
2210 ardbeg_camera_init();
2212 if (board_info.board_id == BOARD_P1761 ||
2213 board_info.board_id == BOARD_E1784 ||
2214 board_info.board_id == BOARD_E1971 ||
2215 board_info.board_id == BOARD_E1991 ||
2216 board_info.board_id == BOARD_E1922) {
2217 platform_add_devices(gadc_thermal_devices,
2218 ARRAY_SIZE(gadc_thermal_devices));
2219 thermistor_table = &tn8_thermistor_table[0];
2220 thermistor_table_size = ARRAY_SIZE(tn8_thermistor_table);
2222 ardbeg_nct72_init();
2224 #if defined(ARCH_TEGRA_12x_SOC)
2225 /* TN8 and PM359 don't have ALS CM32181 */
2226 if (!of_machine_is_compatible("nvidia,tn8") &&
2227 board_info.board_id != BOARD_PM359 &&
2228 board_info.board_id != BOARD_PM375 &&
2229 board_info.board_id != BOARD_PM377)
2230 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
2231 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));