drivers/pinctrl/pinctrl-tegra.c

   1 /*
   2  * Driver for the NVIDIA Tegra pinmux
   3  *
   4  * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Derived from code:
   7  * Copyright (C) 2010 Google, Inc.
   8  * Copyright (C) 2010 NVIDIA Corporation
   9  * Copyright (C) 2009-2011 ST-Ericsson AB
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  */
  20
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/pinctrl/pinconf.h>
  31 #include <linux/slab.h>
  32 #include <linux/syscore_ops.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/pinctrl/pinctrl-tegra.h>
  35
  36 #include <mach/pinconf-tegra.h>
  37 #include <mach/pinmux-defines.h>
  38
  39 #include "core.h"
  40 #include "pinctrl-tegra.h"
  41
  42 static DEFINE_SPINLOCK(mux_lock);
  43
  44 struct tegra_pmx {
  45         struct device *dev;
  46         struct pinctrl_dev *pctl;
  47
  48         const struct tegra_pinctrl_soc_data *soc;
  49
  50         int nbanks;
  51         void __iomem **regs;
  52         int *regs_size;
  53         unsigned int *reg_base;
  54
  55         u32 *pg_data;
  56         unsigned drive_group_start_index;
  57 };
  58
  59 static struct tegra_pmx *pmx;
  60
  61 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
  62                    unsigned group, unsigned long config);
  63
  64 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  65 {
  66         return readl(pmx->regs[bank] + reg);
  67 }
  68
  69 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  70 {
  71         writel(val, pmx->regs[bank] + reg);
  72 }
  73
  74 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  75 {
  76         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  77
  78         return pmx->soc->ngroups;
  79 }
  80
  81 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  82                                                 unsigned group)
  83 {
  84         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  85
  86         return pmx->soc->groups[group].name;
  87 }
  88
  89 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  90                                         unsigned group,
  91                                         const unsigned **pins,
  92                                         unsigned *num_pins)
  93 {
  94         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  95
  96         *pins = pmx->soc->groups[group].pins;
  97         *num_pins = pmx->soc->groups[group].npins;
  98
  99         return 0;
 100 }
 101
 102 #ifdef CONFIG_DEBUG_FS
 103 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 104                                        struct seq_file *s,
 105                                        unsigned offset)
 106 {
 107         seq_printf(s, " %s", dev_name(pctldev->dev));
 108 }
 109 #endif
 110
 111 static int reserve_map(struct device *dev, struct pinctrl_map **map,
 112                        unsigned *reserved_maps, unsigned *num_maps,
 113                        unsigned reserve)
 114 {
 115         unsigned old_num = *reserved_maps;
 116         unsigned new_num = *num_maps + reserve;
 117         struct pinctrl_map *new_map;
 118
 119         if (old_num >= new_num)
 120                 return 0;
 121
 122         new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
 123         if (!new_map) {
 124                 dev_err(dev, "krealloc(map) failed\n");
 125                 return -ENOMEM;
 126         }
 127
 128         memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
 129
 130         *map = new_map;
 131         *reserved_maps = new_num;
 132
 133         return 0;
 134 }
 135
 136 static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
 137                        unsigned *num_maps, const char *group,
 138                        const char *function)
 139 {
 140         if (WARN_ON(*num_maps == *reserved_maps))
 141                 return -ENOSPC;
 142
 143         (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
 144         (*map)[*num_maps].data.mux.group = group;
 145         (*map)[*num_maps].data.mux.function = function;
 146         (*num_maps)++;
 147
 148         return 0;
 149 }
 150
 151 static int add_map_configs(struct device *dev, struct pinctrl_map **map,
 152                            unsigned *reserved_maps, unsigned *num_maps,
 153                            const char *group, unsigned long *configs,
 154                            unsigned num_configs)
 155 {
 156         unsigned long *dup_configs;
 157
 158         if (WARN_ON(*num_maps == *reserved_maps))
 159                 return -ENOSPC;
 160
 161         dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
 162                               GFP_KERNEL);
 163         if (!dup_configs) {
 164                 dev_err(dev, "kmemdup(configs) failed\n");
 165                 return -ENOMEM;
 166         }
 167
 168         (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 169         (*map)[*num_maps].data.configs.group_or_pin = group;
 170         (*map)[*num_maps].data.configs.configs = dup_configs;
 171         (*map)[*num_maps].data.configs.num_configs = num_configs;
 172         (*num_maps)++;
 173
 174         return 0;
 175 }
 176
 177 static int add_config(struct device *dev, unsigned long **configs,
 178                       unsigned *num_configs, unsigned long config)
 179 {
 180         unsigned old_num = *num_configs;
 181         unsigned new_num = old_num + 1;
 182         unsigned long *new_configs;
 183
 184         new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
 185                                GFP_KERNEL);
 186         if (!new_configs) {
 187                 dev_err(dev, "krealloc(configs) failed\n");
 188                 return -ENOMEM;
 189         }
 190
 191         new_configs[old_num] = config;
 192
 193         *configs = new_configs;
 194         *num_configs = new_num;
 195
 196         return 0;
 197 }
 198
 199 static void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
 200                                       struct pinctrl_map *map,
 201                                       unsigned num_maps)
 202 {
 203         int i;
 204
 205         for (i = 0; i < num_maps; i++)
 206                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 207                         kfree(map[i].data.configs.configs);
 208
 209         kfree(map);
 210 }
 211
 212 static const struct cfg_param {
 213         const char *property;
 214         enum tegra_pinconf_param param;
 215 } cfg_params[] = {
 216         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
 217         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 218         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 219         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 220         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 221         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 222         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
 223         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
 224         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
 225         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 226         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 227         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 228         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 229         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 230         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 231 };
 232
 233 static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
 234                                            struct device_node *np,
 235                                            struct pinctrl_map **map,
 236                                            unsigned *reserved_maps,
 237                                            unsigned *num_maps)
 238 {
 239         int ret, i;
 240         const char *function;
 241         u32 val;
 242         unsigned long config;
 243         unsigned long *configs = NULL;
 244         unsigned num_configs = 0;
 245         unsigned reserve;
 246         struct property *prop;
 247         const char *group;
 248
 249         ret = of_property_read_string(np, "nvidia,function", &function);
 250         if (ret < 0) {
 251                 /* EINVAL=missing, which is fine since it's optional */
 252                 if (ret != -EINVAL)
 253                         dev_err(dev,
 254                                 "could not parse property nvidia,function\n");
 255                 function = NULL;
 256         }
 257
 258         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 259                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 260                 if (!ret) {
 261                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 262                         ret = add_config(dev, &configs, &num_configs, config);
 263                         if (ret < 0)
 264                                 goto exit;
 265                 /* EINVAL=missing, which is fine since it's optional */
 266                 } else if (ret != -EINVAL) {
 267                         dev_err(dev, "could not parse property %s\n",
 268                                 cfg_params[i].property);
 269                 }
 270         }
 271
 272         reserve = 0;
 273         if (function != NULL)
 274                 reserve++;
 275         if (num_configs)
 276                 reserve++;
 277         ret = of_property_count_strings(np, "nvidia,pins");
 278         if (ret < 0) {
 279                 dev_err(dev, "could not parse property nvidia,pins\n");
 280                 goto exit;
 281         }
 282         reserve *= ret;
 283
 284         ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
 285         if (ret < 0)
 286                 goto exit;
 287
 288         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 289                 if (function) {
 290                         ret = add_map_mux(map, reserved_maps, num_maps,
 291                                           group, function);
 292                         if (ret < 0)
 293                                 goto exit;
 294                 }
 295
 296                 if (num_configs) {
 297                         ret = add_map_configs(dev, map, reserved_maps,
 298                                               num_maps, group, configs,
 299                                               num_configs);
 300                         if (ret < 0)
 301                                 goto exit;
 302                 }
 303         }
 304
 305         ret = 0;
 306
 307 exit:
 308         kfree(configs);
 309         return ret;
 310 }
 311
 312 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 313                                         struct device_node *np_config,
 314                                         struct pinctrl_map **map,
 315                                         unsigned *num_maps)
 316 {
 317         unsigned reserved_maps;
 318         struct device_node *np;
 319         int ret;
 320
 321         reserved_maps = 0;
 322         *map = NULL;
 323         *num_maps = 0;
 324
 325         for_each_child_of_node(np_config, np) {
 326                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
 327                                                       &reserved_maps, num_maps);
 328                 if (ret < 0) {
 329                         tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
 330                         return ret;
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 static const struct pinctrl_ops tegra_pinctrl_ops = {
 338         .get_groups_count = tegra_pinctrl_get_groups_count,
 339         .get_group_name = tegra_pinctrl_get_group_name,
 340         .get_group_pins = tegra_pinctrl_get_group_pins,
 341 #ifdef CONFIG_DEBUG_FS
 342         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 343 #endif
 344         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 345         .dt_free_map = tegra_pinctrl_dt_free_map,
 346 };
 347
 348 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 349 {
 350         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 351
 352         return pmx->soc->nfunctions;
 353 }
 354
 355 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 356                                                unsigned function)
 357 {
 358         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 359
 360         return pmx->soc->functions[function].name;
 361 }
 362
 363 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 364                                          unsigned function,
 365                                          const char * const **groups,
 366                                          unsigned * const num_groups)
 367 {
 368         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 369
 370         *groups = pmx->soc->functions[function].groups;
 371         *num_groups = pmx->soc->functions[function].ngroups;
 372
 373         return 0;
 374 }
 375
 376 static int tegra_pinconfig_group_set(struct pinctrl_dev *pctldev,
 377                 unsigned group, unsigned long param, unsigned long arg)
 378 {
 379         unsigned long config;
 380         int ret;
 381
 382         config = TEGRA_PINCONF_PACK(param, arg);
 383         ret = tegra_pinconf_group_set(pctldev, group, config);
 384         if (ret < 0)
 385                 dev_err(pctldev->dev,
 386                         "Pinctrl group %u tristate config failed: %d\n",
 387                         group, ret);
 388         return ret;
 389 }
 390
 391 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned req_function,
 392                                unsigned group)
 393 {
 394         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 395         const struct tegra_pingroup *g;
 396         unsigned function = req_function;
 397         int i;
 398         u32 val;
 399         unsigned long flags;
 400         int ret;
 401
 402         g = &pmx->soc->groups[group];
 403
 404         if (WARN_ON(g->mux_reg < 0))
 405                 return -EINVAL;
 406
 407         /* Last function option is safe option */
 408         if (!req_function)
 409                 function = g->func_safe;
 410
 411         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 412                 if (g->funcs[i] == function)
 413                         break;
 414         }
 415         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 416                 return -EINVAL;
 417
 418         spin_lock_irqsave(&mux_lock, flags);
 419
 420         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 421         val &= ~(0x3 << g->mux_bit);
 422         val |= i << g->mux_bit;
 423         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 424
 425         spin_unlock_irqrestore(&mux_lock, flags);
 426
 427         return 0;
 428 }
 429
 430 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 431                                   unsigned function, unsigned group)
 432 {
 433         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 434         const struct tegra_pingroup *g;
 435         u32 val;
 436         unsigned long flags;
 437         int i;
 438
 439         g = &pmx->soc->groups[group];
 440
 441         if (WARN_ON(g->mux_reg < 0))
 442                 return;
 443
 444         spin_lock_irqsave(&mux_lock, flags);
 445
 446         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 447         val &= ~(0x3 << g->mux_bit);
 448         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 449                 if (g->funcs[i] == g->func_safe)
 450                         break;
 451         }
 452         val |= i << g->mux_bit;
 453         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 454
 455         spin_unlock_irqrestore(&mux_lock, flags);
 456 }
 457
 458 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 459                                 struct pinctrl_gpio_range *range,
 460                                 unsigned pin)
 461 {
 462         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 463
 464         if (pmx->soc->gpio_request_enable)
 465                 return pmx->soc->gpio_request_enable(pin);
 466         return 0;
 467 }
 468
 469 static int tegra_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
 470         struct pinctrl_gpio_range *range, unsigned offset, bool input)
 471 {
 472         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 473         unsigned  group;
 474         const unsigned *pins;
 475         unsigned num_pins;
 476         int ret;
 477
 478         for (group = 0; group < pmx->soc->ngroups; ++group) {
 479                 ret = tegra_pinctrl_get_group_pins(pctldev, group,
 480                                 &pins, &num_pins);
 481                 if (ret < 0 || num_pins != 1)
 482                         continue;
 483                 if (offset ==  pins[0])
 484                         break;
 485         }
 486
 487         if (group == pmx->soc->ngroups) {
 488                 dev_err(pctldev->dev,
 489                         "Pingroup not found for pin %u\n", offset);
 490                 return -EINVAL;
 491         }
 492
 493         /*
 494          * Set input = 1 for the input direction and
 495          * tristate = 0 for output direction.
 496          */
 497         if (input)
 498                 ret = tegra_pinconfig_group_set(pctldev, group,
 499                                         TEGRA_PINCONF_PARAM_ENABLE_INPUT, 1);
 500         else
 501                 ret = tegra_pinconfig_group_set(pctldev, group,
 502                                         TEGRA_PINCONF_PARAM_TRISTATE, 0);
 503         return ret;
 504 }
 505
 506 static const struct pinmux_ops tegra_pinmux_ops = {
 507         .get_functions_count = tegra_pinctrl_get_funcs_count,
 508         .get_function_name = tegra_pinctrl_get_func_name,
 509         .get_function_groups = tegra_pinctrl_get_func_groups,
 510         .enable = tegra_pinctrl_enable,
 511         .disable = tegra_pinctrl_disable,
 512         .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 513         .gpio_set_direction = tegra_pinctrl_gpio_set_direction,
 514 };
 515
 516 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 517                              const struct tegra_pingroup *g,
 518                              enum tegra_pinconf_param param,
 519                              bool report_err,
 520                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 521 {
 522         switch (param) {
 523         case TEGRA_PINCONF_PARAM_PULL:
 524                 *bank = g->pupd_bank;
 525                 *reg = g->pupd_reg;
 526                 *bit = g->pupd_bit;
 527                 *width = 2;
 528                 break;
 529         case TEGRA_PINCONF_PARAM_TRISTATE:
 530                 *bank = g->tri_bank;
 531                 *reg = g->tri_reg;
 532                 *bit = g->tri_bit;
 533                 *width = 1;
 534                 break;
 535         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 536                 *bank = g->einput_bank;
 537                 *reg = g->einput_reg;
 538                 *bit = g->einput_bit;
 539                 *width = 1;
 540                 break;
 541         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 542                 *bank = g->odrain_bank;
 543                 *reg = g->odrain_reg;
 544                 *bit = g->odrain_bit;
 545                 *width = 1;
 546                 break;
 547         case TEGRA_PINCONF_PARAM_LOCK:
 548                 *bank = g->lock_bank;
 549                 *reg = g->lock_reg;
 550                 *bit = g->lock_bit;
 551                 *width = 1;
 552                 break;
 553         case TEGRA_PINCONF_PARAM_IORESET:
 554                 *bank = g->ioreset_bank;
 555                 *reg = g->ioreset_reg;
 556                 *bit = g->ioreset_bit;
 557                 *width = 1;
 558                 break;
 559         case TEGRA_PINCONF_PARAM_RCV_SEL:
 560                 *bank = g->rcv_sel_bank;
 561                 *reg = g->rcv_sel_reg;
 562                 *bit = g->rcv_sel_bit;
 563                 *width = 1;
 564                 break;
 565         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 566                 *bank = g->drv_bank;
 567                 *reg = g->drv_reg;
 568                 *bit = g->hsm_bit;
 569                 *width = 1;
 570                 break;
 571         case TEGRA_PINCONF_PARAM_SCHMITT:
 572                 *bank = g->drv_bank;
 573                 *reg = g->drv_reg;
 574                 *bit = g->schmitt_bit;
 575                 *width = 1;
 576                 break;
 577         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 578                 *bank = g->drv_bank;
 579                 *reg = g->drv_reg;
 580                 *bit = g->lpmd_bit;
 581                 *width = 2;
 582                 break;
 583         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 584                 *bank = g->drv_bank;
 585                 *reg = g->drv_reg;
 586                 *bit = g->drvdn_bit;
 587                 *width = g->drvdn_width;
 588                 break;
 589         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 590                 *bank = g->drv_bank;
 591                 *reg = g->drv_reg;
 592                 *bit = g->drvup_bit;
 593                 *width = g->drvup_width;
 594                 break;
 595         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 596                 *bank = g->drv_bank;
 597                 *reg = g->drv_reg;
 598                 *bit = g->slwf_bit;
 599                 *width = g->slwf_width;
 600                 break;
 601         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 602                 *bank = g->drv_bank;
 603                 *reg = g->drv_reg;
 604                 *bit = g->slwr_bit;
 605                 *width = g->slwr_width;
 606                 break;
 607         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 608                 *bank = g->drvtype_bank;
 609                 *reg = g->drvtype_reg;
 610                 *bit = g->drvtype_bit;
 611                 *width = g->drvtype_width;
 612                 break;
 613         default:
 614                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 615                 return -ENOTSUPP;
 616         }
 617
 618         if (*reg < 0 || *bit < 0) {
 619                 if (report_err)
 620                         dev_err(pmx->dev,
 621                                 "Config param %04x not supported on group %s\n",
 622                                 param, g->name);
 623                 return -ENOTSUPP;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 630                              unsigned pin, unsigned long *config)
 631 {
 632         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 633         return -ENOTSUPP;
 634 }
 635
 636 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 637                              unsigned pin, unsigned long config)
 638 {
 639         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 640         return -ENOTSUPP;
 641 }
 642
 643 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 644                                    unsigned group, unsigned long *config)
 645 {
 646         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 647         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 648         u16 arg;
 649         const struct tegra_pingroup *g;
 650         int ret;
 651         s8 bank, bit, width;
 652         s16 reg;
 653         u32 val, mask;
 654         unsigned long flags;
 655
 656         g = &pmx->soc->groups[group];
 657
 658         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 659                                 &width);
 660         if (ret < 0)
 661                 return ret;
 662
 663         spin_lock_irqsave(&mux_lock, flags);
 664
 665         val = pmx_readl(pmx, bank, reg);
 666
 667         spin_unlock_irqrestore(&mux_lock, flags);
 668
 669         mask = (1 << width) - 1;
 670         arg = (val >> bit) & mask;
 671
 672         *config = TEGRA_PINCONF_PACK(param, arg);
 673
 674         return 0;
 675 }
 676
 677 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 678                                    unsigned group, unsigned long config)
 679 {
 680         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 681         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 682         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 683         const struct tegra_pingroup *g;
 684         int ret;
 685         s8 bank, bit, width;
 686         s16 reg;
 687         u32 val, mask;
 688         unsigned long flags;
 689
 690         g = &pmx->soc->groups[group];
 691
 692         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 693                                 &width);
 694         if (ret < 0)
 695                 return ret;
 696
 697         spin_lock_irqsave(&mux_lock, flags);
 698         val = pmx_readl(pmx, bank, reg);
 699
 700         /* LOCK can't be cleared */
 701         if (param == TEGRA_PINCONF_PARAM_LOCK) {
 702                 if ((val & BIT(bit)) && !arg) {
 703                         dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 704                         ret = -EINVAL;
 705                         goto end;
 706                 }
 707         }
 708
 709         /* Special-case Boolean values; allow any non-zero as true */
 710         if (width == 1)
 711                 arg = !!arg;
 712
 713         /* Range-check user-supplied value */
 714         mask = (1 << width) - 1;
 715         if (arg & ~mask) {
 716                 dev_err(pctldev->dev,
 717                         "group %s config %lx: %x too big for %d bit register\n",
 718                         g->name, config, arg, width);
 719                         ret = -EINVAL;
 720                         goto end;
 721         }
 722
 723         /* Update register */
 724         val &= ~(mask << bit);
 725         val |= arg << bit;
 726         pmx_writel(pmx, val, bank, reg);
 727
 728 end:
 729         spin_unlock_irqrestore(&mux_lock, flags);
 730         return ret;
 731 }
 732
 733 #ifdef CONFIG_DEBUG_FS
 734 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 735                                    struct seq_file *s, unsigned offset)
 736 {
 737 }
 738
 739 static const char *strip_prefix(const char *s)
 740 {
 741         const char *comma = strchr(s, ',');
 742         if (!comma)
 743                 return s;
 744
 745         return comma + 1;
 746 }
 747
 748 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 749                                          struct seq_file *s, unsigned group)
 750 {
 751         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 752         const struct tegra_pingroup *g;
 753         int i, ret;
 754         s8 bank, bit, width;
 755         s16 reg;
 756         u32 val;
 757
 758         g = &pmx->soc->groups[group];
 759
 760         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 761                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 762                                         &bank, &reg, &bit, &width);
 763                 if (ret < 0)
 764                         continue;
 765
 766                 val = pmx_readl(pmx, bank, reg);
 767                 val >>= bit;
 768                 val &= (1 << width) - 1;
 769
 770                 seq_printf(s, "\n\t%s=%u",
 771                            strip_prefix(cfg_params[i].property), val);
 772         }
 773 }
 774
 775 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 776                                           struct seq_file *s,
 777                                           unsigned long config)
 778 {
 779         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 780         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 781         const char *pname = "unknown";
 782         int i;
 783
 784         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 785                 if (cfg_params[i].param == param) {
 786                         pname = cfg_params[i].property;
 787                         break;
 788                 }
 789         }
 790
 791         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 792 }
 793 #endif
 794
 795 static const struct pinconf_ops tegra_pinconf_ops = {
 796         .pin_config_get = tegra_pinconf_get,
 797         .pin_config_set = tegra_pinconf_set,
 798         .pin_config_group_get = tegra_pinconf_group_get,
 799         .pin_config_group_set = tegra_pinconf_group_set,
 800 #ifdef CONFIG_DEBUG_FS
 801         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 802         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 803         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 804 #endif
 805 };
 806
 807 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 808         .name = "Tegra GPIOs",
 809         .id = 0,
 810         .base = 0,
 811 };
 812
 813 static struct pinctrl_desc tegra_pinctrl_desc = {
 814         .pctlops = &tegra_pinctrl_ops,
 815         .pmxops = &tegra_pinmux_ops,
 816         .confops = &tegra_pinconf_ops,
 817         .owner = THIS_MODULE,
 818 };
 819
 820 #ifdef CONFIG_PM_SLEEP
 821
 822 static int pinctrl_suspend(void)
 823 {
 824         int i, j;
 825         u32 *pg_data = pmx->pg_data;
 826         u32 *regs;
 827
 828         if (pmx->soc->suspend) {
 829                 int ret;
 830
 831                 ret = pmx->soc->suspend(pg_data);
 832                 if (!ret)
 833                         pinctrl_configure_user_state(pmx->pctl, "suspend");
 834                 return ret;
 835         }
 836
 837         for (i = 0; i < pmx->nbanks; i++) {
 838                 regs = pmx->regs[i];
 839                 for (j = 0; j < pmx->regs_size[i] / 4; j++)
 840                         *pg_data++ = readl(regs++);
 841         }
 842         return 0;
 843 }
 844
 845 static void pinctrl_resume(void)
 846 {
 847         int i, j;
 848         u32 *pg_data = pmx->pg_data;
 849         u32 *regs;
 850
 851         if (pmx->soc->resume) {
 852                 pmx->soc->resume(pg_data);
 853                 return;
 854         }
 855
 856         for (i = 0; i < pmx->nbanks; i++) {
 857                 regs = pmx->regs[i];
 858                 for (j = 0; j < pmx->regs_size[i] / 4; j++)
 859                         writel(*pg_data++, regs++);
 860         }
 861 }
 862
 863 static struct syscore_ops pinctrl_syscore_ops = {
 864         .suspend = pinctrl_suspend,
 865         .resume = pinctrl_resume,
 866         .save = pinctrl_suspend,
 867         .restore = pinctrl_resume,
 868 };
 869
 870 #endif
 871
 872 static int tegra_pinctrl_get_group(struct tegra_pmx *pmx, const char *name)
 873 {
 874         int i;
 875
 876         for (i = 0; i< pmx->soc->ngroups; ++i) {
 877                 if (!strcmp(pmx->soc->groups[i].name, name))
 878                         return i;
 879         }
 880         return -EINVAL;
 881 }
 882
 883 static int tegra_pinctrl_set_config(struct pinctrl_dev *pctldev,
 884         int pg, int param, int val)
 885 {
 886         unsigned long config;
 887
 888         config = TEGRA_PINCONF_PACK(param, val);
 889         return tegra_pinconf_group_set(pmx->pctl, pg, config);
 890 }
 891
 892 static void tegra_pinctrl_default_soc_init(struct tegra_pmx *pmx)
 893 {
 894         struct tegra_pinctrl_group_config_data *cdata;
 895         int group;
 896         int i;
 897
 898         for (i = 0; i < pmx->soc->nconfig_data; ++i) {
 899                 cdata = &pmx->soc->config_data[i];
 900                 group = tegra_pinctrl_get_group(pmx, cdata->name);
 901                 if (group < 0) {
 902                         dev_warn(pmx->dev, "Group name %s not found\n",
 903                                 cdata->name);
 904                         continue;
 905                 }
 906
 907                 if (pmx->soc->groups[i].hsm_bit >= 0)
 908                         tegra_pinctrl_set_config(pmx->pctl, group,
 909                                 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
 910                                 cdata->high_speed_mode);
 911
 912                 if (pmx->soc->groups[i].schmitt_bit >= 0)
 913                         tegra_pinctrl_set_config(pmx->pctl, group,
 914                                 TEGRA_PINCONF_PARAM_SCHMITT,
 915                                 cdata->schmitt);
 916
 917                 if (pmx->soc->groups[i].lpmd_bit >= 0)
 918                         tegra_pinctrl_set_config(pmx->pctl, group,
 919                                 TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
 920                                 cdata->low_power_mode);
 921
 922                 if (pmx->soc->groups[i].drvdn_bit >= 0)
 923                         tegra_pinctrl_set_config(pmx->pctl, group,
 924                                 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
 925                                 cdata->pull_down_strength);
 926
 927                 if (pmx->soc->groups[i].drvup_bit >= 0)
 928                         tegra_pinctrl_set_config(pmx->pctl, group,
 929                                 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
 930                                 cdata->pull_up_strength);
 931
 932                 if (pmx->soc->groups[i].slwf_bit >= 0)
 933                         tegra_pinctrl_set_config(pmx->pctl, group,
 934                                 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
 935                                 cdata->slew_rate_falling);
 936
 937                 if (pmx->soc->groups[i].slwr_bit >= 0)
 938                         tegra_pinctrl_set_config(pmx->pctl, group,
 939                                 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
 940                                 cdata->slew_rate_rising);
 941
 942                 if (pmx->soc->groups[i].drvtype_reg >= 0)
 943                         tegra_pinctrl_set_config(pmx->pctl, group,
 944                                         TEGRA_PINCONF_PARAM_DRIVE_TYPE,
 945                                         cdata->drive_type);
 946         }
 947 }
 948
 949 int tegra_pinctrl_probe(struct platform_device *pdev,
 950                         const struct tegra_pinctrl_soc_data *soc_data)
 951 {
 952         struct resource *res;
 953         int i, pg_data_size = 0;
 954
 955         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 956         if (!pmx) {
 957                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
 958                 return -ENOMEM;
 959         }
 960         pmx->dev = &pdev->dev;
 961         pmx->soc = soc_data;
 962
 963         pmx->drive_group_start_index = -1;
 964
 965         for (i = 0; i < pmx->soc->ngroups; ++i) {
 966                 if (pmx->soc->groups[i].drv_reg < 0)
 967                         continue;
 968                 pmx->drive_group_start_index = i;
 969                 break;
 970         }
 971
 972         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 973         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 974         tegra_pinctrl_desc.pins = pmx->soc->pins;
 975         tegra_pinctrl_desc.npins = pmx->soc->npins;
 976
 977         for (i = 0; ; i++) {
 978                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 979                 if (!res)
 980                         break;
 981                 pg_data_size += resource_size(res);
 982         }
 983         pmx->nbanks = i;
 984
 985         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
 986                                  GFP_KERNEL);
 987         if (!pmx->regs) {
 988                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 989                 return -ENODEV;
 990         }
 991
 992         pmx->reg_base = devm_kzalloc(&pdev->dev, pmx->nbanks *
 993                                         sizeof(*pmx->reg_base), GFP_KERNEL);
 994         if (!pmx->reg_base) {
 995                 dev_err(&pdev->dev, "Can't alloc reg_base pointer\n");
 996                 return -ENOMEM;
 997         }
 998
 999
1000 #ifdef CONFIG_PM_SLEEP
1001         pmx->regs_size = devm_kzalloc(&pdev->dev,
1002                                 pmx->nbanks * sizeof(*(pmx->regs_size)),
1003                                 GFP_KERNEL);
1004         if (!pmx->regs_size) {
1005                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
1006                 return -ENODEV;
1007         }
1008
1009         pmx->pg_data = devm_kzalloc(&pdev->dev, pg_data_size, GFP_KERNEL);
1010         if (!pmx->pg_data) {
1011                 dev_err(&pdev->dev, "Can't alloc pingroup data pointer\n");
1012                 return -ENODEV;
1013         }
1014 #endif
1015
1016         for (i = 0; i < pmx->nbanks; i++) {
1017                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1018                 if (!res) {
1019                         dev_err(&pdev->dev, "Missing MEM resource\n");
1020                         return -ENODEV;
1021                 }
1022
1023                 if (!devm_request_mem_region(&pdev->dev, res->start,
1024                                             resource_size(res),
1025                                             dev_name(&pdev->dev))) {
1026                         dev_err(&pdev->dev,
1027                                 "Couldn't request MEM resource %d\n", i);
1028                         return -ENODEV;
1029                 }
1030
1031                 pmx->reg_base[i] = res->start;
1032                 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
1033                                             resource_size(res));
1034                 if (!pmx->regs[i]) {
1035                         dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
1036                         return -ENODEV;
1037                 }
1038
1039 #ifdef CONFIG_PM_SLEEP
1040                 pmx->regs_size[i] = resource_size(res);
1041 #endif
1042         }
1043
1044         pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
1045         if (!pmx->pctl) {
1046                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1047                 return -ENODEV;
1048         }
1049
1050         pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
1051
1052         platform_set_drvdata(pdev, pmx);
1053
1054         tegra_pinctrl_default_soc_init(pmx);
1055
1056         pinctrl_configure_user_state(pmx->pctl, "drive");
1057         pinctrl_configure_user_state(pmx->pctl, "unused");
1058
1059 #ifdef CONFIG_PM_SLEEP
1060         register_syscore_ops(&pinctrl_syscore_ops);
1061 #endif
1062         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
1063
1064         return 0;
1065 }
1066 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
1067
1068 int tegra_pinctrl_remove(struct platform_device *pdev)
1069 {
1070         struct tegra_pmx *pmx = platform_get_drvdata(pdev);
1071
1072         pinctrl_unregister(pmx->pctl);
1073
1074         return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
1077
1078 /*** To support non-dt pin control */
1079
1080 static const char *tegra_pinctrl_drive_names[TEGRA_MAX_DRIVE] = {
1081         [TEGRA_DRIVE_DIV_8] = "DIV_8",
1082         [TEGRA_DRIVE_DIV_4] = "DIV_4",
1083         [TEGRA_DRIVE_DIV_2] = "DIV_2",
1084         [TEGRA_DRIVE_DIV_1] = "DIV_1",
1085 };
1086
1087 static const char *tegra_pinctrl_slew_names[TEGRA_MAX_SLEW] = {
1088         [TEGRA_SLEW_FASTEST] = "FASTEST",
1089         [TEGRA_SLEW_FAST] = "FAST",
1090         [TEGRA_SLEW_SLOW] = "SLOW",
1091         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
1092 };
1093
1094 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
1095 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
1096 #define LPMD(reg)       (((reg) >> 4) & 0x3)
1097 #define DRVDN(reg, offset, w)      (((reg) >> offset) & (BIT(w) -1))
1098 #define DRVUP(reg, offset, w)      (((reg) >> offset) & (BIT(w) -1))
1099 #define SLWR(reg, offset, w)       (((reg) >> offset) & (BIT(w) -1))
1100 #define SLWF(reg, offset, w)       (((reg) >> offset) & (BIT(w) -1))
1101
1102 static const char *tegra_pinctrl_function_name(enum tegra_mux_func func)
1103 {
1104         if (func == TEGRA_MUX_RSVD1)
1105                 return "RSVD1";
1106
1107         if (func == TEGRA_MUX_RSVD2)
1108                 return "RSVD2";
1109
1110         if (func == TEGRA_MUX_RSVD3)
1111                 return "RSVD3";
1112
1113         if (func == TEGRA_MUX_RSVD4)
1114                 return "RSVD4";
1115
1116         if (func == TEGRA_MUX_INVALID)
1117                 return "INVALID";
1118
1119         if (func < 0 || func >=  TEGRA_MAX_MUX)
1120                 return "<UNKNOWN>";
1121
1122         return tegra_pinctrl_get_func_name(pmx->pctl, func);
1123 }
1124
1125
1126 static const char *tegra_pinctrl_tri_name(unsigned long val)
1127 {
1128         return val ? "TRISTATE" : "NORMAL";
1129 }
1130 static const char *tegra_pinctrl_pupd_name(unsigned long val)
1131 {
1132         switch (val) {
1133         case 0:
1134                 return "NORMAL";
1135
1136         case 1:
1137                 return "PULL_DOWN";
1138
1139         case 2:
1140                 return "PULL_UP";
1141
1142         default:
1143                 return "RSVD";
1144         }
1145 }
1146 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1147 static const char *tegra_pinctrl_lock_name(unsigned long val)
1148 {
1149         switch (val) {
1150         case TEGRA_PIN_LOCK_DEFAULT:
1151                 return "LOCK_DEFUALT";
1152
1153         case TEGRA_PIN_LOCK_DISABLE:
1154                 return "LOCK_DISABLE";
1155
1156         case TEGRA_PIN_LOCK_ENABLE:
1157                 return "LOCK_ENABLE";
1158         default:
1159                 return "LOCK_DEFAULT";
1160         }
1161 }
1162
1163 static const char *tegra_pinctrl_od_name(unsigned long val)
1164 {
1165         switch (val) {
1166         case TEGRA_PIN_OD_DEFAULT:
1167                 return "OD_DEFAULT";
1168
1169         case TEGRA_PIN_OD_DISABLE:
1170                 return "OD_DISABLE";
1171
1172         case TEGRA_PIN_OD_ENABLE:
1173                 return "OD_ENABLE";
1174         default:
1175                 return "OD_DEFAULT";
1176         }
1177 }
1178
1179 static const char *tegra_pinctrl_ioreset_name(unsigned long val)
1180 {
1181         switch (val) {
1182         case TEGRA_PIN_IO_RESET_DEFAULT:
1183                 return "IO_RESET_DEFAULT";
1184
1185         case TEGRA_PIN_IO_RESET_DISABLE:
1186                 return "IO_RESET_DISABLE";
1187
1188         case TEGRA_PIN_IO_RESET_ENABLE:
1189                 return "IO_RESET_ENABLE";
1190         default:
1191                 return "IO_RESET_DEFAULT";
1192         }
1193 }
1194 #endif
1195 static const char *tegra_pinctrl_io_name(unsigned long val)
1196 {
1197         switch (val) {
1198         case 0:
1199                 return "OUTPUT";
1200
1201         case 1:
1202                 return "INPUT";
1203
1204         default:
1205                 return "RSVD";
1206         }
1207 }
1208
1209 static const char *tegra_pinctrl_rcv_sel_name(unsigned long val)
1210 {
1211         switch (val) {
1212         case 0:
1213                 return "RCV-DISABLE";
1214
1215         case 1:
1216                 return "RCV-DISABLE";
1217
1218         default:
1219                 return "RSVD";
1220         }
1221 }
1222
1223 static const char *drive_pinmux_name(int pg)
1224 {
1225         if (pg < 0 || !pmx || pg >=  pmx->soc->ngroups)
1226                 return "<UNKNOWN>";
1227         if (pmx->soc->groups[pg].drv_reg < 0)
1228                 return "<UNKNOWN>";
1229
1230         return pmx->soc->groups[pg].name;
1231 }
1232
1233 static const char *enable_name(unsigned long val)
1234 {
1235         return val ? "ENABLE" : "DISABLE";
1236 }
1237
1238 static const char *drive_name(unsigned long val)
1239 {
1240         if (val >= TEGRA_MAX_DRIVE)
1241                 return "<UNKNOWN>";
1242
1243         return tegra_pinctrl_drive_names[val];
1244 }
1245
1246 static const char *slew_name(unsigned long val)
1247 {
1248         if (val >= TEGRA_MAX_SLEW)
1249                 return "<UNKNOWN>";
1250
1251         return tegra_pinctrl_slew_names[val];
1252 }
1253
1254 u32 tegra_pinctrl_readl(u32 bank, u32 reg)
1255 {
1256         return readl(pmx->regs[bank] + reg);
1257 }
1258 EXPORT_SYMBOL_GPL(tegra_pinctrl_readl);
1259
1260 void tegra_pinctrl_writel(u32 val, u32 bank, u32 reg)
1261 {
1262         writel(val, pmx->regs[bank] + reg);
1263 }
1264 EXPORT_SYMBOL_GPL(tegra_pinctrl_writel);
1265
1266 int tegra_pinctrl_gpio_to_pingroup(int gpio_nr)
1267 {
1268         int i;
1269
1270         if (!pmx || gpio_nr < 0)
1271                 return -EINVAL;
1272
1273         for (i = 0; i < pmx->soc->ngroups; ++i) {
1274                 if (pmx->soc->groups[i].drv_reg >= 0)
1275                         continue;
1276
1277                 if (pmx->soc->groups[i].pins[0] == gpio_nr) {
1278                         if (pmx->soc->groups[i].pins[0] >= pmx->soc->ngpios)
1279                                 return -EINVAL;
1280                         return i;
1281                 }
1282         }
1283         return -EINVAL;
1284 }
1285 EXPORT_SYMBOL(tegra_pinctrl_gpio_to_pingroup);
1286
1287 int tegra_pinctrl_pg_set_func(const struct tegra_pingroup_config *config)
1288 {
1289         int mux = -1;
1290         int i;
1291         int find = 0;
1292         int ret;
1293         int pg = config->pingroup;
1294         enum tegra_mux_func func = config->func;
1295         const struct tegra_pingroup *g;
1296         int func_dt = -1;
1297
1298         if (!pmx) {
1299                 pr_err("Pingroup not registered yet\n");
1300                 return -EPROBE_DEFER;
1301         }
1302
1303         if (pg < 0 || pg >=  pmx->soc->ngroups)
1304                 return -ERANGE;
1305
1306         g = &pmx->soc->groups[pg];
1307
1308         if (g->mux_reg < 0)
1309                 return -EINVAL;
1310
1311         if (func == TEGRA_MUX_INVALID) {
1312                 pr_err("The pingroup %s is not recommended for option %s\n",
1313                                 g->name, tegra_pinctrl_function_name(func));
1314                 WARN_ON(1);
1315                 return -EINVAL;
1316         }
1317
1318         if (func < 0)
1319                 return -ERANGE;
1320
1321         if (func == TEGRA_MUX_SAFE) {
1322                 func = g->func_safe_non_dt;
1323                 func_dt =  g->func_safe;
1324         }
1325         if (func & TEGRA_MUX_RSVD) {
1326                 for (i = 0; i < 4; i++) {
1327                         if (g->funcs_non_dt[i] & TEGRA_MUX_RSVD)
1328                                 mux = i;
1329
1330                         if (g->funcs_non_dt[i] == func) {
1331                                 mux = i;
1332                                 find = 1;
1333                                 break;
1334                         }
1335                 }
1336         } else {
1337                 for (i = 0; i < 4; i++) {
1338                         if (g->funcs_non_dt[i] == func) {
1339                                 mux = i;
1340                                 find = 1;
1341                                 break;
1342                         }
1343                 }
1344         }
1345
1346         if (!find)
1347                 pr_warn("The pingroup %s was configured to %s instead of %s\n",
1348                         g->name,
1349                         tegra_pinctrl_function_name(g->funcs_non_dt[mux]),
1350                         tegra_pinctrl_function_name(func));
1351         if (mux >= 0) {
1352                 func = g->funcs_non_dt[mux];
1353                 func_dt = g->funcs[mux];
1354         }
1355
1356         if (func_dt < 0) {
1357                 pr_warn("The pingroup %s does not have option %s\n",
1358                         g->name,  tegra_pinctrl_function_name(func));
1359                 return -EINVAL;
1360         }
1361
1362         ret = tegra_pinctrl_enable(pmx->pctl, func_dt, pg);
1363         if (ret < 0) {
1364                 pr_err("Not able to set function %s for pin group %s\n",
1365                         tegra_pinctrl_function_name(func), g->name);
1366                 return ret;
1367         }
1368
1369         ret = tegra_pinctrl_pg_set_io(pg, config->io);
1370         if (ret < 0) {
1371                 pr_err("Not able to set io %s for pin group %s\n",
1372                         tegra_pinctrl_io_name(config->io), g->name);
1373                 return ret;
1374         }
1375         return 0;
1376 }
1377 EXPORT_SYMBOL(tegra_pinctrl_pg_set_func);
1378
1379 int tegra_pinctrl_pg_get_func(int pg)
1380 {
1381         int mux;
1382         const struct tegra_pingroup *g;
1383         u32 val;
1384
1385         if (!pmx) {
1386                 pr_err("Pingroup not registered yet\n");
1387                 return -EPROBE_DEFER;
1388         }
1389
1390         if (pg < 0 || pg >=  pmx->soc->ngroups)
1391                 return -ERANGE;
1392
1393         g = &pmx->soc->groups[pg];
1394
1395         if (g->mux_reg < 0 || g->mux_bit)
1396                 return -EINVAL;
1397
1398         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
1399         mux = (val >> g->mux_bit) & 0x3;
1400         return g->funcs_non_dt[mux];
1401 }
1402 EXPORT_SYMBOL(tegra_pinctrl_pg_get_func);
1403
1404 int tegra_pinctrl_pg_set_tristate(int pg, int tristate)
1405 {
1406         if (!pmx) {
1407                 pr_err("Pingroup not registered yet\n");
1408                 return -EPROBE_DEFER;
1409         }
1410
1411         if (pg < 0 || pg >=  pmx->soc->ngroups)
1412                 return -ERANGE;
1413
1414         return tegra_pinctrl_set_config(pmx->pctl, pg,
1415                         TEGRA_PINCONF_PARAM_TRISTATE, tristate);
1416 }
1417 EXPORT_SYMBOL(tegra_pinctrl_pg_set_tristate);
1418
1419 int tegra_pinctrl_pg_set_io(int pg, int input)
1420 {
1421         if (!pmx) {
1422                 pr_err("Pingroup not registered yet\n");
1423                 return -EPROBE_DEFER;
1424         }
1425
1426         if (pg < 0 || pg >=  pmx->soc->ngroups)
1427                 return -ERANGE;
1428
1429         if (pmx->soc->groups[pg].einput_reg < 0)
1430                 return 0;
1431
1432         return tegra_pinctrl_set_config(pmx->pctl, pg,
1433                         TEGRA_PINCONF_PARAM_ENABLE_INPUT, input);
1434 }
1435 EXPORT_SYMBOL(tegra_pinctrl_pg_set_io);
1436
1437 int tegra_pinctrl_pg_set_lock(int pg, int lock)
1438 {
1439         int lv = (lock == TEGRA_PIN_LOCK_ENABLE) ? 1 : 0;
1440
1441         if (!pmx) {
1442                 pr_err("Pingroup not registered yet\n");
1443                 return -EPROBE_DEFER;
1444         }
1445
1446         if (pg < 0 || pg >=  pmx->soc->ngroups)
1447                 return -ERANGE;
1448
1449         if (lock == TEGRA_PIN_LOCK_DEFAULT)
1450                 return 0;
1451
1452         tegra_pinctrl_set_config(pmx->pctl, pg,
1453                         TEGRA_PINCONF_PARAM_LOCK, lv);
1454         return 0;
1455 }
1456 EXPORT_SYMBOL(tegra_pinctrl_pg_set_lock);
1457
1458 int tegra_pinctrl_pg_set_od(int pg, int od)
1459 {
1460         int ov = (od == TEGRA_PIN_OD_ENABLE) ? 1 : 0;
1461
1462         if (!pmx) {
1463                 pr_err("Pingroup not registered yet\n");
1464                 return -EPROBE_DEFER;
1465         }
1466
1467         if (pg < 0 || pg >=  pmx->soc->ngroups)
1468                 return -ERANGE;
1469
1470         if (od == TEGRA_PIN_OD_DEFAULT)
1471                 return 0;
1472
1473         tegra_pinctrl_set_config(pmx->pctl, pg,
1474                         TEGRA_PINCONF_PARAM_OPEN_DRAIN, ov);
1475         return 0;
1476 }
1477 EXPORT_SYMBOL(tegra_pinctrl_pg_set_od);
1478
1479 int tegra_pinctrl_pg_set_ioreset(int pg, int ioreset)
1480 {
1481         int iov = (ioreset == TEGRA_PIN_IO_RESET_ENABLE) ? 1 : 0;
1482
1483         if (!pmx) {
1484                 pr_err("Pingroup not registered yet\n");
1485                 return -EPROBE_DEFER;
1486         }
1487
1488         if (pg < 0 || pg >=  pmx->soc->ngroups)
1489                 return -ERANGE;
1490
1491         if (ioreset == TEGRA_PIN_IO_RESET_DEFAULT)
1492                 return 0;
1493
1494         tegra_pinctrl_set_config(pmx->pctl, pg,
1495                         TEGRA_PINCONF_PARAM_IORESET, iov);
1496         return 0;
1497 }
1498 EXPORT_SYMBOL(tegra_pinctrl_pg_set_ioreset);
1499
1500 int tegra_pinctrl_pg_set_rcv_sel(int pg, int rcv_sel)
1501 {
1502         int rcv = (rcv_sel == TEGRA_PIN_RCV_SEL_HIGH) ? 1 : 0;
1503
1504         if (!pmx) {
1505                 pr_err("Pingroup not registered yet\n");
1506                 return -EPROBE_DEFER;
1507         }
1508
1509         if (pg < 0 || pg >=  pmx->soc->ngroups)
1510                 return -ERANGE;
1511
1512         if (rcv_sel == TEGRA_PIN_RCV_SEL_DEFAULT)
1513                 return 0;
1514
1515         tegra_pinctrl_set_config(pmx->pctl, pg,
1516                         TEGRA_PINCONF_PARAM_RCV_SEL, rcv);
1517         return 0;
1518 }
1519 EXPORT_SYMBOL(tegra_pinctrl_pg_set_rcv_sel);
1520
1521 int tegra_pinctrl_pg_set_pullupdown(int pg, int pupd)
1522 {
1523         if (!pmx) {
1524                 pr_err("Pingroup not registered yet\n");
1525                 return -EPROBE_DEFER;
1526         }
1527
1528         if (pg < 0 || pg >=  pmx->soc->ngroups)
1529                 return -ERANGE;
1530
1531         if (pupd != TEGRA_PUPD_NORMAL &&
1532             pupd != TEGRA_PUPD_PULL_DOWN &&
1533             pupd != TEGRA_PUPD_PULL_UP)
1534                 return -EINVAL;
1535
1536         tegra_pinctrl_set_config(pmx->pctl, pg,
1537                         TEGRA_PINCONF_PARAM_PULL, pupd);
1538         return 0;
1539 }
1540 EXPORT_SYMBOL(tegra_pinctrl_pg_set_pullupdown);
1541
1542 void tegra_pinctrl_pg_config_pingroup(
1543         const struct tegra_pingroup_config *config)
1544 {
1545         int pg = config->pingroup;
1546         enum tegra_mux_func func     = config->func;
1547         enum tegra_pullupdown pupd   = config->pupd;
1548         enum tegra_tristate tristate = config->tristate;
1549 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1550         enum tegra_pin_lock lock     = config->lock;
1551         enum tegra_pin_od od     = config->od;
1552         enum tegra_pin_ioreset ioreset = config->ioreset;
1553         enum tegra_pin_rcv_sel rcv_sel = config->rcv_sel;
1554 #endif
1555         const struct tegra_pingroup *g;
1556         int err;
1557
1558         if (!pmx) {
1559                 pr_err("Pingroup not registered yet\n");
1560                 return;
1561         }
1562
1563         if (pg < 0 || pg >=  pmx->soc->ngroups)
1564                 return;
1565
1566         g = &pmx->soc->groups[pg];
1567
1568         if (g->mux_reg >= 0) {
1569                 err = tegra_pinctrl_pg_set_func(config);
1570                 if (err < 0)
1571                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
1572                                g->name, tegra_pinctrl_function_name(func), err);
1573         }
1574
1575         if (g->pupd_reg >= 0) {
1576                 err = tegra_pinctrl_pg_set_pullupdown(pg, pupd);
1577                 if (err < 0)
1578                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
1579                                g->name, tegra_pinctrl_pupd_name(pupd), err);
1580         }
1581
1582         if (g->tri_reg >= 0) {
1583                 err = tegra_pinctrl_pg_set_tristate(pg, tristate);
1584                 if (err < 0)
1585                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
1586                                g->name, tegra_pinctrl_tri_name(tristate), err);
1587         }
1588
1589 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1590         if (g->mux_reg >= 0) {
1591                 err = tegra_pinctrl_pg_set_lock(pg, lock);
1592                 if (err < 0)
1593                         pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
1594                                g->name, tegra_pinctrl_lock_name(lock), err);
1595         }
1596
1597         if (g->mux_reg >= 0) {
1598                 err = tegra_pinctrl_pg_set_od(pg, od);
1599                 if (err < 0)
1600                         pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
1601                                g->name, tegra_pinctrl_od_name(od), err);
1602         }
1603
1604         if (g->mux_reg >= 0) {
1605                 err = tegra_pinctrl_pg_set_ioreset(pg, ioreset);
1606                 if (err < 0)
1607                         pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
1608                                g->name, tegra_pinctrl_ioreset_name(ioreset),
1609                                 err);
1610         }
1611         if (g->mux_reg >= 0) {
1612                 err = tegra_pinctrl_pg_set_rcv_sel(pg, rcv_sel);
1613                 if (err < 0)
1614                         pr_err("pinmux: can't set pingroup %s rcv_sel to %s: %d\n",
1615                                g->name, tegra_pinctrl_rcv_sel_name(rcv_sel),
1616                                 err);
1617         }
1618 #endif
1619 }
1620 EXPORT_SYMBOL(tegra_pinctrl_pg_config_pingroup);
1621
1622 void tegra_pinctrl_pg_config_table(const struct tegra_pingroup_config *config,
1623                 int len)
1624 {
1625         int i;
1626
1627         for (i = 0; i < len; i++)
1628                 tegra_pinctrl_pg_config_pingroup(&config[i]);
1629 }
1630 EXPORT_SYMBOL(tegra_pinctrl_pg_config_table);
1631
1632 int tegra_pinctrl_pg_drive_set_hsm(int pdg, int hsm)
1633 {
1634         int val = (hsm == TEGRA_HSM_ENABLE) ? 1 : 0;
1635         int pg = pmx->drive_group_start_index + pdg;
1636
1637         if (pg < 0 || pg >=  pmx->soc->ngroups)
1638                 return -ERANGE;
1639
1640         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
1641                 return -EINVAL;
1642
1643         tegra_pinctrl_set_config(pmx->pctl, pg,
1644                         TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, val);
1645         return 0;
1646 }
1647 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_hsm);
1648
1649 int tegra_pinctrl_pg_drive_set_schmitt(int pdg, int schmitt)
1650 {
1651         int pg = pmx->drive_group_start_index + pdg;
1652         int val = (schmitt == TEGRA_SCHMITT_ENABLE) ? 1 : 0;
1653
1654         if (pg < 0 || pg >=  pmx->soc->ngroups)
1655                 return -ERANGE;
1656
1657         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
1658                 return -EINVAL;
1659
1660         tegra_pinctrl_set_config(pmx->pctl, pg,
1661                         TEGRA_PINCONF_PARAM_SCHMITT, val);
1662         return 0;
1663 }
1664 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_schmitt);
1665
1666 int tegra_pinctrl_pg_drive_set_drive(int pdg, int drive)
1667 {
1668         int pg = pmx->drive_group_start_index + pdg;
1669
1670         if (pg < 0 || pg >=  pmx->soc->ngroups)
1671                 return -ERANGE;
1672
1673         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
1674                 return -EINVAL;
1675
1676         tegra_pinctrl_set_config(pmx->pctl, pg,
1677                         TEGRA_PINCONF_PARAM_LOW_POWER_MODE, drive);
1678         return 0;
1679 }
1680 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_drive);
1681
1682 int tegra_pinctrl_pg_drive_set_pull_down(int pdg, int pull_down)
1683 {
1684         int pg = pmx->drive_group_start_index + pdg;
1685
1686         if (pg < 0 || pg >=  pmx->soc->ngroups)
1687                 return -ERANGE;
1688
1689         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
1690                 return -EINVAL;
1691
1692         tegra_pinctrl_set_config(pmx->pctl, pg,
1693                         TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, pull_down);
1694         return 0;
1695 }
1696 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_pull_down);
1697
1698 int tegra_pinctrl_pg_drive_set_pull_up(int pdg, int pull_up)
1699 {
1700         int pg = pmx->drive_group_start_index + pdg;
1701
1702         if (pg < 0 || pg >=  pmx->soc->ngroups)
1703                 return -ERANGE;
1704
1705         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
1706                 return -EINVAL;
1707
1708         tegra_pinctrl_set_config(pmx->pctl, pg,
1709                         TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, pull_up);
1710         return 0;
1711 }
1712 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_pull_up);
1713
1714 int tegra_pinctrl_pg_drive_set_slew_rising(int pdg, int slew_rising)
1715 {
1716         int pg = pmx->drive_group_start_index + pdg;
1717
1718         if (pg < 0 || pg >=  pmx->soc->ngroups)
1719                 return -ERANGE;
1720
1721         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
1722                 return -EINVAL;
1723
1724         tegra_pinctrl_set_config(pmx->pctl, pg,
1725                         TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, slew_rising);
1726         return 0;
1727 }
1728 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_slew_rising);
1729
1730 int tegra_pinctrl_pg_drive_set_slew_falling(int pdg, int slew_falling)
1731 {
1732         int pg = pmx->drive_group_start_index + pdg;
1733
1734         if (pg < 0 || pg >=  pmx->soc->ngroups)
1735                 return -ERANGE;
1736
1737         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
1738                 return -EINVAL;
1739
1740         tegra_pinctrl_set_config(pmx->pctl, pg,
1741                         TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, slew_falling);
1742         return 0;
1743 }
1744 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_slew_falling);
1745
1746 int tegra_pinctrl_pg_drive_set_drive_type(int pdg, int drive_type)
1747 {
1748         int pg = pmx->drive_group_start_index + pdg;
1749
1750         if (pg < 0 || pg >=  pmx->soc->ngroups)
1751                 return -ERANGE;
1752
1753         if (pmx->soc->groups[pg].drvtype_reg < 0)
1754                 return 0;
1755
1756         if (drive_type < 0 || drive_type >= TEGRA_MAX_DRIVE_TYPE)
1757                 return -EINVAL;
1758
1759         tegra_pinctrl_set_config(pmx->pctl, pg,
1760                         TEGRA_PINCONF_PARAM_DRIVE_TYPE, drive_type);
1761         return 0;
1762 }
1763 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_set_drive_type);
1764
1765 void tegra_pinctrl_pg_drive_config_pingroup(int pingroup,
1766         int hsm, int schmitt, int drive, int pull_down,
1767         int pull_up, int slew_rising, int slew_falling,
1768         int drive_type)
1769 {
1770         int err;
1771         int pg = pmx->drive_group_start_index + pingroup;
1772
1773
1774         err = tegra_pinctrl_pg_drive_set_hsm(pingroup, hsm);
1775         if (err < 0)
1776                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
1777                         drive_pinmux_name(pg),
1778                         enable_name(hsm), err);
1779
1780         err = tegra_pinctrl_pg_drive_set_schmitt(pingroup, schmitt);
1781         if (err < 0)
1782                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
1783                         drive_pinmux_name(pg),
1784                         enable_name(schmitt), err);
1785
1786         err = tegra_pinctrl_pg_drive_set_drive(pingroup, drive);
1787         if (err < 0)
1788                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
1789                         drive_pinmux_name(pg),
1790                         drive_name(drive), err);
1791
1792         err = tegra_pinctrl_pg_drive_set_pull_down(pingroup, pull_down);
1793         if (err < 0)
1794                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
1795                         drive_pinmux_name(pg),
1796                         pull_down, err);
1797
1798         err = tegra_pinctrl_pg_drive_set_pull_up(pingroup, pull_up);
1799         if (err < 0)
1800                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
1801                         drive_pinmux_name(pg),
1802                         pull_up, err);
1803
1804         err = tegra_pinctrl_pg_drive_set_slew_rising(pingroup, slew_rising);
1805         if (err < 0)
1806                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
1807                         drive_pinmux_name(pg),
1808                         slew_name(slew_rising), err);
1809
1810         err = tegra_pinctrl_pg_drive_set_slew_falling(pingroup, slew_falling);
1811         if (err < 0)
1812                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
1813                         drive_pinmux_name(pg),
1814                         slew_name(slew_falling), err);
1815
1816         err = tegra_pinctrl_pg_drive_set_drive_type(pingroup, drive_type);
1817         if (err < 0)
1818                 pr_err("pinmux: can't set pingroup %s driver type to %d: %d\n",
1819                         drive_pinmux_name(pg),
1820                         drive_type, err);
1821 }
1822 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_config_pingroup);
1823
1824 void tegra_pinctrl_pg_drive_config_table(
1825         struct tegra_drive_pingroup_config *config, int len)
1826 {
1827         int i;
1828
1829         for (i = 0; i < len; i++)
1830                 tegra_pinctrl_pg_drive_config_pingroup(config[i].pingroup,
1831                                                      config[i].hsm,
1832                                                      config[i].schmitt,
1833                                                      config[i].drive,
1834                                                      config[i].pull_down,
1835                                                      config[i].pull_up,
1836                                                      config[i].slew_rising,
1837                                                      config[i].slew_falling,
1838                                                      config[i].drive_type);
1839 }
1840 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_config_table);
1841
1842 int tegra_pinctrl_pg_drive_get_pingroup(struct device *dev)
1843 {
1844         int pg = -1;
1845         const char *dev_id;
1846
1847         if (!dev || !pmx)
1848                 return -EINVAL;
1849
1850         dev_id = dev_name(dev);
1851         for (pg = 0; pg < pmx->soc->ngroups; pg++) {
1852                 if (pmx->soc->groups[pg].dev_id &&
1853                         !(strcmp(pmx->soc->groups[pg].dev_id, dev_id))) {
1854                         if (pg >= pmx->drive_group_start_index)
1855                                 pg -= pmx->drive_group_start_index;
1856                         break;
1857                 }
1858         }
1859
1860         return (pg == pmx->soc->ngroups) ? -EINVAL : pg;
1861 }
1862 EXPORT_SYMBOL(tegra_pinctrl_pg_drive_get_pingroup);
1863
1864 void tegra_pinctrl_pg_set_safe_pinmux_table(
1865         const struct tegra_pingroup_config *config, int len)
1866 {
1867         int i;
1868         struct tegra_pingroup_config c;
1869
1870         for (i = 0; i < len; i++) {
1871                 int err;
1872                 c = config[i];
1873                 if (c.pingroup < 0 || c.pingroup >= pmx->soc->ngroups) {
1874                         WARN_ON(1);
1875                         continue;
1876                 }
1877                 c.func = pmx->soc->groups[c.pingroup].func_safe;
1878                 err = tegra_pinctrl_pg_set_func(&c);
1879                 if (err < 0)
1880                         pr_err("%s: tegra_pinctrl_pg_set_func returned %d "
1881                                 "setting %s to %s\n", __func__, err,
1882                                 pmx->soc->groups[c.pingroup].name,
1883                                 tegra_pinctrl_function_name(c.func));
1884         }
1885 }
1886 EXPORT_SYMBOL(tegra_pinctrl_pg_set_safe_pinmux_table);
1887
1888 void tegra_pinctrl_pg_config_pinmux_table(
1889         const struct tegra_pingroup_config *config, int len)
1890 {
1891         int i;
1892
1893         for (i = 0; i < len; i++) {
1894                 int err;
1895                 if (config[i].pingroup < 0 ||
1896                     config[i].pingroup >= pmx->soc->ngroups) {
1897                         WARN_ON(1);
1898                         continue;
1899                 }
1900                 err = tegra_pinctrl_pg_set_func(&config[i]);
1901                 if (err < 0)
1902                         pr_err("%s: tegra_pinctrl_pg_set_func returned %d "
1903                                 "setting %s to %s\n", __func__, err,
1904                                 pmx->soc->groups[config[i].pingroup].name,
1905                                tegra_pinctrl_function_name(config[i].func));
1906         }
1907 }
1908 EXPORT_SYMBOL(tegra_pinctrl_pg_config_pinmux_table);
1909
1910 void tegra_pinctrl_pg_config_tristate_table(
1911         const struct tegra_pingroup_config *config,
1912         int len, int tristate)
1913 {
1914         int i;
1915         int err;
1916         int pingroup;
1917
1918         for (i = 0; i < len; i++) {
1919                 pingroup = config[i].pingroup;
1920                 if (pmx->soc->groups[pingroup].tri_reg > 0) {
1921                         err = tegra_pinctrl_pg_set_tristate(pingroup, tristate);
1922                         if (err < 0)
1923                                 pr_err("pinmux: can't set pingroup %s tristate"
1924                                         " to %s: %d\n",
1925                                         pmx->soc->groups[pingroup].name,
1926                                         tegra_pinctrl_tri_name(tristate), err);
1927                 }
1928         }
1929 }
1930 EXPORT_SYMBOL(tegra_pinctrl_pg_config_tristate_table);
1931
1932 void tegra_pinctrl_pg_config_pullupdown_table(
1933         const struct tegra_pingroup_config *config,
1934         int len, int pupd)
1935 {
1936         int i;
1937         int err;
1938         int pingroup;
1939
1940         for (i = 0; i < len; i++) {
1941                 pingroup = config[i].pingroup;
1942                 if (pmx->soc->groups[pingroup].pupd_reg > 0) {
1943                         err = tegra_pinctrl_pg_set_pullupdown(pingroup, pupd);
1944                         if (err < 0)
1945                                 pr_err("pinmux: can't set pingroup %s pullupdown"
1946                                         " to %s: %d\n",
1947                                         pmx->soc->groups[pingroup].name,
1948                                         tegra_pinctrl_pupd_name(pupd), err);
1949                 }
1950         }
1951 }
1952 EXPORT_SYMBOL(tegra_pinctrl_pg_config_pullupdown_table);
1953
1954 #ifdef  CONFIG_DEBUG_FS
1955
1956 #include <linux/debugfs.h>
1957 #include <linux/seq_file.h>
1958
1959 static void dbg_pad_field(struct seq_file *s, int len)
1960 {
1961         seq_putc(s, ',');
1962
1963         while (len-- > -1)
1964                 seq_putc(s, ' ');
1965 }
1966
1967 static int dbg_pinmux_show(struct seq_file *s, void *unused)
1968 {
1969         int i;
1970         int len;
1971
1972         for (i = 0; i < pmx->soc->ngroups; i++) {
1973                 unsigned long reg;
1974                 unsigned long tri;
1975                 unsigned long mux;
1976                 unsigned long pupd;
1977
1978                 if (!pmx->soc->groups[i].name)
1979                         continue;
1980
1981                 if (pmx->soc->groups[i].mux_reg < 0)
1982                         continue;
1983
1984                 seq_printf(s, "\t{%s", pmx->soc->groups[i].name);
1985                 len = strlen(pmx->soc->groups[i].name);
1986                 dbg_pad_field(s, 15 - len);
1987
1988                 if (pmx->soc->groups[i].mux_reg < 0) {
1989                         seq_puts(s, "TEGRA_MUX_NONE");
1990                         len = strlen("NONE");
1991                 } else {
1992                         reg = pmx_readl(pmx, pmx->soc->groups[i].mux_bank,
1993                                         pmx->soc->groups[i].mux_reg);
1994                         mux = (reg >> pmx->soc->groups[i].mux_bit) & 0x3;
1995                         BUG_ON(pmx->soc->groups[i].funcs[mux] == 0);
1996                         if (pmx->soc->groups[i].funcs[mux] ==
1997                                                 TEGRA_MUX_INVALID) {
1998                                 seq_puts(s, "TEGRA_MUX_INVALID");
1999                                 len = 7;
2000                         } else if (pmx->soc->groups[i].funcs[mux] &
2001                                                 TEGRA_MUX_RSVD) {
2002                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux);
2003                                 len = 5;
2004                         } else {
2005                                 seq_printf(s, "TEGRA_MUX_%s",
2006                                         tegra_pinctrl_function_name(
2007                                            pmx->soc->groups[i].funcs[mux]));
2008                                 len = strlen(tegra_pinctrl_function_name(
2009                                         pmx->soc->groups[i].funcs[mux]));
2010                         }
2011                 }
2012                 dbg_pad_field(s, 13-len);
2013
2014                 if (pmx->soc->groups[i].einput_reg >= 0) {
2015                         unsigned long io;
2016                         io = (pmx_readl(pmx, pmx->soc->groups[i].mux_bank,
2017                                 pmx->soc->groups[i].mux_reg) >> 5) & 0x1;
2018                         seq_printf(s, "TEGRA_PIN_%s",
2019                                         tegra_pinctrl_io_name(io));
2020                         len = strlen(tegra_pinctrl_io_name(io));
2021                         dbg_pad_field(s, 6 - len);
2022                 }
2023                 if (pmx->soc->groups[i].pupd_reg < 0) {
2024                         seq_puts(s, "TEGRA_PUPD_NORMAL");
2025                         len = strlen("NORMAL");
2026                 } else {
2027                         reg = pmx_readl(pmx, pmx->soc->groups[i].pupd_bank,
2028                                         pmx->soc->groups[i].pupd_reg);
2029                         pupd = (reg >> pmx->soc->groups[i].pupd_bit) & 0x3;
2030                         seq_printf(s, "TEGRA_PUPD_%s",
2031                                 tegra_pinctrl_pupd_name(pupd));
2032                         len = strlen(tegra_pinctrl_pupd_name(pupd));
2033                 }
2034                 dbg_pad_field(s, 9 - len);
2035
2036                 if (pmx->soc->groups[i].tri_reg < 0) {
2037                         seq_puts(s, "TEGRA_TRI_NORMAL");
2038                 } else {
2039                         reg = pmx_readl(pmx, pmx->soc->groups[i].tri_bank,
2040                                         pmx->soc->groups[i].tri_reg);
2041                         tri = (reg >> pmx->soc->groups[i].tri_bit) & 0x1;
2042
2043                         seq_printf(s, "TEGRA_TRI_%s",
2044                                         tegra_pinctrl_tri_name(tri));
2045                 }
2046                 seq_puts(s, "},\n");
2047         }
2048         return 0;
2049 }
2050
2051 static int dbg_pinmux_open(struct inode *inode, struct file *file)
2052 {
2053         return single_open(file, dbg_pinmux_show, &inode->i_private);
2054 }
2055
2056 /*
2057  * Changing pinmux configuration at runtime
2058  *
2059  * Usage: Feed "<PINGROUP> <FUNCTION> <E_INPUT> <PUPD> <TRISTATE>"
2060  *      to tegra_pinmux
2061  * ex) # echo "HDMI_CEC CEC OUTPUT NORMAL TRISTATE" > /d/tegra_pinmux
2062  */
2063 #define FIELD_DELIMITER " "
2064 #define LINE_DELIMITER  "\n"
2065 static ssize_t dbg_pinmux_write(struct file *file,
2066         const char __user *userbuf, size_t count, loff_t *ppos)
2067 {
2068         char buf[80];
2069         char *pbuf = &buf[0];
2070         char *token;
2071         struct tegra_pingroup_config pg_config;
2072         int i;
2073
2074         if (sizeof(buf) <= count)
2075                 return -EINVAL;
2076         if (copy_from_user(buf, userbuf, count))
2077                 return -EFAULT;
2078
2079         pr_debug("%s buf: %s\n", __func__, buf);
2080
2081         /* ping group index by name */
2082         token = strsep(&pbuf, FIELD_DELIMITER);
2083         for (i = 0; i < pmx->soc->ngroups; i++)
2084                 if (!strcasecmp(token, pmx->soc->groups[i].name))
2085                         break;
2086         if (i == pmx->soc->ngroups) { /* no pingroup matched with name */
2087                 pr_err("no pingroup matched with name\n");
2088                 return -EINVAL;
2089         }
2090         pg_config.pingroup = i;
2091
2092         /* func index by name */
2093         token = strsep(&pbuf, FIELD_DELIMITER);
2094         for (i = 0; i < TEGRA_MAX_MUX; i++)
2095                 if (!strcasecmp(token, tegra_pinctrl_function_name(i)))
2096                         break;
2097         if (i == TEGRA_MAX_MUX) { /* no func matched with name */
2098                 pr_err("no func matched with name\n");
2099                 return -EINVAL;
2100         }
2101         pg_config.func = i;
2102
2103         /* i/o by name */
2104         token = strsep(&pbuf, FIELD_DELIMITER);
2105         i = !strcasecmp(token, "OUTPUT") ? 0 :
2106                 !strcasecmp(token, "INPUT") ? 1 : -1;
2107         if (i == -1) { /* no IO matched with name */
2108                 pr_err("no IO matched with name\n");
2109                 return -EINVAL;
2110         }
2111         pg_config.io = i;
2112
2113         /* pull up/down by name */
2114         token = strsep(&pbuf, FIELD_DELIMITER);
2115         i = !strcasecmp(token, "NORMAL") ? 0 :
2116                 !strcasecmp(token, "PULL_DOWN") ? 1 :
2117                 !strcasecmp(token, "PULL_UP") ? 2 : -1;
2118         if (i == -1) { /* no PUPD matched with  name */
2119                 pr_err("no PUPD matched with  name\n");
2120                 return -EINVAL;
2121         }
2122         pg_config.pupd = i;
2123
2124         /* tristate by name */
2125         token = strsep(&pbuf, LINE_DELIMITER);
2126         i = !strcasecmp(token, "NORMAL") ? 0 :
2127                 !strcasecmp(token, "TRISTATE") ? 1 : -1;
2128         if (i == -1) { /* no tristate matched with name */
2129                 pr_err("no tristate matched with name\n");
2130                 return -EINVAL;
2131         }
2132         pg_config.tristate = i;
2133
2134         pr_debug("pingroup=%d, func=%d, io=%d, pupd=%d, tristate=%d\n",
2135                         pg_config.pingroup, pg_config.func, pg_config.io,
2136                         pg_config.pupd, pg_config.tristate);
2137         tegra_pinctrl_pg_set_func(&pg_config);
2138         tegra_pinctrl_pg_set_pullupdown(pg_config.pingroup, pg_config.pupd);
2139         tegra_pinctrl_pg_set_tristate(pg_config.pingroup, pg_config.tristate);
2140
2141         return count;
2142 }
2143
2144 static const struct file_operations debug_fops = {
2145         .open           = dbg_pinmux_open,
2146         .write          = dbg_pinmux_write,
2147         .read           = seq_read,
2148         .llseek         = seq_lseek,
2149         .release        = single_release,
2150 };
2151
2152 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
2153 {
2154         int i;
2155         int len;
2156         u8 offset;
2157         unsigned int width;
2158
2159         for (i = 0; i < pmx->soc->ngroups; i++) {
2160                 u32 reg;
2161
2162                 if (pmx->soc->groups[i].drv_reg < 0)
2163                         continue;
2164
2165                 seq_printf(s, "\t{%s", pmx->soc->groups[i].name);
2166                 len = strlen(pmx->soc->groups[i].name);
2167                 dbg_pad_field(s, 15 - len);
2168
2169
2170                 reg = pmx_readl(pmx, pmx->soc->groups[i].drv_bank,
2171                                         pmx->soc->groups[i].drv_reg);
2172                 if (pmx->soc->groups[i].hsm_bit >= 0) {
2173                         if (HSM_EN(reg)) {
2174                                 seq_puts(s, "TEGRA_HSM_ENABLE");
2175                                 len = 16;
2176                         } else {
2177                                 seq_puts(s, "TEGRA_HSM_DISABLE");
2178                                 len = 17;
2179                         }
2180                 } else {
2181                         seq_puts(s, "TEGRA_HSM_XXXXXX");
2182                         len = 16;
2183                 }
2184
2185                 dbg_pad_field(s, 17 - len);
2186
2187                 if (pmx->soc->groups[i].schmitt_bit >= 0) {
2188                         if (SCHMT_EN(reg)) {
2189                                 seq_puts(s, "TEGRA_SCHMITT_ENABLE");
2190                                 len = 21;
2191                         } else {
2192                                 seq_puts(s, "TEGRA_SCHMITT_DISABLE");
2193                                 len = 22;
2194                         }
2195                 } else {
2196                         seq_puts(s, "TEGRA_SCHMITT_XXXXXXX");
2197                         len = 22;
2198                 }
2199                 dbg_pad_field(s, 22 - len);
2200
2201                 if (pmx->soc->groups[i].lpmd_bit < 0) {
2202                         seq_printf(s, "TEGRA_DRIVE_XXXXX");
2203                         len = 5;
2204                 } else {
2205                         seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
2206                         len = strlen(drive_name(LPMD(reg)));
2207                 }
2208                 dbg_pad_field(s, 5 - len);
2209
2210                 if (pmx->soc->groups[i].drvdn_bit >= 0) {
2211                         offset = pmx->soc->groups[i].drvdn_bit;
2212                         width = pmx->soc->groups[i].drvdn_width;
2213                         seq_printf(s, "TEGRA_PULL_%lu",
2214                                         DRVDN(reg, offset, width));
2215                         len = DRVDN(reg, offset, width) < 10 ? 1 : 2;
2216                 } else {
2217                         seq_printf(s, "TEGRA_PULL_XXX");
2218                         len = 1;
2219                 }
2220                 dbg_pad_field(s, 2 - len);
2221
2222                 if (pmx->soc->groups[i].drvup_bit >= 0) {
2223                         offset = pmx->soc->groups[i].drvup_bit;
2224                         width = pmx->soc->groups[i].drvup_width;
2225                         seq_printf(s, "TEGRA_PULL_%lu",
2226                                         DRVUP(reg, offset, width));
2227                         len = DRVUP(reg, offset, width) < 10 ? 1 : 2;
2228                 } else {
2229                         seq_printf(s, "TEGRA_PULL_XXX");
2230                         len = 1;
2231                 }
2232                 dbg_pad_field(s, 2 - len);
2233
2234                 if (pmx->soc->groups[i].slwr_bit >= 0) {
2235                         offset = pmx->soc->groups[i].slwr_bit;
2236                         width = pmx->soc->groups[i].slwr_width;
2237                         seq_printf(s, "TEGRA_SLEW_%s",
2238                                 slew_name(SLWR(reg, offset, width)));
2239                         len = strlen(slew_name(SLWR(reg, offset, width)));
2240                 } else {
2241                         seq_printf(s, "TEGRA_SLEW_XXXXXXX");
2242                         len = 7;
2243                 }
2244                 dbg_pad_field(s, 7 - len);
2245
2246                 if (pmx->soc->groups[i].slwf_bit >= 0) {
2247                         offset = pmx->soc->groups[i].slwf_bit;
2248                         width = pmx->soc->groups[i].slwf_width;
2249                         seq_printf(s, "TEGRA_SLEW_%s",
2250                                 slew_name(SLWF(reg, offset, width)));
2251                 } else {
2252                         seq_printf(s, "TEGRA_SLEW_XXXXXXX");
2253                 }
2254
2255                 seq_puts(s, "},\n");
2256         }
2257         return 0;
2258 }
2259
2260 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
2261 {
2262         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
2263 }
2264
2265 static const struct file_operations debug_drive_fops = {
2266         .open           = dbg_drive_pinmux_open,
2267         .read           = seq_read,
2268         .llseek         = seq_lseek,
2269         .release        = single_release,
2270 };
2271
2272 static int dbg_reg_pinmux_show(struct seq_file *s, void *unused)
2273 {
2274         int i;
2275         u32 offset;
2276         u32 reg;
2277         int bank;
2278
2279         for (i = 0; i < pmx->soc->ngroups; i++) {
2280                 if (pmx->soc->groups[i].drv_reg < 0) {
2281                         bank = pmx->soc->groups[i].mux_bank;
2282                         offset = pmx->soc->groups[i].mux_reg;
2283                 } else {
2284                         bank = pmx->soc->groups[i].drv_bank;
2285                         offset = pmx->soc->groups[i].drv_reg;
2286                 }
2287                 reg = pmx_readl(pmx, bank, offset);
2288                 seq_printf(s, "Bank: %d Reg: 0x%08x Val: 0x%08x -> %s\n",
2289                                 bank, pmx->reg_base[bank] + offset, reg,
2290                                 pmx->soc->groups[i].name);
2291         }
2292         return 0;
2293 }
2294
2295 static int dbg_reg_pinmux_open(struct inode *inode, struct file *file)
2296 {
2297         return single_open(file, dbg_reg_pinmux_show, &inode->i_private);
2298 }
2299
2300 static const struct file_operations debug_reg_fops = {
2301         .open           = dbg_reg_pinmux_open,
2302         .read           = seq_read,
2303         .llseek         = seq_lseek,
2304         .release        = single_release,
2305 };
2306
2307 static int __init tegra_pinctrl_debuginit(void)
2308 {
2309         if (!pmx)
2310                 return 0;
2311
2312         (void) debugfs_create_file("tegra_pinctrl", S_IRUGO | S_IWUSR | S_IWGRP,
2313                                         NULL, NULL, &debug_fops);
2314         (void) debugfs_create_file("tegra_pinctrl_drive", S_IRUGO,
2315                                         NULL, NULL, &debug_drive_fops);
2316         (void) debugfs_create_file("tegra_pinctrl_reg", S_IRUGO,
2317                                         NULL, NULL, &debug_reg_fops);
2318         return 0;
2319 }
2320 late_initcall(tegra_pinctrl_debuginit);
2321 #endif