drivers/usb/host/xhci-tegra.c

   1 /*
   2  * xhci-tegra.c - Nvidia xHCI host controller driver
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <linux/ioport.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/irq.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/platform_data/tegra_usb.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/kthread.h>
  34 #include <linux/gpio.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-powergate.h>
  38
  39 #include <mach/tegra_usb_pad_ctrl.h>
  40 #include <mach/tegra_usb_pmc.h>
  41 #include <mach/pm_domains.h>
  42 #include <mach/mc.h>
  43 #include <mach/xusb.h>
  44
  45 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
  46 #include "xhci-tegra.h"
  47 #include "xhci.h"
  48
  49 /* macros */
  50 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
  51 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
  52 #define FW_IOCTL_DATA_SHIFT             (0)
  53 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
  54 #define FW_IOCTL_TYPE_SHIFT             (24)
  55 #define FW_IOCTL_TYPE_MASK              (0xff000000)
  56 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
  57 #define FW_LOG_COUNT                    (4096)
  58 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
  59 #define FW_LOG_PAYLOAD_SIZE             (27)
  60 #define DRIVER                          (0x01)
  61 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
  62 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
  63
  64 /* tegra_xhci_firmware_log.flags bits */
  65 #define FW_LOG_CONTEXT_VALID            (0)
  66 #define FW_LOG_FILE_OPENED              (1)
  67
  68 #define PAGE_SELECT_MASK                        0xFFFFFE00
  69 #define PAGE_SELECT_SHIFT                       9
  70 #define PAGE_OFFSET_MASK                        0x000001FF
  71 #define CSB_PAGE_SELECT(_addr)                                          \
  72         ({                                                              \
  73                 typecheck(u32, _addr);                                  \
  74                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
  75         })
  76 #define CSB_PAGE_OFFSET(_addr)                                          \
  77         ({                                                              \
  78                 typecheck(u32, _addr);                                  \
  79                 (_addr & PAGE_OFFSET_MASK);                             \
  80         })
  81
  82 #define reg_dump(_dev, _base, _reg)                                     \
  83         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
  84                 _reg, readl(_base + _reg))
  85
  86 /* PMC register definition */
  87 #define PMC_PORT_UTMIP_P0               0
  88 #define PMC_PORT_UTMIP_P1               1
  89 #define PMC_PORT_UTMIP_P2               2
  90 #define PMC_PORT_UHSIC_P0               3
  91 #define PMC_PORT_NUM                    4
  92
  93 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
  94 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
  95 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
  96
  97 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
  98
  99 /* private data types */
 100 /* command requests from the firmware */
 101 enum MBOX_CMD_TYPE {
 102         MBOX_CMD_MSG_ENABLED = 1,
 103         MBOX_CMD_INC_FALC_CLOCK,
 104         MBOX_CMD_DEC_FALC_CLOCK,
 105         MBOX_CMD_INC_SSPI_CLOCK,
 106         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
 107         MBOX_CMD_SET_BW,
 108         MBOX_CMD_SET_SS_PWR_GATING,
 109         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
 110         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 111         MBOX_CMD_AIRPLANE_MODE_ENABLED,
 112         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11 */
 113         MBOX_CMD_STAR_HSIC_IDLE,
 114         MBOX_CMD_STOP_HSIC_IDLE,
 115
 116         /* needs to be the last cmd */
 117         MBOX_CMD_MAX,
 118
 119         /* resp msg to ack above commands */
 120         MBOX_CMD_ACK = 128,
 121         MBOX_CMD_NACK
 122 };
 123
 124 struct log_entry {
 125         u32 sequence_no;
 126         u8 data[FW_LOG_PAYLOAD_SIZE];
 127         u8 owner;
 128 };
 129
 130 /* Usb3 Firmware Cfg Table */
 131 struct cfgtbl {
 132         u32 boot_loadaddr_in_imem;
 133         u32 boot_codedfi_offset;
 134         u32 boot_codetag;
 135         u32 boot_codesize;
 136
 137         /* Physical memory reserved by Bootloader/BIOS */
 138         u32 phys_memaddr;
 139         u16 reqphys_memsize;
 140         u16 alloc_phys_memsize;
 141
 142         /* .rodata section */
 143         u32 rodata_img_offset;
 144         u32 rodata_section_start;
 145         u32 rodata_section_end;
 146         u32 main_fnaddr;
 147
 148         u32 fwimg_cksum;
 149         u32 fwimg_created_time;
 150
 151         /* Fields that get filled by linker during linking phase
 152          * or initialized in the FW code.
 153          */
 154         u32 imem_resident_start;
 155         u32 imem_resident_end;
 156         u32 idirect_start;
 157         u32 idirect_end;
 158         u32 l2_imem_start;
 159         u32 l2_imem_end;
 160         u32 version_id;
 161         u8 init_ddirect;
 162         u8 reserved[3];
 163         u32 phys_addr_log_buffer;
 164         u32 total_log_entries;
 165         u32 dequeue_ptr;
 166
 167         /*      Below two dummy variables are used to replace
 168          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
 169          *      retain the size of struct _CFG_TBL used by other AP/Module.
 170          */
 171         u32 dummy_var1;
 172         u32 dummy_var2;
 173
 174         /* fwimg_len */
 175         u32 fwimg_len;
 176         u8 magic[8];
 177         u32 SS_low_power_entry_timeout;
 178         u8 num_hsic_port;
 179         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
 180 };
 181
 182 struct xusb_save_regs {
 183         u32 msi_bar_sz;
 184         u32 msi_axi_barst;
 185         u32 msi_fpci_barst;
 186         u32 msi_vec0;
 187         u32 msi_en_vec0;
 188         u32 fpci_error_masks;
 189         u32 intr_mask;
 190         u32 ipfs_intr_enable;
 191         u32 ufpci_config;
 192         u32 clkgate_hysteresis;
 193         u32 xusb_host_mccif_fifo_cntrl;
 194
 195         /* PG does not mention below */
 196         u32 hs_pls;
 197         u32 fs_pls;
 198         u32 hs_fs_speed;
 199         u32 hs_fs_pp;
 200         u32 cfg_aru;
 201         u32 cfg_order;
 202         u32 cfg_fladj;
 203         u32 cfg_sid;
 204         /* DFE and CTLE */
 205         u32 tap1_val[XUSB_SS_PORT_COUNT];
 206         u32 amp_val[XUSB_SS_PORT_COUNT];
 207         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
 208         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
 209 };
 210
 211 struct tegra_xhci_firmware {
 212         void *data; /* kernel virtual address */
 213         size_t size; /* firmware size */
 214         dma_addr_t dma; /* dma address for controller */
 215 };
 216
 217 struct tegra_xhci_firmware_log {
 218         dma_addr_t phys_addr;           /* dma-able address */
 219         void *virt_addr;                /* kernel va of the shared log buffer */
 220         struct log_entry *dequeue;      /* current dequeue pointer (va) */
 221         struct circ_buf circ;           /* big circular buffer */
 222         u32 seq;                        /* log sequence number */
 223
 224         struct task_struct *thread;     /* a thread to consume log */
 225         struct mutex mutex;
 226         wait_queue_head_t read_wait;
 227         wait_queue_head_t write_wait;
 228         wait_queue_head_t intr_wait;
 229         struct dentry *path;
 230         struct dentry *log_file;
 231         unsigned long flags;
 232 };
 233
 234 /* structure to hold the offsets of padctl registers */
 235 struct tegra_xusb_padctl_regs {
 236         u16 boot_media_0;
 237         u16 usb2_pad_mux_0;
 238         u16 usb2_port_cap_0;
 239         u16 snps_oc_map_0;
 240         u16 usb2_oc_map_0;
 241         u16 ss_port_map_0;
 242         u16 oc_det_0;
 243         u16 elpg_program_0;
 244         u16 usb2_bchrg_otgpad0_ctl0_0;
 245         u16 usb2_bchrg_otgpad0_ctl1_0;
 246         u16 usb2_bchrg_otgpad1_ctl0_0;
 247         u16 usb2_bchrg_otgpad1_ctl1_0;
 248         u16 usb2_bchrg_otgpad2_ctl0_0;
 249         u16 usb2_bchrg_otgpad2_ctl1_0;
 250         u16 usb2_bchrg_bias_pad_0;
 251         u16 usb2_bchrg_tdcd_dbnc_timer_0;
 252         u16 iophy_pll_p0_ctl1_0;
 253         u16 iophy_pll_p0_ctl2_0;
 254         u16 iophy_pll_p0_ctl3_0;
 255         u16 iophy_pll_p0_ctl4_0;
 256         u16 iophy_usb3_pad0_ctl1_0;
 257         u16 iophy_usb3_pad1_ctl1_0;
 258         u16 iophy_usb3_pad0_ctl2_0;
 259         u16 iophy_usb3_pad1_ctl2_0;
 260         u16 iophy_usb3_pad0_ctl3_0;
 261         u16 iophy_usb3_pad1_ctl3_0;
 262         u16 iophy_usb3_pad0_ctl4_0;
 263         u16 iophy_usb3_pad1_ctl4_0;
 264         u16 iophy_misc_pad_p0_ctl1_0;
 265         u16 iophy_misc_pad_p1_ctl1_0;
 266         u16 iophy_misc_pad_p0_ctl2_0;
 267         u16 iophy_misc_pad_p1_ctl2_0;
 268         u16 iophy_misc_pad_p0_ctl3_0;
 269         u16 iophy_misc_pad_p1_ctl3_0;
 270         u16 iophy_misc_pad_p0_ctl4_0;
 271         u16 iophy_misc_pad_p1_ctl4_0;
 272         u16 iophy_misc_pad_p0_ctl5_0;
 273         u16 iophy_misc_pad_p1_ctl5_0;
 274         u16 iophy_misc_pad_p0_ctl6_0;
 275         u16 iophy_misc_pad_p1_ctl6_0;
 276         u16 usb2_otg_pad0_ctl0_0;
 277         u16 usb2_otg_pad1_ctl0_0;
 278         u16 usb2_otg_pad2_ctl0_0;
 279         u16 usb2_otg_pad0_ctl1_0;
 280         u16 usb2_otg_pad1_ctl1_0;
 281         u16 usb2_otg_pad2_ctl1_0;
 282         u16 usb2_bias_pad_ctl0_0;
 283         u16 usb2_bias_pad_ctl1_0;
 284         u16 usb2_hsic_pad0_ctl0_0;
 285         u16 usb2_hsic_pad1_ctl0_0;
 286         u16 usb2_hsic_pad0_ctl1_0;
 287         u16 usb2_hsic_pad1_ctl1_0;
 288         u16 usb2_hsic_pad0_ctl2_0;
 289         u16 usb2_hsic_pad1_ctl2_0;
 290         u16 ulpi_link_trim_ctl0;
 291         u16 ulpi_null_clk_trim_ctl0;
 292         u16 hsic_strb_trim_ctl0;
 293         u16 wake_ctl0;
 294         u16 pm_spare0;
 295         u16 iophy_misc_pad_p2_ctl1_0;
 296         u16 iophy_misc_pad_p3_ctl1_0;
 297         u16 iophy_misc_pad_p4_ctl1_0;
 298         u16 iophy_misc_pad_p2_ctl2_0;
 299         u16 iophy_misc_pad_p3_ctl2_0;
 300         u16 iophy_misc_pad_p4_ctl2_0;
 301         u16 iophy_misc_pad_p2_ctl3_0;
 302         u16 iophy_misc_pad_p3_ctl3_0;
 303         u16 iophy_misc_pad_p4_ctl3_0;
 304         u16 iophy_misc_pad_p2_ctl4_0;
 305         u16 iophy_misc_pad_p3_ctl4_0;
 306         u16 iophy_misc_pad_p4_ctl4_0;
 307         u16 iophy_misc_pad_p2_ctl5_0;
 308         u16 iophy_misc_pad_p3_ctl5_0;
 309         u16 iophy_misc_pad_p4_ctl5_0;
 310         u16 iophy_misc_pad_p2_ctl6_0;
 311         u16 iophy_misc_pad_p3_ctl6_0;
 312         u16 iophy_misc_pad_p4_ctl6_0;
 313         u16 usb3_pad_mux_0;
 314         u16 iophy_pll_s0_ctl1_0;
 315         u16 iophy_pll_s0_ctl2_0;
 316         u16 iophy_pll_s0_ctl3_0;
 317         u16 iophy_pll_s0_ctl4_0;
 318         u16 iophy_misc_pad_s0_ctl1_0;
 319         u16 iophy_misc_pad_s0_ctl2_0;
 320         u16 iophy_misc_pad_s0_ctl3_0;
 321         u16 iophy_misc_pad_s0_ctl4_0;
 322         u16 iophy_misc_pad_s0_ctl5_0;
 323         u16 iophy_misc_pad_s0_ctl6_0;
 324 };
 325
 326 struct tegra_xhci_hcd {
 327         struct platform_device *pdev;
 328         struct xhci_hcd *xhci;
 329         u16 device_id;
 330
 331         spinlock_t lock;
 332         struct mutex sync_lock;
 333
 334         int smi_irq;
 335         int padctl_irq;
 336         int usb3_irq;
 337         int usb2_irq;
 338
 339         bool ss_wake_event;
 340         bool ss_pwr_gated;
 341         bool host_pwr_gated;
 342         bool hs_wake_event;
 343         bool host_resume_req;
 344         bool lp0_exit;
 345         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
 346         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
 347         unsigned long last_jiffies;
 348         unsigned long host_phy_base;
 349         void __iomem *host_phy_virt_base;
 350
 351         void __iomem *padctl_base;
 352         void __iomem *fpci_base;
 353         void __iomem *ipfs_base;
 354
 355         struct tegra_xusb_platform_data *pdata;
 356         struct tegra_xusb_board_data *bdata;
 357         struct tegra_xusb_padctl_regs *padregs;
 358
 359         /* mailbox variables */
 360         struct mutex mbox_lock;
 361         u32 mbox_owner;
 362         u32 cmd_type;
 363         u32 cmd_data;
 364
 365         struct regulator *xusb_s5p0v_reg;
 366         struct regulator *xusb_s5p0v1_reg;
 367         struct regulator *xusb_s5p0v2_reg;
 368         struct regulator *xusb_s1p05v_reg;
 369         struct regulator *xusb_s3p3v_reg;
 370         struct regulator *xusb_s1p8v_reg;
 371         struct regulator *vddio_hsic_reg;
 372         int vddio_hsic_refcnt;
 373
 374         struct work_struct mbox_work;
 375         struct work_struct ss_elpg_exit_work;
 376         struct work_struct host_elpg_exit_work;
 377
 378         struct clk *host_clk;
 379         struct clk *ss_clk;
 380
 381         /* XUSB Falcon SuperSpeed Clock */
 382         struct clk *falc_clk;
 383
 384         /* EMC Clock */
 385         struct clk *emc_clk;
 386         /* XUSB SS PI Clock */
 387         struct clk *ss_src_clk;
 388         /* PLLE Clock */
 389         struct clk *plle_clk;
 390         struct clk *pll_u_480M;
 391         struct clk *clk_m;
 392         /* refPLLE clk */
 393         struct clk *pll_re_vco_clk;
 394         /*
 395          * XUSB/IPFS specific registers these need to be saved/restored in
 396          * addition to spec defined registers
 397          */
 398         struct xusb_save_regs sregs;
 399         bool usb2_rh_suspend;
 400         bool usb3_rh_suspend;
 401         bool hc_in_elpg;
 402
 403         /* otg transceiver */
 404         struct usb_phy *transceiver;
 405         struct notifier_block otgnb;
 406
 407         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
 408         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
 409         /* firmware loading related */
 410         struct tegra_xhci_firmware firmware;
 411
 412         struct tegra_xhci_firmware_log log;
 413 };
 414
 415 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
 416 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
 417
 418 /* functions */
 419 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
 420 {
 421         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
 422 }
 423
 424 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
 425 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 426 {
 427         WARN_ON(tegra->sync_lock.owner != current);
 428 }
 429 #else
 430 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 431 #endif
 432
 433 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
 434 {
 435         int err = 0;
 436
 437         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
 438                 return;
 439
 440         if (tegra->bdata->lane_owner & BIT(0)) {
 441                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
 442                  * GPIO P11 to '0'
 443                  */
 444                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
 445                         "gpio_ss1_sata");
 446                 if (err < 0)
 447                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
 448                                 __func__, err);
 449                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
 450                         & 0xffff), 1);
 451                 if (err < 0)
 452                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
 453                                 __func__, err);
 454                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
 455                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
 456         }
 457 }
 458
 459 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
 460 {
 461         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
 462         __le32 __iomem *addr;
 463
 464         if (port >= num_ports) {
 465                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
 466                 return -1;
 467         }
 468
 469         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
 470         return xhci_readl(xhci, addr);
 471 }
 472
 473 static void debug_print_portsc(struct xhci_hcd *xhci)
 474 {
 475         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
 476         u32 reg;
 477         int i;
 478         int ports;
 479
 480         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 481         for (i = 0; i < ports; i++) {
 482                 reg = xhci_read_portsc(xhci, i);
 483                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
 484                                 addr, i, (unsigned int) reg);
 485                 addr += NUM_PORT_REGS;
 486         }
 487 }
 488 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
 489
 490 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
 491 {
 492         if (!tegra->transceiver)
 493                 return true;
 494         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
 495                 return true;
 496         else
 497                 return false;
 498 }
 499
 500 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
 501 {
 502         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
 503         u32 portsc;
 504
 505         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
 506         if (DEV_FULLSPEED(portsc))
 507                 return USB_PMC_PORT_SPEED_FULL;
 508         else if (DEV_HIGHSPEED(portsc))
 509                 return USB_PMC_PORT_SPEED_HIGH;
 510         else if (DEV_LOWSPEED(portsc))
 511                 return USB_PMC_PORT_SPEED_LOW;
 512         else if (DEV_SUPERSPEED(portsc))
 513                 return USB_PMC_PORT_SPEED_SUPER;
 514         else
 515                 return USB_PMC_PORT_SPEED_UNKNOWN;
 516 }
 517
 518 static void pmc_init(struct tegra_xhci_hcd *tegra)
 519 {
 520         struct tegra_usb_pmc_data *pmc;
 521         struct device *dev = &tegra->pdev->dev;
 522         int pad;
 523
 524         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 525                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 526                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 527                         pmc = &pmc_data[pad];
 528                         pmc->instance = pad;
 529                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
 530                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 531                         pmc->controller_type = TEGRA_USB_3_0;
 532                         tegra_usb_pmc_init(pmc);
 533                 }
 534         }
 535
 536         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
 537                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
 538                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 539
 540                         pmc = &pmc_hsic_data[pad];
 541                         pmc->instance = pad + 1;
 542                         pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
 543                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 544                         pmc->controller_type = TEGRA_USB_3_0;
 545                         tegra_usb_pmc_init(pmc);
 546                 }
 547         }
 548
 549 }
 550
 551 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
 552 {
 553         struct tegra_usb_pmc_data *pmc;
 554         struct device *dev = &tegra->pdev->dev;
 555         u32 portsc;
 556         int port;
 557         int pad;
 558
 559         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
 560                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
 561                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 562
 563                         pmc = &pmc_hsic_data[pad];
 564                         port = hsic_pad_to_port(pad);
 565                         portsc = xhci_read_portsc(tegra->xhci, port);
 566                         dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
 567                                         __func__, pad, portsc);
 568
 569                         if (((int) portsc != -1) && (portsc & PORT_CONNECT))
 570                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 571                 }
 572         }
 573
 574         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 575                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 576                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 577                         pmc = &pmc_data[pad];
 578                         pmc->port_speed = update_speed(tegra, pad);
 579                         if (pad == 0) {
 580                                 if (is_otg_host(tegra))
 581                                         pmc->pmc_ops->setup_pmc_wake_detect(
 582                                                                         pmc);
 583                         } else
 584                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 585                 }
 586         }
 587 }
 588
 589 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
 590 {
 591         struct tegra_usb_pmc_data *pmc;
 592         struct device *dev = &tegra->pdev->dev;
 593         int pad;
 594
 595         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
 596                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
 597                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 598
 599                         pmc = &pmc_hsic_data[pad];
 600                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 601                 }
 602         }
 603
 604         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 605                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 606                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 607                         pmc = &pmc_data[pad];
 608                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 609                 }
 610         }
 611 }
 612
 613 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
 614 {
 615         void __iomem *fpci_base = tegra->fpci_base;
 616         struct platform_device *pdev = tegra->pdev;
 617         u32 input_addr;
 618         u32 data;
 619         u32 csb_page_select;
 620
 621         /* to select the appropriate CSB page to write to */
 622         csb_page_select = CSB_PAGE_SELECT(addr);
 623
 624         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
 625                         csb_page_select);
 626
 627         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 628
 629         /* selects the appropriate offset in the page to read from */
 630         input_addr = CSB_PAGE_OFFSET(addr);
 631         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 632
 633         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
 634                         input_addr, data);
 635         return data;
 636 }
 637
 638 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
 639 {
 640         void __iomem *fpci_base = tegra->fpci_base;
 641         struct platform_device *pdev = tegra->pdev;
 642         u32 input_addr;
 643         u32 csb_page_select;
 644
 645         /* to select the appropriate CSB page to write to */
 646         csb_page_select = CSB_PAGE_SELECT(addr);
 647
 648         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
 649                         csb_page_select);
 650
 651         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 652
 653         /* selects the appropriate offset in the page to write to */
 654         input_addr = CSB_PAGE_OFFSET(addr);
 655         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 656
 657         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
 658                         input_addr, data);
 659 }
 660
 661 /**
 662  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
 663  *      This function takes care of wrapping. That means when current log entry
 664  *      is the last one, it returns with the first one.
 665  *
 666  * @param log   The tegra_xhci_firmware_log context.
 667  * @param this  The current log entry.
 668  * @return      The log entry which is next to the current one.
 669  */
 670 static inline struct log_entry *fw_log_next(
 671                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
 672 {
 673         struct log_entry *first = (struct log_entry *) log->virt_addr;
 674         struct log_entry *last = first + FW_LOG_COUNT - 1;
 675
 676         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
 677
 678         return (this == last) ? first : (this + 1);
 679 }
 680
 681 /**
 682  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
 683  *      tegra_xhci_firmware_log.dequeue.
 684  *
 685  * @param log   The tegra_xhci_firmware_log context.
 686  * @param n     Counts of log entries to fast-forward.
 687  */
 688 static inline void fw_log_update_deq_pointer(
 689                 struct tegra_xhci_firmware_log *log, int n)
 690 {
 691         struct tegra_xhci_hcd *tegra =
 692                         container_of(log, struct tegra_xhci_hcd, log);
 693         struct device *dev = &tegra->pdev->dev;
 694         struct log_entry *deq = tegra->log.dequeue;
 695         dma_addr_t physical_addr;
 696         u32 reg;
 697
 698         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
 699         while (n-- > 0)
 700                 deq = fw_log_next(log, deq);
 701
 702         tegra->log.dequeue = deq;
 703         physical_addr = tegra->log.phys_addr +
 704                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
 705
 706         /* update dequeue pointer to firmware */
 707         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
 708         reg |= (physical_addr & 0xffff); /* lower 16-bits */
 709         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 710
 711         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
 712         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
 713         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 714
 715         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
 716 }
 717
 718 static inline bool circ_buffer_full(struct circ_buf *circ)
 719 {
 720         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
 721
 722         return (space <= FW_LOG_SIZE);
 723 }
 724
 725 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
 726 {
 727         return (tegra->log.dequeue->owner == DRIVER);
 728 }
 729
 730 /**
 731  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
 732  *      log buffer.
 733  * @param tegra:        tegra_xhci_hcd context
 734  * @param msec:         timeout value in millisecond
 735  * @return true:        shared log buffer is empty,
 736  *         false:       shared log buffer isn't empty.
 737  */
 738 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
 739                 unsigned timeout)
 740 {
 741         u32 target = jiffies + msecs_to_jiffies(timeout);
 742         bool ret;
 743
 744         mutex_lock(&tegra->log.mutex);
 745
 746         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
 747                 mutex_unlock(&tegra->log.mutex);
 748                 usleep_range(1000, 2000);
 749                 mutex_lock(&tegra->log.mutex);
 750         }
 751
 752         ret = fw_log_available(tegra);
 753         mutex_unlock(&tegra->log.mutex);
 754
 755         return ret;
 756 }
 757
 758 /**
 759  * fw_log_copy - copy firmware log from device's buffer to driver's circular
 760  *      buffer.
 761  * @param tegra tegra_xhci_hcd context
 762  * @return true,        We still have firmware log in device's buffer to copy.
 763  *                      This function returned due the driver's circular buffer
 764  *                      is full. Caller should invoke this function again as
 765  *                      soon as there is space in driver's circular buffer.
 766  *         false,       Device's buffer is empty.
 767  */
 768 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
 769 {
 770         struct device *dev = &tegra->pdev->dev;
 771         struct circ_buf *circ = &tegra->log.circ;
 772         int head, tail;
 773         int buffer_len, copy_len;
 774         struct log_entry *entry;
 775         struct log_entry *first = tegra->log.virt_addr;
 776
 777         while (fw_log_available(tegra)) {
 778
 779                 /* calculate maximum contiguous driver buffer length */
 780                 head = circ->head;
 781                 tail = ACCESS_ONCE(circ->tail);
 782                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
 783                 /* round down to FW_LOG_SIZE */
 784                 buffer_len -= (buffer_len % FW_LOG_SIZE);
 785                 if (!buffer_len)
 786                         return true; /* log available but no space left */
 787
 788                 /* calculate maximum contiguous log copy length */
 789                 entry = tegra->log.dequeue;
 790                 copy_len = 0;
 791                 do {
 792                         if (tegra->log.seq != entry->sequence_no) {
 793                                 dev_warn(dev,
 794                                 "%s: discontinuous seq no, expect %u get %u\n",
 795                                 __func__, tegra->log.seq, entry->sequence_no);
 796                         }
 797                         tegra->log.seq = entry->sequence_no + 1;
 798
 799                         copy_len += FW_LOG_SIZE;
 800                         buffer_len -= FW_LOG_SIZE;
 801                         if (!buffer_len)
 802                                 break; /* no space left */
 803                         entry = fw_log_next(&tegra->log, entry);
 804                 } while ((entry->owner == DRIVER) && (entry != first));
 805
 806                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
 807                 memset(tegra->log.dequeue, 0, copy_len);
 808                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
 809
 810                 mb();
 811
 812                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
 813
 814                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
 815                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
 816                 wake_up_interruptible(&tegra->log.read_wait);
 817         }
 818
 819         return false;
 820 }
 821
 822 static int fw_log_thread(void *data)
 823 {
 824         struct tegra_xhci_hcd *tegra = data;
 825         struct device *dev = &tegra->pdev->dev;
 826         struct circ_buf *circ = &tegra->log.circ;
 827         bool logs_left;
 828
 829         dev_dbg(dev, "start firmware log thread\n");
 830
 831         do {
 832                 mutex_lock(&tegra->log.mutex);
 833                 if (circ_buffer_full(circ)) {
 834                         mutex_unlock(&tegra->log.mutex);
 835                         dev_info(dev, "%s: circ buffer full\n", __func__);
 836                         wait_event_interruptible(tegra->log.write_wait,
 837                             kthread_should_stop() || !circ_buffer_full(circ));
 838                         mutex_lock(&tegra->log.mutex);
 839                 }
 840
 841                 logs_left = fw_log_copy(tegra);
 842                 mutex_unlock(&tegra->log.mutex);
 843
 844                 /* relax if no logs left  */
 845                 if (!logs_left)
 846                         wait_event_interruptible_timeout(tegra->log.intr_wait,
 847                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
 848         } while (!kthread_should_stop());
 849
 850         dev_dbg(dev, "stop firmware log thread\n");
 851         return 0;
 852 }
 853
 854 static inline bool circ_buffer_empty(struct circ_buf *circ)
 855 {
 856         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
 857 }
 858
 859 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
 860                 size_t count, loff_t *offp)
 861 {
 862         struct tegra_xhci_hcd *tegra = file->private_data;
 863         struct platform_device *pdev = tegra->pdev;
 864         struct circ_buf *circ = &tegra->log.circ;
 865         int head, tail;
 866         size_t n = 0;
 867         int s;
 868
 869         mutex_lock(&tegra->log.mutex);
 870
 871         while (circ_buffer_empty(circ)) {
 872                 mutex_unlock(&tegra->log.mutex);
 873                 if (file->f_flags & O_NONBLOCK)
 874                         return -EAGAIN; /* non-blocking read */
 875
 876                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
 877
 878                 if (wait_event_interruptible(tegra->log.read_wait,
 879                                 !circ_buffer_empty(circ)))
 880                         return -ERESTARTSYS;
 881
 882                 if (mutex_lock_interruptible(&tegra->log.mutex))
 883                         return -ERESTARTSYS;
 884         }
 885
 886         while (count > 0) {
 887                 head = ACCESS_ONCE(circ->head);
 888                 tail = circ->tail;
 889                 s = min_t(int, count,
 890                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
 891
 892                 if (s > 0) {
 893                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
 894                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
 895                                 mutex_unlock(&tegra->log.mutex);
 896                                 return -EFAULT;
 897                         }
 898                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
 899
 900                         count -= s;
 901                         n += s;
 902                 } else
 903                         break;
 904         }
 905
 906         mutex_unlock(&tegra->log.mutex);
 907
 908         wake_up_interruptible(&tegra->log.write_wait);
 909
 910         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
 911
 912         return n;
 913 }
 914
 915 static int fw_log_file_open(struct inode *inode, struct file *file)
 916 {
 917         struct tegra_xhci_hcd *tegra;
 918         file->private_data = inode->i_private;
 919         tegra = file->private_data;
 920
 921         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
 922                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
 923                 return -EBUSY;
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int fw_log_file_close(struct inode *inode, struct file *file)
 930 {
 931         struct tegra_xhci_hcd *tegra = file->private_data;
 932
 933         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
 934
 935         return 0;
 936 }
 937
 938 static const struct file_operations firmware_log_fops = {
 939                 .open           = fw_log_file_open,
 940                 .release        = fw_log_file_close,
 941                 .read           = fw_log_file_read,
 942                 .owner          = THIS_MODULE,
 943 };
 944
 945 static int fw_log_init(struct tegra_xhci_hcd *tegra)
 946 {
 947         struct platform_device *pdev = tegra->pdev;
 948         int rc = 0;
 949
 950         /* allocate buffer to be shared between driver and firmware */
 951         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
 952                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
 953
 954         if (!tegra->log.virt_addr) {
 955                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
 956                                 FW_LOG_RING_SIZE);
 957                 return -ENOMEM;
 958         }
 959
 960         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
 961                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
 962
 963         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
 964         tegra->log.dequeue = tegra->log.virt_addr;
 965
 966         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
 967         if (!tegra->log.circ.buf) {
 968                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
 969                 rc = -ENOMEM;
 970                 goto error_free_dma;
 971         }
 972
 973         tegra->log.circ.head = 0;
 974         tegra->log.circ.tail = 0;
 975
 976         init_waitqueue_head(&tegra->log.read_wait);
 977         init_waitqueue_head(&tegra->log.write_wait);
 978         init_waitqueue_head(&tegra->log.intr_wait);
 979
 980         mutex_init(&tegra->log.mutex);
 981
 982         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
 983         if (IS_ERR_OR_NULL(tegra->log.path)) {
 984                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
 985                 rc = -ENOMEM;
 986                 goto error_free_mem;
 987         }
 988
 989         tegra->log.log_file = debugfs_create_file("firmware_log",
 990                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
 991         if ((!tegra->log.log_file) ||
 992                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
 993                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
 994                 rc = -ENOMEM;
 995                 goto error_remove_debugfs_path;
 996         }
 997
 998         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
 999         if (IS_ERR(tegra->log.thread)) {
1000                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1001                 rc = -ENOMEM;
1002                 goto error_remove_debugfs_file;
1003         }
1004
1005         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1006         return rc;
1007
1008 error_remove_debugfs_file:
1009         debugfs_remove(tegra->log.log_file);
1010 error_remove_debugfs_path:
1011         debugfs_remove(tegra->log.path);
1012 error_free_mem:
1013         vfree(tegra->log.circ.buf);
1014 error_free_dma:
1015         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1016                         tegra->log.virt_addr, tegra->log.phys_addr);
1017         memset(&tegra->log, sizeof(tegra->log), 0);
1018         return rc;
1019 }
1020
1021 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1022 {
1023         struct platform_device *pdev = tegra->pdev;
1024
1025         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1026
1027                 debugfs_remove(tegra->log.log_file);
1028                 debugfs_remove(tegra->log.path);
1029
1030                 wake_up_interruptible(&tegra->log.read_wait);
1031                 wake_up_interruptible(&tegra->log.write_wait);
1032                 kthread_stop(tegra->log.thread);
1033
1034                 mutex_lock(&tegra->log.mutex);
1035                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1036                         tegra->log.virt_addr, tegra->log.phys_addr);
1037                 vfree(tegra->log.circ.buf);
1038                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1039                 mutex_unlock(&tegra->log.mutex);
1040
1041                 mutex_destroy(&tegra->log.mutex);
1042         }
1043 }
1044
1045 /* hsic pad operations */
1046 /*
1047  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1048  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1049  */
1050 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1051 {
1052         struct device *dev = &tegra->pdev->dev;
1053         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1054         int ret;
1055
1056         if (tegra->vddio_hsic_reg)
1057                 goto done;
1058
1059         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1060         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1061                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1062                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1063                 goto get_failed;
1064         }
1065
1066         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1067         ret = regulator_enable(tegra->vddio_hsic_reg);
1068         if (ret < 0) {
1069                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1070                 goto enable_failed;
1071         }
1072
1073 done:
1074         tegra->vddio_hsic_refcnt++;
1075         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1076                         "vddio_hsic_refcnt exceeds\n");
1077         return 0;
1078
1079 enable_failed:
1080         devm_regulator_put(tegra->vddio_hsic_reg);
1081 get_failed:
1082         tegra->vddio_hsic_reg = NULL;
1083         return ret;
1084 }
1085
1086 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1087 {
1088         struct device *dev = &tegra->pdev->dev;
1089         int ret;
1090
1091         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1092
1093         tegra->vddio_hsic_refcnt--;
1094         if (tegra->vddio_hsic_refcnt)
1095                 return 0;
1096
1097         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1098         ret = regulator_disable(tegra->vddio_hsic_reg);
1099         if (ret < 0) {
1100                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1101                 tegra->vddio_hsic_refcnt++;
1102                 return ret;
1103         }
1104
1105         devm_regulator_put(tegra->vddio_hsic_reg);
1106         tegra->vddio_hsic_reg = NULL;
1107
1108         return 0;
1109 }
1110
1111 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1112 {
1113         struct device *dev = &tegra->pdev->dev;
1114         void __iomem *base = tegra->padctl_base;
1115         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic;
1116         u32 reg;
1117
1118         if (pad >= XUSB_HSIC_COUNT) {
1119                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1120                 return -EINVAL;
1121         }
1122
1123         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1124
1125         reg = readl(base + HSIC_PAD_CTL_2(pad));
1126         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1127         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1128         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1129         writel(reg, base + HSIC_PAD_CTL_2(pad));
1130
1131         reg = readl(base + HSIC_PAD_CTL_0(pad));
1132         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1133         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1134         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1135         reg |= TX_SLEWP(hsic->tx_slew_p);
1136         reg |= TX_SLEWN(hsic->tx_slew_n);
1137         writel(reg, base + HSIC_PAD_CTL_0(pad));
1138
1139         reg = readl(base + HSIC_PAD_CTL_1(pad));
1140         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1141         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1142         if (hsic->auto_term_en)
1143                 reg |= AUTO_TERM_EN;
1144         else
1145                 reg &= ~AUTO_TERM_EN;
1146         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1147         writel(reg, base + HSIC_PAD_CTL_1(pad));
1148
1149         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1150         reg &= ~(STRB_TRIM_VAL(~0));
1151         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1152         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1153
1154         reg = readl(base + USB2_PAD_MUX);
1155         reg |= USB2_HSIC_PAD_PORT(pad);
1156         writel(reg, base + USB2_PAD_MUX);
1157
1158         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1159         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1160         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1161         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1162         reg_dump(dev, base, USB2_PAD_MUX);
1163         return 0;
1164 }
1165
1166 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1167 {
1168         struct device *dev = &tegra->pdev->dev;
1169         void __iomem *base = tegra->padctl_base;
1170         u32 reg;
1171
1172         if (pad >= XUSB_HSIC_COUNT) {
1173                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1174                 return -EINVAL;
1175         }
1176
1177         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1178
1179         reg = readl(base + USB2_PAD_MUX);
1180         reg &= ~USB2_HSIC_PAD_PORT(pad);
1181         writel(reg, base + USB2_PAD_MUX);
1182
1183         reg = readl(base + HSIC_PAD_CTL_1(pad));
1184         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1185         writel(reg, base + HSIC_PAD_CTL_1(pad));
1186
1187         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1188         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1189         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1190         reg_dump(dev, base, USB2_PAD_MUX);
1191         return 0;
1192 }
1193
1194 enum hsic_pad_pupd {
1195         PUPD_DISABLE = 0,
1196         PUPD_IDLE,
1197         PUPD_RESET
1198 };
1199
1200 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1201         enum hsic_pad_pupd pupd)
1202 {
1203         struct device *dev = &tegra->pdev->dev;
1204         void __iomem *base = tegra->padctl_base;
1205         u32 reg;
1206
1207         if (pad >= XUSB_HSIC_COUNT) {
1208                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1209                 return -EINVAL;
1210         }
1211
1212         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1213
1214         reg = readl(base + HSIC_PAD_CTL_1(pad));
1215         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1216
1217         if (pupd == PUPD_IDLE)
1218                 reg |= (RPD_DATA | RPU_STROBE);
1219         else if (pupd == PUPD_RESET)
1220                 reg |= (RPD_DATA | RPD_STROBE);
1221         else if (pupd != PUPD_DISABLE) {
1222                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1223                 return -EINVAL;
1224         }
1225
1226         writel(reg, base + HSIC_PAD_CTL_1(pad));
1227
1228         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1229
1230         return 0;
1231 }
1232
1233
1234 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1235 {
1236         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1237         struct xhci_hcd *xhci = tegra->xhci;
1238         u32 reg;
1239
1240         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1241         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1242         xhci_info(xhci, " PAD MUX = %x\n", reg);
1243         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1244         xhci_info(xhci, " PORT CAP = %x\n", reg);
1245         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1246         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1247         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1248         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1249         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1250         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1251         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1252         xhci_info(xhci, " OC DET 0= %x\n", reg);
1253         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1254         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1255         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1256         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1257         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1258         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1259         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1260         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1261         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1262         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1263         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1264         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1265         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1266         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1267         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1268         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1269         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1270         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1271         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1272 }
1273
1274 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1275 {
1276         u32 reg;
1277
1278         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1279         reg |= IPFS_EN_FPCI;
1280         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1281         udelay(10);
1282
1283         /* Program Bar0 Space */
1284         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1285         reg |= tegra->host_phy_base;
1286         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1287         usleep_range(100, 200);
1288
1289         /* Enable Bus Master */
1290         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1291         reg |= 0x7;
1292         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1293
1294         /* Set intr mask to enable intr assertion */
1295         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1296         reg |= IPFS_IP_INT_MASK;
1297         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1298
1299         /* Set hysteris to 0x80 */
1300         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1301 }
1302
1303 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1304                 struct platform_device *pdev)
1305 {
1306         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1307         int err = 0;
1308
1309         tegra->xusb_s3p3v_reg =
1310                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1311         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1312                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1313                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1314                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1315                 goto err_null_regulator;
1316         } else {
1317                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1318                 if (err < 0) {
1319                         dev_err(&pdev->dev,
1320                                 "3p3v: regulator enable failed:%d\n", err);
1321                         goto err_null_regulator;
1322                 }
1323         }
1324
1325         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) &&
1326                                          !tegra->transceiver) {
1327                 tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev,
1328                                                 supply->s5p0v);
1329                 if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1330                         dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1331                                 , PTR_ERR(tegra->xusb_s5p0v_reg));
1332                         err = PTR_ERR(tegra->xusb_s5p0v_reg);
1333                         goto err_put_s3p3v_reg;
1334                 } else {
1335                         err = regulator_enable(tegra->xusb_s5p0v_reg);
1336                         if (err < 0) {
1337                                 dev_err(&pdev->dev,
1338                                         "5p0v: regulator enable failed:%d\n",
1339                                         err);
1340                                 goto err_put_s3p3v_reg;
1341                         }
1342                 }
1343         }
1344
1345         tegra->xusb_s1p8v_reg =
1346                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1347         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1348                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1349                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1350                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1351                 goto err_put_s5p0v_reg;
1352         } else {
1353                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1354                 if (err < 0) {
1355                         dev_err(&pdev->dev,
1356                         "1p8v: regulator enable failed:%d\n", err);
1357                         goto err_put_s5p0v_reg;
1358                 }
1359         }
1360
1361         tegra->xusb_s1p05v_reg =
1362                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1363         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1364                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1365                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1366                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1367                 goto err_put_s1p8v_reg;
1368         } else {
1369                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1370                 if (err < 0) {
1371                         dev_err(&pdev->dev,
1372                         "1p05v: regulator enable failed:%d\n", err);
1373                         goto err_put_s1p8v_reg;
1374                 }
1375         }
1376
1377         if (tegra->bdata->uses_different_vbus_per_port) {
1378                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1379                                                 supply->s5p0v1);
1380                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1381                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1382                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1383                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1384                         goto err_put_s1p05v_reg;
1385                 } else {
1386                         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1387                                 err = regulator_enable(tegra->xusb_s5p0v1_reg);
1388                         if (err < 0) {
1389                                 dev_err(&pdev->dev,
1390                                 "5p0v1: regulator enable failed:%d\n", err);
1391                                 goto err_put_s1p05v_reg;
1392                         }
1393                 }
1394
1395                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1396                                                 supply->s5p0v2);
1397                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1398                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1399                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1400                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1401                         goto err_put_s1p5v1_reg;
1402                 } else {
1403                         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1404                                 err = regulator_enable(tegra->xusb_s5p0v2_reg);
1405                         if (err < 0) {
1406                                 dev_err(&pdev->dev,
1407                                 "5p0v2: regulator enable failed:%d\n", err);
1408                                 goto err_put_s1p5v1_reg;
1409                         }
1410                 }
1411         }
1412         return err;
1413
1414 err_put_s1p5v1_reg:
1415         if (tegra->bdata->uses_different_vbus_per_port &&
1416                 tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1417                 regulator_disable(tegra->xusb_s5p0v1_reg);
1418 err_put_s1p05v_reg:
1419         regulator_disable(tegra->xusb_s1p05v_reg);
1420 err_put_s1p8v_reg:
1421         regulator_disable(tegra->xusb_s1p8v_reg);
1422 err_put_s5p0v_reg:
1423         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) && !tegra->transceiver)
1424                 regulator_disable(tegra->xusb_s5p0v_reg);
1425 err_put_s3p3v_reg:
1426         regulator_disable(tegra->xusb_s3p3v_reg);
1427 err_null_regulator:
1428         tegra->xusb_s5p0v_reg = NULL;
1429         tegra->xusb_s5p0v1_reg = NULL;
1430         tegra->xusb_s5p0v2_reg = NULL;
1431         tegra->xusb_s1p05v_reg = NULL;
1432         tegra->xusb_s3p3v_reg = NULL;
1433         tegra->xusb_s1p8v_reg = NULL;
1434         return err;
1435 }
1436
1437 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1438 {
1439         regulator_disable(tegra->xusb_s1p05v_reg);
1440         regulator_disable(tegra->xusb_s1p8v_reg);
1441         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) && !tegra->transceiver)
1442                 regulator_disable(tegra->xusb_s5p0v_reg);
1443         regulator_disable(tegra->xusb_s3p3v_reg);
1444         if (tegra->bdata->uses_different_vbus_per_port) {
1445                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1446                         regulator_disable(tegra->xusb_s5p0v1_reg);
1447                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1448                         regulator_disable(tegra->xusb_s5p0v2_reg);
1449         }
1450
1451         tegra->xusb_s1p05v_reg = NULL;
1452         tegra->xusb_s1p8v_reg = NULL;
1453         tegra->xusb_s5p0v_reg = NULL;
1454         tegra->xusb_s5p0v1_reg = NULL;
1455         tegra->xusb_s5p0v2_reg = NULL;
1456         tegra->xusb_s3p3v_reg = NULL;
1457 }
1458
1459 /*
1460  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1461  * are under hardware control
1462  */
1463 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1464 {
1465         struct platform_device *pdev = tegra->pdev;
1466         int err = 0;
1467
1468         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1469         if (IS_ERR(tegra->plle_clk)) {
1470                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1471                 err = PTR_ERR(tegra->plle_clk);
1472                 return err;
1473         }
1474         err = clk_enable(tegra->plle_clk);
1475         if (err) {
1476                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1477                         __func__);
1478                 return err;
1479         }
1480
1481         return err;
1482 }
1483
1484 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1485 {
1486         clk_disable(tegra->plle_clk);
1487         tegra->plle_clk = NULL;
1488 }
1489
1490 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1491 {
1492         struct platform_device *pdev = tegra->pdev;
1493         int err = 0;
1494
1495         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1496         if (IS_ERR(tegra->emc_clk)) {
1497                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1498                 return PTR_ERR(tegra->emc_clk);
1499         }
1500
1501         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1502                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1503                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1504                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1505                         err = PTR_ERR(tegra->pll_re_vco_clk);
1506                         goto get_pll_re_vco_clk_failed;
1507                 }
1508         }
1509
1510         /* get the clock handle of 120MHz clock source */
1511         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1512         if (IS_ERR(tegra->pll_u_480M)) {
1513                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1514                 err = PTR_ERR(tegra->pll_u_480M);
1515                 goto get_pll_u_480M_failed;
1516         }
1517
1518         /* get the clock handle of 12MHz clock source */
1519         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1520         if (IS_ERR(tegra->clk_m)) {
1521                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1522                 err = PTR_ERR(tegra->clk_m);
1523                 goto clk_get_clk_m_failed;
1524         }
1525
1526         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1527         if (IS_ERR(tegra->ss_src_clk)) {
1528                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1529                 err = PTR_ERR(tegra->ss_src_clk);
1530                 tegra->ss_src_clk = NULL;
1531                 goto get_ss_src_clk_failed;
1532         }
1533
1534         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1535         if (IS_ERR(tegra->host_clk)) {
1536                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1537                 err = PTR_ERR(tegra->host_clk);
1538                 tegra->host_clk = NULL;
1539                 goto get_host_clk_failed;
1540         }
1541
1542         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1543         if (IS_ERR(tegra->ss_clk)) {
1544                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1545                 err = PTR_ERR(tegra->ss_clk);
1546                 tegra->ss_clk = NULL;
1547                 goto get_ss_clk_failed;
1548         }
1549
1550         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1551                 err = clk_enable(tegra->pll_re_vco_clk);
1552                 if (err) {
1553                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1554                         goto enable_pll_re_vco_clk_failed;
1555                 }
1556         }
1557         return 0;
1558
1559 enable_pll_re_vco_clk_failed:
1560         tegra->ss_clk = NULL;
1561
1562 get_ss_clk_failed:
1563         tegra->host_clk = NULL;
1564
1565 get_host_clk_failed:
1566         tegra->ss_src_clk = NULL;
1567
1568 get_ss_src_clk_failed:
1569         tegra->clk_m = NULL;
1570
1571 clk_get_clk_m_failed:
1572         tegra->pll_u_480M = NULL;
1573
1574 get_pll_u_480M_failed:
1575         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1576                 tegra->pll_re_vco_clk = NULL;
1577
1578 get_pll_re_vco_clk_failed:
1579         tegra->emc_clk = NULL;
1580
1581         return err;
1582 }
1583
1584 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1585 {
1586         clk_disable(tegra->ss_clk);
1587         clk_disable(tegra->host_clk);
1588         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1589                 clk_disable(tegra->pll_re_vco_clk);
1590         tegra->ss_clk = NULL;
1591         tegra->host_clk = NULL;
1592         tegra->ss_src_clk = NULL;
1593         tegra->clk_m = NULL;
1594         tegra->pll_u_480M = NULL;
1595         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1596                 tegra->pll_re_vco_clk = NULL;
1597 }
1598
1599 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1600         bool enable)
1601 {
1602         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1603         u32 reg;
1604
1605         /* Issue is only applicable for T114 */
1606         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1607                 return;
1608
1609         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1610                 reg = readl(tegra->padctl_base +
1611                         padregs->iophy_misc_pad_p0_ctl3_0);
1612                 if (enable) {
1613                         reg &= ~RX_IDLE_MODE;
1614                         reg |= RX_IDLE_MODE_OVRD;
1615                 } else {
1616                         reg |= RX_IDLE_MODE;
1617                         reg &= ~RX_IDLE_MODE_OVRD;
1618                 }
1619                 writel(reg, tegra->padctl_base +
1620                         padregs->iophy_misc_pad_p0_ctl3_0);
1621         }
1622
1623         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1624                 reg = readl(tegra->padctl_base +
1625                         padregs->iophy_misc_pad_p1_ctl3_0);
1626                 if (enable) {
1627                         reg &= ~RX_IDLE_MODE;
1628                         reg |= RX_IDLE_MODE_OVRD;
1629                 } else {
1630                         reg |= RX_IDLE_MODE;
1631                         reg &= ~RX_IDLE_MODE_OVRD;
1632                 }
1633                 writel(reg, tegra->padctl_base +
1634                         padregs->iophy_misc_pad_p1_ctl3_0);
1635
1636                 /* SATA lane also if USB3_SS port1 mapped to it */
1637                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1638                                 tegra->bdata->lane_owner & BIT(0)) {
1639                         reg = readl(tegra->padctl_base +
1640                                 padregs->iophy_misc_pad_s0_ctl3_0);
1641                         if (enable) {
1642                                 reg &= ~RX_IDLE_MODE;
1643                                 reg |= RX_IDLE_MODE_OVRD;
1644                         } else {
1645                                 reg |= RX_IDLE_MODE;
1646                                 reg &= ~RX_IDLE_MODE_OVRD;
1647                         }
1648                         writel(reg, tegra->padctl_base +
1649                                 padregs->iophy_misc_pad_s0_ctl3_0);
1650                 }
1651         }
1652 }
1653
1654 /* Enable ss clk, host clk, falcon clk,
1655  * fs clk, dev clk, plle and refplle
1656  */
1657
1658 static int
1659 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1660                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1661 {
1662         int ret = 0;
1663         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1664         int fw_req_rate = rate, cur_rate;
1665
1666         /* Do not handle clock change as needed for HS disconnect issue */
1667         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1668                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1669                 return ret;
1670         }
1671
1672         /* frequency request from firmware is in KHz.
1673          * Convert it to MHz
1674          */
1675
1676         /* get current rate of clock */
1677         cur_rate = clk_get_rate(clk_handle);
1678         cur_rate /= 1000;
1679
1680         if (fw_req_rate == cur_rate) {
1681                 cmd_ack = MBOX_CMD_ACK;
1682                 *sw_resp = fw_req_rate;
1683         } else {
1684
1685                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1686                         /* Change SS clock source to CLK_M at 12MHz */
1687                         clk_set_parent(clk_handle, tegra->clk_m);
1688                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1689
1690                         /* save leakage power when SS freq is being decreased */
1691                         tegra_xhci_rx_idle_mode_override(tegra, true);
1692                 } else if (clk_handle == tegra->ss_src_clk &&
1693                                 fw_req_rate == 120000) {
1694                         /* Change SS clock source to HSIC_480 at 120MHz */
1695                         clk_set_rate(clk_handle,  3000 * 1000);
1696                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1697
1698                         /* clear ovrd bits when SS freq is being increased */
1699                         tegra_xhci_rx_idle_mode_override(tegra, false);
1700                 }
1701
1702                 *sw_resp = clk_get_rate(clk_handle);
1703                 *sw_resp /= 1000;
1704
1705                 if (*sw_resp != fw_req_rate) {
1706                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1707                                 cur_rate, fw_req_rate);
1708                         cmd_ack = MBOX_CMD_NACK;
1709                 }
1710         }
1711         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1712         return ret;
1713 }
1714
1715 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1716         u8 port)
1717 {
1718         struct xhci_hcd *xhci = tegra->xhci;
1719         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1720         u32 offset;
1721         u32 reg;
1722
1723         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1724                 pr_err("%s invalid SS port number %u\n", __func__, port);
1725                 return;
1726         }
1727
1728         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1729
1730         /* if port1 is mapped to SATA lane then read from SATA register */
1731         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1732                         tegra->bdata->lane_owner & BIT(0))
1733                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1734         else
1735                 offset = MISC_PAD_CTL_6_0(port);
1736
1737         /*
1738          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1739          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1740          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1741          */
1742         reg = readl(tegra->padctl_base + offset);
1743         reg &= ~MISC_OUT_SEL(~0);
1744         reg |= MISC_OUT_SEL(0x32);
1745         writel(reg, tegra->padctl_base + offset);
1746
1747         reg = readl(tegra->padctl_base + offset);
1748         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1749
1750         reg = readl(tegra->padctl_base + offset);
1751         reg &= ~MISC_OUT_SEL(~0);
1752         reg |= MISC_OUT_SEL(0x33);
1753         writel(reg, tegra->padctl_base + offset);
1754
1755         reg = readl(tegra->padctl_base + offset);
1756         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1757
1758         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1759         reg &= ~DFE_CNTL_TAP_VAL(~0);
1760         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1761         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1762
1763         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1764         reg &= ~DFE_CNTL_AMP_VAL(~0);
1765         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1766         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1767
1768         tegra->dfe_ctx_saved[port] = true;
1769 }
1770
1771 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1772         u8 port)
1773 {
1774         struct xhci_hcd *xhci = tegra->xhci;
1775         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1776         u32 offset;
1777         u32 reg;
1778
1779         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1780                 pr_err("%s invalid SS port number %u\n", __func__, port);
1781                 return;
1782         }
1783
1784         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1785
1786         /* if port1 is mapped to SATA lane then read from SATA register */
1787         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1788                         tegra->bdata->lane_owner & BIT(0))
1789                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1790         else
1791                 offset = MISC_PAD_CTL_6_0(port);
1792
1793         /*
1794          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1795          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1796          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1797          */
1798         reg = readl(tegra->padctl_base + offset);
1799         reg &= ~MISC_OUT_SEL(~0);
1800         reg |= MISC_OUT_SEL(0xa1);
1801         writel(reg, tegra->padctl_base + offset);
1802
1803         reg = readl(tegra->padctl_base + offset);
1804         reg &= ~MISC_OUT_SEL(~0);
1805         reg |= MISC_OUT_SEL(0x21);
1806         writel(reg, tegra->padctl_base + offset);
1807
1808         reg = readl(tegra->padctl_base + offset);
1809         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1810
1811         reg = readl(tegra->padctl_base + offset);
1812         reg &= ~MISC_OUT_SEL(~0);
1813         reg |= MISC_OUT_SEL(0x48);
1814         writel(reg, tegra->padctl_base + offset);
1815
1816         reg = readl(tegra->padctl_base + offset);
1817         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1818
1819         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1820         reg &= ~RX_EQ_Z_VAL(~0);
1821         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1822         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1823
1824         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1825         reg &= ~RX_EQ_G_VAL(~0);
1826         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1827         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1828
1829         tegra->ctle_ctx_saved[port] = true;
1830 }
1831
1832 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1833         u8 port)
1834 {
1835         struct xhci_hcd *xhci = tegra->xhci;
1836         u32 reg;
1837
1838         /* don't restore if not saved */
1839         if (tegra->dfe_ctx_saved[port] == false)
1840                 return;
1841
1842         xhci_info(xhci, "restoring dfe context of port %d\n", port);
1843
1844         /* restore dfe_cntl for the port */
1845         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1846         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
1847                         DFE_CNTL_TAP_VAL(~0));
1848         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
1849                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1850         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1851 }
1852
1853 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
1854         u8 port)
1855 {
1856         struct xhci_hcd *xhci = tegra->xhci;
1857         u32 reg;
1858
1859         /* don't restore if not saved */
1860         if (tegra->ctle_ctx_saved[port] == false)
1861                 return;
1862
1863         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
1864
1865         /* restore ctle for the port */
1866         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1867         reg &= ~(RX_EQ_Z_VAL(~0) |
1868                         RX_EQ_G_VAL(~0));
1869         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
1870                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
1871         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1872 }
1873
1874 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1875         u8 port)
1876 {
1877         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1878         u32 reg;
1879
1880         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1881         reg &= ~USB2_ULPI_PAD;
1882         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1883         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1884
1885         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1886         reg &= ~USB2_ULPI_PORT_CAP;
1887         reg |= (tegra->bdata->ulpicap << 24);
1888         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1889         /* FIXME: Program below when more details available
1890          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1891          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1892          */
1893 }
1894
1895 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1896         u8 port)
1897 {
1898         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1899         u32 reg;
1900         u32 ctl0_offset, ctl1_offset;
1901
1902         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1903         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1904         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1905         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1906
1907         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1908         reg &= ~USB2_PORT_CAP_MASK(port);
1909         reg |= USB2_PORT_CAP_HOST(port);
1910         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1911
1912         /*
1913          * Modify only the bits which belongs to the port
1914          * and enable respective VBUS_PAD for the port
1915          */
1916         if (tegra->bdata->uses_external_pmic == false) {
1917                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1918                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1919                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1920                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1921
1922                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1923                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1924                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1925                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1926         }
1927         /*
1928          * enable respective VBUS_PAD if port is mapped to any SS port
1929          */
1930         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1931         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1932                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1933         reg |= (0x4 | port) << (port * 3);
1934         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1935
1936         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1937                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1938                                 padregs->usb2_otg_pad0_ctl0_0;
1939         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1940                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1941                                 padregs->usb2_otg_pad0_ctl1_0;
1942
1943         reg = readl(tegra->padctl_base + ctl0_offset);
1944         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1945                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1946                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1947
1948         reg |= tegra->pdata->hs_slew;
1949         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1950                         port ? tegra->pdata->ls_rslew_pad1 :
1951                         tegra->pdata->ls_rslew_pad0;
1952         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1953                         port ? tegra->pdata->hs_curr_level_pad1 :
1954                         tegra->pdata->hs_curr_level_pad0;
1955         writel(reg, tegra->padctl_base + ctl0_offset);
1956
1957         reg = readl(tegra->padctl_base + ctl1_offset);
1958         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1959                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1960                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1961                 | USB2_OTG_PD_DR);
1962         reg |= (tegra->pdata->hs_iref_cap << 9) |
1963                 (tegra->pdata->hs_term_range_adj << 3);
1964         writel(reg, tegra->padctl_base + ctl1_offset);
1965
1966         /*Release OTG port if not in host mode*/
1967
1968         if ((port == 0) && !is_otg_host(tegra))
1969                 tegra_xhci_release_otg_port(true);
1970 }
1971
1972 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1973         u8 port)
1974 {
1975         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1976         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1977         u32 reg;
1978
1979         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1980                         padregs->iophy_usb3_pad0_ctl2_0;
1981         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1982                         padregs->iophy_usb3_pad0_ctl4_0;
1983         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1984                         padregs->iophy_misc_pad_p0_ctl5_0;
1985
1986         reg = readl(tegra->padctl_base + ctl2_offset);
1987         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1988                 IOPHY_USB3_CDRCNTL);
1989         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1990                 tegra->pdata->cdr_cntl;
1991         writel(reg, tegra->padctl_base + ctl2_offset);
1992
1993         reg = readl(tegra->padctl_base + ctl4_offset);
1994         reg = tegra->pdata->dfe_cntl;
1995         writel(reg, tegra->padctl_base + ctl4_offset);
1996
1997         reg = readl(tegra->padctl_base + ctl5_offset);
1998         reg |= RX_QEYE_EN;
1999         writel(reg, tegra->padctl_base + ctl5_offset);
2000
2001         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2002         reg &= ~SPARE_IN(~0);
2003         reg |= SPARE_IN(tegra->pdata->spare_in);
2004         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2005
2006         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2007         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2008         reg |= (tegra->bdata->ss_portmap &
2009                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2010         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2011
2012         tegra_xhci_restore_dfe_context(tegra, port);
2013         tegra_xhci_restore_ctle_context(tegra, port);
2014 }
2015
2016 /* This function assigns the USB ports to the controllers,
2017  * then programs the port capabilities and pad parameters
2018  * of ports assigned to XUSB after booted to OS.
2019  */
2020 void
2021 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2022 {
2023         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2024         u32 reg, oc_bits = 0;
2025         unsigned pad;
2026
2027         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2028         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2029         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
2030         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2031
2032         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2033         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2034         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2035         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2036
2037         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2038         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2039         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2040                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2041         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2042
2043         /* check if over current seen. Clear if present */
2044         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2045                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2046         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2047                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2048         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2049                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2050
2051         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2052         if (reg & oc_bits) {
2053                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2054                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2055
2056                 usleep_range(100, 200);
2057
2058                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2059                 if (reg & oc_bits)
2060                         xhci_info(tegra->xhci, "Over current still present\n");
2061         }
2062
2063         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2064         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2065         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2066                 reg |= USB2_OC_MAP_PORT2;
2067         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2068
2069         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2070                 tegra_xhci_program_utmip_pad(tegra, 0);
2071         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2072                 tegra_xhci_program_utmip_pad(tegra, 1);
2073         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2074                 tegra_xhci_program_utmip_pad(tegra, 2);
2075
2076         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
2077                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
2078                         hsic_pad_enable(tegra, pad);
2079         }
2080
2081         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2082                 tegra_xhci_program_ulpi_pad(tegra, 0);
2083
2084         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2085                 tegra_xhci_program_ss_pad(tegra, 0);
2086         } else {
2087                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2088                 reg = readl(tegra->padctl_base +
2089                         padregs->iophy_misc_pad_p0_ctl3_0);
2090                 reg &= ~RX_IDLE_MODE;
2091                 reg |= RX_IDLE_MODE_OVRD;
2092                 writel(reg, tegra->padctl_base +
2093                         padregs->iophy_misc_pad_p0_ctl3_0);
2094         }
2095
2096         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2097                 tegra_xhci_program_ss_pad(tegra, 1);
2098         } else {
2099                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2100                 reg = readl(tegra->padctl_base +
2101                         padregs->iophy_misc_pad_p1_ctl3_0);
2102                 reg &= ~RX_IDLE_MODE;
2103                 reg |= RX_IDLE_MODE_OVRD;
2104                 writel(reg, tegra->padctl_base +
2105                         padregs->iophy_misc_pad_p1_ctl3_0);
2106
2107                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2108                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2109                                 tegra->bdata->lane_owner & BIT(0)) {
2110                         reg = readl(tegra->padctl_base +
2111                                 padregs->iophy_misc_pad_s0_ctl3_0);
2112                         reg &= ~RX_IDLE_MODE;
2113                         reg |= RX_IDLE_MODE_OVRD;
2114                         writel(reg, tegra->padctl_base +
2115                                 padregs->iophy_misc_pad_s0_ctl3_0);
2116                 }
2117         }
2118         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2119                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2120                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2121         }
2122 }
2123
2124 /* This function read XUSB registers and stores in device context */
2125 static void
2126 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2127 {
2128
2129         /* a. Save the IPFS registers */
2130         tegra->sregs.msi_bar_sz =
2131                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2132
2133         tegra->sregs.msi_axi_barst =
2134                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2135
2136         tegra->sregs.msi_fpci_barst =
2137                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2138
2139         tegra->sregs.msi_vec0 =
2140                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2141
2142         tegra->sregs.msi_en_vec0 =
2143                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2144
2145         tegra->sregs.fpci_error_masks =
2146                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2147
2148         tegra->sregs.intr_mask =
2149                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2150
2151         tegra->sregs.ipfs_intr_enable =
2152                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2153
2154         tegra->sregs.ufpci_config =
2155                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2156
2157         tegra->sregs.clkgate_hysteresis =
2158                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2159
2160         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2161                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2162
2163         /* b. Save the CFG registers */
2164
2165         tegra->sregs.hs_pls =
2166                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2167
2168         tegra->sregs.fs_pls =
2169                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2170
2171         tegra->sregs.hs_fs_speed =
2172                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2173
2174         tegra->sregs.hs_fs_pp =
2175                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2176
2177         tegra->sregs.cfg_aru =
2178                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2179
2180         tegra->sregs.cfg_order =
2181                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2182
2183         tegra->sregs.cfg_fladj =
2184                 readl(tegra->fpci_base + XUSB_CFG_24);
2185
2186         tegra->sregs.cfg_sid =
2187                 readl(tegra->fpci_base + XUSB_CFG_16);
2188 }
2189
2190 /* This function restores XUSB registers from device context */
2191 static void
2192 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2193 {
2194         /* Restore Cfg registers */
2195         writel(tegra->sregs.hs_pls,
2196                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2197
2198         writel(tegra->sregs.fs_pls,
2199                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2200
2201         writel(tegra->sregs.hs_fs_speed,
2202                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2203
2204         writel(tegra->sregs.hs_fs_pp,
2205                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2206
2207         writel(tegra->sregs.cfg_aru,
2208                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2209
2210         writel(tegra->sregs.cfg_order,
2211                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2212
2213         writel(tegra->sregs.cfg_fladj,
2214                 tegra->fpci_base + XUSB_CFG_24);
2215
2216         writel(tegra->sregs.cfg_sid,
2217                 tegra->fpci_base + XUSB_CFG_16);
2218
2219         /* Restore IPFS registers */
2220
2221         writel(tegra->sregs.msi_bar_sz,
2222                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2223
2224         writel(tegra->sregs.msi_axi_barst,
2225                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2226
2227         writel(tegra->sregs.msi_fpci_barst,
2228                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2229
2230         writel(tegra->sregs.msi_vec0,
2231                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2232
2233         writel(tegra->sregs.msi_en_vec0,
2234                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2235
2236         writel(tegra->sregs.fpci_error_masks,
2237                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2238
2239         writel(tegra->sregs.intr_mask,
2240                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2241
2242         writel(tegra->sregs.ipfs_intr_enable,
2243                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2244
2245         writel(tegra->sregs.ufpci_config,
2246                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2247
2248         writel(tegra->sregs.clkgate_hysteresis,
2249                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2250
2251         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2252                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2253 }
2254
2255 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2256 {
2257         struct platform_device *pdev = tegra->pdev;
2258         u32 reg, timeout = 0xff, cmd;
2259
2260         mutex_lock(&tegra->mbox_lock);
2261
2262         do {
2263                 writel(MBOX_OWNER_SW,
2264                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2265                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2266                 usleep_range(10, 20);
2267         } while (reg != MBOX_OWNER_SW && timeout--);
2268
2269         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
2270                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
2271                 mutex_unlock(&tegra->mbox_lock);
2272                 return;
2273         }
2274
2275         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
2276                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2277
2278         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2279         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2280         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2281
2282         mutex_unlock(&tegra->mbox_lock);
2283 }
2284
2285 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2286 {
2287         struct platform_device *pdev = tegra->pdev;
2288         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2289         u32 phys_addr_lo;
2290         u32 HwReg;
2291         u16 nblocks;
2292         time_t fw_time;
2293         struct tm fw_tm;
2294         u8 hc_caplength;
2295         u32 usbsts, count = 0xff;
2296         struct xhci_cap_regs __iomem *cap_regs;
2297         struct xhci_op_regs __iomem *op_regs;
2298
2299         /* enable mbox interrupt */
2300         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2301                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2302
2303         /* First thing, reset the ARU. By the time we get to
2304          * loading boot code below, reset would be complete.
2305          * alternatively we can busy wait on rst pending bit.
2306          */
2307         /* Don't reset during ELPG/LP0 exit path */
2308         if (resetARU) {
2309                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2310                 usleep_range(1000, 2000);
2311         }
2312
2313         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2314                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2315                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2316                 return 0;
2317         }
2318
2319         /* update the phys_log_buffer and total_entries here */
2320         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2321         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2322
2323         phys_addr_lo = tegra->firmware.dma;
2324         phys_addr_lo += sizeof(struct cfgtbl);
2325
2326         /* Program the size of DFI into ILOAD_ATTR */
2327         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2328
2329         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2330          * to get to the start of the dfi in system memory.
2331          */
2332         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2333
2334         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2335         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2336
2337         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2338         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2339
2340         /* Invalidate L2IMEM. */
2341         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2342
2343         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2344          * Program BootCode location and size in system memory.
2345          */
2346         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2347                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2348                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2349         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2350                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2351                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2352         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2353
2354         /* Trigger L2IMEM Load operation. */
2355         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2356
2357         /* Setup Falcon Auto-fill */
2358         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2359         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2360                 nblocks += 1;
2361         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2362
2363         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2364         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2365                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2366         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2367
2368         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2369         msleep(50);
2370
2371         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2372
2373         /* Start Falcon CPU */
2374         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2375         usleep_range(1000, 2000);
2376
2377         fw_time = cfg_tbl->fwimg_created_time;
2378         time_to_tm(fw_time, 0, &fw_tm);
2379         dev_info(&pdev->dev,
2380                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2381                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2382                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2383                 fw_tm.tm_min, fw_tm.tm_sec,
2384                 csb_read(tegra, XUSB_FALC_CPUCTL));
2385
2386         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2387
2388         /* return fail if firmware status is not good */
2389         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2390                 return -EFAULT;
2391
2392         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2393         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2394         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2395
2396         /* wait for USBSTS_CNR to get set */
2397         do {
2398                 usbsts = ioread32(&op_regs->status);
2399         } while ((usbsts & STS_CNR) && count--);
2400
2401         if (!count && (usbsts & STS_CNR)) {
2402                 dev_err(&pdev->dev, "Controller not ready\n");
2403                 return -EFAULT;
2404         }
2405
2406         /* TODO move this into firmware to avoid race */
2407         writel(0x0, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL0);
2408         writel(0x1000, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL1);
2409         writel(0x10, tegra->fpci_base + XUSB_CFG_HSPX_CORE_HSICWRAP);
2410         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL0);
2411         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL1);
2412         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_HSPX_CORE_HSICWRAP);
2413
2414         return 0;
2415 }
2416
2417 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2418         bool release)
2419 {
2420         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2421         u32 reg;
2422
2423         /* Issue is only applicable for T114 */
2424         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2425                 return;
2426
2427         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2428         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2429                         USB2_OTG_PAD_PORT_MASK(2));
2430
2431         if (!release) {
2432                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2433                         if (is_otg_host(tegra))
2434                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2435                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2436                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2437                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2438                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2439         }
2440
2441         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2442 }
2443 /* SS ELPG Entry initiated by fw */
2444 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2445 {
2446         struct xhci_hcd *xhci = tegra->xhci;
2447         u32 ret = 0;
2448
2449         must_have_sync_lock(tegra);
2450
2451         /* This is SS partition ELPG entry
2452          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2453          */
2454
2455         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2456          * only if it is sw initiated one
2457          */
2458
2459         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2460          * SuperSpeed partition ELPG entry via mailbox protocol
2461          */
2462
2463         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2464          * enable the XUSB wakeup interrupts for the SuperSpeed
2465          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2466          */
2467         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2468
2469         /* STEP 3: xHCI PEP driver initiates the signal sequence
2470          * to enable the XUSB SSwake detection logic for the
2471          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2472          */
2473         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2474
2475         /* STEP 4: System Power Management driver asserts reset
2476          * to XUSB SuperSpeed partition then disables its clocks
2477          */
2478         tegra_periph_reset_assert(tegra->ss_clk);
2479         clk_disable(tegra->ss_clk);
2480
2481         usleep_range(100, 200);
2482
2483         /* STEP 5: System Power Management driver disables the
2484          * XUSB SuperSpeed partition power rails.
2485          */
2486         debug_print_portsc(xhci);
2487
2488         /* tegra_powergate_partition also does partition reset assert */
2489         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2490         if (ret) {
2491                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2492                                 __func__);
2493                 /* TODO: error recovery? */
2494         }
2495         tegra->ss_pwr_gated = true;
2496
2497         /* STEP 6: xHCI PEP driver initiates the signal sequence
2498          * to enable the XUSB SSwake detection logic for the
2499          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2500          */
2501         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2502
2503         return ret;
2504 }
2505
2506 /* Host ELPG Entry */
2507 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2508 {
2509         struct xhci_hcd *xhci = tegra->xhci;
2510         u32 ret;
2511
2512         must_have_sync_lock(tegra);
2513
2514         /* If ss is already powergated skip ss ctx save stuff */
2515         if (tegra->ss_pwr_gated) {
2516                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2517                         __func__);
2518         } else {
2519                 ret = tegra_xhci_ss_elpg_entry(tegra);
2520                 if (ret) {
2521                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2522                                 __func__, ret);
2523                         return ret;
2524                 }
2525         }
2526
2527         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2528
2529         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2530         tegra_xhci_save_xusb_ctx(tegra);
2531
2532         /* calculate rctrl_val and tctrl_val */
2533         tegra_xhci_war_for_tctrl_rctrl(tegra);
2534
2535         pmc_setup_wake_detect(tegra);
2536
2537         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2538         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2539                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2540
2541         /* STEP 4: Assert reset to host clk and disable host clk */
2542         tegra_periph_reset_assert(tegra->host_clk);
2543
2544         clk_disable(tegra->host_clk);
2545
2546         /* wait 150us */
2547         usleep_range(150, 200);
2548
2549         /* flush MC client of XUSB_HOST */
2550         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2551
2552         /* STEP 4: Powergate host partition */
2553         /* tegra_powergate_partition also does partition reset assert */
2554         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2555         if (ret) {
2556                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2557                         __func__, ret);
2558                 /* TODO: error handling? */
2559                 return ret;
2560         }
2561         tegra->host_pwr_gated = true;
2562
2563         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2564                 clk_disable(tegra->pll_re_vco_clk);
2565         clk_disable(tegra->emc_clk);
2566         /* set port ownership to SNPS */
2567         tegra_xhci_release_port_ownership(tegra, true);
2568
2569         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2570                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2571
2572         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2573         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2574                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2575         return ret;
2576 }
2577
2578 /* SS ELPG Exit triggered by PADCTL irq */
2579 /**
2580  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2581  *
2582  * This function must be called with tegra->sync_lock acquired.
2583  *
2584  * @tegra: xhci controller context
2585  * @return 0 for success, or error numbers
2586  */
2587 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2588 {
2589         struct xhci_hcd *xhci = tegra->xhci;
2590         int ret = 0;
2591
2592         must_have_sync_lock(tegra);
2593
2594         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2595                         tegra->hs_wake_event || tegra->host_resume_req)) {
2596
2597                 /*
2598                  * PWR_UNGATE SS partition. XUSBA
2599                  * tegra_unpowergate_partition also does partition reset
2600                  * deassert
2601                  */
2602                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2603                 if (ret) {
2604                         xhci_err(xhci,
2605                         "%s: could not unpowergate xusba partition %d\n",
2606                         __func__, ret);
2607                         goto out;
2608                 }
2609                 if (tegra->ss_wake_event)
2610                         tegra->ss_wake_event = false;
2611
2612         } else {
2613                 xhci_info(xhci, "%s: ss already power gated\n",
2614                         __func__);
2615                 return ret;
2616         }
2617
2618         /* Step 3: Enable clock to ss partition */
2619         clk_enable(tegra->ss_clk);
2620
2621         /* Step 4: Disable ss wake detection logic */
2622         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2623
2624         /* Step 4.1: Disable ss wake detection logic */
2625         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2626
2627         /* wait 150us */
2628         usleep_range(150, 200);
2629
2630         /* Step 4.2: Disable ss wake detection logic */
2631         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2632
2633         /* Step 6 Deassert reset for ss clks */
2634         tegra_periph_reset_deassert(tegra->ss_clk);
2635
2636         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2637         tegra->ss_pwr_gated = false;
2638 out:
2639         return ret;
2640 }
2641
2642 static void ss_partition_elpg_exit_work(struct work_struct *work)
2643 {
2644         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2645                 ss_elpg_exit_work);
2646
2647         mutex_lock(&tegra->sync_lock);
2648         tegra_xhci_ss_partition_elpg_exit(tegra);
2649         mutex_unlock(&tegra->sync_lock);
2650 }
2651
2652 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2653 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2654 {
2655         struct xhci_hcd *xhci = tegra->xhci;
2656         u32 wake2_status;
2657         int port;
2658
2659 #define PMC_WAKE2_STATUS        0x168
2660 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2661
2662         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2663
2664         if (wake2_status & PADCTL_WAKE) {
2665                 /* FIXME: This is customized for Dalmore, find a generic way */
2666                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2667                 /* clear wake status */
2668                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2669         }
2670
2671         /* set all usb2 ports with RESUME link state as wakup ports  */
2672         for (port = 0; port < xhci->num_usb2_ports; port++) {
2673                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2674                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2675                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2676         }
2677
2678         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2679                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2680         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2681                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2682 }
2683
2684 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2685 {
2686         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2687         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2688         int port, num_ports;
2689         unsigned long *remote_wakeup_ports;
2690         u32 portsc;
2691         __le32 __iomem  **port_array;
2692         unsigned char *rh;
2693         unsigned int retry = 64;
2694         struct xhci_bus_state *bus_state;
2695
2696         bus_state = &xhci->bus_state[hcd_index(hcd)];
2697
2698         if (hcd == xhci->shared_hcd) {
2699                 port_array = xhci->usb3_ports;
2700                 num_ports = xhci->num_usb3_ports;
2701                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2702                 rh = "usb3 roothub";
2703         } else {
2704                 port_array = xhci->usb2_ports;
2705                 num_ports = xhci->num_usb2_ports;
2706                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2707                 rh = "usb2 roothub";
2708         }
2709
2710         while (*remote_wakeup_ports && retry--) {
2711                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2712                         bool can_continue;
2713
2714                         portsc = xhci_readl(xhci, port_array[port]);
2715
2716                         if (!(portsc & PORT_CONNECT)) {
2717                                 /* nothing to do if already disconnected */
2718                                 clear_bit(port, remote_wakeup_ports);
2719                                 continue;
2720                         }
2721
2722                         if (hcd == xhci->shared_hcd) {
2723                                 can_continue =
2724                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2725                         } else {
2726                                 unsigned long flags;
2727
2728                                 spin_lock_irqsave(&xhci->lock, flags);
2729                                 can_continue =
2730                                 test_bit(port, &bus_state->resuming_ports);
2731                                 spin_unlock_irqrestore(&xhci->lock, flags);
2732                         }
2733
2734                         if (can_continue)
2735                                 clear_bit(port, remote_wakeup_ports);
2736                         else
2737                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2738                                         __func__, rh, port, portsc);
2739                 }
2740
2741                 if (*remote_wakeup_ports)
2742                         msleep(20); /* give some time, irq will direct U0 */
2743         }
2744
2745         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2746                         *remote_wakeup_ports);
2747 }
2748
2749 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2750 {
2751         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2752         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2753         int port;
2754
2755         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2756         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2757                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2758
2759         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2760                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2761                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2762         }
2763
2764         /* Use xusb padctl space only when xusb owns all UTMIP port */
2765         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2766         if ((pad_mux & portmux) == portowner) {
2767                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2768                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2769                  */
2770                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2771                 reg &= ~((1 << 12) | (1 << 13));
2772                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2773
2774                 /* wait 20us */
2775                 usleep_range(20, 30);
2776
2777                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2778                  * :: TCTRL and RCTRL
2779                  */
2780                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2781                 utmip_rctrl_val = RCTRL(reg);
2782                 utmip_tctrl_val = TCTRL(reg);
2783
2784                 /*
2785                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2786                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2787                  */
2788                 for (port = 0; port < XUSB_UTMI_COUNT; port++) {
2789                         pmc_data[port].utmip_rctrl_val =
2790                                 0xf + ffz(utmip_rctrl_val);
2791                         pmc_data[port].utmip_tctrl_val =
2792                                 0xf + ffz(utmip_tctrl_val);
2793                         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2794                                         pmc_data[port].utmip_rctrl_val,
2795                                         pmc_data[port].utmip_tctrl_val);
2796                 }
2797
2798                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2799                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2800                  */
2801                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2802                 reg |= (1 << 13);
2803                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2804
2805                 /* Program these values into PMC regiseter and program the
2806                  * PMC override. This will be done as part of pmc setup
2807                  */
2808         } else {
2809                 /* TODO use common PMC API to use SNPS register space */
2810         }
2811 }
2812
2813 /* Host ELPG Exit triggered by PADCTL irq */
2814 /**
2815  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2816  *
2817  * This function must be called with tegra->sync_lock acquired.
2818  *
2819  * @tegra: xhci controller context
2820  * @return 0 for success, or error numbers
2821  */
2822 static int
2823 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2824 {
2825         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2826         struct xhci_hcd *xhci = tegra->xhci;
2827         int ret = 0;
2828
2829         must_have_sync_lock(tegra);
2830
2831         if (!tegra->hc_in_elpg)
2832                 return 0;
2833
2834         clk_enable(tegra->emc_clk);
2835         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2836                 clk_enable(tegra->pll_re_vco_clk);
2837
2838         if (tegra->lp0_exit) {
2839                 u32 reg, oc_bits = 0;
2840
2841                 /* Issue is only applicable for T114 */
2842                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2843                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2844                 /* check if over current seen. Clear if present */
2845                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2846                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2847                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2848                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2849                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2850                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2851
2852                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2853                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2854                 if (reg & oc_bits) {
2855                         xhci_info(xhci, "Over current detected. Clearing...\n");
2856                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2857
2858                         usleep_range(100, 200);
2859
2860                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2861                         if (reg & oc_bits)
2862                                 xhci_info(xhci, "Over current still present\n");
2863                 }
2864                 tegra_xhci_padctl_portmap_and_caps(tegra);
2865                 /* release clamps post deassert */
2866                 tegra->lp0_exit = false;
2867         }
2868
2869         /* Clear FLUSH_ENABLE of MC client */
2870         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2871
2872         /* set port ownership back to xusb */
2873         tegra_xhci_release_port_ownership(tegra, false);
2874
2875         /*
2876          * PWR_UNGATE Host partition. XUSBC
2877          * tegra_unpowergate_partition also does partition reset deassert
2878          */
2879         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2880         if (ret) {
2881                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2882                         __func__, ret);
2883                 goto out;
2884         }
2885         clk_enable(tegra->host_clk);
2886
2887         /* Step 4: Deassert reset to host partition clk */
2888         tegra_periph_reset_deassert(tegra->host_clk);
2889
2890         /* Step 6.1: IPFS and XUSB BAR initialization */
2891         tegra_xhci_cfg(tegra);
2892
2893         /* Step 6.2: IPFS and XUSB related restore */
2894         tegra_xhci_restore_ctx(tegra);
2895
2896         /* Step 8: xhci spec related ctx restore
2897          * will be done in xhci_resume().Do it here.
2898          */
2899
2900         tegra_xhci_ss_partition_elpg_exit(tegra);
2901
2902         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2903         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2904                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2905                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2906         }
2907
2908         /* clear ovrd bits */
2909         tegra_xhci_rx_idle_mode_override(tegra, false);
2910
2911         /* Load firmware */
2912         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2913                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2914                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2915                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2916                         __func__,
2917                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2918                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2919                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2920                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2921                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2922                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2923                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2924                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2925                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2926         debug_print_portsc(xhci);
2927
2928         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2929         if (ret < 0) {
2930                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2931                         __func__, ret);
2932                 goto out;
2933         }
2934
2935         pmc_disable_bus_ctrl(tegra);
2936
2937         tegra->hc_in_elpg = false;
2938         ret = xhci_resume(tegra->xhci, 0);
2939         if (ret) {
2940                 xhci_err(xhci, "%s: could not resume right %d\n",
2941                                 __func__, ret);
2942                 goto out;
2943         }
2944
2945         update_remote_wakeup_ports(tegra);
2946
2947         if (tegra->hs_wake_event)
2948                 tegra->hs_wake_event = false;
2949
2950         if (tegra->host_resume_req)
2951                 tegra->host_resume_req = false;
2952
2953         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2954                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2955
2956         tegra->host_pwr_gated = false;
2957 out:
2958         return ret;
2959 }
2960
2961 static void host_partition_elpg_exit_work(struct work_struct *work)
2962 {
2963         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2964                 host_elpg_exit_work);
2965
2966         mutex_lock(&tegra->sync_lock);
2967         tegra_xhci_host_partition_elpg_exit(tegra);
2968         mutex_unlock(&tegra->sync_lock);
2969 }
2970
2971 /* Mailbox handling function. This function handles requests
2972  * from firmware and communicates with clock and powergating
2973  * module to alter clock rates and to power gate/ungate xusb
2974  * partitions.
2975  *
2976  * Following is the structure of mailbox messages.
2977  * bit 31:28 - msg type
2978  * bits 27:0 - mbox data
2979  * FIXME:  Check if we can just call clock functions like below
2980  * or should we schedule it for calling later ?
2981  */
2982
2983 static void
2984 tegra_xhci_process_mbox_message(struct work_struct *work)
2985 {
2986         u32 sw_resp = 0, cmd, data_in, fw_msg;
2987         int ret = 0;
2988         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2989                                         mbox_work);
2990         struct xhci_hcd *xhci = tegra->xhci;
2991         unsigned int freq_khz;
2992         int pad, port;
2993         unsigned long ports;
2994
2995         mutex_lock(&tegra->mbox_lock);
2996
2997         /* get the owner id */
2998         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2999         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
3000
3001         /* get the mbox message from firmware */
3002         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3003
3004         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3005         if (data_in) {
3006                 mutex_unlock(&tegra->mbox_lock);
3007                 return;
3008         }
3009
3010         /* get cmd type and cmd data */
3011         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
3012         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
3013
3014         /* decode the message and make appropriate requests to
3015          * clock or powergating module.
3016          */
3017
3018         switch (tegra->cmd_type) {
3019         case MBOX_CMD_INC_FALC_CLOCK:
3020         case MBOX_CMD_DEC_FALC_CLOCK:
3021                 ret = tegra_xusb_request_clk_rate(
3022                                 tegra,
3023                                 tegra->falc_clk,
3024                                 tegra->cmd_data,
3025                                 &sw_resp);
3026                 if (ret)
3027                         xhci_err(xhci, "%s: could not set required falc rate\n",
3028                                 __func__);
3029                 goto send_sw_response;
3030         case MBOX_CMD_INC_SSPI_CLOCK:
3031         case MBOX_CMD_DEC_SSPI_CLOCK:
3032                 ret = tegra_xusb_request_clk_rate(
3033                                 tegra,
3034                                 tegra->ss_src_clk,
3035                                 tegra->cmd_data,
3036                                 &sw_resp);
3037                 if (ret)
3038                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3039                                 __func__);
3040                 goto send_sw_response;
3041         case MBOX_CMD_SET_BW:
3042                 /* fw sends BW request in MByte/sec */
3043                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
3044                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
3045
3046                 /* clear MBOX_SMI_INT_EN bit */
3047                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3048                 cmd &= ~MBOX_SMI_INT_EN;
3049                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3050
3051                 /* clear mbox owner as ACK will not be sent for this request */
3052                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3053                 break;
3054         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3055                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3056                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3057                 sw_resp |= tegra->cmd_data | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
3058                 goto send_sw_response;
3059
3060         case MBOX_CMD_STAR_HSIC_IDLE:
3061                 ports = sw_resp = tegra->cmd_data;
3062                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
3063                         pad = port_to_hsic_pad(port - 1);
3064                         mutex_lock(&tegra->sync_lock);
3065                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3066                         mutex_unlock(&tegra->sync_lock);
3067                         if (ret)
3068                                 break;
3069                 }
3070
3071                 if (!ret)
3072                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
3073                 else
3074                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
3075
3076                 goto send_sw_response;
3077
3078         case MBOX_CMD_STOP_HSIC_IDLE:
3079                 ports = sw_resp = tegra->cmd_data;
3080                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
3081                         pad = port_to_hsic_pad(port - 1);
3082                         mutex_lock(&tegra->sync_lock);
3083                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3084                         mutex_unlock(&tegra->sync_lock);
3085                         if (ret)
3086                                 break;
3087                 }
3088
3089                 if (!ret)
3090                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
3091                 else
3092                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
3093
3094                 goto send_sw_response;
3095
3096         case MBOX_CMD_ACK:
3097                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3098                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3099                 break;
3100         case MBOX_CMD_NACK:
3101                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3102                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3103                 break;
3104         default:
3105                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3106                                 __func__, tegra->cmd_type);
3107         }
3108         mutex_unlock(&tegra->mbox_lock);
3109         return;
3110
3111 send_sw_response:
3112         if (((sw_resp & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT) == MBOX_CMD_NACK)
3113                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3114                                 __func__, fw_msg);
3115
3116         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3117         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3118         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3119         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3120
3121         mutex_unlock(&tegra->mbox_lock);
3122 }
3123
3124 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3125 {
3126         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3127         struct xhci_hcd *xhci = tegra->xhci;
3128
3129         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3130         return IRQ_HANDLED;
3131 }
3132
3133 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3134 {
3135         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3136         struct xhci_hcd *xhci = tegra->xhci;
3137         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3138         u32 elpg_program0 = 0;
3139
3140         spin_lock(&tegra->lock);
3141
3142         tegra->last_jiffies = jiffies;
3143
3144         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3145         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3146
3147         /* Clear the interrupt cause. We already read the intr status. */
3148         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3149         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3150
3151         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3152         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3153                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3154         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3155                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3156         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3157                 __func__,
3158                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3159         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3160                 __func__,
3161                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3162         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3163                 __func__,
3164                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3165
3166         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3167                 tegra->ss_wake_event = true;
3168         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3169                         USB2_PORT1_WAKEUP_EVENT |
3170                         USB2_PORT2_WAKEUP_EVENT |
3171                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3172                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3173                 tegra->hs_wake_event = true;
3174
3175         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3176                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3177                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3178                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3179                 } else if (tegra->ss_pwr_gated
3180                                 && tegra->host_pwr_gated) {
3181                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3182                                 __func__);
3183                         schedule_work(&tegra->host_elpg_exit_work);
3184                 }
3185         } else {
3186                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3187                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3188         }
3189         spin_unlock(&tegra->lock);
3190         return IRQ_HANDLED;
3191 }
3192
3193 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3194 {
3195         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3196         u32 temp;
3197
3198         spin_lock(&tegra->lock);
3199
3200         /* clear the mbox intr status 1st thing. Other
3201          * bits are W1C bits, so just write to SMI bit.
3202          */
3203
3204         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3205
3206         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3207         temp = MBOX_SMI_INTR_EN;
3208         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3209
3210         schedule_work(&tegra->mbox_work);
3211
3212         spin_unlock(&tegra->lock);
3213         return IRQ_HANDLED;
3214 }
3215
3216 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3217 {
3218         /*
3219          * As of now platform drivers don't provide MSI support so we ensure
3220          * here that the generic code does not try to make a pci_dev from our
3221          * dev struct in order to setup MSI
3222          */
3223         xhci->quirks |= XHCI_BROKEN_MSI;
3224         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3225 }
3226
3227 /* called during probe() after chip reset completes */
3228 static int xhci_plat_setup(struct usb_hcd *hcd)
3229 {
3230         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3231 }
3232
3233 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3234         const char *name, void __iomem **region)
3235 {
3236         struct resource *res;
3237         void __iomem *mem;
3238
3239         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3240         if (!res) {
3241                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3242                 return -ENODEV;
3243         }
3244
3245         mem = devm_request_and_ioremap(&pdev->dev, res);
3246         if (!mem) {
3247                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3248                 return -EFAULT;
3249         }
3250         *region = mem;
3251
3252         return 0;
3253 }
3254
3255 static int tegra_xhci_request_irq(struct platform_device *pdev,
3256         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3257         const char *devname, int *irq_no)
3258 {
3259         int ret;
3260         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3261         struct resource *res;
3262
3263         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3264         if (!res) {
3265                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3266                 return -ENODEV;
3267         }
3268
3269         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3270                         devname, tegra);
3271         if (ret != 0) {
3272                 dev_err(&pdev->dev,
3273                         "failed to request_irq for %s (irq %d), error = %d\n",
3274                         devname, res->start, ret);
3275                 return ret;
3276         }
3277         *irq_no = res->start;
3278
3279         return 0;
3280 }
3281
3282 #ifdef CONFIG_PM
3283
3284 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3285 {
3286         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3287         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3288         int err = 0;
3289         unsigned long flags;
3290
3291         mutex_lock(&tegra->sync_lock);
3292
3293         if (xhci->shared_hcd == hcd) {
3294                 tegra->usb3_rh_suspend = true;
3295                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3296         } else if (xhci->main_hcd == hcd) {
3297                 tegra->usb2_rh_suspend = true;
3298                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3299         }
3300
3301         WARN_ON(tegra->hc_in_elpg);
3302
3303         /* suspend xhci bus. This will also set remote mask */
3304         err = xhci_bus_suspend(hcd);
3305         if (err) {
3306                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3307                                 __func__, err);
3308                 goto xhci_bus_suspend_failed;
3309         }
3310
3311         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3312                 goto done; /* one of the root hubs is still working */
3313
3314         spin_lock_irqsave(&tegra->lock, flags);
3315         tegra->hc_in_elpg = true;
3316         spin_unlock_irqrestore(&tegra->lock, flags);
3317
3318         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3319
3320         /* save xhci spec ctx. Already done by xhci_suspend */
3321         err = xhci_suspend(tegra->xhci);
3322         if (err) {
3323                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3324                 goto xhci_suspend_failed;
3325         }
3326
3327         /* Powergate host. Include ss power gate if not already done */
3328         err = tegra_xhci_host_elpg_entry(tegra);
3329         if (err) {
3330                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3331                                 __func__, err);
3332                 goto tegra_xhci_host_elpg_entry_failed;
3333         }
3334
3335         /* At this point,ensure ss/hs intr enables are always on */
3336         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3337         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3338
3339         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3340         if (fw_log_wait_empty_timeout(tegra, 100))
3341                 xhci_warn(xhci, "%s still has logs\n", __func__);
3342         tegra->log.dequeue = tegra->log.virt_addr;
3343         tegra->log.seq = 0;
3344
3345 done:
3346         /* pads are disabled only if usb2 root hub in xusb is idle */
3347         /* pads will actually be disabled only when all usb2 ports are idle */
3348         if (xhci->main_hcd == hcd) {
3349                 utmi_phy_pad_disable();
3350                 utmi_phy_iddq_override(true);
3351         }
3352         mutex_unlock(&tegra->sync_lock);
3353         return 0;
3354
3355 tegra_xhci_host_elpg_entry_failed:
3356
3357 xhci_suspend_failed:
3358         tegra->hc_in_elpg = false;
3359 xhci_bus_suspend_failed:
3360         if (xhci->shared_hcd == hcd)
3361                 tegra->usb3_rh_suspend = false;
3362         else if (xhci->main_hcd == hcd)
3363                 tegra->usb2_rh_suspend = false;
3364
3365         mutex_unlock(&tegra->sync_lock);
3366         return err;
3367 }
3368
3369 /* First, USB2HCD and then USB3HCD resume will be called */
3370 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3371 {
3372         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3373         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3374         int err = 0;
3375
3376         mutex_lock(&tegra->sync_lock);
3377
3378         tegra->host_resume_req = true;
3379
3380         if (xhci->shared_hcd == hcd)
3381                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3382         else if (xhci->main_hcd == hcd)
3383                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3384
3385         /* pads are disabled only if usb2 root hub in xusb is idle */
3386         /* pads will actually be disabled only when all usb2 ports are idle */
3387         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3388                 utmi_phy_pad_enable();
3389                 utmi_phy_iddq_override(false);
3390         }
3391         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3392                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3393                         tegra_xhci_host_partition_elpg_exit(tegra);
3394         }
3395
3396          /* handle remote wakeup before resuming bus */
3397         wait_remote_wakeup_ports(hcd);
3398
3399         err = xhci_bus_resume(hcd);
3400         if (err) {
3401                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3402                                 __func__, err);
3403                 goto xhci_bus_resume_failed;
3404         }
3405
3406         if (xhci->shared_hcd == hcd)
3407                 tegra->usb3_rh_suspend = false;
3408         else if (xhci->main_hcd == hcd)
3409                 tegra->usb2_rh_suspend = false;
3410
3411         mutex_unlock(&tegra->sync_lock);
3412         return 0;
3413
3414 xhci_bus_resume_failed:
3415         /* TODO: reverse elpg? */
3416         mutex_unlock(&tegra->sync_lock);
3417         return err;
3418 }
3419 #endif
3420
3421 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3422 {
3423         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3424         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3425         irqreturn_t iret = IRQ_HANDLED;
3426         u32 status;
3427
3428         spin_lock(&tegra->lock);
3429         if (tegra->hc_in_elpg) {
3430                 spin_lock(&xhci->lock);
3431                 if (HCD_HW_ACCESSIBLE(hcd)) {
3432                         status = xhci_readl(xhci, &xhci->op_regs->status);
3433                         status |= STS_EINT;
3434                         xhci_writel(xhci, status, &xhci->op_regs->status);
3435                 }
3436                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3437                                 __func__);
3438                 schedule_work(&tegra->host_elpg_exit_work);
3439                 spin_unlock(&xhci->lock);
3440         } else
3441                 iret = xhci_irq(hcd);
3442         spin_unlock(&tegra->lock);
3443
3444         wake_up_interruptible(&tegra->log.intr_wait);
3445
3446         return iret;
3447 }
3448
3449
3450 static const struct hc_driver tegra_plat_xhci_driver = {
3451         .description =          "tegra-xhci",
3452         .product_desc =         "Nvidia xHCI Host Controller",
3453         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3454
3455         /*
3456          * generic hardware linkage
3457          */
3458         .irq =                  tegra_xhci_irq,
3459         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3460
3461         /*
3462          * basic lifecycle operations
3463          */
3464         .reset =                xhci_plat_setup,
3465         .start =                xhci_run,
3466         .stop =                 xhci_stop,
3467         .shutdown =             xhci_shutdown,
3468
3469         /*
3470          * managing i/o requests and associated device resources
3471          */
3472         .urb_enqueue =          xhci_urb_enqueue,
3473         .urb_dequeue =          xhci_urb_dequeue,
3474         .alloc_dev =            xhci_alloc_dev,
3475         .free_dev =             xhci_free_dev,
3476         .alloc_streams =        xhci_alloc_streams,
3477         .free_streams =         xhci_free_streams,
3478         .add_endpoint =         xhci_add_endpoint,
3479         .drop_endpoint =        xhci_drop_endpoint,
3480         .endpoint_reset =       xhci_endpoint_reset,
3481         .check_bandwidth =      xhci_check_bandwidth,
3482         .reset_bandwidth =      xhci_reset_bandwidth,
3483         .address_device =       xhci_address_device,
3484         .update_hub_device =    xhci_update_hub_device,
3485         .reset_device =         xhci_discover_or_reset_device,
3486
3487         /*
3488          * scheduling support
3489          */
3490         .get_frame_number =     xhci_get_frame,
3491
3492         /* Root hub support */
3493         .hub_control =          xhci_hub_control,
3494         .hub_status_data =      xhci_hub_status_data,
3495
3496 #ifdef CONFIG_PM
3497         .bus_suspend =          tegra_xhci_bus_suspend,
3498         .bus_resume =           tegra_xhci_bus_resume,
3499 #endif
3500 };
3501
3502 #ifdef CONFIG_PM
3503 static int
3504 tegra_xhci_suspend(struct platform_device *pdev,
3505                                                 pm_message_t state)
3506 {
3507         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3508         struct xhci_hcd *xhci = tegra->xhci;
3509
3510         int ret = 0;
3511
3512         mutex_lock(&tegra->sync_lock);
3513         if (!tegra->hc_in_elpg) {
3514                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3515                                 __func__);
3516                 mutex_unlock(&tegra->sync_lock);
3517                 return -EBUSY;
3518         }
3519         mutex_unlock(&tegra->sync_lock);
3520
3521         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3522         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3523
3524         /* enable_irq_wake for ss ports */
3525         ret = enable_irq_wake(tegra->padctl_irq);
3526         if (ret < 0) {
3527                 xhci_err(xhci,
3528                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3529                 __func__, tegra->padctl_irq, ret);
3530         }
3531
3532         /* enable_irq_wake for utmip/uhisc wakes */
3533         ret = enable_irq_wake(tegra->usb3_irq);
3534         if (ret < 0) {
3535                 xhci_err(xhci,
3536                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3537                 __func__, tegra->usb3_irq, ret);
3538         }
3539
3540         /* enable_irq_wake for utmip/uhisc wakes */
3541         ret = enable_irq_wake(tegra->usb2_irq);
3542         if (ret < 0) {
3543                 xhci_err(xhci,
3544                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3545                 __func__, tegra->usb2_irq, ret);
3546         }
3547
3548         regulator_disable(tegra->xusb_s1p8v_reg);
3549         regulator_disable(tegra->xusb_s1p05v_reg);
3550         tegra_usb2_clocks_deinit(tegra);
3551
3552         return ret;
3553 }
3554
3555 static int
3556 tegra_xhci_resume(struct platform_device *pdev)
3557 {
3558         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3559
3560         dev_dbg(&pdev->dev, "%s\n", __func__);
3561
3562         tegra->last_jiffies = jiffies;
3563
3564         disable_irq_wake(tegra->padctl_irq);
3565         disable_irq_wake(tegra->usb3_irq);
3566         disable_irq_wake(tegra->usb2_irq);
3567         tegra->lp0_exit = true;
3568
3569         regulator_enable(tegra->xusb_s1p05v_reg);
3570         regulator_enable(tegra->xusb_s1p8v_reg);
3571         tegra_usb2_clocks_init(tegra);
3572
3573         return 0;
3574 }
3575 #endif
3576
3577
3578 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3579 {
3580         struct platform_device *pdev = tegra->pdev;
3581         void __iomem *fw_mmio_base;
3582         phys_addr_t fw_mem_phy_addr;
3583         size_t fw_size;
3584         dma_addr_t fw_dma;
3585 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3586         int ret;
3587         DEFINE_DMA_ATTRS(attrs);
3588 #endif
3589
3590         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3591         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3592
3593         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3594                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3595
3596         if (!fw_mmio_base) {
3597                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3598                                         fw_mem_phy_addr);
3599                         return -ENOMEM;
3600         }
3601
3602         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3603         devm_iounmap(&pdev->dev, fw_mmio_base);
3604
3605         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3606                         fw_mem_phy_addr, fw_size);
3607         if (!fw_mmio_base) {
3608                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3609                                         fw_mem_phy_addr);
3610                         return -ENOMEM;
3611         }
3612
3613         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3614                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3615
3616 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3617         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3618         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3619                         DMA_TO_DEVICE, &attrs);
3620
3621         if (fw_dma == DMA_ERROR_CODE) {
3622                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3623                                 __func__);
3624                 ret = -ENOMEM;
3625                 goto error_iounmap;
3626         }
3627 #else
3628         fw_dma = fw_mem_phy_addr;
3629 #endif
3630         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3631                         (void *) fw_dma, fw_size);
3632
3633         /* all set and ready to go */
3634         tegra->firmware.data = fw_mmio_base;
3635         tegra->firmware.dma = fw_dma;
3636         tegra->firmware.size = fw_size;
3637
3638         return 0;
3639
3640 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3641 error_iounmap:
3642         devm_iounmap(&pdev->dev, fw_mmio_base);
3643         return ret;
3644 #endif
3645 }
3646
3647 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3648 {
3649         struct platform_device *pdev = tegra->pdev;
3650         void __iomem *fw_mmio_base = tegra->firmware.data;
3651
3652 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3653         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3654                         tegra->firmware.size, DMA_TO_DEVICE);
3655 #endif
3656         devm_iounmap(&pdev->dev, fw_mmio_base);
3657
3658         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3659 }
3660
3661 static int init_firmware(struct tegra_xhci_hcd *tegra)
3662 {
3663         return init_bootloader_firmware(tegra);
3664 }
3665
3666 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3667 {
3668         deinit_bootloader_firmware(tegra);
3669 }
3670
3671 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3672                 struct platform_device *pdev)
3673 {
3674         int err = 0;
3675         /* enable ss clock */
3676         err = clk_enable(tegra->host_clk);
3677         if (err) {
3678                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3679                 goto enable_host_clk_failed;
3680         }
3681
3682         err = clk_enable(tegra->ss_clk);
3683         if (err) {
3684                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3685                 goto eanble_ss_clk_failed;
3686         }
3687
3688         err = clk_enable(tegra->emc_clk);
3689         if (err) {
3690                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3691                 goto eanble_emc_clk_failed;
3692         }
3693
3694         return 0;
3695
3696 eanble_emc_clk_failed:
3697         clk_disable(tegra->ss_clk);
3698
3699 eanble_ss_clk_failed:
3700         clk_disable(tegra->host_clk);
3701
3702 enable_host_clk_failed:
3703         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3704                 clk_disable(tegra->pll_re_vco_clk);
3705         return err;
3706 }
3707
3708 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3709         .boot_media_0                   = 0x0,
3710         .usb2_pad_mux_0                 = 0x4,
3711         .usb2_port_cap_0                = 0x8,
3712         .snps_oc_map_0                  = 0xc,
3713         .usb2_oc_map_0                  = 0x10,
3714         .ss_port_map_0                  = 0x14,
3715         .oc_det_0                       = 0x18,
3716         .elpg_program_0                 = 0x1c,
3717         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3718         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3719         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3720         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3721         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3722         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3723         .usb2_bchrg_bias_pad_0          = 0x28,
3724         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3725         .iophy_pll_p0_ctl1_0            = 0x30,
3726         .iophy_pll_p0_ctl2_0            = 0x34,
3727         .iophy_pll_p0_ctl3_0            = 0x38,
3728         .iophy_pll_p0_ctl4_0            = 0x3c,
3729         .iophy_usb3_pad0_ctl1_0         = 0x40,
3730         .iophy_usb3_pad1_ctl1_0         = 0x44,
3731         .iophy_usb3_pad0_ctl2_0         = 0x48,
3732         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3733         .iophy_usb3_pad0_ctl3_0         = 0x50,
3734         .iophy_usb3_pad1_ctl3_0         = 0x54,
3735         .iophy_usb3_pad0_ctl4_0         = 0x58,
3736         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3737         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3738         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3739         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3740         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3741         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3742         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3743         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3744         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3745         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3746         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3747         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3748         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3749         .usb2_otg_pad0_ctl0_0           = 0x90,
3750         .usb2_otg_pad1_ctl0_0           = 0x94,
3751         .usb2_otg_pad2_ctl0_0           = 0xffff,
3752         .usb2_otg_pad0_ctl1_0           = 0x98,
3753         .usb2_otg_pad1_ctl1_0           = 0x9c,
3754         .usb2_otg_pad2_ctl1_0           = 0xffff,
3755         .usb2_bias_pad_ctl0_0           = 0xa0,
3756         .usb2_bias_pad_ctl1_0           = 0xa4,
3757         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3758         .usb2_hsic_pad1_ctl0_0          = 0xac,
3759         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3760         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3761         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3762         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3763         .ulpi_link_trim_ctl0            = 0xc0,
3764         .ulpi_null_clk_trim_ctl0        = 0xc4,
3765         .hsic_strb_trim_ctl0            = 0xc8,
3766         .wake_ctl0                      = 0xcc,
3767         .pm_spare0                      = 0xd0,
3768         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3769         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3770         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3771         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3772         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3773         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3774         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3775         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3776         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3777         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3778         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3779         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3780         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3781         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3782         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3783         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3784         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3785         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3786         .usb3_pad_mux_0                 = 0xffff,
3787         .iophy_pll_s0_ctl1_0            = 0xffff,
3788         .iophy_pll_s0_ctl2_0            = 0xffff,
3789         .iophy_pll_s0_ctl3_0            = 0xffff,
3790         .iophy_pll_s0_ctl4_0            = 0xffff,
3791         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3792         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3793         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3794         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3795         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3796         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3797 };
3798
3799 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3800         .boot_media_0                   = 0x0,
3801         .usb2_pad_mux_0                 = 0x4,
3802         .usb2_port_cap_0                = 0x8,
3803         .snps_oc_map_0                  = 0xc,
3804         .usb2_oc_map_0                  = 0x10,
3805         .ss_port_map_0                  = 0x14,
3806         .oc_det_0                       = 0x18,
3807         .elpg_program_0                 = 0x1c,
3808         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3809         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3810         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3811         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3812         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3813         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3814         .usb2_bchrg_bias_pad_0          = 0x38,
3815         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3816         .iophy_pll_p0_ctl1_0            = 0x40,
3817         .iophy_pll_p0_ctl2_0            = 0x44,
3818         .iophy_pll_p0_ctl3_0            = 0x48,
3819         .iophy_pll_p0_ctl4_0            = 0x4c,
3820         .iophy_usb3_pad0_ctl1_0         = 0x50,
3821         .iophy_usb3_pad1_ctl1_0         = 0x54,
3822         .iophy_usb3_pad0_ctl2_0         = 0x58,
3823         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3824         .iophy_usb3_pad0_ctl3_0         = 0x60,
3825         .iophy_usb3_pad1_ctl3_0         = 0x64,
3826         .iophy_usb3_pad0_ctl4_0         = 0x68,
3827         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3828         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3829         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3830         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3831         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3832         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3833         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3834         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3835         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3836         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3837         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3838         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3839         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3840         .usb2_otg_pad0_ctl0_0           = 0xa0,
3841         .usb2_otg_pad1_ctl0_0           = 0xa4,
3842         .usb2_otg_pad2_ctl0_0           = 0xa8,
3843         .usb2_otg_pad0_ctl1_0           = 0xac,
3844         .usb2_otg_pad1_ctl1_0           = 0xb0,
3845         .usb2_otg_pad2_ctl1_0           = 0xb4,
3846         .usb2_bias_pad_ctl0_0           = 0xb8,
3847         .usb2_bias_pad_ctl1_0           = 0xbc,
3848         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3849         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3850         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3851         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3852         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3853         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3854         .ulpi_link_trim_ctl0            = 0xd8,
3855         .ulpi_null_clk_trim_ctl0        = 0xdc,
3856         .hsic_strb_trim_ctl0            = 0xe0,
3857         .wake_ctl0                      = 0xe4,
3858         .pm_spare0                      = 0xe8,
3859         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3860         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3861         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3862         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3863         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3864         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3865         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3866         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3867         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3868         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3869         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3870         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3871         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3872         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3873         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3874         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3875         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3876         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3877         .usb3_pad_mux_0                 = 0x134,
3878         .iophy_pll_s0_ctl1_0            = 0x138,
3879         .iophy_pll_s0_ctl2_0            = 0x13c,
3880         .iophy_pll_s0_ctl3_0            = 0x140,
3881         .iophy_pll_s0_ctl4_0            = 0x144,
3882         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3883         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3884         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3885         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3886         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3887         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3888 };
3889
3890 /* FIXME: using notifier to transfer control to host from suspend
3891  * for otg port when xhci is in elpg. Find  better alternative
3892  */
3893 static int tegra_xhci_otg_notify(struct notifier_block *nb,
3894                                    unsigned long event, void *unused)
3895 {
3896         struct tegra_xhci_hcd *tegra = container_of(nb,
3897                                         struct tegra_xhci_hcd, otgnb);
3898
3899         if ((event == USB_EVENT_ID))
3900                 if (tegra->hc_in_elpg) {
3901                         schedule_work(&tegra->host_elpg_exit_work);
3902                         tegra->host_resume_req = true;
3903         }
3904
3905         return NOTIFY_OK;
3906 }
3907
3908 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3909 static int tegra_xhci_probe(struct platform_device *pdev)
3910 {
3911         const struct hc_driver *driver;
3912         struct xhci_hcd *xhci;
3913         struct tegra_xhci_hcd *tegra;
3914         struct resource *res;
3915         struct usb_hcd  *hcd;
3916         unsigned pad;
3917         unsigned port;
3918         u32 val;
3919         int ret;
3920         int irq;
3921
3922         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3923
3924         if (usb_disabled())
3925                 return -ENODEV;
3926
3927         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3928         if (!tegra) {
3929                 dev_err(&pdev->dev, "memory alloc failed\n");
3930                 return -ENOMEM;
3931         }
3932         tegra->pdev = pdev;
3933         tegra->pdata = dev_get_platdata(&pdev->dev);
3934         tegra->bdata = tegra->pdata->bdata;
3935
3936         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3937                         &tegra->padctl_base);
3938         if (ret) {
3939                 dev_err(&pdev->dev, "failed to map padctl\n");
3940                 return ret;
3941         }
3942
3943         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3944         if (ret) {
3945                 dev_err(&pdev->dev, "failed to map fpci\n");
3946                 return ret;
3947         }
3948
3949         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3950         if (ret) {
3951                 dev_err(&pdev->dev, "failed to map ipfs\n");
3952                 return ret;
3953         }
3954
3955         ret = tegra_xusb_partitions_clk_init(tegra);
3956         if (ret) {
3957                 dev_err(&pdev->dev,
3958                         "failed to initialize xusb partitions clocks\n");
3959                 return ret;
3960         }
3961
3962         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
3963                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
3964                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
3965                         dev_err(&pdev->dev, "failed to get usb phy\n");
3966                         tegra->transceiver = NULL;
3967                 } else {
3968                         otg_set_host(tegra->transceiver->otg, &hcd->self);
3969                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
3970                         usb_register_notifier(tegra->transceiver,
3971                                 &tegra->otgnb);
3972                 }
3973         }
3974         /* Enable power rails to the PAD,VBUS
3975          * and pull-up voltage.Initialize the regulators
3976          */
3977         ret = tegra_xusb_regulator_init(tegra, pdev);
3978         if (ret) {
3979                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3980                 goto err_deinit_xusb_partition_clk;
3981         }
3982
3983         /* Enable UTMIP, PLLU and PLLE */
3984         ret = tegra_usb2_clocks_init(tegra);
3985         if (ret) {
3986                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3987                 goto err_deinit_tegra_xusb_regulator;
3988         }
3989
3990         /* tegra_unpowergate_partition also does partition reset deassert */
3991         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3992         if (ret)
3993                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3994
3995         /* tegra_unpowergate_partition also does partition reset deassert */
3996         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3997         if (ret)
3998                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3999
4000         ret = tegra_enable_xusb_clk(tegra, pdev);
4001         if (ret)
4002                 dev_err(&pdev->dev, "could not enable partition clock\n");
4003
4004         /* reset the pointer back to NULL. driver uses it */
4005         /* platform_set_drvdata(pdev, NULL); */
4006
4007         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
4008         if (!res) {
4009                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4010                 ret = -ENODEV;
4011                 goto err_deinit_usb2_clocks;
4012         }
4013         tegra->host_phy_base = res->start;
4014
4015         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4016                                 res->start, resource_size(res));
4017         if (!tegra->host_phy_virt_base) {
4018                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4019                 ret = -ENOMEM;
4020                 goto err_deinit_usb2_clocks;
4021         }
4022
4023         /* Setup IPFS access and BAR0 space */
4024         tegra_xhci_cfg(tegra);
4025
4026         val = readl(tegra->fpci_base + XUSB_CFG_0);
4027         tegra->device_id = (val >> 16) & 0xffff;
4028
4029         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4030                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4031
4032         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4033                 tegra->padregs = &t114_padregs_offset;
4034         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4035                 tegra->padregs = &t124_padregs_offset;
4036         } else {
4037                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4038                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4039                 tegra->padregs = &t124_padregs_offset;
4040         }
4041
4042         /* calculate rctrl_val and tctrl_val once at boot time */
4043         /* Issue is only applicable for T114 */
4044         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4045                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4046
4047         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4048                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4049                         hsic_power_rail_enable(tegra);
4050         }
4051
4052         /* Program the XUSB pads to take ownership of ports */
4053         tegra_xhci_padctl_portmap_and_caps(tegra);
4054
4055         /* Release XUSB wake logic state latching */
4056         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4057         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4058
4059         /* Deassert reset to XUSB host, ss, dev clocks */
4060         tegra_periph_reset_deassert(tegra->host_clk);
4061         tegra_periph_reset_deassert(tegra->ss_clk);
4062
4063         fw_log_init(tegra);
4064         ret = init_firmware(tegra);
4065         if (ret < 0) {
4066                 dev_err(&pdev->dev, "failed to init firmware\n");
4067                 ret = -ENODEV;
4068                 goto err_deinit_usb2_clocks;
4069         }
4070
4071         ret = load_firmware(tegra, true /* do reset ARU */);
4072         if (ret < 0) {
4073                 dev_err(&pdev->dev, "failed to load firmware\n");
4074                 ret = -ENODEV;
4075                 goto err_deinit_firmware;
4076         }
4077
4078         spin_lock_init(&tegra->lock);
4079         mutex_init(&tegra->sync_lock);
4080         mutex_init(&tegra->mbox_lock);
4081         pmc_init(tegra);
4082
4083         device_init_wakeup(&pdev->dev, 1);
4084         driver = &tegra_plat_xhci_driver;
4085
4086         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4087         if (!hcd) {
4088                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4089                 ret = -ENOMEM;
4090                 goto err_deinit_firmware;
4091         }
4092
4093         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
4094         if (ret) {
4095                 dev_err(&pdev->dev, "failed to map host\n");
4096                 goto err_put_usb2_hcd;
4097         }
4098         hcd->rsrc_start = res->start;
4099         hcd->rsrc_len = resource_size(res);
4100
4101         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
4102         if (!res) {
4103                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4104                 ret = -ENODEV;
4105                 goto err_put_usb2_hcd;
4106         }
4107         irq = res->start;
4108         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4109         if (ret) {
4110                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4111                 goto err_put_usb2_hcd;
4112         }
4113
4114         /* USB 2.0 roothub is stored in the platform_device now. */
4115         hcd = dev_get_drvdata(&pdev->dev);
4116         xhci = hcd_to_xhci(hcd);
4117         tegra->xhci = xhci;
4118         platform_set_drvdata(pdev, tegra);
4119
4120         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4121                                                 dev_name(&pdev->dev), hcd);
4122         if (!xhci->shared_hcd) {
4123                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4124                 ret = -ENOMEM;
4125                 goto err_remove_usb2_hcd;
4126         }
4127
4128         /*
4129          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4130          * is called by usb_add_hcd().
4131          */
4132         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4133
4134         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4135         if (ret) {
4136                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4137                 goto err_put_usb3_hcd;
4138         }
4139
4140         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4141         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4142
4143         /* do mailbox related initializations */
4144         tegra->mbox_owner = 0xffff;
4145         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4146
4147         tegra_xhci_enable_fw_message(tegra);
4148
4149         /* do ss partition elpg exit related initialization */
4150         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4151
4152         /* do host partition elpg exit related initialization */
4153         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4154
4155         /* Register interrupt handler for SMI line to handle mailbox
4156          * interrupt from firmware
4157          */
4158         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
4159                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4160         if (ret != 0)
4161                 goto err_remove_usb3_hcd;
4162
4163         /* Register interrupt handler for PADCTRL line to
4164          * handle wake on connect irqs interrupt from
4165          * firmware
4166          */
4167         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4168                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4169                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4170         if (ret != 0)
4171                 goto err_remove_usb3_hcd;
4172
4173         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4174                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4175                 &tegra->usb2_irq);
4176         if (ret != 0)
4177                 goto err_remove_usb3_hcd;
4178
4179         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4180                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4181                 &tegra->usb3_irq);
4182         if (ret != 0)
4183                 goto err_remove_usb3_hcd;
4184
4185         tegra->ss_pwr_gated = false;
4186         tegra->host_pwr_gated = false;
4187         tegra->hc_in_elpg = false;
4188         tegra->hs_wake_event = false;
4189         tegra->host_resume_req = false;
4190         tegra->lp0_exit = false;
4191
4192         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4193                 tegra->ctle_ctx_saved[port] = false;
4194                 tegra->dfe_ctx_saved[port] = false;
4195         }
4196
4197         tegra_xhci_debug_read_pads(tegra);
4198         utmi_phy_pad_enable();
4199         utmi_phy_iddq_override(false);
4200
4201         tegra_pd_add_device(&pdev->dev);
4202
4203         return 0;
4204
4205 err_remove_usb3_hcd:
4206         usb_remove_hcd(xhci->shared_hcd);
4207 err_put_usb3_hcd:
4208         usb_put_hcd(xhci->shared_hcd);
4209 err_remove_usb2_hcd:
4210         kfree(tegra->xhci);
4211         usb_remove_hcd(hcd);
4212 err_put_usb2_hcd:
4213         usb_put_hcd(hcd);
4214 err_deinit_firmware:
4215         deinit_firmware(tegra);
4216 err_deinit_usb2_clocks:
4217         tegra_usb2_clocks_deinit(tegra);
4218 err_deinit_tegra_xusb_regulator:
4219         tegra_xusb_regulator_deinit(tegra);
4220 err_deinit_xusb_partition_clk:
4221         usb_unregister_notifier(tegra->transceiver,
4222                 &tegra->otgnb);
4223         tegra_xusb_partitions_clk_deinit(tegra);
4224
4225         return ret;
4226 }
4227
4228 static int tegra_xhci_remove(struct platform_device *pdev)
4229 {
4230         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4231         struct xhci_hcd *xhci = NULL;
4232         struct usb_hcd *hcd = NULL;
4233         unsigned pad;
4234
4235         if (tegra == NULL)
4236                 return -EINVAL;
4237
4238         xhci = tegra->xhci;
4239         hcd = xhci_to_hcd(xhci);
4240
4241         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4242                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4243                         hsic_pad_disable(tegra, pad);
4244         }
4245
4246         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4247                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4248                         hsic_power_rail_disable(tegra);
4249         }
4250
4251         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4252         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4253         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4254         usb_remove_hcd(xhci->shared_hcd);
4255         usb_put_hcd(xhci->shared_hcd);
4256         usb_remove_hcd(hcd);
4257         usb_put_hcd(hcd);
4258         kfree(xhci);
4259
4260         deinit_firmware(tegra);
4261         fw_log_deinit(tegra);
4262         tegra_xusb_regulator_deinit(tegra);
4263         usb_unregister_notifier(tegra->transceiver,
4264                 &tegra->otgnb);
4265         tegra_usb2_clocks_deinit(tegra);
4266         if (!tegra->hc_in_elpg)
4267                 tegra_xusb_partitions_clk_deinit(tegra);
4268         utmi_phy_pad_disable();
4269         utmi_phy_iddq_override(true);
4270
4271         tegra_pd_remove_device(&pdev->dev);
4272         return 0;
4273 }
4274
4275 static void tegra_xhci_shutdown(struct platform_device *pdev)
4276 {
4277         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4278         struct xhci_hcd *xhci = NULL;
4279         struct usb_hcd *hcd = NULL;
4280
4281         if (tegra == NULL)
4282                 return;
4283
4284         if (tegra->hc_in_elpg) {
4285                 pmc_disable_bus_ctrl(tegra);
4286         } else {
4287                 xhci = tegra->xhci;
4288                 hcd = xhci_to_hcd(xhci);
4289                 xhci_shutdown(hcd);
4290         }
4291 }
4292
4293 static struct platform_driver tegra_xhci_driver = {
4294         .probe  = tegra_xhci_probe,
4295         .remove = tegra_xhci_remove,
4296         .shutdown = tegra_xhci_shutdown,
4297 #ifdef CONFIG_PM
4298         .suspend = tegra_xhci_suspend,
4299         .resume  = tegra_xhci_resume,
4300 #endif
4301         .driver = {
4302                 .name = "tegra-xhci",
4303         },
4304 };
4305 MODULE_ALIAS("platform:tegra-xhci");
4306
4307 int tegra_xhci_register_plat(void)
4308 {
4309         return platform_driver_register(&tegra_xhci_driver);
4310 }
4311
4312 void tegra_xhci_unregister_plat(void)
4313 {
4314         platform_driver_unregister(&tegra_xhci_driver);
4315 }