arch/arm/mach-tegra/board-ardbeg.c

   1 /*
   2  * arch/arm/mach-tegra/board-ardbeg.c
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/i2c-hid.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/delay.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/gpio.h>
  33 #include <linux/input.h>
  34 #include <linux/platform_data/tegra_usb.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/rm31080a_ts.h>
  37 #include <linux/maxim_sti.h>
  38 #include <linux/memblock.h>
  39 #include <linux/spi/spi-tegra.h>
  40 #include <linux/nfc/pn544.h>
  41 #include <linux/rfkill-gpio.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/ti_wilink_st.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/smb349-charger.h>
  46 #include <linux/max17048_battery.h>
  47 #include <linux/leds.h>
  48 #include <linux/i2c/at24.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/i2c.h>
  51 #include <linux/i2c-tegra.h>
  52 #include <linux/platform_data/serial-tegra.h>
  53 #include <linux/edp.h>
  54 #include <linux/usb/tegra_usb_phy.h>
  55 #include <linux/mfd/palmas.h>
  56 #include <linux/clk/tegra.h>
  57 #include <media/tegra_dtv.h>
  58 #include <linux/clocksource.h>
  59 #include <linux/irqchip.h>
  60 #include <linux/irqchip/tegra.h>
  61 #include <linux/tegra-soc.h>
  62 #include <linux/tegra_fiq_debugger.h>
  63 #include <linux/platform_data/tegra_usb_modem_power.h>
  64 #include <linux/platform_data/tegra_ahci.h>
  65 #include <linux/irqchip/tegra.h>
  66 #include <sound/max98090.h>
  67
  68 #include <mach/irqs.h>
  69 #include <mach/pinmux.h>
  70 #include <mach/pinmux-t12.h>
  71 #include <mach/io_dpd.h>
  72 #include <mach/i2s.h>
  73 #include <mach/isomgr.h>
  74 #include <mach/tegra_asoc_pdata.h>
  75 #include <mach/dc.h>
  76 #include <mach/tegra_usb_pad_ctrl.h>
  77
  78 #include <asm/mach-types.h>
  79 #include <asm/mach/arch.h>
  80 #include <mach/gpio-tegra.h>
  81 #include <mach/xusb.h>
  82
  83 #include "board.h"
  84 #include "board-ardbeg.h"
  85 #include "board-common.h"
  86 #include "board-touch-raydium.h"
  87 #include "board-touch-maxim_sti.h"
  88 #include "clock.h"
  89 #include "common.h"
  90 #include "devices.h"
  91 #include "gpio-names.h"
  92 #include "iomap.h"
  93 #include "pm.h"
  94 #include "tegra-board-id.h"
  95 #include "tegra-of-dev-auxdata.h"
  96
  97 static struct board_info board_info, display_board_info;
  98
  99 static struct resource ardbeg_bluedroid_pm_resources[] = {
 100         [0] = {
 101                 .name   = "shutdown_gpio",
 102                 .start  = TEGRA_GPIO_PR1,
 103                 .end    = TEGRA_GPIO_PR1,
 104                 .flags  = IORESOURCE_IO,
 105         },
 106         [1] = {
 107                 .name = "host_wake",
 108                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 109         },
 110         [2] = {
 111                 .name = "gpio_ext_wake",
 112                 .start  = TEGRA_GPIO_PEE1,
 113                 .end    = TEGRA_GPIO_PEE1,
 114                 .flags  = IORESOURCE_IO,
 115         },
 116         [3] = {
 117                 .name = "gpio_host_wake",
 118                 .start  = TEGRA_GPIO_PU6,
 119                 .end    = TEGRA_GPIO_PU6,
 120                 .flags  = IORESOURCE_IO,
 121         },
 122         [4] = {
 123                 .name = "reset_gpio",
 124                 .start  = TEGRA_GPIO_PX1,
 125                 .end    = TEGRA_GPIO_PX1,
 126                 .flags  = IORESOURCE_IO,
 127         },
 128 };
 129
 130 static struct platform_device ardbeg_bluedroid_pm_device = {
 131         .name = "bluedroid_pm",
 132         .id             = 0,
 133         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
 134         .resource       = ardbeg_bluedroid_pm_resources,
 135 };
 136
 137 static noinline void __init ardbeg_setup_bluedroid_pm(void)
 138 {
 139         ardbeg_bluedroid_pm_resources[1].start =
 140                 ardbeg_bluedroid_pm_resources[1].end =
 141                                 gpio_to_irq(TEGRA_GPIO_PU6);
 142         platform_device_register(&ardbeg_bluedroid_pm_device);
 143 }
 144
 145 static struct i2c_board_info __initdata rt5639_board_info = {
 146         I2C_BOARD_INFO("rt5639", 0x1c),
 147 };
 148
 149 static struct max98090_eq_cfg max98090_eq_cfg[] = {
 150 };
 151
 152 static struct max98090_pdata norrin_max98090_pdata = {
 153         /* Equalizer Configuration */
 154         .eq_cfg = max98090_eq_cfg,
 155         .eq_cfgcnt = ARRAY_SIZE(max98090_eq_cfg),
 156
 157         /* Microphone Configuration */
 158         .digmic_left_mode = 1,
 159         .digmic_right_mode = 1,
 160 };
 161
 162 static struct i2c_board_info __initdata max98090_board_info = {
 163         I2C_BOARD_INFO("max98090", 0x10),
 164         .platform_data  = &norrin_max98090_pdata,
 165 };
 166
 167 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
 168         /* name         parent          rate            enabled */
 169         { "pll_m",      NULL,           0,              false},
 170         { "hda",        "pll_p",        108000000,      false},
 171         { "hda2codec_2x", "pll_p",      48000000,       false},
 172         { "pwm",        "pll_p",        48000000,       false},
 173         { "i2s1",       "pll_a_out0",   0,              false},
 174         { "i2s3",       "pll_a_out0",   0,              false},
 175         { "i2s4",       "pll_a_out0",   0,              false},
 176         { "spdif_out",  "pll_a_out0",   0,              false},
 177         { "d_audio",    "clk_m",        12000000,       false},
 178         { "dam0",       "clk_m",        12000000,       false},
 179         { "dam1",       "clk_m",        12000000,       false},
 180         { "dam2",       "clk_m",        12000000,       false},
 181         { "audio1",     "i2s1_sync",    0,              false},
 182         { "audio3",     "i2s3_sync",    0,              false},
 183         { "vi_sensor",  "pll_p",        150000000,      false},
 184         { "vi_sensor2", "pll_p",        150000000,      false},
 185         { "cilab",      "pll_p",        150000000,      false},
 186         { "cilcd",      "pll_p",        150000000,      false},
 187         { "cile",       "pll_p",        150000000,      false},
 188         { "i2c1",       "pll_p",        3200000,        false},
 189         { "i2c2",       "pll_p",        3200000,        false},
 190         { "i2c3",       "pll_p",        3200000,        false},
 191         { "i2c4",       "pll_p",        3200000,        false},
 192         { "i2c5",       "pll_p",        3200000,        false},
 193         { "sbc1",       "pll_p",        25000000,       false},
 194         { "sbc2",       "pll_p",        25000000,       false},
 195         { "sbc3",       "pll_p",        25000000,       false},
 196         { "sbc4",       "pll_p",        25000000,       false},
 197         { "sbc5",       "pll_p",        25000000,       false},
 198         { "sbc6",       "pll_p",        25000000,       false},
 199         { "uarta",      "pll_p",        408000000,      false},
 200         { "uartb",      "pll_p",        408000000,      false},
 201         { "uartc",      "pll_p",        408000000,      false},
 202         { "uartd",      "pll_p",        408000000,      false},
 203         { NULL,         NULL,           0,              0},
 204 };
 205
 206 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
 207         .hid_descriptor_address = 0x0,
 208 };
 209
 210 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
 211         I2C_BOARD_INFO("hid", 0x3B),
 212         .platform_data  = &i2c_keyboard_pdata,
 213 };
 214
 215 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
 216         .hid_descriptor_address = 0x20,
 217 };
 218
 219 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
 220         I2C_BOARD_INFO("hid", 0x2C),
 221         .platform_data  = &i2c_touchpad_pdata,
 222 };
 223
 224 static void ardbeg_i2c_init(void)
 225 {
 226         struct board_info board_info;
 227         tegra_get_board_info(&board_info);
 228
 229         if (board_info.board_id == BOARD_PM374) {
 230                 i2c_register_board_info(0, &max98090_board_info, 1);
 231         } else if (board_info.board_id != BOARD_PM359)
 232                 i2c_register_board_info(0, &rt5639_board_info, 1);
 233
 234         if (board_info.board_id == BOARD_PM359 ||
 235                 board_info.board_id == BOARD_PM358 ||
 236                 board_info.board_id == BOARD_PM363 ||
 237                 board_info.board_id == BOARD_PM374) {
 238                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
 239                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
 240
 241                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
 242                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
 243         }
 244 }
 245
 246 #ifndef CONFIG_USE_OF
 247 static struct platform_device *ardbeg_uart_devices[] __initdata = {
 248         &tegra_uarta_device,
 249         &tegra_uartb_device,
 250         &tegra_uartc_device,
 251 };
 252
 253 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
 254         .dma_req_selector = 8,
 255         .modem_interrupt = false,
 256 };
 257
 258 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
 259         .dma_req_selector = 9,
 260         .modem_interrupt = false,
 261 };
 262
 263 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
 264         .dma_req_selector = 10,
 265         .modem_interrupt = false,
 266 };
 267 #endif
 268
 269 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
 270         .dma_req_selector = 19,
 271         .modem_interrupt = false,
 272 };
 273
 274 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
 275         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 276         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 277         .gpio_spkr_en = -1,
 278         .gpio_int_mic_en = -1,
 279         .gpio_ext_mic_en = -1,
 280         .gpio_hp_mute = -1,
 281         .gpio_codec1 = -1,
 282         .gpio_codec2 = -1,
 283         .gpio_codec3 = -1,
 284         .i2s_param[HIFI_CODEC]       = {
 285                 .audio_port_id = 1,
 286                 .is_i2s_master = 1,
 287                 .i2s_mode = TEGRA_DAIFMT_I2S,
 288                 .sample_size    = 16,
 289                 .channels       = 2,
 290                 .bit_clk        = 1536000,
 291         },
 292         .i2s_param[BT_SCO] = {
 293                 .audio_port_id = 3,
 294                 .is_i2s_master = 1,
 295                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 296         },
 297         .i2s_param[BASEBAND]    = {
 298                 .audio_port_id  = 0,
 299                 .is_i2s_master  = 1,
 300                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 301                 .sample_size    = 16,
 302                 .rate           = 16000,
 303                 .channels       = 2,
 304                 .bit_clk        = 1024000,
 305         },
 306 };
 307
 308 static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
 309         .gpio_hp_det            = NORRIN_GPIO_HP_DET,
 310         .gpio_ext_mic_en        = TEGRA_GPIO_HP_DET,
 311         .gpio_hp_mute           = -1,
 312         .edp_support            = true,
 313         .edp_states             = {1080, 842, 0},
 314         .i2s_param[HIFI_CODEC]  = {
 315                 .audio_port_id  = 1,
 316                 .is_i2s_master  = 1,
 317                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 318                 .sample_size    = 16,
 319                 .channels       = 2,
 320                 .bit_clk        = 1536000,
 321         },
 322         .i2s_param[BT_SCO]      = {
 323                 .audio_port_id  = 3,
 324                 .is_i2s_master  = 1,
 325                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 326                 .sample_size    = 16,
 327                 .channels       = 1,
 328                 .bit_clk        = 512000,
 329         },
 330 };
 331
 332 static void ardbeg_audio_init(void)
 333 {
 334         struct board_info board_info;
 335         tegra_get_board_info(&board_info);
 336         if (board_info.board_id == BOARD_PM359 ||
 337                         board_info.board_id == BOARD_PM358 ||
 338                         board_info.board_id == BOARD_PM370 ||
 339                         board_info.board_id == BOARD_PM374 ||
 340                         board_info.board_id == BOARD_PM375 ||
 341                         board_info.board_id == BOARD_PM363) {
 342                 /*Laguna*/
 343                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
 344                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
 345                 if (board_info.board_id != BOARD_PM363)
 346                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
 347         } else {
 348                 /*Ardbeg*/
 349
 350                 if (board_info.board_id == BOARD_E1762 ||
 351                         board_info.board_id == BOARD_P1761 ||
 352                         board_info.board_id == BOARD_E1922) {
 353                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 354                                 TEGRA_GPIO_CDC_IRQ;
 355                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 356                 } else {
 357                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 358                                 TEGRA_GPIO_HP_DET;
 359                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
 360                 }
 361                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 362                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 363         }
 364
 365         if (board_info.board_id == BOARD_E1971) {
 366                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
 367                 ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 368                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 369                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 370         }
 371
 372         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
 373         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
 374
 375         norrin_audio_pdata_max98090.codec_name = "max98090.0-0010";
 376         norrin_audio_pdata_max98090.codec_dai_name = "HiFi";
 377 }
 378
 379 static struct platform_device ardbeg_audio_device_rt5639 = {
 380         .name = "tegra-snd-rt5639",
 381         .id = 0,
 382         .dev = {
 383                 .platform_data = &ardbeg_audio_pdata_rt5639,
 384         },
 385 };
 386
 387 static struct platform_device norrin_audio_device_max98090 = {
 388         .name   = "tegra-snd-max98090",
 389         .id     = 0,
 390         .dev    = {
 391                 .platform_data = &norrin_audio_pdata_max98090,
 392         },
 393 };
 394
 395 static void __init ardbeg_uart_init(void)
 396 {
 397
 398 #ifndef CONFIG_USE_OF
 399         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
 400         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
 401         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
 402         platform_add_devices(ardbeg_uart_devices,
 403                         ARRAY_SIZE(ardbeg_uart_devices));
 404 #endif
 405         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 406         if (!is_tegra_debug_uartport_hs()) {
 407                 int debug_port_id = uart_console_debug_init(3);
 408                 if (debug_port_id < 0)
 409                         return;
 410
 411 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
 412                 tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
 413 #else
 414                 platform_device_register(uart_console_debug_device);
 415 #endif
 416         } else {
 417                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 418                 platform_device_register(&tegra_uartd_device);
 419         }
 420 }
 421
 422 static struct resource tegra_rtc_resources[] = {
 423         [0] = {
 424                 .start = TEGRA_RTC_BASE,
 425                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
 426                 .flags = IORESOURCE_MEM,
 427         },
 428         [1] = {
 429                 .start = INT_RTC,
 430                 .end = INT_RTC,
 431                 .flags = IORESOURCE_IRQ,
 432         },
 433 };
 434
 435 static struct platform_device tegra_rtc_device = {
 436         .name = "tegra_rtc",
 437         .id   = -1,
 438         .resource = tegra_rtc_resources,
 439         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
 440 };
 441
 442 static struct platform_device *ardbeg_devices[] __initdata = {
 443         &tegra_pmu_device,
 444         &tegra_rtc_device,
 445 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
 446         &tegratab_tegra_wakeup_monitor_device,
 447 #endif
 448         &tegra_udc_device,
 449 #if defined(CONFIG_TEGRA_WATCHDOG)
 450         &tegra_wdt0_device,
 451 #endif
 452 #if defined(CONFIG_TEGRA_AVP)
 453         &tegra_avp_device,
 454 #endif
 455 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
 456         &tegra12_se_device,
 457 #endif
 458         &tegra_ahub_device,
 459         &tegra_dam_device0,
 460         &tegra_dam_device1,
 461         &tegra_dam_device2,
 462         &tegra_i2s_device0,
 463         &tegra_i2s_device1,
 464         &tegra_i2s_device3,
 465         &tegra_i2s_device4,
 466         &tegra_spdif_device,
 467         &spdif_dit_device,
 468         &bluetooth_dit_device,
 469         &baseband_dit_device,
 470         &tegra_hda_device,
 471         &tegra_offload_device,
 472         &tegra30_avp_audio_device,
 473 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
 474         &tegra_aes_device,
 475 #endif
 476         &tegra_hier_ictlr_device,
 477 };
 478
 479 static struct tegra_usb_platform_data tegra_udc_pdata = {
 480         .port_otg = true,
 481         .has_hostpc = true,
 482         .unaligned_dma_buf_supported = false,
 483         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 484         .op_mode = TEGRA_USB_OPMODE_DEVICE,
 485         .u_data.dev = {
 486                 .vbus_pmu_irq = 0,
 487                 .vbus_gpio = -1,
 488                 .charging_supported = true,
 489                 .remote_wakeup_supported = false,
 490         },
 491         .u_cfg.utmi = {
 492                 .hssync_start_delay = 0,
 493                 .elastic_limit = 16,
 494                 .idle_wait_delay = 17,
 495                 .term_range_adj = 6,
 496                 .xcvr_setup = 8,
 497                 .xcvr_lsfslew = 2,
 498                 .xcvr_lsrslew = 2,
 499                 .xcvr_setup_offset = 0,
 500                 .xcvr_use_fuses = 1,
 501         },
 502 };
 503
 504 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
 505         .port_otg = true,
 506         .has_hostpc = true,
 507         .unaligned_dma_buf_supported = true,
 508         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 509         .op_mode = TEGRA_USB_OPMODE_HOST,
 510         .u_data.host = {
 511                 .vbus_gpio = -1,
 512                 .hot_plug = false,
 513                 .remote_wakeup_supported = true,
 514                 .power_off_on_suspend = true,
 515         },
 516         .u_cfg.utmi = {
 517                 .hssync_start_delay = 0,
 518                 .elastic_limit = 16,
 519                 .idle_wait_delay = 17,
 520                 .term_range_adj = 6,
 521                 .xcvr_setup = 15,
 522                 .xcvr_lsfslew = 0,
 523                 .xcvr_lsrslew = 3,
 524                 .xcvr_setup_offset = 0,
 525                 .xcvr_use_fuses = 1,
 526                 .vbus_oc_map = 0x4,
 527                 .xcvr_hsslew_lsb = 2,
 528         },
 529 };
 530
 531 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
 532         .port_otg = false,
 533         .has_hostpc = true,
 534         .unaligned_dma_buf_supported = true,
 535         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 536         .op_mode = TEGRA_USB_OPMODE_HOST,
 537         .u_data.host = {
 538                 .vbus_gpio = -1,
 539                 .hot_plug = false,
 540                 .remote_wakeup_supported = true,
 541                 .power_off_on_suspend = true,
 542         },
 543         .u_cfg.utmi = {
 544                 .hssync_start_delay = 0,
 545                 .elastic_limit = 16,
 546                 .idle_wait_delay = 17,
 547                 .term_range_adj = 6,
 548                 .xcvr_setup = 8,
 549                 .xcvr_lsfslew = 2,
 550                 .xcvr_lsrslew = 2,
 551                 .xcvr_setup_offset = 0,
 552                 .xcvr_use_fuses = 1,
 553                 .vbus_oc_map = 0x5,
 554         },
 555 };
 556
 557 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
 558         .port_otg = false,
 559         .has_hostpc = true,
 560         .unaligned_dma_buf_supported = true,
 561         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 562         .op_mode = TEGRA_USB_OPMODE_HOST,
 563         .u_data.host = {
 564                 .vbus_gpio = -1,
 565                 .hot_plug = false,
 566                 .remote_wakeup_supported = true,
 567                 .power_off_on_suspend = true,
 568         },
 569         .u_cfg.utmi = {
 570         .hssync_start_delay = 0,
 571                 .elastic_limit = 16,
 572                 .idle_wait_delay = 17,
 573                 .term_range_adj = 6,
 574                 .xcvr_setup = 8,
 575                 .xcvr_lsfslew = 2,
 576                 .xcvr_lsrslew = 2,
 577                 .xcvr_setup_offset = 0,
 578                 .xcvr_use_fuses = 1,
 579                 .vbus_oc_map = 0x5,
 580         },
 581 };
 582
 583 static struct gpio modem_gpios[] = { /* Bruce modem */
 584         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
 585         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
 586         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
 587 };
 588
 589 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
 590         .port_otg = false,
 591         .has_hostpc = true,
 592         .unaligned_dma_buf_supported = true,
 593         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 594         .op_mode = TEGRA_USB_OPMODE_HOST,
 595         .u_data.host = {
 596                 .vbus_gpio = -1,
 597                 .hot_plug = false,
 598                 .remote_wakeup_supported = true,
 599                 .power_off_on_suspend = true,
 600         },
 601 };
 602
 603 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
 604         .port_otg = false,
 605         .has_hostpc = true,
 606         .unaligned_dma_buf_supported = true,
 607         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 608         .op_mode        = TEGRA_USB_OPMODE_HOST,
 609         .u_data.host = {
 610                 .vbus_gpio = -1,
 611                 .hot_plug = false,
 612                 .remote_wakeup_supported = true,
 613                 .power_off_on_suspend = true,
 614         },
 615 };
 616
 617
 618 static struct tegra_usb_otg_data tegra_otg_pdata = {
 619         .ehci_device = &tegra_ehci1_device,
 620         .ehci_pdata = &tegra_ehci1_utmi_pdata,
 621 };
 622
 623 static void ardbeg_usb_init(void)
 624 {
 625         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 626         int modem_id = tegra_get_modem_id();
 627         struct board_info bi;
 628         tegra_get_pmu_board_info(&bi);
 629
 630         if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
 631                                         board_info.board_id == BOARD_E1784)
 632                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
 633
 634         if (board_info.board_id == BOARD_PM359 ||
 635                         board_info.board_id == BOARD_PM358 ||
 636                         board_info.board_id == BOARD_PM370 ||
 637                         board_info.board_id == BOARD_PM374 ||
 638                         board_info.board_id == BOARD_PM375 ||
 639                         board_info.board_id == BOARD_PM363) {
 640                 /* Laguna */
 641                 /* Host cable is detected through AMS PMU Interrupt */
 642                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 643                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 644                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
 645         } else {
 646                 /* Ardbeg and TN8 */
 647
 648                 /*
 649                  * TN8 supports vbus changing and it can handle
 650                  * vbus voltages larger then 5V.  Enable this.
 651                  */
 652                 if (board_info.board_id == BOARD_P1761 ||
 653                         board_info.board_id == BOARD_E1784 ||
 654                         board_info.board_id == BOARD_E1780) {
 655
 656                         /*
 657                          * Set the maximum voltage that can be supplied
 658                          * over USB vbus that the board supports if we use
 659                          * a quick charge 2 wall charger.
 660                          */
 661                         tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_9V;
 662                         tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1200;
 663
 664                         /* charger needs to be set to 2A - h/w will do 1.8A */
 665                         tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 2000;
 666                 }
 667
 668                 switch (bi.board_id) {
 669                 case BOARD_E1733:
 670                         /* Host cable is detected through PMU Interrupt */
 671                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 672                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 673                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 674                                                          "as3722-extcon";
 675                         break;
 676                 case BOARD_E1736:
 677                 case BOARD_E1769:
 678                 case BOARD_E1735:
 679                 case BOARD_E1936:
 680                 case BOARD_P1761:
 681                         /* Device cable is detected through PMU Interrupt */
 682                         tegra_udc_pdata.support_pmu_vbus = true;
 683                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
 684                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
 685                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
 686                                                          "palmas-extcon";
 687                         /* Host cable is detected through PMU Interrupt */
 688                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 689                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 690                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 691                                                          "palmas-extcon";
 692                 }
 693         }
 694
 695         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
 696                 tegra_otg_pdata.is_xhci = false;
 697                 tegra_udc_pdata.u_data.dev.is_xhci = false;
 698         } else {
 699                 tegra_otg_pdata.is_xhci = true;
 700                 tegra_udc_pdata.u_data.dev.is_xhci = true;
 701         }
 702         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
 703         platform_device_register(&tegra_otg_device);
 704         /* Setup the udc platform data */
 705         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
 706
 707         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 708                 if (!modem_id) {
 709                         if ((bi.board_id != BOARD_P1761) &&
 710                             (bi.board_id != BOARD_E1922) &&
 711                             (bi.board_id != BOARD_E1784)) {
 712                                 tegra_ehci2_device.dev.platform_data =
 713                                         &tegra_ehci2_utmi_pdata;
 714                                 platform_device_register(&tegra_ehci2_device);
 715                         }
 716                 }
 717         }
 718
 719         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 720                 if ((bi.board_id != BOARD_P1761) &&
 721                     (bi.board_id != BOARD_E1922) &&
 722                     (bi.board_id != BOARD_E1784)) {
 723                         tegra_ehci3_device.dev.platform_data =
 724                                 &tegra_ehci3_utmi_pdata;
 725                         platform_device_register(&tegra_ehci3_device);
 726                 }
 727         }
 728
 729 }
 730
 731 static struct tegra_xusb_platform_data xusb_pdata = {
 732         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
 733                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
 734 };
 735
 736 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 737 static void ardbeg_xusb_init(void)
 738 {
 739         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 740
 741         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
 742
 743         if (board_info.board_id == BOARD_PM359 ||
 744                         board_info.board_id == BOARD_PM358 ||
 745                         board_info.board_id == BOARD_PM374 ||
 746                         board_info.board_id == BOARD_PM375 ||
 747                         board_info.board_id == BOARD_PM370 ||
 748                         board_info.board_id == BOARD_PM363) {
 749                 if (board_info.board_id == BOARD_PM374 ||
 750                         board_info.board_id == BOARD_PM370)
 751                         pr_info("Norrin. 0x%x\n", board_info.board_id);
 752                 else
 753                         pr_info("Laguna. 0x%x\n", board_info.board_id);
 754
 755                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 756                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 757                                 TEGRA_XUSB_SS_P0);
 758
 759                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 760                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 761                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
 762
 763                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 764         } else {
 765                 /* Ardbeg */
 766                 if (board_info.board_id == BOARD_E1781) {
 767                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
 768                         /* Shield ERS-S */
 769                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 770                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 771
 772                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 773                                 xusb_pdata.portmap &= ~(
 774                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
 775                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 776                 } else {
 777                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
 778                         /* Shield ERS */
 779                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 780                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 781                                         TEGRA_XUSB_SS_P0);
 782
 783                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 784                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 785                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 786                 }
 787                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 788         }
 789
 790         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
 791                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
 792
 793         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
 794                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
 795 }
 796 #endif
 797
 798 static int baseband_init(void)
 799 {
 800         int ret;
 801
 802         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
 803         if (ret) {
 804                 pr_warn("%s:gpio request failed\n", __func__);
 805                 return ret;
 806         }
 807
 808         /* enable pull-down for MDM_COLD_BOOT */
 809         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
 810                                     TEGRA_PUPD_PULL_DOWN);
 811
 812         /* Release modem reset to start boot */
 813         gpio_set_value(MDM_RST, 1);
 814
 815         /* export GPIO for user space access through sysfs */
 816         gpio_export(MDM_RST, false);
 817         gpio_export(MDM_SAR0, false);
 818
 819         return 0;
 820 }
 821
 822 static const struct tegra_modem_operations baseband_operations = {
 823         .init = baseband_init,
 824 };
 825
 826 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
 827         .ops = &baseband_operations,
 828         .regulator_name = "vdd_wwan_mdm",
 829         .wake_gpio = -1,
 830         .boot_gpio = MDM_COLDBOOT,
 831         .boot_irq_flags = IRQF_TRIGGER_RISING |
 832                                     IRQF_TRIGGER_FALLING |
 833                                     IRQF_ONESHOT,
 834         .autosuspend_delay = 2000,
 835         .short_autosuspend_delay = 50,
 836         .tegra_ehci_device = &tegra_ehci2_device,
 837         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
 838         .mdm_power_report_gpio = MDM_POWER_REPORT,
 839         .mdm_power_irq_flags = IRQF_TRIGGER_RISING |
 840                                 IRQF_TRIGGER_FALLING |
 841                                 IRQF_ONESHOT,
 842 };
 843
 844 static struct platform_device icera_bruce_device = {
 845         .name = "tegra_usb_modem_power",
 846         .id = -1,
 847         .dev = {
 848                 .platform_data = &baseband_pdata,
 849         },
 850 };
 851
 852 static void ardbeg_modem_init(void)
 853 {
 854         int modem_id = tegra_get_modem_id();
 855         struct board_info board_info;
 856         struct board_info pmu_board_info;
 857         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 858
 859         tegra_get_board_info(&board_info);
 860         tegra_get_pmu_board_info(&pmu_board_info);
 861         pr_info("%s: modem_id = %d\n", __func__, modem_id);
 862
 863         switch (modem_id) {
 864         case TEGRA_BB_BRUCE:
 865                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 866                         /* Set specific USB wake source for Ardbeg */
 867                         if (board_info.board_id == BOARD_E1780)
 868                                 tegra_set_wake_source(42, INT_USB2);
 869                         if (pmu_board_info.board_id == BOARD_E1736 ||
 870                                 pmu_board_info.board_id == BOARD_E1769 ||
 871                                 pmu_board_info.board_id == BOARD_E1936)
 872                                 baseband_pdata.regulator_name = NULL;
 873                         platform_device_register(&icera_bruce_device);
 874                 }
 875                 break;
 876         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
 877                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 878                         tegra_ehci2_device.dev.platform_data =
 879                                 &tegra_ehci2_hsic_smsc_hub_pdata;
 880                         /* Set specific USB wake source for Ardbeg */
 881                         if (board_info.board_id == BOARD_E1780)
 882                                 tegra_set_wake_source(42, INT_USB2);
 883                         platform_device_register(&tegra_ehci2_device);
 884                 } else
 885                         xusb_pdata.pretend_connect_0 = true;
 886                 break;
 887         default:
 888                 return;
 889         }
 890 }
 891
 892 #ifdef CONFIG_USE_OF
 893 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
 894         T124_SPI_OF_DEV_AUXDATA,
 895         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
 896                                 NULL),
 897         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
 898         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
 899                 NULL),
 900         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
 901                 "gk20a.0", NULL),
 902 #ifdef CONFIG_ARCH_TEGRA_VIC
 903         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
 904 #endif
 905         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
 906                 NULL),
 907         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
 908         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
 909         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
 910         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
 911         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
 912                                 NULL),
 913         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
 914                                 NULL),
 915         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
 916                                 NULL),
 917         T124_I2C_OF_DEV_AUXDATA,
 918         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
 919                                 &xusb_pdata),
 920         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
 921                 NULL),
 922         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
 923                 NULL),
 924         OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
 925                                 NULL),
 926         OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
 927         OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
 928                 NULL),
 929         OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
 930                 NULL),
 931         OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
 932                 NULL),
 933         OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
 934                                 NULL),
 935         OF_DEV_AUXDATA("nvidia,tegra114-ahci-sata", 0x70027000, "tegra-sata.0",
 936                 NULL),
 937         {}
 938 };
 939 #endif
 940
 941 struct maxim_sti_pdata maxim_sti_pdata = {
 942         .touch_fusion         = "/vendor/bin/touch_fusion",
 943         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 944         .fw_name              = "maxim_fp35.bin",
 945         .nl_family            = TF_FAMILY_NAME,
 946         .nl_mc_groups         = 5,
 947         .chip_access_method   = 2,
 948         .default_reset_state  = 0,
 949         .tx_buf_size          = 4100,
 950         .rx_buf_size          = 4100,
 951         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 952         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 953 };
 954
 955 struct maxim_sti_pdata maxim_sti_pdata_rd = {
 956         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
 957         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 958         .fw_name              = "maxim_fp35.bin",
 959         .nl_family            = TF_FAMILY_NAME,
 960         .nl_mc_groups         = 5,
 961         .chip_access_method   = 2,
 962         .default_reset_state  = 0,
 963         .tx_buf_size          = 4100,
 964         .rx_buf_size          = 4100,
 965         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 966         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 967 };
 968
 969 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
 970         .rx_clk_tap_delay = 0,
 971         .is_hw_based_cs = true,
 972         .tx_clk_tap_delay = 0,
 973 };
 974
 975 struct spi_board_info maxim_sti_spi_board = {
 976         .modalias = MAXIM_STI_NAME,
 977         .bus_num = TOUCH_SPI_ID,
 978         .chip_select = TOUCH_SPI_CS,
 979         .max_speed_hz = 12 * 1000 * 1000,
 980         .mode = SPI_MODE_0,
 981         .platform_data = &maxim_sti_pdata,
 982         .controller_data = &maxim_dev_cdata,
 983 };
 984
 985 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
 986         /* name         parent          rate            enabled */
 987         { "extern2",    "pll_p",        41000000,       false},
 988         { "clk_out_2",  "extern2",      40800000,       false},
 989         { NULL,         NULL,           0,              0},
 990 };
 991
 992 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
 993         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 994         .config = 0,
 995         .platform_id = RM_PLATFORM_A010,
 996         .name_of_clock = "clk_out_2",
 997         .name_of_clock_con = "extern2",
 998 };
 999
1000 static struct rm_spi_ts_platform_data rm31080ts_tn8_data = {
1001         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1002         .config = 0,
1003         .platform_id = RM_PLATFORM_T008,
1004         .name_of_clock = "clk_out_2",
1005         .name_of_clock_con = "extern2",
1006 };
1007
1008 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
1009         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1010         .config = 0,
1011         .platform_id = RM_PLATFORM_P140,
1012         .name_of_clock = "clk_out_2",
1013         .name_of_clock_con = "extern2",
1014 };
1015
1016 struct rm_spi_ts_platform_data rm31080ts_t132loki_data = {
1017         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1018         .config = 0,
1019         .platform_id = RM_PLATFORM_L005,
1020         .name_of_clock = "clk_out_2",
1021         .name_of_clock_con = "extern2",
1022 };
1023
1024 struct rm_spi_ts_platform_data rm31080ts_t132loki_data_jdi_5 = {
1025         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1026         .config = 0,
1027         .platform_id = RM_PLATFORM_L005,
1028         .name_of_clock = "clk_out_2",
1029         .name_of_clock_con = "extern2",
1030         .gpio_sensor_select0 = false,
1031         .gpio_sensor_select1 = true,
1032 };
1033 static struct tegra_spi_device_controller_data dev_cdata = {
1034         .rx_clk_tap_delay = 0,
1035         .tx_clk_tap_delay = 16,
1036 };
1037
1038 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1039         {
1040                 .modalias = "rm_ts_spidev",
1041                 .bus_num = TOUCH_SPI_ID,
1042                 .chip_select = TOUCH_SPI_CS,
1043                 .max_speed_hz = 12 * 1000 * 1000,
1044                 .mode = SPI_MODE_0,
1045                 .controller_data = &dev_cdata,
1046                 .platform_data = &rm31080ts_ardbeg_data,
1047         },
1048 };
1049
1050 static struct spi_board_info rm31080a_tn8_spi_board[1] = {
1051         {
1052                 .modalias = "rm_ts_spidev",
1053                 .bus_num = TOUCH_SPI_ID,
1054                 .chip_select = TOUCH_SPI_CS,
1055                 .max_speed_hz = 12 * 1000 * 1000,
1056                 .mode = SPI_MODE_0,
1057                 .controller_data = &dev_cdata,
1058                 .platform_data = &rm31080ts_tn8_data,
1059         },
1060 };
1061
1062 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
1063         {
1064                 .modalias = "rm_ts_spidev",
1065                 .bus_num = NORRIN_TOUCH_SPI_ID,
1066                 .chip_select = NORRIN_TOUCH_SPI_CS,
1067                 .max_speed_hz = 12 * 1000 * 1000,
1068                 .mode = SPI_MODE_0,
1069                 .controller_data = &dev_cdata,
1070                 .platform_data = &rm31080ts_norrin_data,
1071         },
1072 };
1073
1074 static int __init ardbeg_touch_init(void)
1075 {
1076         tegra_get_board_info(&board_info);
1077
1078         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1079                 pr_info("%s init maxim touch\n", __func__);
1080 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1081         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1082                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1083                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1084                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1085 #endif
1086         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1087                 pr_info("%s init raydium touch\n", __func__);
1088                 tegra_clk_init_from_table(touch_clk_init_table);
1089                 if (board_info.board_id == BOARD_PM374) {
1090                         rm31080a_norrin_spi_board[0].irq =
1091                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1092                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1093                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1094                                         &rm31080ts_norrin_data,
1095                                         &rm31080a_norrin_spi_board[0],
1096                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1097                 } else if ((board_info.board_id == BOARD_P2530) ||
1098                         (board_info.board_id == BOARD_E2548)) {
1099                         if (board_info.sku == BOARD_SKU_FOSTER)
1100                                 return 0;
1101                         if (tegra_get_touch_panel_id() == TOUCHPANEL_LOKI_JDI5)
1102                                 rm31080a_ardbeg_spi_board[0].platform_data =
1103                                         &rm31080ts_t132loki_data_jdi_5;
1104                         else
1105                                 rm31080a_ardbeg_spi_board[0].platform_data =
1106                                         &rm31080ts_t132loki_data;
1107                         if (board_info.fab >= 0xa3) {
1108                                 rm31080ts_t132loki_data.name_of_clock = NULL;
1109                                 rm31080ts_t132loki_data.name_of_clock_con = NULL;
1110                         } else
1111                                 tegra_clk_init_from_table(touch_clk_init_table);
1112                                 rm31080a_ardbeg_spi_board[0].irq =
1113                                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1114                                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1115                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1116                                         &rm31080ts_t132loki_data,
1117                                         &rm31080a_ardbeg_spi_board[0],
1118                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1119                 } else if (board_info.board_id == BOARD_P1761) {
1120                         rm31080a_ardbeg_spi_board[0].irq =
1121                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1122                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1123                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1124                                 &rm31080ts_tn8_data,
1125                                 &rm31080a_tn8_spi_board[0],
1126                                 ARRAY_SIZE(rm31080a_tn8_spi_board));
1127                 } else {
1128                         rm31080a_ardbeg_spi_board[0].irq =
1129                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1130                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1131                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1132                                         &rm31080ts_ardbeg_data,
1133                                         &rm31080a_ardbeg_spi_board[0],
1134                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1135                 }
1136         }
1137         return 0;
1138 }
1139
1140 static void __init ardbeg_sysedp_init(void)
1141 {
1142         struct board_info bi;
1143
1144         tegra_get_board_info(&bi);
1145
1146         switch (bi.board_id) {
1147         case BOARD_E1780:
1148                 if (bi.sku == 1100) {
1149                         tn8_new_sysedp_init();
1150                 }
1151                 else
1152                         shield_new_sysedp_init();
1153                 break;
1154         case BOARD_E1971:
1155         case BOARD_E1922:
1156         case BOARD_E1784:
1157         case BOARD_P1761:
1158                 tn8_new_sysedp_init();
1159                 break;
1160         case BOARD_PM358:
1161         case BOARD_PM359:
1162         case BOARD_PM375:
1163         default:
1164                 break;
1165         }
1166 }
1167
1168 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1169 {
1170         struct board_info bi;
1171
1172         tegra_get_board_info(&bi);
1173
1174         switch (bi.board_id) {
1175         case BOARD_E1780:
1176                 if (bi.sku == 1100)
1177                         tn8_sysedp_dynamic_capping_init();
1178                 else
1179                         shield_sysedp_dynamic_capping_init();
1180                 break;
1181         case BOARD_E1971:
1182         case BOARD_E1922:
1183         case BOARD_E1784:
1184         case BOARD_P1761:
1185                 tn8_sysedp_dynamic_capping_init();
1186                 break;
1187         case BOARD_PM358:
1188         case BOARD_PM359:
1189         case BOARD_PM375:
1190         default:
1191                 break;
1192         }
1193 }
1194
1195 static void __init ardbeg_sysedp_batmon_init(void)
1196 {
1197         struct board_info bi;
1198
1199         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1200                 return;
1201
1202         tegra_get_board_info(&bi);
1203
1204         switch (bi.board_id) {
1205         case BOARD_E1780:
1206                 if (bi.sku != 1100)
1207                         shield_sysedp_batmon_init();
1208                 break;
1209         case BOARD_PM358:
1210         case BOARD_PM359:
1211         case BOARD_PM375:
1212         default:
1213                 break;
1214         }
1215 }
1216
1217
1218
1219 static void __init edp_init(void)
1220 {
1221         struct board_info bi;
1222
1223         tegra_get_board_info(&bi);
1224
1225         switch (bi.board_id) {
1226         case BOARD_E1780:
1227                 if (bi.sku == 1100)
1228                         tn8_edp_init();
1229                 else
1230                         ardbeg_edp_init();
1231                 break;
1232         case BOARD_P1761:
1233                         tn8_edp_init();
1234                         break;
1235         case BOARD_PM358:
1236         case BOARD_PM359:
1237         case BOARD_PM375:
1238                         laguna_edp_init();
1239                         break;
1240         case BOARD_P2530:
1241         case BOARD_E2548:
1242                         loki_edp_init();
1243                         break;
1244         default:
1245                         ardbeg_edp_init();
1246                         break;
1247         }
1248 }
1249
1250 static void __init tegra_ardbeg_early_init(void)
1251 {
1252         ardbeg_sysedp_init();
1253         tegra_clk_init_from_table(ardbeg_clk_init_table);
1254         tegra_clk_verify_parents();
1255         if (of_machine_is_compatible("nvidia,laguna"))
1256                 tegra_soc_device_init("laguna");
1257         else if (of_machine_is_compatible("nvidia,tn8"))
1258                 tegra_soc_device_init("tn8");
1259         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1260                 tegra_soc_device_init("ardbeg_sata");
1261         else if (of_machine_is_compatible("nvidia,norrin"))
1262                 tegra_soc_device_init("norrin");
1263         else if (of_machine_is_compatible("nvidia,bowmore"))
1264                 tegra_soc_device_init("bowmore");
1265         else if (of_machine_is_compatible("nvidia,t132loki"))
1266                 tegra_soc_device_init("t132loki");
1267         else
1268                 tegra_soc_device_init("ardbeg");
1269 }
1270
1271 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1272         .dma_req_selector = 11,
1273 };
1274
1275 static void __init ardbeg_dtv_init(void)
1276 {
1277         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1278         platform_device_register(&tegra_dtv_device);
1279 }
1280
1281 static struct tegra_io_dpd pexbias_io = {
1282         .name                   = "PEX_BIAS",
1283         .io_dpd_reg_index       = 0,
1284         .io_dpd_bit             = 4,
1285 };
1286 static struct tegra_io_dpd pexclk1_io = {
1287         .name                   = "PEX_CLK1",
1288         .io_dpd_reg_index       = 0,
1289         .io_dpd_bit             = 5,
1290 };
1291 static struct tegra_io_dpd pexclk2_io = {
1292         .name                   = "PEX_CLK2",
1293         .io_dpd_reg_index       = 0,
1294         .io_dpd_bit             = 6,
1295 };
1296
1297 static void __init tegra_ardbeg_late_init(void)
1298 {
1299         struct board_info board_info;
1300         tegra_get_board_info(&board_info);
1301         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1302                 board_info.board_id, board_info.sku,
1303                 board_info.fab, board_info.major_revision,
1304                 board_info.minor_revision);
1305
1306         if (board_info.board_id == BOARD_E2548 ||
1307                         board_info.board_id == BOARD_P2530)
1308                 loki_pinmux_init();
1309 #ifndef CONFIG_MACH_EXUMA
1310         ardbeg_display_init();
1311 #endif
1312         ardbeg_uart_init();
1313         ardbeg_usb_init();
1314         ardbeg_modem_init();
1315 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
1316         ardbeg_xusb_init();
1317 #endif
1318         ardbeg_i2c_init();
1319         ardbeg_audio_init();
1320         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1321         if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
1322                 platform_device_register(&norrin_audio_device_max98090);
1323         else if (board_info.board_id != BOARD_PM359)
1324                 platform_device_register(&ardbeg_audio_device_rt5639);
1325         tegra_io_dpd_init();
1326         if (board_info.board_id == BOARD_E2548 ||
1327                         board_info.board_id == BOARD_P2530)
1328                 loki_sdhci_init();
1329         else
1330                 ardbeg_sdhci_init();
1331         if (board_info.board_id == BOARD_PM359 ||
1332                         board_info.board_id == BOARD_PM358 ||
1333                         board_info.board_id == BOARD_PM370 ||
1334                         board_info.board_id == BOARD_PM363)
1335                 laguna_regulator_init();
1336         else if (board_info.board_id == BOARD_PM374)
1337                 norrin_regulator_init();
1338         else if (board_info.board_id == BOARD_E2548 ||
1339                         board_info.board_id == BOARD_P2530)
1340                 loki_regulator_init();
1341         else
1342                 ardbeg_regulator_init();
1343         ardbeg_dtv_init();
1344         ardbeg_suspend_init();
1345
1346         if ((board_info.board_id == BOARD_PM374) ||
1347                 (board_info.board_id == BOARD_E1971) ||
1348                 (board_info.board_id == BOARD_E1973))
1349                 norrin_emc_init();
1350         else if (board_info.board_id == BOARD_E2548 ||
1351                         board_info.board_id == BOARD_P2530)
1352                 loki_emc_init();
1353         else
1354                 ardbeg_emc_init();
1355
1356         edp_init();
1357         isomgr_init();
1358         ardbeg_touch_init();
1359         if (board_info.board_id == BOARD_E2548 ||
1360                         board_info.board_id == BOARD_P2530)
1361                 loki_panel_init();
1362         else
1363                 ardbeg_panel_init();
1364
1365                 /* put PEX pads into DPD mode to save additional power */
1366                 tegra_io_dpd_enable(&pexbias_io);
1367                 tegra_io_dpd_enable(&pexclk1_io);
1368                 tegra_io_dpd_enable(&pexclk2_io);
1369
1370         if (board_info.board_id == BOARD_E2548 ||
1371                         board_info.board_id == BOARD_P2530)
1372                 loki_kbc_init();
1373
1374 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1375         tegra_wdt_recovery_init();
1376 #endif
1377
1378
1379         if (board_info.board_id == BOARD_PM374 ||
1380                 board_info.board_id == BOARD_PM359 ||
1381                 board_info.board_id == BOARD_PM358 ||
1382                 board_info.board_id == BOARD_PM370 ||
1383                 board_info.board_id == BOARD_PM375 ||
1384                 board_info.board_id == BOARD_PM363) {
1385                 ardbeg_sensors_init();
1386                 norrin_soctherm_init();
1387         }       else if (board_info.board_id == BOARD_E2548 ||
1388                         board_info.board_id == BOARD_P2530) {
1389                 loki_sensors_init();
1390                 loki_fan_init();
1391                 loki_soctherm_init();
1392         }       else {
1393                 ardbeg_sensors_init();
1394                 ardbeg_soctherm_init();
1395         }
1396
1397         ardbeg_setup_bluedroid_pm();
1398         ardbeg_sysedp_dynamic_capping_init();
1399         ardbeg_sysedp_batmon_init();
1400 }
1401
1402 static void __init tegra_ardbeg_init_early(void)
1403 {
1404         tegra_get_board_info(&board_info);
1405         if (board_info.board_id == BOARD_E2548 ||
1406                         board_info.board_id == BOARD_P2530)
1407                 loki_rail_alignment_init();
1408         else
1409                 ardbeg_rail_alignment_init();
1410         tegra12x_init_early();
1411 }
1412
1413 static void __init tegra_ardbeg_dt_init(void)
1414 {
1415         tegra_get_board_info(&board_info);
1416         tegra_get_display_board_info(&display_board_info);
1417
1418         tegra_ardbeg_early_init();
1419 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1420         carveout_linear_set(&tegra_generic_cma_dev);
1421         carveout_linear_set(&tegra_vpr_cma_dev);
1422 #endif
1423 #ifdef CONFIG_USE_OF
1424         ardbeg_camera_auxdata(ardbeg_auxdata_lookup);
1425         of_platform_populate(NULL,
1426                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1427                 &platform_bus);
1428 #endif
1429
1430         tegra_ardbeg_late_init();
1431 }
1432
1433 static void __init tegra_ardbeg_reserve(void)
1434 {
1435 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1436                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1437         /* 1920*1200*4*2 = 18432000 bytes */
1438         tegra_reserve4(0, SZ_16M + SZ_2M, SZ_16M, 186 * SZ_1M);
1439 #else
1440         tegra_reserve4(SZ_1G, SZ_16M + SZ_2M, SZ_4M, 186 * SZ_1M);
1441 #endif
1442 }
1443
1444 static const char * const ardbeg_dt_board_compat[] = {
1445         "nvidia,ardbeg",
1446         NULL
1447 };
1448
1449 static const char * const laguna_dt_board_compat[] = {
1450         "nvidia,laguna",
1451         NULL
1452 };
1453
1454 static const char * const tn8_dt_board_compat[] = {
1455         "nvidia,tn8",
1456         NULL
1457 };
1458
1459 static const char * const ardbeg_sata_dt_board_compat[] = {
1460         "nvidia,ardbeg_sata",
1461         NULL
1462 };
1463
1464 static const char * const norrin_dt_board_compat[] = {
1465         "nvidia,norrin",
1466         NULL
1467 };
1468
1469 static const char * const bowmore_dt_board_compat[] = {
1470         "nvidia,bowmore",
1471         NULL
1472 };
1473
1474 static const char * const loki_dt_board_compat[] = {
1475         "nvidia,t132loki",
1476         NULL
1477 };
1478
1479 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1480 DT_MACHINE_START(LOKI, "t132loki")
1481         .atag_offset    = 0x100,
1482         .smp            = smp_ops(tegra_smp_ops),
1483         .map_io         = tegra_map_common_io,
1484         .reserve        = tegra_ardbeg_reserve,
1485         .init_early     = tegra_ardbeg_init_early,
1486         .init_irq       = irqchip_init,
1487         .init_time      = clocksource_of_init,
1488         .init_machine   = tegra_ardbeg_dt_init,
1489         .restart        = tegra_assert_system_reset,
1490         .dt_compat      = loki_dt_board_compat,
1491         .init_late      = tegra_init_late
1492 MACHINE_END
1493 #endif
1494
1495 DT_MACHINE_START(LAGUNA, "laguna")
1496         .atag_offset    = 0x100,
1497         .smp            = smp_ops(tegra_smp_ops),
1498         .map_io         = tegra_map_common_io,
1499         .reserve        = tegra_ardbeg_reserve,
1500         .init_early     = tegra_ardbeg_init_early,
1501         .init_irq       = irqchip_init,
1502         .init_time      = clocksource_of_init,
1503         .init_machine   = tegra_ardbeg_dt_init,
1504         .restart        = tegra_assert_system_reset,
1505         .dt_compat      = laguna_dt_board_compat,
1506         .init_late      = tegra_init_late
1507 MACHINE_END
1508
1509 DT_MACHINE_START(TN8, "tn8")
1510         .atag_offset    = 0x100,
1511         .smp            = smp_ops(tegra_smp_ops),
1512         .map_io         = tegra_map_common_io,
1513         .reserve        = tegra_ardbeg_reserve,
1514         .init_early     = tegra_ardbeg_init_early,
1515         .init_irq       = irqchip_init,
1516         .init_time      = clocksource_of_init,
1517         .init_machine   = tegra_ardbeg_dt_init,
1518         .restart        = tegra_assert_system_reset,
1519         .dt_compat      = tn8_dt_board_compat,
1520         .init_late      = tegra_init_late
1521 MACHINE_END
1522
1523 DT_MACHINE_START(NORRIN, "norrin")
1524         .atag_offset    = 0x100,
1525         .smp            = smp_ops(tegra_smp_ops),
1526         .map_io         = tegra_map_common_io,
1527         .reserve        = tegra_ardbeg_reserve,
1528         .init_early     = tegra_ardbeg_init_early,
1529         .init_irq       = irqchip_init,
1530         .init_time      = clocksource_of_init,
1531         .init_machine   = tegra_ardbeg_dt_init,
1532         .restart        = tegra_assert_system_reset,
1533         .dt_compat      = norrin_dt_board_compat,
1534         .init_late      = tegra_init_late
1535 MACHINE_END
1536
1537 DT_MACHINE_START(BOWMORE, "bowmore")
1538         .atag_offset    = 0x100,
1539         .smp            = smp_ops(tegra_smp_ops),
1540         .map_io         = tegra_map_common_io,
1541         .reserve        = tegra_ardbeg_reserve,
1542         .init_early     = tegra_ardbeg_init_early,
1543         .init_irq       = irqchip_init,
1544         .init_time      = clocksource_of_init,
1545         .init_machine   = tegra_ardbeg_dt_init,
1546         .restart        = tegra_assert_system_reset,
1547         .dt_compat      = bowmore_dt_board_compat,
1548         .init_late      = tegra_init_late
1549 MACHINE_END
1550
1551 DT_MACHINE_START(ARDBEG, "ardbeg")
1552         .atag_offset    = 0x100,
1553         .smp            = smp_ops(tegra_smp_ops),
1554         .map_io         = tegra_map_common_io,
1555         .reserve        = tegra_ardbeg_reserve,
1556         .init_early     = tegra_ardbeg_init_early,
1557         .init_irq       = irqchip_init,
1558         .init_time      = clocksource_of_init,
1559         .init_machine   = tegra_ardbeg_dt_init,
1560         .restart        = tegra_assert_system_reset,
1561         .dt_compat      = ardbeg_dt_board_compat,
1562         .init_late      = tegra_init_late
1563 MACHINE_END
1564
1565 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1566         .atag_offset    = 0x100,
1567         .smp            = smp_ops(tegra_smp_ops),
1568         .map_io         = tegra_map_common_io,
1569         .reserve        = tegra_ardbeg_reserve,
1570         .init_early     = tegra_ardbeg_init_early,
1571         .init_irq       = irqchip_init,
1572         .init_time      = clocksource_of_init,
1573         .init_machine   = tegra_ardbeg_dt_init,
1574         .restart        = tegra_assert_system_reset,
1575         .dt_compat      = ardbeg_sata_dt_board_compat,
1576         .init_late      = tegra_init_late
1577
1578 MACHINE_END