2 * arch/ppc/kernel/head_fsl_booke.S
4 * Kernel execution entry point code.
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 * Copyright 2004 Freescale Semiconductor, Inc
27 * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the
31 * Free Software Foundation; either version 2 of the License, or (at your
32 * option) any later version.
35 #include <linux/config.h>
36 #include <linux/threads.h>
37 #include <asm/processor.h>
40 #include <asm/pgtable.h>
41 #include <asm/cputable.h>
42 #include <asm/thread_info.h>
43 #include <asm/ppc_asm.h>
44 #include <asm/offsets.h>
45 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
62 * Reserve a word at a fixed location to store the address
67 * Save parameters we are passed
74 li r24,0 /* CPU number */
76 /* We try to not make any assumptions about how the boot loader
77 * setup or used the TLBs. We invalidate all mappings from the
78 * boot loader and load a single entry in TLB1[0] to map the
79 * first 16M of kernel memory. Any boot info passed from the
80 * bootloader needs to live in this first 16M.
82 * Requirement on bootloader:
83 * - The page we're executing in needs to reside in TLB1 and
84 * have IPROT=1. If not an invalidate broadcast could
85 * evict the entry we're currently executing in.
87 * r3 = Index of TLB1 were executing in
88 * r4 = Current MSR[IS]
89 * r5 = Index of TLB1 temp mapping
91 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
95 /* 1. Find the index of the entry we're executing in */
96 bl invstr /* Find our address */
97 invstr: mflr r6 /* Make it accessible */
99 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
104 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
106 andis. r7,r7,MAS1_VALID@h
112 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
114 andis. r7,r7,MAS1_VALID@h
120 tlbsx 0,r6 /* Fall through, we had to match */
123 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
125 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
126 oris r7,r7,MAS1_IPROT@h
130 /* 2. Invalidate all entries except the entry we're executing in */
131 mfspr r9,SPRN_TLB1CFG
133 li r6,0 /* Set Entry counter to 0 */
134 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
135 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
139 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
141 beq skpinv /* Dont update the current execution TLB */
145 skpinv: addi r6,r6,1 /* Increment */
146 cmpw r6,r9 /* Are we done? */
147 bne 1b /* If not, repeat */
149 /* Invalidate TLB0 */
155 /* Invalidate TLB1 */
163 /* 3. Setup a temp mapping and jump to it */
164 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
166 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
167 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
171 /* Just modify the entry ID and EPN for the temp mapping */
172 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
173 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
175 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
177 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
178 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
181 li r7,0 /* temp EPN = 0 */
187 slwi r6,r6,5 /* setup new context with other address space */
188 bl 1f /* Find our address */
196 /* 4. Clear out PIDs & Search info */
203 /* 5. Invalidate mapping we started in */
204 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
205 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
211 /* Invalidate TLB1 */
219 /* 6. Setup KERNELBASE mapping in TLB1[0] */
220 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
222 lis r6,(MAS1_VALID|MAS1_IPROT)@h
223 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
227 ori r6,r6,KERNELBASE@l
230 li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
234 /* 7. Jump to KERNELBASE mapping */
236 bl 1f /* Find our address */
242 rfi /* start execution out of TLB1[0] entry */
244 /* 8. Clear out the temp mapping */
245 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
246 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
251 /* Invalidate TLB1 */
259 /* Establish the interrupt vector offsets */
260 SET_IVOR(0, CriticalInput);
261 SET_IVOR(1, MachineCheck);
262 SET_IVOR(2, DataStorage);
263 SET_IVOR(3, InstructionStorage);
264 SET_IVOR(4, ExternalInput);
265 SET_IVOR(5, Alignment);
266 SET_IVOR(6, Program);
267 SET_IVOR(7, FloatingPointUnavailable);
268 SET_IVOR(8, SystemCall);
269 SET_IVOR(9, AuxillaryProcessorUnavailable);
270 SET_IVOR(10, Decrementer);
271 SET_IVOR(11, FixedIntervalTimer);
272 SET_IVOR(12, WatchdogTimer);
273 SET_IVOR(13, DataTLBError);
274 SET_IVOR(14, InstructionTLBError);
276 SET_IVOR(32, SPEUnavailable);
277 SET_IVOR(33, SPEFloatingPointData);
278 SET_IVOR(34, SPEFloatingPointRound);
279 SET_IVOR(35, PerformanceMonitor);
281 /* Establish the interrupt vector base */
282 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
285 /* Setup the defaults for TLB entries */
286 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
292 oris r2,r2,HID0_DOZE@h
297 * This is where the main kernel code starts.
302 ori r2,r2,init_task@l
304 /* ptr to current thread */
305 addi r4,r2,THREAD /* init task's THREAD */
309 lis r1,init_thread_union@h
310 ori r1,r1,init_thread_union@l
312 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
316 mfspr r3,SPRN_TLB1CFG
318 lis r4,num_tlbcam_entries@ha
319 stw r3,num_tlbcam_entries@l(r4)
321 * Decide what sort of machine this is and initialize the MMU.
331 /* Setup PTE pointers for the Abatron bdiGDB */
332 lis r6, swapper_pg_dir@h
333 ori r6, r6, swapper_pg_dir@l
334 lis r5, abatron_pteptrs@h
335 ori r5, r5, abatron_pteptrs@l
337 ori r4, r4, KERNELBASE@l
338 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
342 lis r4,start_kernel@h
343 ori r4,r4,start_kernel@l
345 ori r3,r3,MSR_KERNEL@l
348 rfi /* change context and jump to start_kernel */
351 * Interrupt vector entry code
353 * The Book E MMUs are always on so we don't need to handle
354 * interrupts in real mode as with previous PPC processors. In
355 * this case we handle interrupts in the kernel virtual address
358 * Interrupt vectors are dynamically placed relative to the
359 * interrupt prefix as determined by the address of interrupt_base.
360 * The interrupt vectors offsets are programmed using the labels
361 * for each interrupt vector entry.
363 * Interrupt vectors must be aligned on a 16 byte boundary.
364 * We align on a 32 byte cache line boundary for good measure.
368 /* Critical Input Interrupt */
369 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
371 /* Machine Check Interrupt */
372 MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
374 /* Data Storage Interrupt */
375 START_EXCEPTION(DataStorage)
376 mtspr SPRN_SPRG0, r10 /* Save some working registers */
377 mtspr SPRN_SPRG1, r11
378 mtspr SPRN_SPRG4W, r12
379 mtspr SPRN_SPRG5W, r13
381 mtspr SPRN_SPRG7W, r11
384 * Check if it was a store fault, if not then bail
385 * because a user tried to access a kernel or
386 * read-protected page. Otherwise, get the
387 * offending address and handle it.
390 andis. r10, r10, ESR_ST@h
393 mfspr r10, SPRN_DEAR /* Get faulting address */
395 /* If we are faulting a kernel address, we have to use the
396 * kernel page tables.
399 ori r11, r11, TASK_SIZE@l
403 /* Get the PGD for the current thread */
408 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
409 lwz r11, 0(r11) /* Get L1 entry */
410 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
411 beq 2f /* Bail if no table */
413 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
414 lwz r11, 0(r12) /* Get Linux PTE */
416 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
417 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
418 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
419 bne 2f /* Bail if not */
421 /* Update 'changed'. */
422 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
423 stw r11, 0(r12) /* Update Linux page table */
425 /* MAS2 not updated as the entry does exist in the tlb, this
426 fault taken to detect state transition (eg: COW -> DIRTY)
429 ori r12, r12, _PAGE_HWEXEC | MAS3_RPN@l
431 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
432 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
434 /* update search PID in MAS6, AS = 0 */
439 /* find the TLB index that caused the fault. It has to be here. */
445 /* Done...restore registers and get out of here. */
446 mfspr r11, SPRN_SPRG7R
448 mfspr r13, SPRN_SPRG5R
449 mfspr r12, SPRN_SPRG4R
450 mfspr r11, SPRN_SPRG1
451 mfspr r10, SPRN_SPRG0
452 rfi /* Force context change */
456 * The bailout. Restore registers to pre-exception conditions
457 * and call the heavyweights to help us out.
459 mfspr r11, SPRN_SPRG7R
461 mfspr r13, SPRN_SPRG5R
462 mfspr r12, SPRN_SPRG4R
463 mfspr r11, SPRN_SPRG1
464 mfspr r10, SPRN_SPRG0
467 /* Instruction Storage Interrupt */
468 INSTRUCTION_STORAGE_EXCEPTION
470 /* External Input Interrupt */
471 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
473 /* Alignment Interrupt */
476 /* Program Interrupt */
479 /* Floating Point Unavailable Interrupt */
480 EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
482 /* System Call Interrupt */
483 START_EXCEPTION(SystemCall)
484 NORMAL_EXCEPTION_PROLOG
485 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
487 /* Auxillary Processor Unavailable Interrupt */
488 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
490 /* Decrementer Interrupt */
491 DECREMENTER_EXCEPTION
493 /* Fixed Internal Timer Interrupt */
494 /* TODO: Add FIT support */
495 EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
497 /* Watchdog Timer Interrupt */
498 /* TODO: Add watchdog support */
499 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
501 /* Data TLB Error Interrupt */
502 START_EXCEPTION(DataTLBError)
503 mtspr SPRN_SPRG0, r10 /* Save some working registers */
504 mtspr SPRN_SPRG1, r11
505 mtspr SPRN_SPRG4W, r12
506 mtspr SPRN_SPRG5W, r13
508 mtspr SPRN_SPRG7W, r11
509 mfspr r10, SPRN_DEAR /* Get faulting address */
511 /* If we are faulting a kernel address, we have to use the
512 * kernel page tables.
515 ori r11, r11, TASK_SIZE@l
518 lis r11, swapper_pg_dir@h
519 ori r11, r11, swapper_pg_dir@l
521 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
522 rlwinm r12,r12,0,16,1
527 /* Get the PGD for the current thread */
533 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
534 lwz r11, 0(r11) /* Get L1 entry */
535 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
536 beq 2f /* Bail if no table */
538 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
539 lwz r11, 0(r12) /* Get Linux PTE */
540 andi. r13, r11, _PAGE_PRESENT
543 ori r11, r11, _PAGE_ACCESSED
546 /* Jump to common tlb load */
549 /* The bailout. Restore registers to pre-exception conditions
550 * and call the heavyweights to help us out.
552 mfspr r11, SPRN_SPRG7R
554 mfspr r13, SPRN_SPRG5R
555 mfspr r12, SPRN_SPRG4R
556 mfspr r11, SPRN_SPRG1
557 mfspr r10, SPRN_SPRG0
560 /* Instruction TLB Error Interrupt */
562 * Nearly the same as above, except we get our
563 * information from different registers and bailout
564 * to a different point.
566 START_EXCEPTION(InstructionTLBError)
567 mtspr SPRN_SPRG0, r10 /* Save some working registers */
568 mtspr SPRN_SPRG1, r11
569 mtspr SPRN_SPRG4W, r12
570 mtspr SPRN_SPRG5W, r13
572 mtspr SPRN_SPRG7W, r11
573 mfspr r10, SPRN_SRR0 /* Get faulting address */
575 /* If we are faulting a kernel address, we have to use the
576 * kernel page tables.
579 ori r11, r11, TASK_SIZE@l
582 lis r11, swapper_pg_dir@h
583 ori r11, r11, swapper_pg_dir@l
585 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
586 rlwinm r12,r12,0,16,1
591 /* Get the PGD for the current thread */
597 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
598 lwz r11, 0(r11) /* Get L1 entry */
599 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
600 beq 2f /* Bail if no table */
602 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
603 lwz r11, 0(r12) /* Get Linux PTE */
604 andi. r13, r11, _PAGE_PRESENT
607 ori r11, r11, _PAGE_ACCESSED
610 /* Jump to common TLB load point */
614 /* The bailout. Restore registers to pre-exception conditions
615 * and call the heavyweights to help us out.
617 mfspr r11, SPRN_SPRG7R
619 mfspr r13, SPRN_SPRG5R
620 mfspr r12, SPRN_SPRG4R
621 mfspr r11, SPRN_SPRG1
622 mfspr r10, SPRN_SPRG0
626 /* SPE Unavailable */
627 START_EXCEPTION(SPEUnavailable)
628 NORMAL_EXCEPTION_PROLOG
630 addi r3,r1,STACK_FRAME_OVERHEAD
631 EXC_XFER_EE_LITE(0x2010, KernelSPE)
633 EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
634 #endif /* CONFIG_SPE */
636 /* SPE Floating Point Data */
638 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
640 EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
641 #endif /* CONFIG_SPE */
643 /* SPE Floating Point Round */
644 EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
646 /* Performance Monitor */
647 EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD)
650 /* Debug Interrupt */
657 * Data TLB exceptions will bail out to this point
658 * if they can't resolve the lightweight TLB fault.
661 NORMAL_EXCEPTION_PROLOG
662 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
664 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
665 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
667 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
669 addi r3,r1,STACK_FRAME_OVERHEAD
670 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
674 * Both the instruction and data TLB miss get to this
675 * point to load the TLB.
677 * r11 - TLB (info from Linux PTE)
678 * r12, r13 - available to use
679 * CR5 - results of addr < TASK_SIZE
680 * MAS0, MAS1 - loaded with proper value when we get here
681 * MAS2, MAS3 - will need additional info from Linux PTE
682 * Upon exit, we reload everything and RFI.
686 * We set execute, because we don't have the granularity to
687 * properly set this at the page level (Linux problem).
688 * Many of these bits are software only. Bits we don't set
689 * here we (properly should) assume have the appropriate value.
693 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
698 /* addr > TASK_SIZE */
699 li r10, (MAS3_UX | MAS3_UW | MAS3_UR)
700 andi. r13, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
701 andi. r12, r11, _PAGE_USER /* Test for _PAGE_USER */
705 or r12, r12, r10 /* Copy user perms into supervisor */
708 /* addr <= TASK_SIZE */
709 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
710 ori r12, r12, (MAS3_SX | MAS3_SR)
712 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
716 /* Done...restore registers and get out of here. */
717 mfspr r11, SPRN_SPRG7R
719 mfspr r13, SPRN_SPRG5R
720 mfspr r12, SPRN_SPRG4R
721 mfspr r11, SPRN_SPRG1
722 mfspr r10, SPRN_SPRG0
723 rfi /* Force context change */
726 /* Note that the SPE support is closely modeled after the AltiVec
727 * support. Changes to one are likely to be applicable to the
731 * Disable SPE for the task which had SPE previously,
732 * and save its SPE registers in its thread_struct.
733 * Enables SPE for use in the kernel on return.
734 * On SMP we know the SPE units are free, since we give it up every
739 mtmsr r5 /* enable use of SPE now */
742 * For SMP, we don't do lazy SPE switching because it just gets too
743 * horrendously complex, especially when a task switches from one CPU
744 * to another. Instead we call giveup_spe in switch_to.
747 lis r3,last_task_used_spe@ha
748 lwz r4,last_task_used_spe@l(r3)
751 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
753 evxor evr10, evr10, evr10 /* clear out evr10 */
754 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
756 evstddx evr10, r4, r5 /* save off accumulator */
758 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
760 andc r4,r4,r10 /* disable SPE for previous task */
761 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
763 #endif /* CONFIG_SMP */
764 /* enable use of SPE after return */
766 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
769 stw r4,THREAD_USED_SPE(r5)
775 stw r4,last_task_used_spe@l(r3)
776 #endif /* CONFIG_SMP */
777 /* restore registers and return */
778 2: REST_4GPRS(3, r11)
794 * SPE unavailable trap from kernel - print a message, but let
795 * the task use SPE in the kernel until it returns to user mode.
800 stw r3,_MSR(r1) /* enable use of SPE after return */
803 mr r4,r2 /* current */
807 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
810 #endif /* CONFIG_SPE */
817 * extern void loadcam_entry(unsigned int index)
819 * Load TLBCAM[index] entry in to the L2 CAM MMU
821 _GLOBAL(loadcam_entry)
839 * extern void giveup_altivec(struct task_struct *prev)
841 * The e500 core does not have an AltiVec unit.
843 _GLOBAL(giveup_altivec)
848 * extern void giveup_spe(struct task_struct *prev)
855 mtmsr r5 /* enable use of SPE now */
858 beqlr- /* if no previous owner, done */
859 addi r3,r3,THREAD /* want THREAD of task */
862 SAVE_32EVR(0, r4, r3)
863 evxor evr6, evr6, evr6 /* clear out evr6 */
864 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
866 evstddx evr6, r4, r3 /* save off accumulator */
867 mfspr r6,SPRN_SPEFSCR
868 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
870 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
872 andc r4,r4,r3 /* disable SPE for previous task */
873 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
877 lis r4,last_task_used_spe@ha
878 stw r5,last_task_used_spe@l(r4)
879 #endif /* CONFIG_SMP */
881 #endif /* CONFIG_SPE */
884 * extern void giveup_fpu(struct task_struct *prev)
886 * The e500 core does not have an FPU.
892 * extern void abort(void)
894 * At present, this routine just applies a system reset.
898 mtspr SPRN_DBCR0,r13 /* disable all debug events */
900 ori r13,r13,MSR_DE@l /* Enable Debug Events */
903 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
908 #ifdef CONFIG_BDI_SWITCH
909 /* Context switch the PTE pointer for the Abatron BDI2000.
910 * The PGDIR is the second parameter.
912 lis r5, abatron_pteptrs@h
913 ori r5, r5, abatron_pteptrs@l
917 isync /* Force context change */
921 * We put a few things here that have to be page-aligned. This stuff
922 * goes at the beginning of the data segment, which is page-aligned.
926 _GLOBAL(empty_zero_page)
928 _GLOBAL(swapper_pg_dir)
931 /* Reserved 4k for the critical exception stack & 4k for the machine
932 * check stack per CPU for kernel mode exceptions */
935 exception_stack_bottom:
936 .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
937 _GLOBAL(exception_stack_top)
940 * This space gets a copy of optional info passed to us by the bootstrap
941 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
947 * Room for two PTE pointers, usually the kernel and current user pointers
948 * to their respective root page table.