drivers/media/platform/soc_camera/tegra_camera/vi2.c

   1 /*
   2  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/freezer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kthread.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/clk.h>
  27 #include <linux/reset.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/nvhost.h>
  30
  31 #include <media/soc_camera.h>
  32 #include <media/soc_mediabus.h>
  33 #include <media/tegra_v4l2_camera.h>
  34
  35 #include <mach/clk.h>
  36 #include <mach/io_dpd.h>
  37
  38 #include "nvhost_syncpt.h"
  39 #include "nvhost_acm.h"
  40 #include "bus_client.h"
  41 #include "t124/t124.h"
  42 #include "t210/t210.h"
  43 #include "common.h"
  44
  45 static int tpg_mode;
  46 module_param(tpg_mode, int, 0644);
  47
  48 #define VI2_CAM_DRV_NAME                                "vi"
  49 #define VI2_CAM_CARD_NAME                               "vi"
  50 #define VI2_CAM_VERSION                                 KERNEL_VERSION(0, 0, 5)
  51
  52 #define TEGRA_SYNCPT_RETRY_COUNT                        10
  53
  54 #define TEGRA_SYNCPT_CSI_WAIT_TIMEOUT                   200
  55
  56 /* VI registers */
  57 #define TEGRA_VI_CFG_VI_INCR_SYNCPT                     0x000
  58 #if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) || \
  59         IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
  60 #define         VI_MW_REQ_DONE                          4
  61 #define         VI_MW_ACK_DONE                          6
  62 #define         VI_FRAME_START                          9
  63 #define         VI_LINE_START                           11
  64 #else
  65 #define         VI_LINE_START                           4
  66 #define         VI_FRAME_START                          5
  67 #define         VI_MW_REQ_DONE                          6
  68 #define         VI_MW_ACK_DONE                          7
  69 #endif
  70
  71 #define TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL               0x004
  72 #define TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR               0x008
  73 #define TEGRA_VI_CFG_CTXSW                              0x020
  74 #define TEGRA_VI_CFG_INTSTATUS                          0x024
  75 #define TEGRA_VI_CFG_PWM_CONTROL                        0x038
  76 #define TEGRA_VI_CFG_PWM_HIGH_PULSE                     0x03c
  77 #define TEGRA_VI_CFG_PWM_LOW_PULSE                      0x040
  78 #define TEGRA_VI_CFG_PWM_SELECT_PULSE_A                 0x044
  79 #define TEGRA_VI_CFG_PWM_SELECT_PULSE_B                 0x048
  80 #define TEGRA_VI_CFG_PWM_SELECT_PULSE_C                 0x04c
  81 #define TEGRA_VI_CFG_PWM_SELECT_PULSE_D                 0x050
  82 #define TEGRA_VI_CFG_VGP1                               0x064
  83 #define TEGRA_VI_CFG_VGP2                               0x068
  84 #define TEGRA_VI_CFG_VGP3                               0x06c
  85 #define TEGRA_VI_CFG_VGP4                               0x070
  86 #define TEGRA_VI_CFG_VGP5                               0x074
  87 #define TEGRA_VI_CFG_VGP6                               0x078
  88 #define TEGRA_VI_CFG_INTERRUPT_MASK                     0x08c
  89 #define TEGRA_VI_CFG_INTERRUPT_TYPE_SELECT              0x090
  90 #define TEGRA_VI_CFG_INTERRUPT_POLARITY_SELECT          0x094
  91 #define TEGRA_VI_CFG_INTERRUPT_STATUS                   0x098
  92 #define TEGRA_VI_CFG_VGP_SYNCPT_CONFIG                  0x0ac
  93 #define TEGRA_VI_CFG_VI_SW_RESET                        0x0b4
  94 #define TEGRA_VI_CFG_CG_CTRL                            0x0b8
  95 #define TEGRA_VI_CFG_VI_MCCIF_FIFOCTRL                  0x0e4
  96 #define TEGRA_VI_CFG_TIMEOUT_WCOAL_VI                   0x0e8
  97 #define TEGRA_VI_CFG_DVFS                               0x0f0
  98 #define TEGRA_VI_CFG_RESERVE                            0x0f4
  99 #define TEGRA_VI_CFG_RESERVE_1                          0x0f8
 100
 101 /* CSI registers */
 102 #define TEGRA_VI_CSI_0_BASE                             0x100
 103 #define TEGRA_VI_CSI_1_BASE                             0x200
 104 #define TEGRA_VI_CSI_2_BASE                             0x300
 105 #define TEGRA_VI_CSI_3_BASE                             0x400
 106 #define TEGRA_VI_CSI_4_BASE                             0x500
 107 #define TEGRA_VI_CSI_5_BASE                             0x600
 108
 109 #define TEGRA_VI_CSI_SW_RESET                           0x000
 110 #define TEGRA_VI_CSI_SINGLE_SHOT                        0x004
 111 #define TEGRA_VI_CSI_SINGLE_SHOT_STATE_UPDATE           0x008
 112 #define TEGRA_VI_CSI_IMAGE_DEF                          0x00c
 113 #define TEGRA_VI_CSI_RGB2Y_CTRL                         0x010
 114 #define TEGRA_VI_CSI_MEM_TILING                         0x014
 115 #define TEGRA_VI_CSI_IMAGE_SIZE                         0x018
 116 #define TEGRA_VI_CSI_IMAGE_SIZE_WC                      0x01c
 117 #define TEGRA_VI_CSI_IMAGE_DT                           0x020
 118 #define TEGRA_VI_CSI_SURFACE0_OFFSET_MSB                0x024
 119 #define TEGRA_VI_CSI_SURFACE0_OFFSET_LSB                0x028
 120 #define TEGRA_VI_CSI_SURFACE1_OFFSET_MSB                0x02c
 121 #define TEGRA_VI_CSI_SURFACE1_OFFSET_LSB                0x030
 122 #define TEGRA_VI_CSI_SURFACE2_OFFSET_MSB                0x034
 123 #define TEGRA_VI_CSI_SURFACE2_OFFSET_LSB                0x038
 124 #define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_MSB             0x03c
 125 #define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_LSB             0x040
 126 #define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_MSB             0x044
 127 #define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_LSB             0x048
 128 #define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_MSB             0x04c
 129 #define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_LSB             0x050
 130 #define TEGRA_VI_CSI_SURFACE0_STRIDE                    0x054
 131 #define TEGRA_VI_CSI_SURFACE1_STRIDE                    0x058
 132 #define TEGRA_VI_CSI_SURFACE2_STRIDE                    0x05c
 133 #define TEGRA_VI_CSI_SURFACE_HEIGHT0                    0x060
 134 #define TEGRA_VI_CSI_ISPINTF_CONFIG                     0x064
 135 #define TEGRA_VI_CSI_ERROR_STATUS                       0x084
 136 #define TEGRA_VI_CSI_ERROR_INT_MASK                     0x088
 137 #define TEGRA_VI_CSI_WD_CTRL                            0x08c
 138 #define TEGRA_VI_CSI_WD_PERIOD                          0x090
 139
 140 #define TEGRA_CSI_CSI_CAP_CIL                           0x808
 141 #define TEGRA_CSI_CSI_CAP_CSI                           0x818
 142 #define TEGRA_CSI_CSI_CAP_PP                            0x828
 143
 144 /* CSI Pixel Parser registers */
 145 #define TEGRA_CSI_PIXEL_PARSER_0_BASE                   0x0838
 146 #define TEGRA_CSI_PIXEL_PARSER_1_BASE                   0x086c
 147 #define TEGRA_CSI_PIXEL_PARSER_2_BASE                   0x1038
 148 #define TEGRA_CSI_PIXEL_PARSER_3_BASE                   0x106c
 149 #define TEGRA_CSI_PIXEL_PARSER_4_BASE                   0x1838
 150 #define TEGRA_CSI_PIXEL_PARSER_5_BASE                   0x186c
 151
 152 #define TEGRA_CSI_INPUT_STREAM_CONTROL                  0x000
 153 #define TEGRA_CSI_PIXEL_STREAM_CONTROL0                 0x004
 154 #define TEGRA_CSI_PIXEL_STREAM_CONTROL1                 0x008
 155 #define TEGRA_CSI_PIXEL_STREAM_GAP                      0x00c
 156 #define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND               0x010
 157 #define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME           0x014
 158 #define TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK           0x018
 159 #define TEGRA_CSI_PIXEL_PARSER_STATUS                   0x01c
 160 #define TEGRA_CSI_CSI_SW_SENSOR_RESET                   0x020
 161
 162 /* CSI PHY registers */
 163 #define TEGRA_CSI_CIL_PHY_0_BASE                        0x0908
 164 #define TEGRA_CSI_CIL_PHY_1_BASE                        0x1108
 165 #define TEGRA_CSI_CIL_PHY_2_BASE                        0x1908
 166 #define TEGRA_CSI_PHY_CIL_COMMAND                       0x0908
 167
 168 /* CSI CIL registers */
 169 #define TEGRA_CSI_CIL_0_BASE                            0x092c
 170 #define TEGRA_CSI_CIL_1_BASE                            0x0960
 171 #define TEGRA_CSI_CIL_2_BASE                            0x112c
 172 #define TEGRA_CSI_CIL_3_BASE                            0x1160
 173 #define TEGRA_CSI_CIL_4_BASE                            0x192c
 174 #define TEGRA_CSI_CIL_5_BASE                            0x1960
 175
 176 #define TEGRA_CSI_CIL_PAD_CONFIG0                       0x000
 177 #define TEGRA_CSI_CIL_PAD_CONFIG1                       0x004
 178 #define TEGRA_CSI_CIL_PHY_CONTROL                       0x008
 179 #define TEGRA_CSI_CIL_INTERRUPT_MASK                    0x00c
 180 #define TEGRA_CSI_CIL_STATUS                            0x010
 181 #define TEGRA_CSI_CILX_STATUS                           0x014
 182 #define TEGRA_CSI_CIL_ESCAPE_MODE_COMMAND               0x018
 183 #define TEGRA_CSI_CIL_ESCAPE_MODE_DATA                  0x01c
 184 #define TEGRA_CSI_CIL_SW_SENSOR_RESET                   0x020
 185
 186 /* CSI Pattern Generator registers */
 187 #if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) || \
 188             IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
 189 #define TEGRA_CSI_PATTERN_GENERATOR_0_BASE              0xa68
 190 #define TEGRA_CSI_PATTERN_GENERATOR_1_BASE              0xa9c
 191 #else
 192 #define TEGRA_CSI_PATTERN_GENERATOR_0_BASE              0x09c4
 193 #define TEGRA_CSI_PATTERN_GENERATOR_1_BASE              0x09f8
 194 #define TEGRA_CSI_PATTERN_GENERATOR_2_BASE              0x11c4
 195 #define TEGRA_CSI_PATTERN_GENERATOR_3_BASE              0x11f8
 196 #define TEGRA_CSI_PATTERN_GENERATOR_4_BASE              0x19c4
 197 #define TEGRA_CSI_PATTERN_GENERATOR_5_BASE              0x19f8
 198 #endif
 199
 200 #define TEGRA_CSI_PATTERN_GENERATOR_CTRL                0x000
 201 #define TEGRA_CSI_PG_BLANK                              0x004
 202 #define TEGRA_CSI_PG_PHASE                              0x008
 203 #define TEGRA_CSI_PG_RED_FREQ                           0x00c
 204 #define TEGRA_CSI_PG_RED_FREQ_RATE                      0x010
 205 #define TEGRA_CSI_PG_GREEN_FREQ                         0x014
 206 #define TEGRA_CSI_PG_GREEN_FREQ_RATE                    0x018
 207 #define TEGRA_CSI_PG_BLUE_FREQ                          0x01c
 208 #define TEGRA_CSI_PG_BLUE_FREQ_RATE                     0x020
 209 #define TEGRA_CSI_PG_AOHDR                              0x024
 210
 211 #define TEGRA_CSI_DPCM_CTRL_A                           0xad0
 212 #define TEGRA_CSI_DPCM_CTRL_B                           0xad4
 213 #define TEGRA_CSI_STALL_COUNTER                         0xae8
 214 #define TEGRA_CSI_CSI_READONLY_STATUS                   0xaec
 215 #define TEGRA_CSI_CSI_SW_STATUS_RESET                   0xaf0
 216 #define TEGRA_CSI_CLKEN_OVERRIDE                        0xaf4
 217 #define TEGRA_CSI_DEBUG_CONTROL                         0xaf8
 218 #define TEGRA_CSI_DEBUG_COUNTER_0                       0xafc
 219 #define TEGRA_CSI_DEBUG_COUNTER_1                       0xb00
 220 #define TEGRA_CSI_DEBUG_COUNTER_2                       0xb04
 221
 222 /* These go into the TEGRA_VI_CSI_n_IMAGE_DEF registers bits 23:16 */
 223 #define TEGRA_IMAGE_FORMAT_T_L8                         16
 224 #define TEGRA_IMAGE_FORMAT_T_R16_I                      32
 225 #define TEGRA_IMAGE_FORMAT_T_B5G6R5                     33
 226 #define TEGRA_IMAGE_FORMAT_T_R5G6B5                     34
 227 #define TEGRA_IMAGE_FORMAT_T_A1B5G5R5                   35
 228 #define TEGRA_IMAGE_FORMAT_T_A1R5G5B5                   36
 229 #define TEGRA_IMAGE_FORMAT_T_B5G5R5A1                   37
 230 #define TEGRA_IMAGE_FORMAT_T_R5G5B5A1                   38
 231 #define TEGRA_IMAGE_FORMAT_T_A4B4G4R4                   39
 232 #define TEGRA_IMAGE_FORMAT_T_A4R4G4B4                   40
 233 #define TEGRA_IMAGE_FORMAT_T_B4G4R4A4                   41
 234 #define TEGRA_IMAGE_FORMAT_T_R4G4B4A4                   42
 235 #define TEGRA_IMAGE_FORMAT_T_A8B8G8R8                   64
 236 #define TEGRA_IMAGE_FORMAT_T_A8R8G8B8                   65
 237 #define TEGRA_IMAGE_FORMAT_T_B8G8R8A8                   66
 238 #define TEGRA_IMAGE_FORMAT_T_R8G8B8A8                   67
 239 #define TEGRA_IMAGE_FORMAT_T_A2B10G10R10                68
 240 #define TEGRA_IMAGE_FORMAT_T_A2R10G10B10                69
 241 #define TEGRA_IMAGE_FORMAT_T_B10G10R10A2                70
 242 #define TEGRA_IMAGE_FORMAT_T_R10G10B10A2                71
 243 #define TEGRA_IMAGE_FORMAT_T_A8Y8U8V8                   193
 244 #define TEGRA_IMAGE_FORMAT_T_V8U8Y8A8                   194
 245 #define TEGRA_IMAGE_FORMAT_T_A2Y10U10V10                197
 246 #define TEGRA_IMAGE_FORMAT_T_V10U10Y10A2                198
 247 #define TEGRA_IMAGE_FORMAT_T_Y8_U8__Y8_V8               200
 248 #define TEGRA_IMAGE_FORMAT_T_Y8_V8__Y8_U8               201
 249 #define TEGRA_IMAGE_FORMAT_T_U8_Y8__V8_Y8               202
 250 #define TEGRA_IMAGE_FORMAT_T_V8_Y8__U8_Y8               203
 251 #define TEGRA_IMAGE_FORMAT_T_Y8__U8__V8_N444            224
 252 #define TEGRA_IMAGE_FORMAT_T_Y8__U8V8_N444              225
 253 #define TEGRA_IMAGE_FORMAT_T_Y8__V8U8_N444              226
 254 #define TEGRA_IMAGE_FORMAT_T_Y8__U8__V8_N422            227
 255 #define TEGRA_IMAGE_FORMAT_T_Y8__U8V8_N422              228
 256 #define TEGRA_IMAGE_FORMAT_T_Y8__V8U8_N422              229
 257 #define TEGRA_IMAGE_FORMAT_T_Y8__U8__V8_N420            230
 258 #define TEGRA_IMAGE_FORMAT_T_Y8__U8V8_N420              231
 259 #define TEGRA_IMAGE_FORMAT_T_Y8__V8U8_N420              232
 260 #define TEGRA_IMAGE_FORMAT_T_X2Lc10Lb10La10             233
 261 #define TEGRA_IMAGE_FORMAT_T_A2R6R6R6R6R6               234
 262
 263 /* These go into the TEGRA_VI_CSI_n_CSI_IMAGE_DT registers bits 7:0 */
 264 #define TEGRA_IMAGE_DT_YUV420_8                         24
 265 #define TEGRA_IMAGE_DT_YUV420_10                        25
 266 #define TEGRA_IMAGE_DT_YUV420CSPS_8                     28
 267 #define TEGRA_IMAGE_DT_YUV420CSPS_10                    29
 268 #define TEGRA_IMAGE_DT_YUV422_8                         30
 269 #define TEGRA_IMAGE_DT_YUV422_10                        31
 270 #define TEGRA_IMAGE_DT_RGB444                           32
 271 #define TEGRA_IMAGE_DT_RGB555                           33
 272 #define TEGRA_IMAGE_DT_RGB565                           34
 273 #define TEGRA_IMAGE_DT_RGB666                           35
 274 #define TEGRA_IMAGE_DT_RGB888                           36
 275 #define TEGRA_IMAGE_DT_RAW6                             40
 276 #define TEGRA_IMAGE_DT_RAW7                             41
 277 #define TEGRA_IMAGE_DT_RAW8                             42
 278 #define TEGRA_IMAGE_DT_RAW10                            43
 279 #define TEGRA_IMAGE_DT_RAW12                            44
 280 #define TEGRA_IMAGE_DT_RAW14                            45
 281
 282 struct chan_regs_config {
 283         u32 csi_base;
 284         u32 csi_pp_base;
 285         u32 cil_base;
 286         u32 cil_phy_base;
 287         u32 tpg_base;
 288 };
 289
 290 #define csi_regs_write(cam, chan, offset, val) \
 291                 TC_VI_REG_WT(cam, chan->regs.csi_base + offset, val)
 292 #define csi_regs_read(cam, chan, offset) \
 293                 TC_VI_REG_RD(cam, chan->regs.csi_base + offset)
 294 #define csi_pp_regs_write(cam, chan, offset, val) \
 295                 TC_VI_REG_WT(cam, chan->regs.csi_pp_base + offset, val)
 296 #define csi_pp_regs_read(cam, chan, offset) \
 297                 TC_VI_REG_RD(cam, chan->regs.csi_pp_base + offset)
 298 #define cil_regs_write(cam, chan, offset, val) \
 299                 TC_VI_REG_WT(cam, chan->regs.cil_base + offset, val)
 300 #define cil_regs_read(cam, chan, offset) \
 301                 TC_VI_REG_RD(cam, chan->regs.cil_base + offset)
 302 #define cil_phy_reg_write(cam, chan, val) \
 303                 TC_VI_REG_WT(cam, chan->regs.cil_phy_base, val)
 304 #define cil_phy_reg_read(cam, chan) TC_VI_REG_RD(cam, chan->regs.cil_phy_base)
 305 #define tpg_regs_write(cam, chan, offset, val) \
 306                 TC_VI_REG_WT(cam, chan->regs.tpg_base + offset, val)
 307 #define tpg_regs_read(cam, chan, offset) \
 308                 TC_VI_REG_RD(cam, chan->regs.tpg_base + offset)
 309
 310 static struct tegra_io_dpd vi2_io_dpd[] = {
 311         {
 312                 .name                   = "CSIA",
 313                 .io_dpd_reg_index       = 0,
 314                 .io_dpd_bit             = 0,
 315         },
 316         {
 317                 .name                   = "CSIB",
 318                 .io_dpd_reg_index       = 0,
 319                 .io_dpd_bit             = 1,
 320         },
 321         {
 322                 .name                   = "CSIC",
 323                 .io_dpd_reg_index       = 1,
 324                 .io_dpd_bit             = 10,
 325         },
 326         {
 327                 .name                   = "CSID",
 328                 .io_dpd_reg_index       = 1,
 329                 .io_dpd_bit             = 11,
 330         },
 331         {
 332                 .name                   = "CSIE",
 333                 .io_dpd_reg_index       = 1,
 334                 .io_dpd_bit             = 12,
 335         },
 336         {
 337                 .name                   = "CSIF",
 338                 .io_dpd_reg_index       = 1,
 339                 .io_dpd_bit             = 13,
 340         },
 341 };
 342
 343 struct vi2_camera_clk {
 344         const char                      *name;
 345         struct clk                      *clk;
 346         u32                             freq;
 347         int                             use_devname;
 348 };
 349
 350 #define MAX_CHAN_NUM    6
 351
 352 struct vi2_channel {
 353         struct vi2_camera               *vi2_cam;
 354
 355         /* syncpt ids */
 356         u32                             syncpt_id;
 357         u32                             syncpt_thresh;
 358
 359         struct tegra_io_dpd             *dpd;
 360         struct vi2_camera_clk           *clks;
 361         int                             num_clks;
 362
 363         struct chan_regs_config         regs;
 364
 365         struct list_head                capture;
 366         spinlock_t                      start_lock;
 367         struct list_head                done;
 368         spinlock_t                      done_lock;
 369
 370         struct task_struct              *kthread_capture_start;
 371         wait_queue_head_t               start_wait;
 372         struct task_struct              *kthread_capture_done;
 373         wait_queue_head_t               done_wait;
 374
 375         int                             port;
 376         int                             lanes;
 377         s32                             bytes_per_line;
 378         int                             fourcc;
 379         int                             code;
 380         int                             surface;
 381         int                             width;
 382         int                             height;
 383
 384         int                             sequence;
 385         int                             sof;
 386 };
 387
 388 struct vi2_camera {
 389         struct tegra_camera             cam;
 390
 391         void __iomem                    *reg_base;
 392
 393         struct nvhost_device_data       *ndata;
 394
 395         struct regulator                *reg;
 396         const char                      *regulator_name;
 397
 398         struct vi2_camera_clk           *clks;
 399         int                             num_clks;
 400
 401         struct vi2_channel              channels[MAX_CHAN_NUM];
 402
 403                 /* Test Pattern Generator mode */
 404         int                             tpg_mode;
 405         struct vi2_camera_clk           *tpg_clk;
 406
 407         int                             enable_refcnt;
 408 };
 409
 410 /* Clock settings for camera */
 411 static struct vi2_camera_clk vi2_common_clks[] = {
 412         {
 413                 .name = "vi",
 414                 .freq = 408000000,
 415                 .use_devname = 1,
 416         },
 417         {
 418                 .name = "csi",
 419                 .freq = 408000000,
 420                 .use_devname = 1,
 421         },
 422         {
 423                 .name = "isp",
 424                 .freq = 0,
 425         },
 426         {
 427                 .name = "csus",
 428                 .freq = 0,
 429                 .use_devname = 1,
 430         },
 431         {
 432                 .name = "sclk",
 433                 .freq = 80000000,
 434         },
 435         {
 436                 .name = "emc",
 437                 .freq = 300000000,
 438                 .use_devname = 1,
 439         },
 440 };
 441
 442 static struct vi2_camera_clk vi2_clks_tpg = {
 443         .name = "pll_d",
 444         .freq = 927000000,
 445 };
 446
 447 static struct vi2_camera_clk vi2_clks_ab[] = {
 448         {
 449                 .name = "vi_sensor",
 450                 .freq = 24000000,
 451         },
 452         {
 453                 .name = "cilab",
 454                 .freq = 102000000,
 455                 .use_devname = 1,
 456         },
 457 };
 458
 459 static struct vi2_camera_clk vi2_clks_cd[] = {
 460         {
 461                 .name = "vi_sensor2",
 462                 .freq = 24000000,
 463         },
 464         {
 465                 .name = "cilcd",
 466                 .freq = 102000000,
 467                 .use_devname = 1,
 468         },
 469 };
 470
 471 static struct vi2_camera_clk vi2_clks_ef[] = {
 472         {
 473                 .name = "cile",
 474                 .freq = 102000000,
 475                 .use_devname = 1,
 476         },
 477 };
 478
 479 static const struct soc_mbus_pixelfmt vi2_tpg_format = {
 480         .fourcc                 = V4L2_PIX_FMT_RGB32,
 481         .name                   = "RGBA 8-8-8-8",
 482         .bits_per_sample        = 32,
 483         .packing                = SOC_MBUS_PACKING_NONE,
 484         .order                  = SOC_MBUS_ORDER_LE,
 485 };
 486
 487 #define MAX_DEVID_LENGTH        16
 488
 489 static void vi2_init_syncpts(struct vi2_channel *chan)
 490 {
 491         chan->syncpt_id = nvhost_get_syncpt_client_managed("vi");
 492 }
 493
 494 static void vi2_free_syncpts(struct vi2_channel *chan)
 495 {
 496         nvhost_free_syncpt(chan->syncpt_id);
 497 }
 498
 499 static u32 vi2_syncpt_cond(u32 cond, int port)
 500 {
 501         if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) ||
 502             IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
 503                 return (cond + port * 1) << 8;
 504         else
 505                 return (cond + port * 4) << 8;
 506 }
 507
 508 static int vi2_clock_start(struct vi2_camera *vi2_cam,
 509                            struct vi2_camera_clk *clks, int num_clks)
 510 {
 511         struct tegra_camera *cam = (struct tegra_camera *)vi2_cam;
 512         struct platform_device *pdev = cam->pdev;
 513         struct vi2_camera_clk *vi2_clk;
 514         int i;
 515
 516         for (i = 0; i < num_clks; i++) {
 517                 vi2_clk = &clks[i];
 518
 519                 if (vi2_clk->use_devname) {
 520                         char devname[MAX_DEVID_LENGTH];
 521                         snprintf(devname, MAX_DEVID_LENGTH,
 522                                  "tegra_%s", dev_name(&pdev->dev));
 523                         vi2_clk->clk = clk_get_sys(devname, vi2_clk->name);
 524                 } else
 525                         vi2_clk->clk = clk_get(&pdev->dev, vi2_clk->name);
 526
 527                 if (!IS_ERR_OR_NULL(vi2_clk->clk)) {
 528                         clk_prepare_enable(vi2_clk->clk);
 529                         if (vi2_clk->freq > 0)
 530                                 clk_set_rate(vi2_clk->clk, vi2_clk->freq);
 531                 } else {
 532                         dev_err(&pdev->dev, "Failed to get clock %s.\n",
 533                                 vi2_clk->name);
 534                         return PTR_ERR(vi2_clk->clk);
 535                 }
 536         }
 537
 538         return 0;
 539 }
 540
 541 static int vi2_common_clock_start(struct vi2_camera *vi2_cam)
 542 {
 543         int ret;
 544
 545         vi2_cam->num_clks = ARRAY_SIZE(vi2_common_clks);
 546         vi2_cam->clks = vi2_common_clks;
 547         ret = vi2_clock_start(vi2_cam, vi2_cam->clks, vi2_cam->num_clks);
 548         if (ret)
 549                 return ret;
 550
 551         if (vi2_cam->tpg_mode) {
 552                 vi2_cam->tpg_clk = &vi2_clks_tpg;
 553                 ret = vi2_clock_start(vi2_cam, vi2_cam->tpg_clk, 1);
 554                 if (!ret) {
 555                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 556                                         TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
 557                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 558                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
 559                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 560                                         TEGRA_CLK_MIPI_CSI_OUT_ENB, 0);
 561                 }
 562         }
 563
 564         return ret;
 565 }
 566
 567 static void vi2_clock_stop(struct vi2_camera_clk *clks, int num_clks)
 568 {
 569         struct vi2_camera_clk *vi2_clk;
 570         int i;
 571
 572         for (i = 0; i < num_clks; i++) {
 573                 vi2_clk = &clks[i];
 574                 if (!IS_ERR_OR_NULL(vi2_clk->clk)) {
 575                         clk_disable_unprepare(vi2_clk->clk);
 576                         clk_put(vi2_clk->clk);
 577                 }
 578                 vi2_clk->clk = NULL;
 579         }
 580 }
 581
 582 static void vi2_common_clock_stop(struct vi2_camera *vi2_cam)
 583 {
 584         vi2_clock_stop(vi2_cam->clks, vi2_cam->num_clks);
 585
 586         if (vi2_cam->tpg_mode) {
 587                 if (!IS_ERR(vi2_cam->tpg_clk->clk)) {
 588                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 589                                          TEGRA_CLK_MIPI_CSI_OUT_ENB, 1);
 590                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 591                                          TEGRA_CLK_PLLD_CSI_OUT_ENB, 0);
 592                         tegra_clk_cfg_ex(vi2_cam->tpg_clk->clk,
 593                                          TEGRA_CLK_PLLD_DSI_OUT_ENB, 0);
 594                         clk_disable_unprepare(vi2_cam->tpg_clk->clk);
 595                         clk_put(vi2_cam->tpg_clk->clk);
 596                         vi2_cam->tpg_clk->clk = NULL;
 597                 }
 598         }
 599 }
 600
 601 static u32 vi2_cal_regs_base(u32 regs_base, int port)
 602 {
 603         return regs_base + (port / 2 * 0x800) + (port & 1) * 0x34;
 604 }
 605
 606 static int vi2_channel_capture_frame(struct vi2_channel *chan,
 607                                      struct tegra_camera_buffer *buf);
 608
 609 static int vi2_channel_kthread_capture_start(void *data)
 610 {
 611         struct vi2_channel *chan = data;
 612         struct tegra_camera_buffer *buf;
 613
 614         set_freezable();
 615
 616         while (1) {
 617                 try_to_freeze();
 618                 wait_event_interruptible(chan->start_wait,
 619                                 !list_empty(&chan->capture) ||
 620                                 kthread_should_stop());
 621                 if (kthread_should_stop())
 622                         break;
 623
 624                 spin_lock(&chan->start_lock);
 625                 if (list_empty(&chan->capture)) {
 626                         spin_unlock(&chan->start_lock);
 627                         continue;
 628                 }
 629
 630                 buf = list_entry(chan->capture.next, struct tegra_camera_buffer,
 631                                  queue);
 632                 list_del_init(&buf->queue);
 633                 spin_unlock(&chan->start_lock);
 634
 635                 vi2_channel_capture_frame(chan, buf);
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int vi2_channel_capture_done(struct vi2_channel *chan,
 642                                     struct tegra_camera_buffer *buf);
 643
 644 static int vi2_channel_kthread_capture_done(void *data)
 645 {
 646         struct vi2_channel *chan = data;
 647         struct tegra_camera_buffer *buf;
 648
 649         set_freezable();
 650
 651         while (1) {
 652                 try_to_freeze();
 653                 wait_event_interruptible(chan->done_wait,
 654                                 !list_empty(&chan->done) ||
 655                                 kthread_should_stop());
 656                 if (kthread_should_stop() && list_empty(&chan->done))
 657                         break;
 658
 659                 spin_lock(&chan->done_lock);
 660                 if (list_empty(&chan->done)) {
 661                         spin_unlock(&chan->done_lock);
 662                         continue;
 663                 }
 664
 665                 buf = list_entry(chan->done.next, struct tegra_camera_buffer,
 666                                 queue);
 667                 list_del_init(&buf->queue);
 668                 spin_unlock(&chan->done_lock);
 669
 670                 vi2_channel_capture_done(chan, buf);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static s32 vi2_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf);
 677
 678 static int vi2_channel_init(struct vi2_camera *vi2_cam,
 679                             struct soc_camera_device *icd)
 680 {
 681         int port = icd_to_port(icd);
 682         struct vi2_channel *chan = &vi2_cam->channels[port];
 683         struct chan_regs_config *regs = &chan->regs;
 684
 685         INIT_LIST_HEAD(&chan->capture);
 686         INIT_LIST_HEAD(&chan->done);
 687         spin_lock_init(&chan->start_lock);
 688         spin_lock_init(&chan->done_lock);
 689         init_waitqueue_head(&chan->start_wait);
 690         init_waitqueue_head(&chan->done_wait);
 691
 692         chan->dpd = &vi2_io_dpd[port];
 693         chan->vi2_cam = vi2_cam;
 694         chan->sequence = 0;
 695         chan->surface = 0;
 696         chan->sof = 1;
 697         chan->port = port;
 698         chan->lanes = icd_to_lanes(icd);
 699
 700         if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) ||
 701             IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
 702                 /* Init and start channel related clocks */
 703                 if (port == TEGRA_CAMERA_PORT_CSI_A) {
 704                         chan->clks = vi2_clks_ab;
 705                         chan->num_clks = ARRAY_SIZE(vi2_clks_ab);
 706                 } else {
 707                         chan->clks = vi2_clks_cd;
 708                         chan->num_clks = ARRAY_SIZE(vi2_clks_cd);
 709                 }
 710         else {
 711                 /* Init and start channel related clocks */
 712                 switch (port) {
 713                 case TEGRA_CAMERA_PORT_CSI_A:
 714                 case TEGRA_CAMERA_PORT_CSI_B:
 715                         chan->clks = vi2_clks_ab;
 716                         chan->num_clks = ARRAY_SIZE(vi2_clks_ab);
 717                         break;
 718                 case TEGRA_CAMERA_PORT_CSI_C:
 719                 case TEGRA_CAMERA_PORT_CSI_D:
 720                         chan->clks = vi2_clks_cd;
 721                         chan->num_clks = ARRAY_SIZE(vi2_clks_cd);
 722                         break;
 723                 case TEGRA_CAMERA_PORT_CSI_E:
 724                 case TEGRA_CAMERA_PORT_CSI_F:
 725                         chan->clks = vi2_clks_ef;
 726                         chan->num_clks = ARRAY_SIZE(vi2_clks_ef);
 727                         break;
 728                 default:
 729                         return -EINVAL;
 730                 }
 731         }
 732
 733         vi2_clock_start(vi2_cam, chan->clks, chan->num_clks);
 734
 735         tegra_io_dpd_disable(chan->dpd);
 736
 737         /* Init syncpts */
 738         vi2_init_syncpts(chan);
 739
 740         /* Init channel register base */
 741         regs->csi_base = TEGRA_VI_CSI_0_BASE + port * 0x100;
 742         regs->csi_pp_base = vi2_cal_regs_base(TEGRA_CSI_PIXEL_PARSER_0_BASE,
 743                             port);
 744         regs->cil_base = vi2_cal_regs_base(TEGRA_CSI_CIL_0_BASE, port);
 745         regs->cil_phy_base = TEGRA_CSI_CIL_PHY_0_BASE + port / 2 * 0x800;
 746         regs->tpg_base = vi2_cal_regs_base(TEGRA_CSI_PATTERN_GENERATOR_0_BASE,
 747                          port);
 748
 749         /* Clean up status */
 750         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_STATUS, 0xFFFFFFFF);
 751         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CILX_STATUS, 0xFFFFFFFF);
 752         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_PARSER_STATUS,
 753                           0xFFFFFFFF);
 754         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_ERROR_STATUS, 0xFFFFFFFF);
 755
 756         return 0;
 757 }
 758
 759 static void vi2_channel_deinit(struct vi2_camera *vi2_cam,
 760                                struct soc_camera_device *icd)
 761 {
 762         int port = icd_to_port(icd);
 763         struct vi2_channel *chan = &vi2_cam->channels[port];
 764
 765         /* free syncpts */
 766         vi2_free_syncpts(chan);
 767         chan->sequence = 0;
 768         chan->sof = 0;
 769         tegra_io_dpd_enable(chan->dpd);
 770         vi2_clock_stop(chan->clks, chan->num_clks);
 771 }
 772
 773 static int vi2_camera_activate(struct vi2_camera *vi2_cam)
 774 {
 775         int ret = 0;
 776
 777         /* Init and start common clocks */
 778         vi2_common_clock_start(vi2_cam);
 779
 780         ret = nvhost_module_busy_ext(vi2_cam->cam.pdev);
 781         if (ret) {
 782                 dev_err(&vi2_cam->cam.pdev->dev, "nvhost module is busy\n");
 783                 goto exit;
 784         }
 785
 786         /* Enable external power */
 787         if (vi2_cam->reg) {
 788                 ret = regulator_enable(vi2_cam->reg);
 789                 if (ret)
 790                         dev_err(&vi2_cam->cam.pdev->dev,
 791                                 "enabling regulator failed\n");
 792         }
 793
 794         /* Reset VI2/CSI2 when activating, no sepecial ops for deactiving  */
 795         /* T12_CG_2ND_LEVEL_EN */
 796         TC_VI_REG_WT(vi2_cam, TEGRA_VI_CFG_CG_CTRL, 1);
 797         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CLKEN_OVERRIDE, 0x0);
 798         udelay(10);
 799
 800         /* Unpowergate VE */
 801         tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
 802
 803         return 0;
 804
 805 exit:
 806         vi2_common_clock_stop(vi2_cam);
 807         return ret;
 808 }
 809
 810 static int vi2_add_device(struct soc_camera_device *icd)
 811 {
 812         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 813         struct tegra_camera *cam = ici->priv;
 814         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
 815         int ret;
 816
 817         if (!vi2_cam->enable_refcnt) {
 818                 ret = vi2_camera_activate(vi2_cam);
 819                 if (ret)
 820                         return ret;
 821         }
 822         vi2_channel_init(vi2_cam, icd);
 823         vi2_cam->enable_refcnt++;
 824
 825         return 0;
 826 }
 827
 828 static void vi2_camera_deactivate(struct vi2_camera *vi2_cam)
 829 {
 830         vi2_common_clock_stop(vi2_cam);
 831
 832         /* Powergate VE */
 833         tegra_powergate_partition(TEGRA_POWERGATE_VENC);
 834
 835         /* Disable external power */
 836         if (vi2_cam->reg)
 837                 regulator_disable(vi2_cam->reg);
 838
 839         nvhost_module_idle_ext(vi2_cam->cam.pdev);
 840 }
 841
 842 static void vi2_remove_device(struct soc_camera_device *icd)
 843 {
 844         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 845         struct tegra_camera *cam = ici->priv;
 846         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
 847
 848         vi2_cam->enable_refcnt--;
 849         vi2_channel_deinit(vi2_cam, icd);
 850         if (!vi2_cam->enable_refcnt)
 851                 vi2_camera_deactivate(vi2_cam);
 852 }
 853
 854 static bool vi2_port_is_valid(int port)
 855 {
 856         return (((port) >= TEGRA_CAMERA_PORT_CSI_A) &&
 857                 ((port) <= TEGRA_CAMERA_PORT_CSI_F));
 858 }
 859
 860 static s32 vi2_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf)
 861 {
 862         s32 bytes_per_line = soc_mbus_bytes_per_line(width, mf);
 863
 864         if (bytes_per_line % 64)
 865                 bytes_per_line = bytes_per_line + (64 - (bytes_per_line % 64));
 866
 867         return bytes_per_line;
 868 }
 869
 870 static bool vi2_ignore_subdev_fmt(struct tegra_camera *cam)
 871 {
 872         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
 873
 874         /* If we are in TPG mode, we ignore the subdev's supported formats. */
 875         return vi2_cam->tpg_mode;
 876 }
 877
 878 static int vi2_get_formats(struct soc_camera_device *icd,
 879                            unsigned int idx,
 880                            struct soc_camera_format_xlate *xlate)
 881 {
 882         struct device *dev = icd->parent;
 883         struct soc_camera_host *ici = to_soc_camera_host(dev);
 884         struct vi2_camera *vi2_cam = ici->priv;
 885
 886         /*
 887          * If we are not in TPG mode, then let the regular get_formats handler
 888          * handle this.
 889          */
 890         if (!vi2_cam->tpg_mode)
 891                 return -EAGAIN;
 892
 893         if (xlate) {
 894                 xlate->host_fmt = &vi2_tpg_format;
 895                 xlate->code = V4L2_MBUS_FMT_RGBA8888_4X8_LE;
 896         }
 897
 898         return 1;
 899 }
 900
 901 /*
 902  * vi2_try_mbus_fmt() and vi2_s_mbus_fmt(): Tegra's VI2 camera host controller
 903  * can only support widths of multiples of 4.  In addition, though it doesn't
 904  * affect these functions but is just an interesting point, Tegra's VI2 camera
 905  * host controller will only output lines to memory in multiples of 64 bytes.
 906  * an image width that results in a line stride that is not a multiple of 64
 907  * bytes will result in the line being padded in order to satisfy the multiple
 908  * of 64 line stride (see vi2_bytes_per_line()).
 909  */
 910 static int vi2_try_mbus_fmt(struct v4l2_subdev *sd,
 911                             struct v4l2_mbus_framefmt *mf)
 912 {
 913         if (mf->width % 4) {
 914                 int width;
 915                 int ret;
 916
 917                 /* First, clamp our width to a multiple of 4. */
 918                 mf->width = ALIGN(mf->width, 4);
 919
 920                 /*
 921                  * Remember this new width, and ask the subdev if this width
 922                  * is okay.
 923                  */
 924                 width = mf->width;
 925                 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, mf);
 926                 if (IS_ERR_VALUE(ret))
 927                         return ret;
 928
 929                 /* If this new width is not okay with the subdev, we fail. */
 930                 if (mf->width != width)
 931                         return -EINVAL;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int vi2_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
 938 {
 939         if (mf->width % 4)
 940                 return -EINVAL;
 941
 942         return 0;
 943 }
 944
 945 static void vi2_videobuf_queue(struct tegra_camera *cam,
 946                                struct soc_camera_device *icd,
 947                                struct tegra_camera_buffer *buf)
 948 {
 949         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
 950         int port = icd_to_port(icd);
 951         struct vi2_channel *chan = &vi2_cam->channels[port];
 952
 953         if (icd->current_fmt) {
 954                 chan->fourcc = icd->current_fmt->host_fmt->fourcc;
 955                 chan->code = icd->current_fmt->code;
 956                 chan->bytes_per_line = vi2_bytes_per_line(icd->user_width,
 957                                 icd->current_fmt->host_fmt);
 958                 chan->width = icd->user_width;
 959                 chan->height = icd->user_height;
 960         }
 961
 962         spin_lock(&chan->start_lock);
 963         list_add_tail(&buf->queue, &chan->capture);
 964         spin_unlock(&chan->start_lock);
 965
 966         /* Wait up kthread for capture */
 967         wake_up_interruptible(&chan->start_wait);
 968 }
 969
 970 static int vi2_start_streaming(struct tegra_camera *cam,
 971                                struct soc_camera_device *icd,
 972                                unsigned int count)
 973 {
 974         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
 975         int port = icd_to_port(icd);
 976         struct vi2_channel *chan = &vi2_cam->channels[port];
 977
 978         /* Start kthread to capture data to buffer */
 979         chan->kthread_capture_start = kthread_run(
 980                                         vi2_channel_kthread_capture_start, chan,
 981                                         "vi2_channel:%d_0", port);
 982         if (IS_ERR(chan->kthread_capture_start)) {
 983                 dev_err(&vi2_cam->cam.pdev->dev,
 984                         "failed to run kthread for capture start!\n");
 985                 return PTR_ERR(chan->kthread_capture_start);
 986         }
 987
 988         chan->kthread_capture_done = kthread_run(
 989                                         vi2_channel_kthread_capture_done, chan,
 990                                         "vi2_channel:%d_1", port);
 991         if (IS_ERR(chan->kthread_capture_done)) {
 992                 dev_err(&vi2_cam->cam.pdev->dev,
 993                         "failed to run kthread for capture done!\n");
 994                 return PTR_ERR(chan->kthread_capture_done);
 995         }
 996
 997         return 0;
 998 }
 999
1000 static int vi2_stop_streaming(struct tegra_camera *cam,
1001                               struct soc_camera_device *icd)
1002 {
1003         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
1004         int port = icd_to_port(icd);
1005         struct vi2_channel *chan = &vi2_cam->channels[port];
1006
1007         /* Stop the kthread for capture */
1008         kthread_stop(chan->kthread_capture_start);
1009         chan->kthread_capture_start = NULL;
1010         kthread_stop(chan->kthread_capture_done);
1011         chan->kthread_capture_done = NULL;
1012
1013         return 0;
1014 }
1015
1016 #define TEGRA_CSI_CILA_PAD_CONFIG0      0x92c
1017 #define TEGRA_CSI_CILB_PAD_CONFIG0      0x960
1018 #define TEGRA_CSI_CILC_PAD_CONFIG0      0x994
1019 #define TEGRA_CSI_CILD_PAD_CONFIG0      0x9c8
1020 #define TEGRA_CSI_CILE_PAD_CONFIG0      0xa08
1021
1022 #define TEGRA_CSI_CSI_CIL_A_INTERRUPT_MASK      0x938
1023 #define TEGRA_CSI_CSI_CIL_B_INTERRUPT_MASK      0x96c
1024 #define TEGRA_CSI_CSI_CIL_C_INTERRUPT_MASK      0x9a0
1025 #define TEGRA_CSI_CSI_CIL_D_INTERRUPT_MASK      0x9d4
1026 #define TEGRA_CSI_CSI_CIL_E_INTERRUPT_MASK      0xa14
1027
1028 #define TEGRA_CSI_PHY_CILA_CONTROL0     0x934
1029 #define TEGRA_CSI_PHY_CILB_CONTROL0     0x968
1030 #define TEGRA_CSI_PHY_CILC_CONTROL0     0x99c
1031 #define TEGRA_CSI_PHY_CILD_CONTROL0     0x9d0
1032 #define TEGRA_CSI_PHY_CILE_CONTROL0     0xa10
1033
1034 static void vi2_capture_setup_cil_t124(struct vi2_camera *vi2_cam, int port)
1035 {
1036         if (port == TEGRA_CAMERA_PORT_CSI_A) {
1037                 /*
1038                  * PAD_CILA_PDVCLAMP 0, PAD_CILA_PDIO_CLK 0,
1039                  * PAD_CILA_PDIO 0, PAD_AB_BK_MODE 1
1040                  */
1041                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CILA_PAD_CONFIG0, 0x10000);
1042
1043                 /* PAD_CILB_PDVCLAMP 0, PAD_CILB_PDIO_CLK 0, PAD_CILB_PDIO 0 */
1044                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CILB_PAD_CONFIG0, 0x0);
1045
1046                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CSI_CIL_A_INTERRUPT_MASK, 0x0);
1047                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CSI_CIL_B_INTERRUPT_MASK, 0x0);
1048
1049 #ifdef DEBUG
1050                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_DEBUG_CONTROL,
1051                              0x3 | (0x1 << 5) | (0x40 << 8));
1052 #endif
1053                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CILA_CONTROL0, 0x9);
1054                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CILB_CONTROL0, 0x9);
1055         } else {
1056                 /*
1057                  * PAD_CILC_PDVCLAMP 0, PAD_CILC_PDIO_CLK 0,
1058                  * PAD_CILC_PDIO 0, PAD_CD_BK_MODE 1
1059                  */
1060                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CILC_PAD_CONFIG0, 0x10000);
1061
1062                 /* PAD_CILD_PDVCLAMP 0, PAD_CILD_PDIO_CLK 0, PAD_CILD_PDIO 0 */
1063                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CILD_PAD_CONFIG0, 0x0);
1064
1065                 /* PAD_CILE_PDVCLAMP 0, PAD_CILE_PDIO_CLK 0, PAD_CILE_PDIO 0 */
1066                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CILE_PAD_CONFIG0, 0x0);
1067
1068                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CSI_CIL_C_INTERRUPT_MASK, 0x0);
1069                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CSI_CIL_D_INTERRUPT_MASK, 0x0);
1070                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_CSI_CIL_E_INTERRUPT_MASK, 0x0);
1071 #ifdef DEBUG
1072                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_DEBUG_CONTROL,
1073                                 0x5 | (0x1 << 5) | (0x50 << 8));
1074 #endif
1075                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CILC_CONTROL0, 0x9);
1076                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CILD_CONTROL0, 0x9);
1077                 TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CILE_CONTROL0, 0x9);
1078         }
1079 }
1080
1081 static void vi2_capture_setup_cil_phy_t124(struct vi2_camera *vi2_cam,
1082                                            int lanes, int port)
1083 {
1084         u32 val;
1085
1086         /* Shared register */
1087         val = TC_VI_REG_RD(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND);
1088         if (port == TEGRA_CAMERA_PORT_CSI_A) {
1089                 if (lanes == 4)
1090                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1091                                         (val & 0xFFFF0000) | 0x0101);
1092                 else
1093                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1094                                         (val & 0xFFFF0000) | 0x0201);
1095         } else {
1096                 if (lanes == 4)
1097                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1098                                         (val & 0x0000FFFF) | 0x21010000);
1099                 else if (lanes == 1)
1100                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1101                                         (val & 0x0000FFFF) | 0x12020000);
1102                 else
1103                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1104                                         (val & 0x0000FFFF) | 0x22010000);
1105         }
1106 }
1107
1108 static int vi2_channel_capture_setup(struct vi2_channel *chan)
1109 {
1110         struct vi2_camera *vi2_cam = chan->vi2_cam;
1111         int port = chan->port;
1112         int lanes = chan->lanes;
1113         int width = chan->width;
1114         int height = chan->height;
1115         struct chan_regs_config *regs = &chan->regs;
1116         int format = 0, data_type = 0, image_size = 0;
1117         int bypass_pixel_transform = 0;
1118
1119         /* Skip VI2/CSI2 setup for second and later frame capture */
1120         if (!chan->sof)
1121                 return 0;
1122
1123         /* CIL PHY register setup */
1124         if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) ||
1125                         IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
1126                 vi2_capture_setup_cil_t124(vi2_cam, port);
1127         else {
1128                 if (port & 0x1) {
1129                         cil_regs_write(vi2_cam, chan,
1130                                        TEGRA_CSI_CIL_PAD_CONFIG0 - 0x34, 0x0);
1131                         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PAD_CONFIG0,
1132                                        0x0);
1133                 } else {
1134                         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PAD_CONFIG0,
1135                                        0x10000);
1136                         cil_regs_write(vi2_cam, chan,
1137                                        TEGRA_CSI_CIL_PAD_CONFIG0 + 0x34,
1138                                        0x0);
1139                 }
1140
1141                 cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_INTERRUPT_MASK,
1142                                0x0);
1143                 cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);
1144                 if (lanes == 4) {
1145                         regs->cil_base = vi2_cal_regs_base(TEGRA_CSI_CIL_0_BASE,
1146                                                            port + 1);
1147                         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PAD_CONFIG0,
1148                                        0x0);
1149                         cil_regs_write(vi2_cam, chan,
1150                                        TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
1151                         cil_regs_write(vi2_cam, chan, TEGRA_CSI_CIL_PHY_CONTROL,
1152                                        0xA);
1153                         regs->cil_base = vi2_cal_regs_base(TEGRA_CSI_CIL_0_BASE,
1154                                                            port);
1155                 }
1156         }
1157
1158         /* CSI pixel parser registers setup */
1159         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
1160                           0xf007);
1161         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK,
1162                           0x0);
1163         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_CONTROL0,
1164                           0x280301f0 | (port & 0x1));
1165         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
1166                           0xf007);
1167         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_CONTROL1, 0x11);
1168         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_GAP, 0x140000);
1169         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME,
1170                           0x0);
1171         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_INPUT_STREAM_CONTROL,
1172                           0x3f0000 | (lanes - 1));
1173
1174         /* CIL PHY register setup */
1175         if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) ||
1176             IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
1177                 vi2_capture_setup_cil_phy_t124(vi2_cam, lanes, port);
1178         else {
1179                 if (lanes == 4)
1180                         cil_phy_reg_write(vi2_cam, chan, 0x0101);
1181                 else {
1182                         u32 val = cil_phy_reg_read(vi2_cam, chan);
1183                         if (port & 0x1)
1184                                 val = (val & ~(0x100)) | (0x100);
1185                         else
1186                                 val = (val & ~(0x1)) | (0x1);
1187                         cil_phy_reg_write(vi2_cam, chan, val);
1188                 }
1189         }
1190
1191         if (vi2_cam->tpg_mode) {
1192                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PATTERN_GENERATOR_CTRL,
1193                                 ((vi2_cam->tpg_mode - 1) << 2) | 0x1);
1194                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_PHASE, 0x0);
1195                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_RED_FREQ, 0x100010);
1196                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_RED_FREQ_RATE, 0x0);
1197                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_GREEN_FREQ,
1198                                0x100010);
1199                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_GREEN_FREQ_RATE,
1200                                0x0);
1201                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_BLUE_FREQ, 0x100010);
1202                 tpg_regs_write(vi2_cam, chan, TEGRA_CSI_PG_BLUE_FREQ_RATE, 0x0);
1203                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) ||
1204                     IS_ENABLED(CONFIG_ARCH_TEGRA_13x_SOC))
1205                         TC_VI_REG_WT(vi2_cam, TEGRA_CSI_PHY_CIL_COMMAND,
1206                                      0x22020202);
1207                 else
1208                         cil_phy_reg_write(vi2_cam, chan, 0x0202);
1209
1210                 format = TEGRA_IMAGE_FORMAT_T_A8B8G8R8;
1211                 data_type = TEGRA_IMAGE_DT_RGB888;
1212                 image_size = width * 3;
1213                 bypass_pixel_transform = 0;
1214         } else if ((chan->code == V4L2_MBUS_FMT_UYVY8_2X8) ||
1215                    (chan->code == V4L2_MBUS_FMT_VYUY8_2X8) ||
1216                    (chan->code == V4L2_MBUS_FMT_YUYV8_2X8) ||
1217                    (chan->code == V4L2_MBUS_FMT_YVYU8_2X8)) {
1218                 switch (chan->code) {
1219                 case V4L2_MBUS_FMT_UYVY8_2X8:
1220                         format = TEGRA_IMAGE_FORMAT_T_U8_Y8__V8_Y8;
1221                         break;
1222                 case V4L2_MBUS_FMT_VYUY8_2X8:
1223                         format = TEGRA_IMAGE_FORMAT_T_V8_Y8__U8_Y8;
1224                         break;
1225                 case V4L2_MBUS_FMT_YUYV8_2X8:
1226                         format = TEGRA_IMAGE_FORMAT_T_Y8_U8__Y8_V8;
1227                         break;
1228                 case V4L2_MBUS_FMT_YVYU8_2X8:
1229                         format = TEGRA_IMAGE_FORMAT_T_Y8_V8__Y8_U8;
1230                         break;
1231                 }
1232                 data_type = TEGRA_IMAGE_DT_YUV422_8;
1233                 image_size = width * 2;
1234                 bypass_pixel_transform = 0;
1235         } else if ((chan->code == V4L2_MBUS_FMT_SBGGR8_1X8) ||
1236                    (chan->code == V4L2_MBUS_FMT_SGBRG8_1X8)) {
1237                 format = TEGRA_IMAGE_FORMAT_T_L8;
1238                 data_type = TEGRA_IMAGE_DT_RAW8;
1239                 image_size = width;
1240                 bypass_pixel_transform = 1;
1241         } else if ((chan->code == V4L2_MBUS_FMT_SBGGR10_1X10) ||
1242                    (chan->code == V4L2_MBUS_FMT_SRGGB10_1X10)) {
1243                 format = TEGRA_IMAGE_FORMAT_T_R16_I;
1244                 data_type = TEGRA_IMAGE_DT_RAW10;
1245                 image_size = width * 10 / 8;
1246                 bypass_pixel_transform = 1;
1247         } else if (chan->code == V4L2_MBUS_FMT_SRGGB12_1X12) {
1248                 format = TEGRA_IMAGE_FORMAT_T_R16_I;
1249                 data_type = TEGRA_IMAGE_DT_RAW12;
1250                 image_size = width * 12 / 8;
1251                 bypass_pixel_transform = 1;
1252         }
1253
1254         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_IMAGE_DEF,
1255                         (bypass_pixel_transform << 24) | (format << 16) |
1256                         0x1);
1257         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_IMAGE_DT, data_type);
1258         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_IMAGE_SIZE_WC, image_size);
1259         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_IMAGE_SIZE,
1260                         (height << 16) | width);
1261
1262         /* Start pixel parser in single shot mode at beginning */
1263         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
1264                           0xf005);
1265
1266         return 0;
1267 }
1268
1269 static int vi2_capture_buffer_setup(struct vi2_channel *chan,
1270                                     struct tegra_camera_buffer *buf)
1271 {
1272         struct vi2_camera *vi2_cam = chan->vi2_cam;
1273
1274         switch (chan->fourcc) {
1275         case V4L2_PIX_FMT_YUV420:
1276         case V4L2_PIX_FMT_YVU420:
1277                 /* FIXME: Setup YUV buffer */
1278
1279         case V4L2_PIX_FMT_UYVY:
1280         case V4L2_PIX_FMT_VYUY:
1281         case V4L2_PIX_FMT_YUYV:
1282         case V4L2_PIX_FMT_YVYU:
1283         case V4L2_PIX_FMT_SBGGR8:
1284         case V4L2_PIX_FMT_SGBRG8:
1285         case V4L2_PIX_FMT_SBGGR10:
1286         case V4L2_PIX_FMT_SRGGB10:
1287         case V4L2_PIX_FMT_SRGGB12:
1288         case V4L2_PIX_FMT_RGB32:
1289                 csi_regs_write(vi2_cam, chan,
1290                                TEGRA_VI_CSI_SURFACE0_OFFSET_MSB +
1291                                chan->surface * 8,
1292                                0x0);
1293                 csi_regs_write(vi2_cam, chan,
1294                                TEGRA_VI_CSI_SURFACE0_OFFSET_LSB +
1295                                chan->surface * 8,
1296                                buf->buffer_addr);
1297                 csi_regs_write(vi2_cam, chan,
1298                                TEGRA_VI_CSI_SURFACE0_STRIDE +
1299                                chan->surface * 4,
1300                                chan->bytes_per_line);
1301                 break;
1302         default:
1303                 dev_err(&vi2_cam->cam.pdev->dev, "Wrong host format %d\n",
1304                         chan->fourcc);
1305                 return -EINVAL;
1306         }
1307
1308         return 0;
1309 }
1310
1311 static void vi2_capture_error_status(struct vi2_channel *chan, int err)
1312 {
1313         struct vi2_camera *vi2_cam = chan->vi2_cam;
1314         u32 val;
1315
1316         dev_err(&vi2_cam->cam.pdev->dev,
1317                 "CSI %d syncpt timeout, syncpt = %d, err = %d\n",
1318                 chan->port, chan->syncpt_id, err);
1319
1320 #ifdef DEBUG
1321         val = TC_VI_REG_RD(vi2_cam, TEGRA_CSI_DEBUG_COUNTER_0);
1322         dev_err(&vi2_cam->cam.pdev->dev,
1323                 "TEGRA_CSI_DEBUG_COUNTER_0 0x%08x\n", val);
1324 #endif
1325         val = cil_regs_read(vi2_cam, chan, TEGRA_CSI_CIL_STATUS);
1326         dev_err(&vi2_cam->cam.pdev->dev,
1327                 "TEGRA_CSI_CSI_CIL_STATUS 0x%08x\n", val);
1328         val = cil_regs_read(vi2_cam, chan, TEGRA_CSI_CILX_STATUS);
1329         dev_err(&vi2_cam->cam.pdev->dev,
1330                 "TEGRA_CSI_CSI_CILX_STATUS 0x%08x\n", val);
1331         val = csi_pp_regs_read(vi2_cam, chan, TEGRA_CSI_PIXEL_PARSER_STATUS);
1332         dev_err(&vi2_cam->cam.pdev->dev,
1333                 "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val);
1334         val = csi_regs_read(vi2_cam, chan, TEGRA_VI_CSI_ERROR_STATUS);
1335         dev_err(&vi2_cam->cam.pdev->dev,
1336                 "TEGRA_VI_CSI_ERROR_STATUS 0x%08x\n", val);
1337 }
1338
1339 static int vi2_channel_capture_frame(struct vi2_channel *chan,
1340                                      struct tegra_camera_buffer *buf)
1341 {
1342         struct vi2_camera *vi2_cam = chan->vi2_cam;
1343         struct tegra_camera *cam = &vi2_cam->cam;
1344         u32 val;
1345         int err;
1346
1347         /* Setup capture registers */
1348         vi2_channel_capture_setup(chan);
1349
1350         /* Start capture */
1351         err = vi2_capture_buffer_setup(chan, buf);
1352         if (err < 0)
1353                 return err;
1354
1355         chan->syncpt_thresh = nvhost_syncpt_incr_max_ext(cam->pdev,
1356                         chan->syncpt_id, 1);
1357
1358         TC_VI_REG_WT(vi2_cam, TEGRA_VI_CFG_VI_INCR_SYNCPT,
1359                      vi2_syncpt_cond(VI_FRAME_START,  chan->port) |
1360                      chan->syncpt_id);
1361
1362         csi_regs_write(vi2_cam, chan, TEGRA_VI_CSI_SINGLE_SHOT, 0x1);
1363
1364         /* Move buffer to capture done queue */
1365         spin_lock(&chan->done_lock);
1366         list_add_tail(&buf->queue, &chan->done);
1367         spin_unlock(&chan->done_lock);
1368
1369         /* Wait up kthread for capture done */
1370         wake_up_interruptible(&chan->done_wait);
1371
1372         err = nvhost_syncpt_wait_timeout_ext(cam->pdev,
1373                         chan->syncpt_id, chan->syncpt_thresh,
1374                         TEGRA_SYNCPT_CSI_WAIT_TIMEOUT,
1375                         NULL,
1376                         NULL);
1377
1378         /* Mark SOF flag to Zero after we captured the FIRST frame */
1379         if (chan->sof)
1380                 chan->sof = 0;
1381
1382         /* Capture syncpt timeout err, then dump error status */
1383         if (err)
1384                 vi2_capture_error_status(chan, err);
1385
1386         return err;
1387 }
1388
1389
1390 static int vi2_channel_capture_done(struct vi2_channel *chan,
1391                                     struct tegra_camera_buffer *buf)
1392 {
1393         struct vi2_camera *vi2_cam = chan->vi2_cam;
1394         struct tegra_camera *cam = &vi2_cam->cam;
1395         struct vb2_buffer *vb = &buf->vb;
1396         int err = 0;
1397
1398         chan->syncpt_thresh = nvhost_syncpt_incr_max_ext(cam->pdev,
1399                                 chan->syncpt_id, 1);
1400
1401         /*
1402          * Make sure recieve VI_MW_ACK_DONE of the last frame before
1403          * stop and dequeue buffer, otherwise MC error will shows up
1404          * for the last frame.
1405          */
1406         TC_VI_REG_WT(vi2_cam, TEGRA_VI_CFG_VI_INCR_SYNCPT,
1407                      vi2_syncpt_cond(VI_MW_ACK_DONE,  chan->port) |
1408                      chan->syncpt_id);
1409
1410         /*
1411          * Ignore error here and just stop pixel parser after waiting,
1412          * even if it's timeout
1413          */
1414         err = nvhost_syncpt_wait_timeout_ext(cam->pdev,
1415                         chan->syncpt_id, chan->syncpt_thresh,
1416                         TEGRA_SYNCPT_CSI_WAIT_TIMEOUT,
1417                         NULL,
1418                         NULL);
1419         if (err)
1420                 dev_err(&vi2_cam->cam.pdev->dev,
1421                         "MW_ACK_DONE syncpoint time out!\n");
1422
1423         csi_pp_regs_write(vi2_cam, chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
1424                           0xf002);
1425
1426         /* Captured one frame */
1427         do_gettimeofday(&vb->v4l2_buf.timestamp);
1428         vb->v4l2_buf.sequence = chan->sequence++;
1429         vb->v4l2_buf.field = V4L2_FIELD_NONE;
1430         vb2_buffer_done(vb, err < 0 ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
1431
1432         return err;
1433 }
1434
1435 struct tegra_camera_ops vi2_ops = {
1436         .add_device             = vi2_add_device,
1437         .remove_device          = vi2_remove_device,
1438         .port_is_valid          = vi2_port_is_valid,
1439         .bytes_per_line         = vi2_bytes_per_line,
1440         .ignore_subdev_fmt      = vi2_ignore_subdev_fmt,
1441         .get_formats            = vi2_get_formats,
1442         .try_mbus_fmt           = vi2_try_mbus_fmt,
1443         .s_mbus_fmt             = vi2_s_mbus_fmt,
1444         .videobuf_queue         = vi2_videobuf_queue,
1445         .start_streaming        = vi2_start_streaming,
1446         .stop_streaming         = vi2_stop_streaming,
1447 };
1448
1449 static struct of_device_id vi2_of_match[] = {
1450         { .compatible = "nvidia,tegra124-vi",
1451                 .data = (struct nvhost_device_data *)&t124_vi_info },
1452         { .compatible = "nvidia,tegra210-vi",
1453                 .data = (struct nvhost_device_data *)&t21_vi_info },
1454         { },
1455 };
1456
1457 static int tegra_camera_slcg_handler(struct notifier_block *nb,
1458                 unsigned long action, void *data)
1459 {
1460         struct clk *clk;
1461         int ret = 0;
1462
1463         struct nvhost_device_data *pdata =
1464                 container_of(nb, struct nvhost_device_data,
1465                         toggle_slcg_notifier);
1466
1467         /* Skip this operation for TPG mode */
1468         if (tpg_mode)
1469                 return NOTIFY_OK;
1470
1471         clk = clk_get(&pdata->pdev->dev, "pll_d");
1472         if (IS_ERR(clk))
1473                 return -EINVAL;
1474
1475         /* Make CSI sourced from PLL_D */
1476         ret = tegra_clk_cfg_ex(clk, TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1477         if (ret) {
1478                 dev_err(&pdata->pdev->dev,
1479                 "%s: failed to select CSI source pll_d: %d\n",
1480                 __func__, ret);
1481                 return ret;
1482         }
1483
1484         /* Enable PLL_D */
1485         ret = clk_prepare_enable(clk);
1486         if (ret) {
1487                 dev_err(&pdata->pdev->dev, "Can't enable pll_d: %d\n", ret);
1488                 return ret;
1489         }
1490
1491         udelay(1);
1492
1493         /* Disable PLL_D */
1494         clk_disable_unprepare(clk);
1495
1496         /* Restore CSI source */
1497         ret = tegra_clk_cfg_ex(clk, TEGRA_CLK_MIPI_CSI_OUT_ENB, 1);
1498         if (ret) {
1499                 dev_err(&pdata->pdev->dev,
1500                 "%s: failed to restore csi source: %d\n",
1501                 __func__, ret);
1502                 return ret;
1503         }
1504
1505         clk_put(clk);
1506
1507         return NOTIFY_OK;
1508 }
1509
1510 static int vi2_probe(struct platform_device *pdev)
1511 {
1512         struct vi2_camera *vi2_cam;
1513         struct nvhost_device_data *ndata = NULL;
1514         int err = 0;
1515
1516         if (pdev->dev.of_node) {
1517                 const struct of_device_id *match;
1518
1519                 match = of_match_device(vi2_of_match, &pdev->dev);
1520                 if (match) {
1521                         ndata = (struct nvhost_device_data *)match->data;
1522                         pdev->dev.platform_data = ndata;
1523                 }
1524
1525                 /*
1526                  * Device Tree will initialize this ID as -1
1527                  * Set it to the right value for future usage
1528                  */
1529                 pdev->id = pdev->dev.id;
1530         } else
1531                 ndata = pdev->dev.platform_data;
1532
1533         if (!ndata) {
1534                 dev_err(&pdev->dev, "No nvhost device data!\n");
1535                 return -EINVAL;
1536         }
1537
1538         /* vi.1 has to wait vi.0 initialized, so defer probing */
1539         if (pdev->id && ndata->master) {
1540                 struct nvhost_device_data *master_ndata =
1541                         ndata->master->dev.platform_data;
1542                 if (master_ndata == platform_get_drvdata(ndata->master))
1543                         return -EPROBE_DEFER;
1544         }
1545
1546         vi2_cam = devm_kzalloc(&pdev->dev, sizeof(struct vi2_camera),
1547                                GFP_KERNEL);
1548         if (!vi2_cam) {
1549                 dev_err(&pdev->dev, "couldn't allocate cam\n");
1550                 return -ENOMEM;
1551         }
1552
1553         vi2_cam->ndata = ndata;
1554         ndata->pdev = pdev;
1555         vi2_cam->cam.pdev = pdev;
1556
1557         /* Init Regulator */
1558         vi2_cam->regulator_name = "avdd_dsi_csi";
1559         vi2_cam->reg = devm_regulator_get(&pdev->dev, vi2_cam->regulator_name);
1560         if (IS_ERR_OR_NULL(vi2_cam->reg)) {
1561                 dev_err(&pdev->dev, "%s: couldn't get regulator %s, err %ld\n",
1562                         __func__, vi2_cam->regulator_name,
1563                         PTR_ERR(vi2_cam->reg));
1564                 return PTR_ERR(vi2_cam->reg);
1565         }
1566
1567         /* Initialize our nvhost client */
1568         mutex_init(&ndata->lock);
1569         platform_set_drvdata(pdev, ndata);
1570         err = nvhost_client_device_get_resources(pdev);
1571         if (err) {
1572                 dev_err(&pdev->dev, "%s: nvhost get resources failed %d\n",
1573                                 __func__, err);
1574                 return err;
1575         }
1576
1577         if (!ndata->aperture[0]) {
1578                 if (ndata->master) {
1579                         struct nvhost_device_data *master_ndata =
1580                                 ndata->master->dev.platform_data;
1581                         ndata->aperture[0] = master_ndata->aperture[0];
1582                 } else {
1583                         dev_err(&pdev->dev, "%s: failed to map register base\n",
1584                                 __func__);
1585                         return -ENXIO;
1586                 }
1587         }
1588
1589         /* Match the nvhost_module_init VENC powergating */
1590         tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
1591         nvhost_module_init(pdev);
1592
1593         err = nvhost_client_device_init(pdev);
1594         if (err) {
1595                 dev_err(&pdev->dev, "%s: nvhost init failed %d\n",
1596                         __func__, err);
1597                 return err;
1598         }
1599
1600         /* Get the VI register base */
1601         vi2_cam->reg_base = ndata->aperture[0];
1602
1603         /* Match the nvhost_module_init VENC powergating */
1604         if (ndata->slcg_notifier_enable &&
1605                         (ndata->powergate_id != -1)) {
1606                 ndata->toggle_slcg_notifier.notifier_call =
1607                 &tegra_camera_slcg_handler;
1608
1609                 slcg_register_notifier(ndata->powergate_id,
1610                         &ndata->toggle_slcg_notifier);
1611         }
1612
1613         platform_set_drvdata(pdev, vi2_cam);
1614
1615         vi2_cam->tpg_mode = tpg_mode;
1616
1617         /* Init VI2/CSI2 ops */
1618         strlcpy(vi2_cam->cam.card, VI2_CAM_CARD_NAME,
1619                 sizeof(vi2_cam->cam.card));
1620         vi2_cam->cam.version = VI2_CAM_VERSION;
1621         vi2_cam->cam.ops = &vi2_ops;
1622
1623         err = tegra_camera_init(pdev, &vi2_cam->cam);
1624         if (err) {
1625                 platform_set_drvdata(pdev, vi2_cam->ndata);
1626                 nvhost_client_device_release(pdev);
1627                 vi2_cam->ndata->aperture[0] = NULL;
1628                 return err;
1629         }
1630
1631         dev_notice(&pdev->dev, "Tegra camera driver loaded.\n");
1632
1633         return 0;
1634 }
1635
1636 static int vi2_remove(struct platform_device *pdev)
1637 {
1638         struct soc_camera_host *ici = to_soc_camera_host(&pdev->dev);
1639         struct tegra_camera *cam = container_of(ici,
1640                                         struct tegra_camera, ici);
1641         struct vi2_camera *vi2_cam = (struct vi2_camera *)cam;
1642         struct nvhost_device_data *ndata = vi2_cam->ndata;
1643
1644         tegra_camera_deinit(pdev, &vi2_cam->cam);
1645
1646         platform_set_drvdata(pdev, vi2_cam->ndata);
1647
1648         if (ndata->slcg_notifier_enable &&
1649             (ndata->powergate_id != -1))
1650                 slcg_unregister_notifier(ndata->powergate_id,
1651                                          &ndata->toggle_slcg_notifier);
1652
1653         nvhost_client_device_release(pdev);
1654         vi2_cam->ndata->aperture[0] = NULL;
1655
1656         dev_notice(&pdev->dev, "Tegra camera host driver unloaded\n");
1657
1658         return 0;
1659 }
1660
1661 static struct platform_driver vi2_driver = {
1662         .driver = {
1663                 .name   = VI2_CAM_DRV_NAME,
1664                 .of_match_table = of_match_ptr(vi2_of_match),
1665         },
1666         .probe          = vi2_probe,
1667         .remove         = vi2_remove,
1668 };
1669
1670 module_platform_driver(vi2_driver);
1671
1672 MODULE_DESCRIPTION("TEGRA SoC Camera Host driver");
1673 MODULE_AUTHOR("Bryan Wu <pengw@nvidia.com>");
1674 MODULE_LICENSE("GPL v2");
1675 MODULE_ALIAS("nvhost:" VI2_CAM_DRV_NAME);