2 * Pinctrl data for the NVIDIA Tegra124 pinmux
4 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/tegra-pmc.h>
23 #include "mach/pinmux-defines.h"
24 #include "pinctrl-tegra.h"
27 * Most pins affected by the pinmux can also be GPIOs. Define these first.
28 * These must match how the GPIO driver names/numbers its pins.
30 #define _GPIO(offset) (offset)
32 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
33 #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
34 #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
35 #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
36 #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
37 #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
38 #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
39 #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
40 #define TEGRA_PIN_PB0 _GPIO(8)
41 #define TEGRA_PIN_PB1 _GPIO(9)
42 #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
43 #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
44 #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
45 #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
46 #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
47 #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
48 #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
49 #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
50 #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
51 #define TEGRA_PIN_PC7 _GPIO(23)
52 #define TEGRA_PIN_PG0 _GPIO(48)
53 #define TEGRA_PIN_PG1 _GPIO(49)
54 #define TEGRA_PIN_PG2 _GPIO(50)
55 #define TEGRA_PIN_PG3 _GPIO(51)
56 #define TEGRA_PIN_PG4 _GPIO(52)
57 #define TEGRA_PIN_PG5 _GPIO(53)
58 #define TEGRA_PIN_PG6 _GPIO(54)
59 #define TEGRA_PIN_PG7 _GPIO(55)
60 #define TEGRA_PIN_PH0 _GPIO(56)
61 #define TEGRA_PIN_PH1 _GPIO(57)
62 #define TEGRA_PIN_PH2 _GPIO(58)
63 #define TEGRA_PIN_PH3 _GPIO(59)
64 #define TEGRA_PIN_PH4 _GPIO(60)
65 #define TEGRA_PIN_PH5 _GPIO(61)
66 #define TEGRA_PIN_PH6 _GPIO(62)
67 #define TEGRA_PIN_PH7 _GPIO(63)
68 #define TEGRA_PIN_PI0 _GPIO(64)
69 #define TEGRA_PIN_PI1 _GPIO(65)
70 #define TEGRA_PIN_PI2 _GPIO(66)
71 #define TEGRA_PIN_PI3 _GPIO(67)
72 #define TEGRA_PIN_PI4 _GPIO(68)
73 #define TEGRA_PIN_PI5 _GPIO(69)
74 #define TEGRA_PIN_PI6 _GPIO(70)
75 #define TEGRA_PIN_PI7 _GPIO(71)
76 #define TEGRA_PIN_PJ0 _GPIO(72)
77 #define TEGRA_PIN_PJ2 _GPIO(74)
78 #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
79 #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
80 #define TEGRA_PIN_PJ7 _GPIO(79)
81 #define TEGRA_PIN_PK0 _GPIO(80)
82 #define TEGRA_PIN_PK1 _GPIO(81)
83 #define TEGRA_PIN_PK2 _GPIO(82)
84 #define TEGRA_PIN_PK3 _GPIO(83)
85 #define TEGRA_PIN_PK4 _GPIO(84)
86 #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
87 #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
88 #define TEGRA_PIN_PK7 _GPIO(87)
89 #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
90 #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
91 #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
92 #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
93 #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
94 #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
95 #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
96 #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
97 #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
98 #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
99 #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
100 #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
101 #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
102 #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
103 #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
104 #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
105 #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
106 #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
107 #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
108 #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
109 #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
110 #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
111 #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
112 #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
113 #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
114 #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
115 #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
116 #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
117 #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
118 #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
119 #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
120 #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
121 #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
122 #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
123 #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
124 #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
125 #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
126 #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
127 #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
128 #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
129 #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
130 #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
131 #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
132 #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
133 #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
134 #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
135 #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
136 #define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
137 #define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
138 #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
139 #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
140 #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
141 #define TEGRA_PIN_PU0 _GPIO(160)
142 #define TEGRA_PIN_PU1 _GPIO(161)
143 #define TEGRA_PIN_PU2 _GPIO(162)
144 #define TEGRA_PIN_PU3 _GPIO(163)
145 #define TEGRA_PIN_PU4 _GPIO(164)
146 #define TEGRA_PIN_PU5 _GPIO(165)
147 #define TEGRA_PIN_PU6 _GPIO(166)
148 #define TEGRA_PIN_PV0 _GPIO(168)
149 #define TEGRA_PIN_PV1 _GPIO(169)
150 #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
151 #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
152 #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
153 #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
154 #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
155 #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
156 #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
157 #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
158 #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
159 #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
160 #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
161 #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
162 #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
163 #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
164 #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
165 #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
166 #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
167 #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
168 #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
169 #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
170 #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
171 #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
172 #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
173 #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
174 #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
175 #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
176 #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
177 #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
178 #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
179 #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
180 #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
181 #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
182 #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
183 #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
184 #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
185 #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
186 #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
187 #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
188 #define TEGRA_PIN_PBB0 _GPIO(216)
189 #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
190 #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
191 #define TEGRA_PIN_PBB3 _GPIO(219)
192 #define TEGRA_PIN_PBB4 _GPIO(220)
193 #define TEGRA_PIN_PBB5 _GPIO(221)
194 #define TEGRA_PIN_PBB6 _GPIO(222)
195 #define TEGRA_PIN_PBB7 _GPIO(223)
196 #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
197 #define TEGRA_PIN_PCC1 _GPIO(225)
198 #define TEGRA_PIN_PCC2 _GPIO(226)
199 #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
200 #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
201 #define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
202 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
203 #define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
204 #define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
205 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
206 #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
207 #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
208 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
209 #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
210 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
211 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
212 #define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
213 #define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
214 #define TEGRA_PIN_PFF2 _GPIO(250)
216 /* All non-GPIO pins follow */
217 #define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
218 #define _PIN(offset) (NUM_GPIOS + (offset))
221 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
222 #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
223 #define TEGRA_PIN_PWR_INT_N _PIN(2)
224 #define TEGRA_PIN_GMI_CLK_LB _PIN(3)
225 #define TEGRA_PIN_RESET_OUT_N _PIN(4)
226 #define TEGRA_PIN_OWR _PIN(5)
227 #define TEGRA_PIN_CLK_32K_IN _PIN(6)
228 #define TEGRA_PIN_JTAG_RTCK _PIN(7)
230 static const struct pinctrl_pin_desc tegra124_pins[] = {
231 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
232 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
233 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
234 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
235 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
236 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
237 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
238 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
239 PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
240 PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
241 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
242 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
243 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
244 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
245 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
246 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
247 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
248 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
249 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
250 PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
251 PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
252 PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
253 PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
254 PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
255 PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
256 PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
257 PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
258 PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
259 PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
260 PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
261 PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
262 PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
263 PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
264 PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
265 PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
266 PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
267 PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
268 PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
269 PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
270 PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
271 PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
272 PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
273 PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
274 PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
275 PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
276 PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
277 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
278 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
279 PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
280 PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
281 PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
282 PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
283 PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
284 PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
285 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
286 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
287 PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
288 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
289 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
290 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
291 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
292 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
293 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
294 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
295 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
296 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
297 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
298 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
299 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
300 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
301 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
302 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
303 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
304 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
305 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
306 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
307 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
308 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
309 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
310 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
311 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
312 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
313 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
314 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
315 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
316 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
317 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
318 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
319 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
320 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
321 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
322 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
323 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
324 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
325 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
326 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
327 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
328 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
329 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
330 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"),
331 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"),
332 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"),
333 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"),
334 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"),
335 PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"),
336 PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"),
337 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
338 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
339 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
340 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
341 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
342 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
343 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
344 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
345 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
346 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
347 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
348 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
349 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
350 PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
351 PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
352 PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
353 PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
354 PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
355 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
356 PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
357 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
358 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
359 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
360 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
361 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
362 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
363 PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
364 PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
365 PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
366 PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
367 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
368 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
369 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
370 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
371 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
372 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
373 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
374 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
375 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
376 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
377 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
378 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
379 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
380 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
381 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
382 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
383 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
384 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
385 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
386 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
387 PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
388 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
389 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
390 PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
391 PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
392 PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
393 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
394 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
395 PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
396 PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
397 PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
398 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
399 PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
400 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
401 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
402 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
403 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
404 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
405 PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
406 PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
407 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
408 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
409 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
410 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
411 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
412 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
413 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
414 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
415 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
416 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
417 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
418 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
419 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
420 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
421 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
424 static const unsigned clk_32k_out_pa0_pins[] = {
425 TEGRA_PIN_CLK_32K_OUT_PA0,
428 static const unsigned uart3_cts_n_pa1_pins[] = {
429 TEGRA_PIN_UART3_CTS_N_PA1,
432 static const unsigned dap2_fs_pa2_pins[] = {
433 TEGRA_PIN_DAP2_FS_PA2,
436 static const unsigned dap2_sclk_pa3_pins[] = {
437 TEGRA_PIN_DAP2_SCLK_PA3,
440 static const unsigned dap2_din_pa4_pins[] = {
441 TEGRA_PIN_DAP2_DIN_PA4,
444 static const unsigned dap2_dout_pa5_pins[] = {
445 TEGRA_PIN_DAP2_DOUT_PA5,
448 static const unsigned sdmmc3_clk_pa6_pins[] = {
449 TEGRA_PIN_SDMMC3_CLK_PA6,
452 static const unsigned sdmmc3_cmd_pa7_pins[] = {
453 TEGRA_PIN_SDMMC3_CMD_PA7,
456 static const unsigned pb0_pins[] = {
460 static const unsigned pb1_pins[] = {
464 static const unsigned sdmmc3_dat3_pb4_pins[] = {
465 TEGRA_PIN_SDMMC3_DAT3_PB4,
468 static const unsigned sdmmc3_dat2_pb5_pins[] = {
469 TEGRA_PIN_SDMMC3_DAT2_PB5,
472 static const unsigned sdmmc3_dat1_pb6_pins[] = {
473 TEGRA_PIN_SDMMC3_DAT1_PB6,
476 static const unsigned sdmmc3_dat0_pb7_pins[] = {
477 TEGRA_PIN_SDMMC3_DAT0_PB7,
480 static const unsigned uart3_rts_n_pc0_pins[] = {
481 TEGRA_PIN_UART3_RTS_N_PC0,
484 static const unsigned uart2_txd_pc2_pins[] = {
485 TEGRA_PIN_UART2_TXD_PC2,
488 static const unsigned uart2_rxd_pc3_pins[] = {
489 TEGRA_PIN_UART2_RXD_PC3,
492 static const unsigned gen1_i2c_scl_pc4_pins[] = {
493 TEGRA_PIN_GEN1_I2C_SCL_PC4,
496 static const unsigned gen1_i2c_sda_pc5_pins[] = {
497 TEGRA_PIN_GEN1_I2C_SDA_PC5,
500 static const unsigned pc7_pins[] = {
504 static const unsigned pg0_pins[] = {
508 static const unsigned pg1_pins[] = {
512 static const unsigned pg2_pins[] = {
516 static const unsigned pg3_pins[] = {
520 static const unsigned pg4_pins[] = {
524 static const unsigned pg5_pins[] = {
528 static const unsigned pg6_pins[] = {
532 static const unsigned pg7_pins[] = {
536 static const unsigned ph0_pins[] = {
540 static const unsigned ph1_pins[] = {
544 static const unsigned ph2_pins[] = {
548 static const unsigned ph3_pins[] = {
552 static const unsigned ph4_pins[] = {
556 static const unsigned ph5_pins[] = {
560 static const unsigned ph6_pins[] = {
564 static const unsigned ph7_pins[] = {
568 static const unsigned pi0_pins[] = {
572 static const unsigned pi1_pins[] = {
576 static const unsigned pi2_pins[] = {
580 static const unsigned pi3_pins[] = {
584 static const unsigned pi4_pins[] = {
588 static const unsigned pi5_pins[] = {
592 static const unsigned pi6_pins[] = {
596 static const unsigned pi7_pins[] = {
600 static const unsigned pj0_pins[] = {
604 static const unsigned pj2_pins[] = {
608 static const unsigned uart2_cts_n_pj5_pins[] = {
609 TEGRA_PIN_UART2_CTS_N_PJ5,
612 static const unsigned uart2_rts_n_pj6_pins[] = {
613 TEGRA_PIN_UART2_RTS_N_PJ6,
616 static const unsigned pj7_pins[] = {
620 static const unsigned pk0_pins[] = {
624 static const unsigned pk1_pins[] = {
628 static const unsigned pk2_pins[] = {
632 static const unsigned pk3_pins[] = {
636 static const unsigned pk4_pins[] = {
640 static const unsigned spdif_out_pk5_pins[] = {
641 TEGRA_PIN_SPDIF_OUT_PK5,
644 static const unsigned spdif_in_pk6_pins[] = {
645 TEGRA_PIN_SPDIF_IN_PK6,
648 static const unsigned pk7_pins[] = {
652 static const unsigned dap1_fs_pn0_pins[] = {
653 TEGRA_PIN_DAP1_FS_PN0,
656 static const unsigned dap1_din_pn1_pins[] = {
657 TEGRA_PIN_DAP1_DIN_PN1,
660 static const unsigned dap1_dout_pn2_pins[] = {
661 TEGRA_PIN_DAP1_DOUT_PN2,
664 static const unsigned dap1_sclk_pn3_pins[] = {
665 TEGRA_PIN_DAP1_SCLK_PN3,
668 static const unsigned usb_vbus_en0_pn4_pins[] = {
669 TEGRA_PIN_USB_VBUS_EN0_PN4,
672 static const unsigned usb_vbus_en1_pn5_pins[] = {
673 TEGRA_PIN_USB_VBUS_EN1_PN5,
676 static const unsigned hdmi_int_pn7_pins[] = {
677 TEGRA_PIN_HDMI_INT_PN7,
680 static const unsigned ulpi_data7_po0_pins[] = {
681 TEGRA_PIN_ULPI_DATA7_PO0,
684 static const unsigned ulpi_data0_po1_pins[] = {
685 TEGRA_PIN_ULPI_DATA0_PO1,
688 static const unsigned ulpi_data1_po2_pins[] = {
689 TEGRA_PIN_ULPI_DATA1_PO2,
692 static const unsigned ulpi_data2_po3_pins[] = {
693 TEGRA_PIN_ULPI_DATA2_PO3,
696 static const unsigned ulpi_data3_po4_pins[] = {
697 TEGRA_PIN_ULPI_DATA3_PO4,
700 static const unsigned ulpi_data4_po5_pins[] = {
701 TEGRA_PIN_ULPI_DATA4_PO5,
704 static const unsigned ulpi_data5_po6_pins[] = {
705 TEGRA_PIN_ULPI_DATA5_PO6,
708 static const unsigned ulpi_data6_po7_pins[] = {
709 TEGRA_PIN_ULPI_DATA6_PO7,
712 static const unsigned dap3_fs_pp0_pins[] = {
713 TEGRA_PIN_DAP3_FS_PP0,
716 static const unsigned dap3_din_pp1_pins[] = {
717 TEGRA_PIN_DAP3_DIN_PP1,
720 static const unsigned dap3_dout_pp2_pins[] = {
721 TEGRA_PIN_DAP3_DOUT_PP2,
724 static const unsigned dap3_sclk_pp3_pins[] = {
725 TEGRA_PIN_DAP3_SCLK_PP3,
728 static const unsigned dap4_fs_pp4_pins[] = {
729 TEGRA_PIN_DAP4_FS_PP4,
732 static const unsigned dap4_din_pp5_pins[] = {
733 TEGRA_PIN_DAP4_DIN_PP5,
736 static const unsigned dap4_dout_pp6_pins[] = {
737 TEGRA_PIN_DAP4_DOUT_PP6,
740 static const unsigned dap4_sclk_pp7_pins[] = {
741 TEGRA_PIN_DAP4_SCLK_PP7,
744 static const unsigned kb_col0_pq0_pins[] = {
745 TEGRA_PIN_KB_COL0_PQ0,
748 static const unsigned kb_col1_pq1_pins[] = {
749 TEGRA_PIN_KB_COL1_PQ1,
752 static const unsigned kb_col2_pq2_pins[] = {
753 TEGRA_PIN_KB_COL2_PQ2,
756 static const unsigned kb_col3_pq3_pins[] = {
757 TEGRA_PIN_KB_COL3_PQ3,
760 static const unsigned kb_col4_pq4_pins[] = {
761 TEGRA_PIN_KB_COL4_PQ4,
764 static const unsigned kb_col5_pq5_pins[] = {
765 TEGRA_PIN_KB_COL5_PQ5,
768 static const unsigned kb_col6_pq6_pins[] = {
769 TEGRA_PIN_KB_COL6_PQ6,
772 static const unsigned kb_col7_pq7_pins[] = {
773 TEGRA_PIN_KB_COL7_PQ7,
776 static const unsigned kb_row0_pr0_pins[] = {
777 TEGRA_PIN_KB_ROW0_PR0,
780 static const unsigned kb_row1_pr1_pins[] = {
781 TEGRA_PIN_KB_ROW1_PR1,
784 static const unsigned kb_row2_pr2_pins[] = {
785 TEGRA_PIN_KB_ROW2_PR2,
788 static const unsigned kb_row3_pr3_pins[] = {
789 TEGRA_PIN_KB_ROW3_PR3,
792 static const unsigned kb_row4_pr4_pins[] = {
793 TEGRA_PIN_KB_ROW4_PR4,
796 static const unsigned kb_row5_pr5_pins[] = {
797 TEGRA_PIN_KB_ROW5_PR5,
800 static const unsigned kb_row6_pr6_pins[] = {
801 TEGRA_PIN_KB_ROW6_PR6,
804 static const unsigned kb_row7_pr7_pins[] = {
805 TEGRA_PIN_KB_ROW7_PR7,
808 static const unsigned kb_row8_ps0_pins[] = {
809 TEGRA_PIN_KB_ROW8_PS0,
812 static const unsigned kb_row9_ps1_pins[] = {
813 TEGRA_PIN_KB_ROW9_PS1,
816 static const unsigned kb_row10_ps2_pins[] = {
817 TEGRA_PIN_KB_ROW10_PS2,
820 static const unsigned kb_row11_ps3_pins[] = {
821 TEGRA_PIN_KB_ROW11_PS3,
824 static const unsigned kb_row12_ps4_pins[] = {
825 TEGRA_PIN_KB_ROW12_PS4,
828 static const unsigned kb_row13_ps5_pins[] = {
829 TEGRA_PIN_KB_ROW13_PS5,
832 static const unsigned kb_row14_ps6_pins[] = {
833 TEGRA_PIN_KB_ROW14_PS6,
836 static const unsigned kb_row15_ps7_pins[] = {
837 TEGRA_PIN_KB_ROW15_PS7,
840 static const unsigned kb_row16_pt0_pins[] = {
841 TEGRA_PIN_KB_ROW16_PT0,
844 static const unsigned kb_row17_pt1_pins[] = {
845 TEGRA_PIN_KB_ROW17_PT1,
848 static const unsigned gen2_i2c_scl_pt5_pins[] = {
849 TEGRA_PIN_GEN2_I2C_SCL_PT5,
852 static const unsigned gen2_i2c_sda_pt6_pins[] = {
853 TEGRA_PIN_GEN2_I2C_SDA_PT6,
856 static const unsigned sdmmc4_cmd_pt7_pins[] = {
857 TEGRA_PIN_SDMMC4_CMD_PT7,
860 static const unsigned pu0_pins[] = {
864 static const unsigned pu1_pins[] = {
868 static const unsigned pu2_pins[] = {
872 static const unsigned pu3_pins[] = {
876 static const unsigned pu4_pins[] = {
880 static const unsigned pu5_pins[] = {
884 static const unsigned pu6_pins[] = {
888 static const unsigned pv0_pins[] = {
892 static const unsigned pv1_pins[] = {
896 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
897 TEGRA_PIN_SDMMC3_CD_N_PV2,
900 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
901 TEGRA_PIN_SDMMC1_WP_N_PV3,
904 static const unsigned ddc_scl_pv4_pins[] = {
905 TEGRA_PIN_DDC_SCL_PV4,
908 static const unsigned ddc_sda_pv5_pins[] = {
909 TEGRA_PIN_DDC_SDA_PV5,
912 static const unsigned gpio_w2_aud_pw2_pins[] = {
913 TEGRA_PIN_GPIO_W2_AUD_PW2,
916 static const unsigned gpio_w3_aud_pw3_pins[] = {
917 TEGRA_PIN_GPIO_W3_AUD_PW3,
920 static const unsigned dap_mclk1_pw4_pins[] = {
921 TEGRA_PIN_DAP_MCLK1_PW4,
924 static const unsigned clk2_out_pw5_pins[] = {
925 TEGRA_PIN_CLK2_OUT_PW5,
928 static const unsigned uart3_txd_pw6_pins[] = {
929 TEGRA_PIN_UART3_TXD_PW6,
932 static const unsigned uart3_rxd_pw7_pins[] = {
933 TEGRA_PIN_UART3_RXD_PW7,
936 static const unsigned dvfs_pwm_px0_pins[] = {
937 TEGRA_PIN_DVFS_PWM_PX0,
940 static const unsigned gpio_x1_aud_px1_pins[] = {
941 TEGRA_PIN_GPIO_X1_AUD_PX1,
944 static const unsigned dvfs_clk_px2_pins[] = {
945 TEGRA_PIN_DVFS_CLK_PX2,
948 static const unsigned gpio_x3_aud_px3_pins[] = {
949 TEGRA_PIN_GPIO_X3_AUD_PX3,
952 static const unsigned gpio_x4_aud_px4_pins[] = {
953 TEGRA_PIN_GPIO_X4_AUD_PX4,
956 static const unsigned gpio_x5_aud_px5_pins[] = {
957 TEGRA_PIN_GPIO_X5_AUD_PX5,
960 static const unsigned gpio_x6_aud_px6_pins[] = {
961 TEGRA_PIN_GPIO_X6_AUD_PX6,
964 static const unsigned gpio_x7_aud_px7_pins[] = {
965 TEGRA_PIN_GPIO_X7_AUD_PX7,
968 static const unsigned ulpi_clk_py0_pins[] = {
969 TEGRA_PIN_ULPI_CLK_PY0,
972 static const unsigned ulpi_dir_py1_pins[] = {
973 TEGRA_PIN_ULPI_DIR_PY1,
976 static const unsigned ulpi_nxt_py2_pins[] = {
977 TEGRA_PIN_ULPI_NXT_PY2,
980 static const unsigned ulpi_stp_py3_pins[] = {
981 TEGRA_PIN_ULPI_STP_PY3,
984 static const unsigned sdmmc1_dat3_py4_pins[] = {
985 TEGRA_PIN_SDMMC1_DAT3_PY4,
988 static const unsigned sdmmc1_dat2_py5_pins[] = {
989 TEGRA_PIN_SDMMC1_DAT2_PY5,
992 static const unsigned sdmmc1_dat1_py6_pins[] = {
993 TEGRA_PIN_SDMMC1_DAT1_PY6,
996 static const unsigned sdmmc1_dat0_py7_pins[] = {
997 TEGRA_PIN_SDMMC1_DAT0_PY7,
1000 static const unsigned sdmmc1_clk_pz0_pins[] = {
1001 TEGRA_PIN_SDMMC1_CLK_PZ0,
1004 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1005 TEGRA_PIN_SDMMC1_CMD_PZ1,
1008 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1009 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1012 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1013 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1016 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1017 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1020 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1021 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1024 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1025 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1028 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1029 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1032 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1033 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1036 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1037 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1040 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1041 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1044 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1045 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1048 static const unsigned pbb0_pins[] = {
1052 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1053 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1056 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1057 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1060 static const unsigned pbb3_pins[] = {
1064 static const unsigned pbb4_pins[] = {
1068 static const unsigned pbb5_pins[] = {
1072 static const unsigned pbb6_pins[] = {
1076 static const unsigned pbb7_pins[] = {
1080 static const unsigned cam_mclk_pcc0_pins[] = {
1081 TEGRA_PIN_CAM_MCLK_PCC0,
1084 static const unsigned pcc1_pins[] = {
1088 static const unsigned pcc2_pins[] = {
1092 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1093 TEGRA_PIN_SDMMC4_CLK_PCC4,
1096 static const unsigned clk2_req_pcc5_pins[] = {
1097 TEGRA_PIN_CLK2_REQ_PCC5,
1100 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1101 TEGRA_PIN_PEX_L0_RST_N_PDD1,
1104 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1105 TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1108 static const unsigned pex_wake_n_pdd3_pins[] = {
1109 TEGRA_PIN_PEX_WAKE_N_PDD3,
1112 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1113 TEGRA_PIN_PEX_L1_RST_N_PDD5,
1116 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1117 TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1120 static const unsigned clk3_out_pee0_pins[] = {
1121 TEGRA_PIN_CLK3_OUT_PEE0,
1124 static const unsigned clk3_req_pee1_pins[] = {
1125 TEGRA_PIN_CLK3_REQ_PEE1,
1128 static const unsigned dap_mclk1_req_pee2_pins[] = {
1129 TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1132 static const unsigned hdmi_cec_pee3_pins[] = {
1133 TEGRA_PIN_HDMI_CEC_PEE3,
1136 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1137 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1140 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1141 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1143 static const unsigned dp_hpd_pff0_pins[] = {
1144 TEGRA_PIN_DP_HPD_PFF0,
1147 static const unsigned usb_vbus_en2_pff1_pins[] = {
1148 TEGRA_PIN_USB_VBUS_EN2_PFF1,
1151 static const unsigned pff2_pins[] = {
1155 static const unsigned core_pwr_req_pins[] = {
1156 TEGRA_PIN_CORE_PWR_REQ,
1159 static const unsigned cpu_pwr_req_pins[] = {
1160 TEGRA_PIN_CPU_PWR_REQ,
1163 static const unsigned owr_pins[] = {
1167 static const unsigned pwr_int_n_pins[] = {
1168 TEGRA_PIN_PWR_INT_N,
1171 static const unsigned reset_out_n_pins[] = {
1172 TEGRA_PIN_RESET_OUT_N,
1175 static const unsigned clk_32k_in_pins[] = {
1176 TEGRA_PIN_CLK_32K_IN,
1179 static const unsigned gmi_clk_lb_pins[] = {
1180 TEGRA_PIN_GMI_CLK_LB,
1183 static const unsigned jtag_rtck_pins[] = {
1184 TEGRA_PIN_JTAG_RTCK,
1187 static const unsigned drive_ao1_pins[] = {
1188 TEGRA_PIN_KB_ROW0_PR0,
1189 TEGRA_PIN_KB_ROW1_PR1,
1190 TEGRA_PIN_KB_ROW2_PR2,
1191 TEGRA_PIN_KB_ROW3_PR3,
1192 TEGRA_PIN_KB_ROW4_PR4,
1193 TEGRA_PIN_KB_ROW5_PR5,
1194 TEGRA_PIN_KB_ROW6_PR6,
1195 TEGRA_PIN_KB_ROW7_PR7,
1196 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1197 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1200 static const unsigned drive_ao2_pins[] = {
1201 TEGRA_PIN_CLK_32K_OUT_PA0,
1202 TEGRA_PIN_CLK_32K_IN,
1203 TEGRA_PIN_KB_COL0_PQ0,
1204 TEGRA_PIN_KB_COL1_PQ1,
1205 TEGRA_PIN_KB_COL2_PQ2,
1206 TEGRA_PIN_KB_COL3_PQ3,
1207 TEGRA_PIN_KB_COL4_PQ4,
1208 TEGRA_PIN_KB_COL5_PQ5,
1209 TEGRA_PIN_KB_COL6_PQ6,
1210 TEGRA_PIN_KB_COL7_PQ7,
1211 TEGRA_PIN_KB_ROW8_PS0,
1212 TEGRA_PIN_KB_ROW9_PS1,
1213 TEGRA_PIN_KB_ROW10_PS2,
1214 TEGRA_PIN_KB_ROW11_PS3,
1215 TEGRA_PIN_KB_ROW12_PS4,
1216 TEGRA_PIN_KB_ROW13_PS5,
1217 TEGRA_PIN_KB_ROW14_PS6,
1218 TEGRA_PIN_KB_ROW15_PS7,
1219 TEGRA_PIN_KB_ROW16_PT0,
1220 TEGRA_PIN_KB_ROW17_PT1,
1221 TEGRA_PIN_SDMMC3_CD_N_PV2,
1222 TEGRA_PIN_CORE_PWR_REQ,
1223 TEGRA_PIN_CPU_PWR_REQ,
1224 TEGRA_PIN_PWR_INT_N,
1227 static const unsigned drive_at1_pins[] = {
1234 static const unsigned drive_at2_pins[] = {
1252 static const unsigned drive_at3_pins[] = {
1257 static const unsigned drive_at4_pins[] = {
1265 static const unsigned drive_at5_pins[] = {
1266 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1267 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1270 static const unsigned drive_cdev1_pins[] = {
1271 TEGRA_PIN_DAP_MCLK1_PW4,
1272 TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1275 static const unsigned drive_cdev2_pins[] = {
1276 TEGRA_PIN_CLK2_OUT_PW5,
1277 TEGRA_PIN_CLK2_REQ_PCC5,
1280 static const unsigned drive_dap1_pins[] = {
1281 TEGRA_PIN_DAP1_FS_PN0,
1282 TEGRA_PIN_DAP1_DIN_PN1,
1283 TEGRA_PIN_DAP1_DOUT_PN2,
1284 TEGRA_PIN_DAP1_SCLK_PN3,
1287 static const unsigned drive_dap2_pins[] = {
1288 TEGRA_PIN_DAP2_FS_PA2,
1289 TEGRA_PIN_DAP2_SCLK_PA3,
1290 TEGRA_PIN_DAP2_DIN_PA4,
1291 TEGRA_PIN_DAP2_DOUT_PA5,
1294 static const unsigned drive_dap3_pins[] = {
1295 TEGRA_PIN_DAP3_FS_PP0,
1296 TEGRA_PIN_DAP3_DIN_PP1,
1297 TEGRA_PIN_DAP3_DOUT_PP2,
1298 TEGRA_PIN_DAP3_SCLK_PP3,
1301 static const unsigned drive_dap4_pins[] = {
1302 TEGRA_PIN_DAP4_FS_PP4,
1303 TEGRA_PIN_DAP4_DIN_PP5,
1304 TEGRA_PIN_DAP4_DOUT_PP6,
1305 TEGRA_PIN_DAP4_SCLK_PP7,
1308 static const unsigned drive_dbg_pins[] = {
1309 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1310 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1320 static const unsigned drive_sdio3_pins[] = {
1321 TEGRA_PIN_SDMMC3_CLK_PA6,
1322 TEGRA_PIN_SDMMC3_CMD_PA7,
1323 TEGRA_PIN_SDMMC3_DAT3_PB4,
1324 TEGRA_PIN_SDMMC3_DAT2_PB5,
1325 TEGRA_PIN_SDMMC3_DAT1_PB6,
1326 TEGRA_PIN_SDMMC3_DAT0_PB7,
1327 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1328 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1331 static const unsigned drive_spi_pins[] = {
1332 TEGRA_PIN_DVFS_PWM_PX0,
1333 TEGRA_PIN_GPIO_X1_AUD_PX1,
1334 TEGRA_PIN_DVFS_CLK_PX2,
1335 TEGRA_PIN_GPIO_X3_AUD_PX3,
1336 TEGRA_PIN_GPIO_X4_AUD_PX4,
1337 TEGRA_PIN_GPIO_X5_AUD_PX5,
1338 TEGRA_PIN_GPIO_X6_AUD_PX6,
1339 TEGRA_PIN_GPIO_X7_AUD_PX7,
1340 TEGRA_PIN_GPIO_W2_AUD_PW2,
1341 TEGRA_PIN_GPIO_W3_AUD_PW3,
1344 static const unsigned drive_uaa_pins[] = {
1345 TEGRA_PIN_ULPI_DATA0_PO1,
1346 TEGRA_PIN_ULPI_DATA1_PO2,
1347 TEGRA_PIN_ULPI_DATA2_PO3,
1348 TEGRA_PIN_ULPI_DATA3_PO4,
1351 static const unsigned drive_uab_pins[] = {
1352 TEGRA_PIN_ULPI_DATA7_PO0,
1353 TEGRA_PIN_ULPI_DATA4_PO5,
1354 TEGRA_PIN_ULPI_DATA5_PO6,
1355 TEGRA_PIN_ULPI_DATA6_PO7,
1360 static const unsigned drive_uart2_pins[] = {
1361 TEGRA_PIN_UART2_TXD_PC2,
1362 TEGRA_PIN_UART2_RXD_PC3,
1363 TEGRA_PIN_UART2_CTS_N_PJ5,
1364 TEGRA_PIN_UART2_RTS_N_PJ6,
1367 static const unsigned drive_uart3_pins[] = {
1368 TEGRA_PIN_UART3_CTS_N_PA1,
1369 TEGRA_PIN_UART3_RTS_N_PC0,
1370 TEGRA_PIN_UART3_TXD_PW6,
1371 TEGRA_PIN_UART3_RXD_PW7,
1374 static const unsigned drive_sdio1_pins[] = {
1375 TEGRA_PIN_SDMMC1_DAT3_PY4,
1376 TEGRA_PIN_SDMMC1_DAT2_PY5,
1377 TEGRA_PIN_SDMMC1_DAT1_PY6,
1378 TEGRA_PIN_SDMMC1_DAT0_PY7,
1379 TEGRA_PIN_SDMMC1_CLK_PZ0,
1380 TEGRA_PIN_SDMMC1_CMD_PZ1,
1383 static const unsigned drive_ddc_pins[] = {
1384 TEGRA_PIN_DDC_SCL_PV4,
1385 TEGRA_PIN_DDC_SDA_PV5,
1388 static const unsigned drive_gma_pins[] = {
1389 TEGRA_PIN_SDMMC4_CLK_PCC4,
1390 TEGRA_PIN_SDMMC4_CMD_PT7,
1391 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1392 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1393 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1394 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1395 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1396 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1397 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1398 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1401 static const unsigned drive_gme_pins[] = {
1403 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1404 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1409 static const unsigned drive_gmf_pins[] = {
1416 static const unsigned drive_gmg_pins[] = {
1417 TEGRA_PIN_CAM_MCLK_PCC0,
1420 static const unsigned drive_gmh_pins[] = {
1424 static const unsigned drive_owr_pins[] = {
1425 TEGRA_PIN_SDMMC3_CD_N_PV2,
1429 static const unsigned drive_uda_pins[] = {
1430 TEGRA_PIN_ULPI_CLK_PY0,
1431 TEGRA_PIN_ULPI_DIR_PY1,
1432 TEGRA_PIN_ULPI_NXT_PY2,
1433 TEGRA_PIN_ULPI_STP_PY3,
1436 static const unsigned drive_gpv_pins[] = {
1437 TEGRA_PIN_PEX_L0_RST_N_PDD1,
1438 TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1439 TEGRA_PIN_PEX_WAKE_N_PDD3,
1440 TEGRA_PIN_PEX_L1_RST_N_PDD5,
1441 TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1442 TEGRA_PIN_USB_VBUS_EN2_PFF1,
1446 static const unsigned drive_cec_pins[] = {
1447 TEGRA_PIN_HDMI_CEC_PEE3,
1450 static const unsigned drive_dev3_pins[] = {
1451 TEGRA_PIN_CLK3_OUT_PEE0,
1452 TEGRA_PIN_CLK3_REQ_PEE1,
1455 static const unsigned drive_at6_pins[] = {
1468 static const unsigned drive_dap5_pins[] = {
1469 TEGRA_PIN_SPDIF_IN_PK6,
1470 TEGRA_PIN_SPDIF_OUT_PK5,
1471 TEGRA_PIN_DP_HPD_PFF0,
1474 static const unsigned drive_usb_vbus_en_pins[] = {
1475 TEGRA_PIN_USB_VBUS_EN0_PN4,
1476 TEGRA_PIN_USB_VBUS_EN1_PN5,
1479 static const unsigned drive_ao3_pins[] = {
1480 TEGRA_PIN_RESET_OUT_N,
1483 static const unsigned drive_ao0_pins[] = {
1484 TEGRA_PIN_JTAG_RTCK,
1487 static const unsigned drive_hv0_pins[] = {
1488 TEGRA_PIN_HDMI_INT_PN7,
1491 static const unsigned drive_sdio4_pins[] = {
1492 TEGRA_PIN_SDMMC1_WP_N_PV3,
1495 static const unsigned drive_ao4_pins[] = {
1496 TEGRA_PIN_JTAG_RTCK,
1503 TEGRA_MUX_DT_CLDVFS,
1510 TEGRA_MUX_DT_DISPLAYA,
1511 TEGRA_MUX_DT_DISPLAYA_ALT,
1512 TEGRA_MUX_DT_DISPLAYB,
1514 TEGRA_MUX_DT_EXTPERIPH1,
1515 TEGRA_MUX_DT_EXTPERIPH2,
1516 TEGRA_MUX_DT_EXTPERIPH3,
1518 TEGRA_MUX_DT_GMI_ALT,
1525 TEGRA_MUX_DT_I2CPWR,
1540 TEGRA_MUX_DT_RESET_OUT_N,
1545 TEGRA_MUX_DT_SDMMC1,
1546 TEGRA_MUX_DT_SDMMC2,
1547 TEGRA_MUX_DT_SDMMC3,
1548 TEGRA_MUX_DT_SDMMC4,
1571 TEGRA_MUX_DT_VI_ALT1,
1572 TEGRA_MUX_DT_VI_ALT3,
1573 TEGRA_MUX_DT_VIMCLK2,
1574 TEGRA_MUX_DT_VIMCLK2_ALT,
1587 static const char * const blink_groups[] = {
1591 static const char * const cec_groups[] = {
1595 static const char * const cldvfs_groups[] = {
1604 static const char * const clk12_groups[] = {
1609 static const char * const cpu_groups[] = {
1613 static const char * const dap_groups[] = {
1618 static const char * const dap1_groups[] = {
1622 static const char * const dap2_groups[] = {
1627 static const char * const dev3_groups[] = {
1631 static const char * const displaya_groups[] = {
1648 static const char * const displaya_alt_groups[] = {
1652 static const char * const displayb_groups[] = {
1673 static const char * const dtv_groups[] = {
1684 static const char * const extperiph1_groups[] = {
1688 static const char * const extperiph2_groups[] = {
1692 static const char * const extperiph3_groups[] = {
1696 static const char * const gmi_groups[] = {
1793 static const char * const gmi_alt_groups[] = {
1799 static const char * const hda_groups[] = {
1810 static const char * const hsi_groups[] = {
1821 static const char * const i2c1_groups[] = {
1828 static const char * const i2c2_groups[] = {
1833 static const char * const i2c3_groups[] = {
1840 static const char * const i2c4_groups[] = {
1845 static const char * const i2cpwr_groups[] = {
1850 static const char * const i2s0_groups[] = {
1857 static const char * const i2s1_groups[] = {
1864 static const char * const i2s2_groups[] = {
1871 static const char * const i2s3_groups[] = {
1878 static const char * const i2s4_groups[] = {
1885 static const char * const irda_groups[] = {
1892 static const char * const kbc_groups[] = {
1922 static const char * const owr_groups[] = {
1929 static const char * const pmi_groups[] = {
1933 static const char * const pwm0_groups[] = {
1941 static const char * const pwm1_groups[] = {
1948 static const char * const pwm2_groups[] = {
1955 static const char * const pwm3_groups[] = {
1961 static const char * const pwron_groups[] = {
1965 static const char * const reset_out_n_groups[] = {
1969 static const char * const rsvd1_groups[] = {
2002 static const char * const rsvd2_groups[] = {
2091 "pex_l0_rst_n_pdd1",
2092 "pex_l0_clkreq_n_pdd2",
2094 "pex_l1_rst_n_pdd5",
2095 "pex_l1_clkreq_n_pdd6",
2101 "sdmmc3_clk_lb_out_pee4",
2102 "sdmmc3_clk_lb_in_pee5",
2108 "usb_vbus_en2_pff1",
2112 static const char * const rsvd3_groups[] = {
2169 "pex_l0_rst_n_pdd1",
2170 "pex_l0_clkreq_n_pdd2",
2172 "pex_l1_rst_n_pdd5",
2173 "pex_l1_clkreq_n_pdd6",
2179 "sdmmc3_clk_lb_out_pee4",
2180 "sdmmc3_clk_lb_in_pee5",
2185 "usb_vbus_en2_pff1",
2189 static const char * const rsvd4_groups[] = {
2276 "dap_mclk1_req_pee2",
2292 "pex_l0_rst_n_pdd1",
2293 "pex_l0_clkreq_n_pdd2",
2295 "pex_l1_rst_n_pdd5",
2296 "pex_l1_clkreq_n_pdd6",
2302 "sdmmc3_clk_lb_out_pee4",
2303 "sdmmc3_clk_lb_in_pee5",
2307 "usb_vbus_en2_pff1",
2311 static const char * const sdmmc1_groups[] = {
2324 static const char * const sdmmc2_groups[] = {
2349 static const char * const sdmmc3_groups[] = {
2364 "sdmmc3_clk_lb_in_pee5",
2365 "sdmmc3_clk_lb_out_pee4",
2368 static const char * const sdmmc4_groups[] = {
2381 static const char * const soc_groups[] = {
2388 static const char * const spdif_groups[] = {
2397 static const char * const spi1_groups[] = {
2410 static const char * const spi2_groups[] = {
2432 static const char * const spi3_groups[] = {
2452 static const char * const spi4_groups[] = {
2476 static const char * const spi5_groups[] = {
2487 static const char * const spi6_groups[] = {
2497 static const char * const trace_groups[] = {
2510 static const char * const uarta_groups[] = {
2553 static const char * const uartb_groups[] = {
2558 static const char * const uartc_groups[] = {
2567 static const char * const uartd_groups[] = {
2580 static const char * const ulpi_groups[] = {
2595 static const char * const usb_groups[] = {
2599 "usb_vbus_en2_pff1",
2602 static const char * const vgp1_groups[] = {
2606 static const char * const vgp2_groups[] = {
2610 static const char * const vgp3_groups[] = {
2614 static const char * const vgp4_groups[] = {
2618 static const char * const vgp5_groups[] = {
2622 static const char * const vgp6_groups[] = {
2626 static const char * const vi_groups[] = {
2630 static const char * const vi_alt1_groups[] = {
2634 static const char * const vi_alt3_groups[] = {
2638 static const char * const vimclk2_groups[] = {
2642 static const char * const vimclk2_alt_groups[] = {
2646 static const char * const sata_groups[] = {
2647 "dap_mclk1_req_pee2",
2652 static const char * const ccla_groups[] = {
2656 static const char * const rtck_groups[] = {
2660 static const char * const sys_groups[] = {
2664 static const char * const pe0_groups[] = {
2665 "pex_l0_rst_n_pdd1",
2666 "pex_l0_clkreq_n_pdd2",
2669 static const char * const pe_groups[] = {
2673 static const char * const pe1_groups[] = {
2674 "pex_l1_rst_n_pdd5",
2675 "pex_l1_clkreq_n_pdd6",
2678 static const char * const dp_groups[] = {
2682 static const char * const clk_groups[] = {
2686 static const char * const tmds_groups[] = {
2692 static const char * const safe_groups[] = {
2841 "dap_mclk1_req_pee2",
2863 "pex_l0_rst_n_pdd1",
2864 "pex_l0_clkreq_n_pdd2",
2866 "pex_l1_rst_n_pdd5",
2867 "pex_l1_clkreq_n_pdd6",
2875 "sdmmc3_clk_lb_out_pee4",
2876 "sdmmc3_clk_lb_in_pee5",
2881 "usb_vbus_en2_pff1",
2886 #define FUNCTION(fname) \
2889 .groups = fname##_groups, \
2890 .ngroups = ARRAY_SIZE(fname##_groups), \
2893 static const struct tegra_function tegra124_functions[] = {
2905 FUNCTION(displaya_alt),
2908 FUNCTION(extperiph1),
2909 FUNCTION(extperiph2),
2910 FUNCTION(extperiph3),
2934 FUNCTION(reset_out_n),
2968 FUNCTION(vimclk2_alt),
2981 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2982 #define PINGROUP_REG_A 0x3000 /* bank 1 */
2984 #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2985 #define PINGROUP_REG_N(r) -1
2987 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2990 .pins = pg_name##_pins, \
2991 .npins = ARRAY_SIZE(pg_name##_pins), \
2993 TEGRA_MUX_DT_ ## f0, \
2994 TEGRA_MUX_DT_ ## f1, \
2995 TEGRA_MUX_DT_ ## f2, \
2996 TEGRA_MUX_DT_ ## f3, \
2998 .func_safe = TEGRA_MUX_DT_ ## f_safe, \
3005 .func_safe_non_dt = TEGRA_MUX_## f_safe, \
3006 .mux_reg = PINGROUP_REG_Y(r), \
3009 .pupd_reg = PINGROUP_REG_Y(r), \
3012 .tri_reg = PINGROUP_REG_Y(r), \
3015 .einput_reg = PINGROUP_REG_Y(r), \
3018 .odrain_reg = PINGROUP_REG_##od(r), \
3021 .lock_reg = PINGROUP_REG_Y(r), \
3024 .ioreset_reg = PINGROUP_REG_##ior(r), \
3025 .ioreset_bank = 1, \
3027 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
3028 .rcv_sel_bank = 1, \
3031 .drvtype_reg = -1, \
3034 #define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
3035 #define DRV_PINGROUP_DVRTYPE_N(r) -1
3037 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
3038 drvdn_b, drvdn_w, drvup_b, drvup_w, \
3039 slwr_b, slwr_w, slwf_b, slwf_w, \
3042 .name = "drive_" #pg_name, \
3043 .pins = drive_##pg_name##_pins, \
3044 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
3051 .ioreset_reg = -1, \
3052 .rcv_sel_reg = -1, \
3053 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
3056 .schmitt_bit = schmitt_b, \
3057 .lpmd_bit = lpmd_b, \
3058 .drvdn_bit = drvdn_b, \
3059 .drvdn_width = drvdn_w, \
3060 .drvup_bit = drvup_b, \
3061 .drvup_width = drvup_w, \
3062 .slwr_bit = slwr_b, \
3063 .slwr_width = slwr_w, \
3064 .slwf_bit = slwf_b, \
3065 .slwf_width = slwf_w, \
3066 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
3067 .drvtype_bank = 0, \
3069 .drvtype_width = 2, \
3072 static const struct tegra_pingroup tegra124_groups[] = {
3073 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
3074 /* FIXME: Fill in correct data in safe column */
3075 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, SPI3, 0x3000, N, N, N),
3076 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, SPI3, 0x3004, N, N, N),
3077 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, SPI3, 0x3008, N, N, N),
3078 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, SPI3, 0x300c, N, N, N),
3079 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, SPI2, 0x3010, N, N, N),
3080 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, SPI2, 0x3014, N, N, N),
3081 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, SPI2, 0x3018, N, N, N),
3082 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, SPI2, 0x301c, N, N, N),
3083 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3020, N, N, N),
3084 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3024, N, N, N),
3085 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3028, N, N, N),
3086 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, SPI1, 0x302c, N, N, N),
3087 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N),
3088 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N),
3089 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, I2S2, 0x3038, N, N, N),
3090 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, I2S2, 0x303c, N, N, N),
3091 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3040, N, N, N),
3092 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3044, N, N, N),
3093 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD3, 0x3048, N, N, N),
3094 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N),
3095 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N),
3096 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N),
3097 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N),
3098 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, SDMMC1, 0x305c, N, N, N),
3099 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, EXTPERIPH2, 0x3068, N, N, N),
3100 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, DAP, 0x306c, N, N, N),
3101 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3110, N, N, Y),
3102 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3114, N, N, Y),
3103 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3118, N, N, Y),
3104 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N),
3105 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N),
3106 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, UARTA, 0x316c, N, N, N),
3107 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, UARTA, 0x3170, N, N, N),
3108 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3174, N, N, N),
3109 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3178, N, N, N),
3110 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, UARTC, 0x317c, N, N, N),
3111 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, UARTC, 0x3180, N, N, N),
3112 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, RSVD4, 0x3184, N, N, N),
3113 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x3188, N, N, N),
3114 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x318c, N, N, N),
3115 PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, PWM0, 0x3190, N, N, N),
3116 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, PWM1, 0x3194, N, N, N),
3117 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, PWM2, 0x3198, N, N, N),
3118 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, RSVD3, 0x319c, N, N, N),
3119 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a0, Y, N, N),
3120 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a4, Y, N, N),
3121 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, I2S3, 0x31a8, N, N, N),
3122 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31ac, N, N, N),
3123 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, I2S3, 0x31b0, N, N, N),
3124 PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31b4, N, N, N),
3125 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD3, 0x31b8, N, N, N),
3126 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N),
3127 PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N),
3128 PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x31c4, N, N, N),
3129 PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, RSVD1, 0x31c8, N, N, N),
3130 PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, RSVD1, 0x31cc, N, N, N),
3131 PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x31d0, N, N, N),
3132 PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, RSVD1, 0x31d4, N, N, N),
3133 PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, RSVD1, 0x31d8, N, N, N),
3134 PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, GMI, 0x31dc, N, N, N),
3135 PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, GMI, 0x31e0, N, N, N),
3136 PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31e4, N, N, N),
3137 PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x31e8, N, N, N),
3138 PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, RSVD1, 0x31ec, N, N, N),
3139 PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f0, N, N, N),
3140 PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f4, N, N, N),
3141 PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31f8, N, N, N),
3142 PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31fc, N, N, N),
3143 PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, RSVD1, 0x3200, N, N, N),
3144 PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3204, N, N, N),
3145 PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3208, N, N, N),
3146 PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x320c, N, N, N),
3147 PINGROUP(ph0, PWM0, TRACE, GMI, DTV, GMI, 0x3210, N, N, N),
3148 PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, GMI, 0x3214, N, N, N),
3149 PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, GMI, 0x3218, N, N, N),
3150 PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, GMI, 0x321c, N, N, N),
3151 PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3220, N, N, N),
3152 PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3224, N, N, N),
3153 PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, GMI, 0x3228, N, N, N),
3154 PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, GMI, 0x322c, N, N, N),
3155 PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, RSVD2, 0x3230, N, N, N),
3156 PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3234, N, N, N),
3157 PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3238, N, N, N),
3158 PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x323c, N, N, N),
3159 PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x3240, N, N, N),
3160 PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, RSVD1, 0x3244, N, N, N),
3161 PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x3248, N, N, N),
3162 PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, GMI, 0x324c, N, N, N),
3163 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3250, Y, N, N),
3164 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3254, Y, N, N),
3165 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x3258, N, Y, N),
3166 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x325c, N, Y, N),
3167 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3260, N, Y, N),
3168 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3264, N, Y, N),
3169 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3268, N, Y, N),
3170 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x326c, N, Y, N),
3171 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N),
3172 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N),
3173 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N),
3174 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD1, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N),
3175 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N),
3176 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N),
3177 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N),
3178 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N),
3179 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N),
3180 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, VGP3, 0x3298, N, N, N),
3181 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, VGP4, 0x329c, N, N, N),
3182 PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, VGP5, 0x32a0, N, N, N),
3183 PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, I2S4, 0x32a4, N, N, N),
3184 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x32a8, N, N, N),
3185 PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, I2S4, 0x32ac, N, N, N),
3186 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x32b0, N, N, N),
3187 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b4, Y, N, N),
3188 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b8, Y, N, N),
3189 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N),
3190 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N),
3191 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N),
3192 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, KBC, 0x32c8, N, N, N),
3193 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32cc, N, N, N),
3194 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32d0, N, N, N),
3195 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N),
3196 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N),
3197 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N),
3198 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e0, N, N, N),
3199 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e4, N, N, N),
3200 PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32e8, N, N, N),
3201 PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32ec, N, N, N),
3202 PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f0, N, N, N),
3203 PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f4, N, N, N),
3204 PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, KBC, 0x32f8, N, N, N),
3205 PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32fc, N, N, N),
3206 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3300, N, N, N),
3207 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3304, N, N, N),
3208 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N),
3209 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N),
3210 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, RSVD4, 0x3310, N, N, N),
3211 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3314, N, N, N),
3212 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3318, N, N, N),
3213 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD3, 0x331c, N, N, N),
3214 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD2, 0x3324, N, N, N),
3215 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD2, 0x3328, N, N, N),
3216 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD2, 0x332c, N, N, N),
3217 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, RSVD2, 0x3330, N, N, N),
3218 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x3334, N, N, Y),
3219 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N),
3220 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N),
3221 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, I2S0, 0x3340, N, N, N),
3222 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, I2S0, 0x3344, N, N, N),
3223 PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, DAP, 0x3348, N, N, N),
3224 PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD3, 0x334c, N, N, N),
3225 PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3350, N, N, N),
3226 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3354, N, N, N),
3227 PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, I2S1, 0x3358, N, N, N),
3228 PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, I2S1, 0x335c, N, N, N),
3229 PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, I2S1, 0x3360, N, N, N),
3230 PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, I2S1, 0x3364, N, N, N),
3231 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3368, N, N, N),
3232 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, SPI6, 0x336c, N, N, N),
3233 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, SPI6, 0x3370, N, N, N),
3234 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3374, N, N, N),
3235 PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, SPI1, 0x3378, N, N, N),
3236 PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, SPI1, 0x337c, N, N, N),
3237 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, SPI1, 0x3380, N, N, N),
3238 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, SPI1, 0x3384, N, N, N),
3239 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3390, N, N, N),
3240 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N),
3241 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3398, N, N, N),
3242 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N),
3243 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N),
3244 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N),
3245 PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33bc, N, N, N),
3246 PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33c0, N, N, N),
3247 PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, PE, 0x33c4, N, N, N),
3248 PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33cc, N, N, N),
3249 PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33d0, N, N, N),
3250 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, CEC, 0x33e0, Y, N, N),
3251 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N),
3252 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, SDMMC3, 0x33e8, N, N, N),
3253 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N),
3254 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI1, 0x33f0, N, N, N),
3255 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f4, Y, N, N),
3256 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f8, Y, N, N),
3257 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x33fc, N, N, N),
3258 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x3400, N, N, N),
3259 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, SDMMC2, 0x3404, N, N, N),
3260 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD1, 0x3408, N, N, N),
3261 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, KBC, 0x340c, N, N, N),
3262 PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, KBC, 0x3410, N, N, N),
3263 PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, USB, 0x3414, Y, N, N),
3264 PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, RSVD2, 0x3418, Y, N, N),
3265 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, DP, 0x3430, N, N, N),
3267 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
3268 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3269 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3270 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3271 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3272 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3273 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3274 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3275 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3276 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3277 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3278 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3279 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3280 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3281 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3282 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
3283 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3284 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3285 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3286 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3287 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3288 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
3289 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3290 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
3291 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3292 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3293 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3294 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3295 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3296 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3297 DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3298 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3299 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3300 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3301 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3302 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3303 DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
3304 DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3305 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
3306 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3307 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3311 static int tegra124_pinctrl_suspend(u32 *pg_data)
3316 for (i = 0; i < ARRAY_SIZE(tegra124_groups); i++) {
3317 if (tegra124_groups[i].drv_reg < 0)
3318 *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].mux_bank,
3319 tegra124_groups[i].mux_reg);
3321 *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].drv_bank,
3322 tegra124_groups[i].drv_reg);
3328 static void tegra124_pinctrl_resume(u32 *pg_data)
3333 if (tegra_is_dpd_mode) {
3336 for (i = 0; i < ARRAY_SIZE(tegra124_groups); i++) {
3337 if (tegra124_groups[i].drv_reg < 0) {
3339 reg_value |= BIT(4);
3340 tegra_pinctrl_writel(reg_value,
3341 tegra124_groups[i].mux_bank,
3342 tegra124_groups[i].mux_reg);
3346 tegra_pmc_remove_dpd_req();
3347 tegra_is_dpd_mode = false;
3349 for (i = 0; i < ARRAY_SIZE(tegra124_groups); i++) {
3350 if (tegra124_groups[i].drv_reg < 0)
3351 tegra_pinctrl_writel(*ctx++, tegra124_groups[i].mux_bank,
3352 tegra124_groups[i].mux_reg);
3354 tegra_pinctrl_writel(*ctx++, tegra124_groups[i].drv_bank,
3355 tegra124_groups[i].drv_reg);
3357 /* Clear DPD sample */
3358 tegra_pmc_clear_dpd_sample();
3361 static struct tegra_pinctrl_group_config_data t124_pin_drv_group_soc_data[] = {
3362 TEGRA_PINCTRL_SET_DRIVE(dap2, 0, 1, 3, 5, 6, 0, 0, 0),
3363 TEGRA_PINCTRL_SET_DRIVE(dap1, 0, 1, 3, 5, 6, 0, 0, 0),
3364 TEGRA_PINCTRL_SET_DRIVE(dap3, 0, 1, 3, 5, 6, 0, 0, 0),
3365 TEGRA_PINCTRL_SET_DRIVE(dap4, 0, 1, 3, 5, 6, 0, 0, 0),
3366 TEGRA_PINCTRL_SET_DRIVE(dap5, 0, 1, 3, 5, 6, 0, 0, 0),
3367 TEGRA_PINCTRL_SET_DRIVE(dbg, 1, 1, 0, 5, 5, 0, 0, 0),
3368 TEGRA_PINCTRL_SET_DRIVE(at5, 1, 1, 0, 5, 5, 0, 0, 0),
3369 TEGRA_PINCTRL_SET_DRIVE(gme, 1, 1, 0, 5, 5, 0, 0, 0),
3370 TEGRA_PINCTRL_SET_DRIVE(ddc, 1, 1, 0, 5, 5, 0, 0, 0),
3371 TEGRA_PINCTRL_SET_DRIVE(ao1, 1, 1, 0, 5, 5, 0, 0, 0),
3372 TEGRA_PINCTRL_SET_DRIVE(uart2, 0, 0, 3, 0, 0, 3, 3, 0),
3373 TEGRA_PINCTRL_SET_DRIVE(uart3, 0, 0, 3, 0, 0, 3, 3, 0),
3374 TEGRA_PINCTRL_SET_DRIVE(at2, 0, 0, 0, 55, 63, 0, 0, 0),
3375 TEGRA_PINCTRL_SET_DRIVE(uda, 0, 0, 0, 23, 23, 3, 3, 0),
3376 TEGRA_PINCTRL_SET_DRIVE(uaa, 0, 0, 0, 23, 23, 3, 3, 0),
3379 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
3380 .ngpios = NUM_GPIOS,
3381 .pins = tegra124_pins,
3382 .npins = ARRAY_SIZE(tegra124_pins),
3383 .functions = tegra124_functions,
3384 .nfunctions = ARRAY_SIZE(tegra124_functions),
3385 .groups = tegra124_groups,
3386 .ngroups = ARRAY_SIZE(tegra124_groups),
3387 .suspend = tegra124_pinctrl_suspend,
3388 .resume = tegra124_pinctrl_resume,
3389 .config_data = t124_pin_drv_group_soc_data,
3390 .nconfig_data = ARRAY_SIZE(t124_pin_drv_group_soc_data),
3393 static int tegra124_pinctrl_probe(struct platform_device *pdev)
3395 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
3398 static struct of_device_id tegra124_pinctrl_of_match[] = {
3399 { .compatible = "nvidia,tegra124-pinmux", },
3402 MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
3404 static struct platform_driver tegra124_pinctrl_driver = {
3406 .name = "tegra124-pinctrl",
3407 .owner = THIS_MODULE,
3408 .of_match_table = tegra124_pinctrl_of_match,
3410 .probe = tegra124_pinctrl_probe,
3411 .remove = tegra_pinctrl_remove,
3414 static int __init tegra124_pinctrl_init(void)
3416 return platform_driver_register(&tegra124_pinctrl_driver);
3418 postcore_initcall_sync(tegra124_pinctrl_init);
3420 static void __exit tegra124_pinctrl_exit(void)
3422 platform_driver_unregister(&tegra124_pinctrl_driver);
3424 module_exit(tegra124_pinctrl_exit);
3426 MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
3427 MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
3428 MODULE_LICENSE("GPL v2");