_coreEnableEventBusExport_();
/* Enable response to ECC errors indicated by CPU for accesses to flash */
- flashWREG->FEDACCTRL1 = 0x000A060A;
+ /*flashWREG->FEDACCTRL1 = 0x000A060A;*/
/* Enable CPU ECC checking for ATCM (flash accesses) */
- _coreEnableFlashEcc_();
+ /*_coreEnableFlashEcc_();*/
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
* to return the code execution to the instruction following the one that was aborted.
*
*/
+ /*
checkFlashECC();
- flashWREG->FDIAGCTRL = 0x000A0007; /* disable flash diagnostic mode */
+ flashWREG->FDIAGCTRL = 0x000A0007; */ /* disable flash diagnostic mode */
/* Wait for PBIST for CPU RAM to be completed */
while(!pbistIsTestCompleted());