Fix pins multiplexing for RM48

Used peripherals: ADC1, CAN1-3, GIOA, GIOB, HET1, EMIF, SCI
Some pins fron NHET1 port has been disabled, bacause they are shared
with SCI, which is also used.

diff --git a/rpp/include/hal/gpio_tms570_def.h b/rpp/include/hal/gpio_tms570_def.h
index 0bc1805492faeb05528a1f213be79160e080882d..ff3242d5e99165d5b04fdca8bda12fac0019af2b 100644 (file)
--- a/rpp/include/hal/gpio_tms570_def.h
+++ b/rpp/include/hal/gpio_tms570_def.h
@@ -68,7 +68,7 @@ typedef struct pin_map_element {
        uint32_t pin_desc;              // Pin descriptor assigned to the pin name
 } pin_map_element_t;
 
-#define MAX_PIN_CNT     48
+#define MAX_PIN_CNT     46
 #define MAX_PORT_CNT    5
 /* Begin and end indexes of each port group to pin map */
 #define PIN_MAP_GIOA_BEGIN  0

diff --git a/rpp/include/hal/port_def.h b/rpp/include/hal/port_def.h
index 8e75803339e9e9d44e905b8742a0922e6d11bd00..9c85386f66cfabfad1987b55497759bc139b1012 100644 (file)
--- a/rpp/include/hal/port_def.h
+++ b/rpp/include/hal/port_def.h
@@ -73,16 +73,17 @@ typedef struct port_def_st {
 #define PORT_SFC_GIOB           &hal_gio_port_set_val
 #define PORT_INT_TYPE_GIOB      PORT_INTERFACE_GPIO
 
+/* Some pins are commented out, because they are muxed with SCI.  */
 #define PORT_NAME_NHET1          "NHET1"
 #define PORT_CFG_NHET1           { PIN_DSC_NHET1_0, PIN_DSC_NHET1_1, PIN_DSC_NHET1_2, PIN_DSC_NHET1_3, \
-                                                                  PIN_DSC_NHET1_4, PIN_DSC_NHET1_5, PIN_DSC_NHET1_6, PIN_DSC_NHET1_7, \
+                                                                  PIN_DSC_NHET1_4, PIN_DSC_NHET1_5, /*PIN_DSC_NHET1_6,*/ PIN_DSC_NHET1_7, \
                                                                   PIN_DSC_NHET1_8, PIN_DSC_NHET1_9, PIN_DSC_NHET1_10, PIN_DSC_NHET1_11, \
-                                                                  PIN_DSC_NHET1_12, PIN_DSC_NHET1_13, PIN_DSC_NHET1_14, PIN_DSC_NHET1_15, \
+                                                                  PIN_DSC_NHET1_12, /*PIN_DSC_NHET1_13,*/ PIN_DSC_NHET1_14, PIN_DSC_NHET1_15, \
                                                                   PIN_DSC_NHET1_16, PIN_DSC_NHET1_17, PIN_DSC_NHET1_18, PIN_DSC_NHET1_19, \
                                                                   PIN_DSC_NHET1_20, PIN_DSC_NHET1_21, PIN_DSC_NHET1_22, PIN_DSC_NHET1_23, \
                                                                   PIN_DSC_NHET1_24, PIN_DSC_NHET1_25, PIN_DSC_NHET1_26, PIN_DSC_NHET1_27, \
                                                                   PIN_DSC_NHET1_28, PIN_DSC_NHET1_29, PIN_DSC_NHET1_30, PIN_DSC_NHET1_31 }
-#define PORT_NV_NHET1            32
+#define PORT_NV_NHET1            30
 #define PORT_GFC_NHET1           &hal_gio_port_get_val
 #define PORT_SFC_NHET1           &hal_gio_port_set_val
 #define PORT_INT_TYPE_NHET1      PORT_INTERFACE_GPIO

diff --git a/rpp/include/sys/sys_pinmux.h b/rpp/include/sys/sys_pinmux.h
index a0c5b62c1e867a26c1ed9255fe59e63d3e57daba..9600f2700ec93daac7fb191c79e93675b086c739 100644 (file)
--- a/rpp/include/sys/sys_pinmux.h
+++ b/rpp/include/sys/sys_pinmux.h
@@ -8,6 +8,7 @@
 /* (c) Texas Instruments 2009-2012, All rights reserved. */
 
 #include "base.h"
+#include "system.h"
 
 #ifndef __PINMUX_H__
 #define __PINMUX_H__
@@ -604,7 +605,8 @@
 #define PINMUX_BALL_W10_W2FC_RXDI                               (0x4 <<  PINMUX_BALL_W10_SHIFT)
 
 #define PINMUX_GATE_EMIF_CLK                                    (0x0 <<  PINMUX_GATE_EMIF_CLK_SHIFT)      /**/
-#define PINMUX_GIOB_DISABLE_HET2                                (0x1 <<  PINMUX_GIOB_DISABLE_HET2_SHIFT)
+#define PINMUX_GIOB_DISABLE_HET2_ON                             (0x1 <<  PINMUX_GIOB_DISABLE_HET2_SHIFT)
+#define PINMUX_GIOB_DISABLE_HET2_OFF                            (0x0 <<  PINMUX_GIOB_DISABLE_HET2_SHIFT)
 #define PINMUX_ALT_ADC_TRIGGER_1                                (0x1 <<  PINMUX_ALT_ADC_TRIGGER_SHIFT)
 #define PINMUX_ALT_ADC_TRIGGER_2                                (0x2 <<  PINMUX_ALT_ADC_TRIGGER_SHIFT)
 #define PINMUX_ETHERNET_MII                                     (0x0 <<  PINMUX_ETHERNET_SHIFT)

diff --git a/rpp/src/hal/gpio_tms570_def.c b/rpp/src/hal/gpio_tms570_def.c
index 22885673e412137c87828c9a117e666d64946d61..fc22a9473e3406b0573ee92894e76850ef4f45d1 100644 (file)
--- a/rpp/src/hal/gpio_tms570_def.c
+++ b/rpp/src/hal/gpio_tms570_def.c
@@ -38,6 +38,7 @@ gioPORT_t *port_id_map[MAX_PORT_CNT] = {
        (gioPORT_t *)hetPORT2
 };
 
+/* Some pins are commented out, because they are pinmuxed with SCI. */
 /**
  * Map of pin names to pin descriptors. Each pin can be then easily
  * found just by its name given as a string to hal_gpio_get_pin_dsc
@@ -66,14 +67,14 @@ pin_map_element_t pin_map[MAX_PIN_CNT] = {
        { .pin_name = PIN_NAME_NHET1_3, .pin_desc = PIN_DSC_NHET1_3 },
        { .pin_name = PIN_NAME_NHET1_4, .pin_desc = PIN_DSC_NHET1_4 },
        { .pin_name = PIN_NAME_NHET1_5, .pin_desc = PIN_DSC_NHET1_5 },
-       { .pin_name = PIN_NAME_NHET1_6, .pin_desc = PIN_DSC_NHET1_6 },
+       /*{ .pin_name = PIN_NAME_NHET1_6, .pin_desc = PIN_DSC_NHET1_6 },*/
        { .pin_name = PIN_NAME_NHET1_7, .pin_desc = PIN_DSC_NHET1_7 },
        { .pin_name = PIN_NAME_NHET1_8, .pin_desc = PIN_DSC_NHET1_8 },
        { .pin_name = PIN_NAME_NHET1_9, .pin_desc = PIN_DSC_NHET1_9 },
        { .pin_name = PIN_NAME_NHET1_10, .pin_desc = PIN_DSC_NHET1_10 },
        { .pin_name = PIN_NAME_NHET1_11, .pin_desc = PIN_DSC_NHET1_11 },
        { .pin_name = PIN_NAME_NHET1_12, .pin_desc = PIN_DSC_NHET1_12 },
-       { .pin_name = PIN_NAME_NHET1_13, .pin_desc = PIN_DSC_NHET1_13 },
+       /*{ .pin_name = PIN_NAME_NHET1_13, .pin_desc = PIN_DSC_NHET1_13 },*/
        { .pin_name = PIN_NAME_NHET1_14, .pin_desc = PIN_DSC_NHET1_14 },
        { .pin_name = PIN_NAME_NHET1_15, .pin_desc = PIN_DSC_NHET1_15 },
        { .pin_name = PIN_NAME_NHET1_16, .pin_desc = PIN_DSC_NHET1_16 },

diff --git a/rpp/src/sys/sys_pinmux.c b/rpp/src/sys/sys_pinmux.c
index 7370a3ce4a88fe0ff35b155c9385815dba25b3cf..1f7d90f59ed098a192e83c5c727167cfcee6c553 100644 (file)
--- a/rpp/src/sys/sys_pinmux.c
+++ b/rpp/src/sys/sys_pinmux.c
@@ -17,8 +17,8 @@
 #define PINMUX_GATE_EMIF_CLK_ENABLE     \
             pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK
 
-#define PINMUX_GIOB_DISABLE_HET2_ENABLE \
-            pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state)  \
+            (pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state))
 
 #define PINMUX_ALT_ADC_TRIGGER_SELECT(num)  \
             pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
@@ -32,84 +32,80 @@ void muxInit(void){
     kickerReg->KICKER0 = 0x83E70B13;
     kickerReg->KICKER1 = 0x95A4F1E0;
 
-    pinMuxReg->PINMUX0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA;
+    pinMuxReg->PINMUX0 =    PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_HET1_29 | PINMUX_BALL_B2_HET1_27;
 
-    pinMuxReg->PINMUX1 = PINMUX_BALL_E3_MIBSPI3NCS_4 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
+    pinMuxReg->PINMUX1 =    PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
 
-    pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
+    pinMuxReg->PINMUX2 =    PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
 
-    pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
+    pinMuxReg->PINMUX3 =    PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
 
-    pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_SPI4NCS_0;
+    pinMuxReg->PINMUX4 =    PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
 
-    pinMuxReg->PINMUX5 = PINMUX_BALL_K18_SPI4CLK | PINMUX_BALL_W5_SPI4SIMO | PINMUX_BALL_V6_SPI4SOMI | PINMUX_BALL_N5_EMIF_DATA_10;
+    pinMuxReg->PINMUX5 =    PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_EMIF_DATA_10;
 
-    pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
+    pinMuxReg->PINMUX6 =    PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
 
-    pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;
+    pinMuxReg->PINMUX7 =    PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_HET1_25 | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;
 
-    pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MDIO | PINMUX_BALL_N1_MIBSPI1NCS_4 | PINMUX_BALL_R8_EMIF_DATA_15;
+    pinMuxReg->PINMUX8 =    PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_HET1_19 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_EMIF_DATA_15;
 
-    pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
+    pinMuxReg->PINMUX9 = ((~(pinMuxReg->PINMUX9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_HET1_31 | PINMUX_BALL_V10_GIOB_2 | PINMUX_BALL_J3_HET1_21;
 
-    pinMuxReg->PINMUX10 = PINMUX_BALL_N19_MII_RX_ER | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
+    pinMuxReg->PINMUX10 =   PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
 
-    pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_MII_RXD_0;
+    pinMuxReg->PINMUX11 =   PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;
 
-    pinMuxReg->PINMUX12 = PINMUX_BALL_A14_MII_RXD_1 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MII_RXD_2 | PINMUX_BALL_H18_MII_RXD_3;
+    pinMuxReg->PINMUX12 =   PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_HET1_23 | PINMUX_BALL_H18_MIBSPI5NENA;
 
-    pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MII_TXD_0 | PINMUX_BALL_J19_MII_TXD_1 | PINMUX_BALL_H19_MII_TXEN | PINMUX_BALL_R2_MII_TXD_2;
+    pinMuxReg->PINMUX13 =   PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
 
-    pinMuxReg->PINMUX14 = PINMUX_BALL_E18_MII_TXD_3 | PINMUX_BALL_K19_MII_RXCLK | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
+    pinMuxReg->PINMUX14 =   PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
 
-    pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
+    pinMuxReg->PINMUX15 =   PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
 
-    pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
+    pinMuxReg->PINMUX16 =   PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
 
-    pinMuxReg->PINMUX17 = PINMUX_BALL_D19_MII_TX_CLK | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_MII_CRS | PINMUX_BALL_E9_EMIF_ADDR_5;
+    pinMuxReg->PINMUX17 =   PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_EMIF_ADDR_5;
 
-    pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
+    pinMuxReg->PINMUX18 =   PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
 
-    pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_MII_RX_DV | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
+    pinMuxReg->PINMUX19 =   PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
 
-    pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MII_COL | PINMUX_BALL_C9_EMIF_ADDR_11;
+    pinMuxReg->PINMUX20 =   PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_HET1_17 | PINMUX_BALL_C9_EMIF_ADDR_11;
 
-    pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
+    pinMuxReg->PINMUX21 =   PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
 
-    pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
+    pinMuxReg->PINMUX22 =   PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
 
-    pinMuxReg->PINMUX23 =  0x00010100|  /* SPI4SOMI is on ball W6 */
-                               PINMUX_BALL_C6_EMIF_ADDR_8;
+    pinMuxReg->PINMUX23 = ((~(pinMuxReg->PINMUX5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8;
 
-    pinMuxReg->PINMUX24 = 0x01010101;
+    pinMuxReg->PINMUX24 = ((~(pinMuxReg->PINMUX4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMUX4 >> 25U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX20 >> 17U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX8 >> 9U) & 0x00000001U ) << 24U);
 
-    pinMuxReg->PINMUX25 = 0x01010101;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    pinMuxReg->PINMUX25 = ((~(pinMuxReg->PINMUX12 >> 17U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX7 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX0 >> 26U) & 0x00000001U ) << 24U);
 
-    /* Halcogen fix enabling N2HET1[29], N2HET1[31] */
-    pinMuxReg->PINMUX26 = 0x0101 | PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;
-
-    pinMuxReg->PINMUX27 = PINMUX_BALL_E19_DMM_DATA_5 | PINMUX_BALL_B6_DMM_DATA_6 | PINMUX_BALL_E16_DMM_DATA_9 | PINMUX_BALL_H17_DMM_DATA_10;
-
-    pinMuxReg->PINMUX28 = PINMUX_BALL_G17_DMM_DATA_11 | PINMUX_BALL_E17_DMM_DATA_13 | PINMUX_BALL_H16_DMM_DATA_14 | PINMUX_BALL_G16_DMM_DATA_15;
-
-    pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NCS_1;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    pinMuxReg->PINMUX26 = ((~(pinMuxReg->PINMUX0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMUX9 >> 10U) & 0x00000001U ) << 8U) | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
 
+    pinMuxReg->PINMUX27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
 
+    pinMuxReg->PINMUX28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
 
+    pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA;
 
+    PINMUX_GATE_EMIF_CLK_ENABLE;
+    PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
     PINMUX_ALT_ADC_TRIGGER_SELECT(1);
-    PINMUX_ETHERNET_SELECT(MII);
-
-    PINMUX_SET(0,A5,GIOA_0);
-    PINMUX_SET(18,A11,HET1_14);
-    PINMUX_SET(3,B3,HET1_22);
-    PINMUX_SET(1,C2,GIOA_1);
-    PINMUX_SET(21,K2,GIOB_1);
-    PINMUX_SET(0,W10,GIOB_3);
+    PINMUX_ETHERNET_SELECT(RMII);
 
     /* Disable Pin Muxing */
-    kickerReg->KICKER0 = 0x00000000;
-    kickerReg->KICKER1 = 0x00000000;
+    kickerReg->KICKER0 = 0x00000000U;
+    kickerReg->KICKER1 = 0x00000000U;
+
+       /* Bit 31 of register GPREG1 is used to gate off the
+       EMIF module outputs */
+       systemREG1->GPREG1 |= 0x80000;
 }
 
 /*