The same as in previous commit, but for lower layers than the RPP.
This commit refs #1024
rpp_lib_SOURCES_7.0.2_tms570 += \
rpp/src/drv/adc.c \
- rpp/src/drv/dac.c \
rpp/src/drv/din.c \
- rpp/src/drv/emac.c \
- rpp/src/drv/fr_tms570.c \
- rpp/src/drv/fray.c \
- rpp/src/drv/hbridge.c \
- rpp/src/drv/hout.c \
- rpp/src/drv/lout.c \
- rpp/src/drv/mout.c \
rpp/src/drv/sci.c \
rpp/src/hal/gpio_tms570.c \
rpp/src/hal/gpio_tms570_def.c \
rpp/src/hal/pom_vect_remap.c \
rpp/src/hal/port_def.c \
rpp/src/hal/port_gpio.c \
- rpp/src/hal/port_spi.c \
- rpp/src/hal/spi.c \
- rpp/src/hal/spi_resp_transl.c \
- rpp/src/hal/spi_tms570.c \
rpp/src/sys/asm/dabort.asm \
rpp/src/sys/asm/sys_core.asm \
rpp/src/sys/asm/sys_intvecs.asm \
rpp/src/sys/ti_drv_mibspi.c \
rpp/src/sys/ti_drv_sci.c
-
-rpp_lib_SOURCES_7.0.2_tms570 += \
- lwip/src/api/api_lib.c \
- lwip/src/api/api_msg.c \
- lwip/src/api/err.c \
- lwip/src/api/netbuf.c \
- lwip/src/api/netdb.c \
- lwip/src/api/netifapi.c \
- lwip/src/api/sockets.c \
- lwip/src/api/tcpip.c \
- lwip/src/arch/perf.c \
- lwip/src/arch/sys_arch.c \
- lwip/src/core/def.c \
- lwip/src/core/dhcp.c \
- lwip/src/core/dns.c \
- lwip/src/core/inet_chksum.c \
- lwip/src/core/init.c \
- lwip/src/core/ipv4/autoip.c \
- lwip/src/core/ipv4/icmp.c \
- lwip/src/core/ipv4/igmp.c \
- lwip/src/core/ipv4/ip4.c \
- lwip/src/core/ipv4/ip4_addr.c \
- lwip/src/core/ipv4/ip_frag.c \
- lwip/src/core/ipv6/dhcp6.c \
- lwip/src/core/ipv6/ethip6.c \
- lwip/src/core/ipv6/icmp6.c \
- lwip/src/core/ipv6/inet6.c \
- lwip/src/core/ipv6/ip6.c \
- lwip/src/core/ipv6/ip6_addr.c \
- lwip/src/core/ipv6/ip6_frag.c \
- lwip/src/core/ipv6/mld6.c \
- lwip/src/core/ipv6/nd6.c \
- lwip/src/core/mem.c \
- lwip/src/core/memp.c \
- lwip/src/core/netif.c \
- lwip/src/core/pbuf.c \
- lwip/src/core/raw.c \
- lwip/src/core/snmp/asn1_dec.c \
- lwip/src/core/snmp/asn1_enc.c \
- lwip/src/core/snmp/mib2.c \
- lwip/src/core/snmp/mib_structs.c \
- lwip/src/core/snmp/msg_in.c \
- lwip/src/core/snmp/msg_out.c \
- lwip/src/core/stats.c \
- lwip/src/core/sys.c \
- lwip/src/core/tcp.c \
- lwip/src/core/tcp_in.c \
- lwip/src/core/tcp_out.c \
- lwip/src/core/timers.c \
- lwip/src/core/udp.c \
- lwip/src/netif/etharp.c \
- lwip/src/netif/ethernetif.c \
- lwip/src/netif/ppp/auth.c \
- lwip/src/netif/ppp/chap.c \
- lwip/src/netif/ppp/chpms.c \
- lwip/src/netif/ppp/fsm.c \
- lwip/src/netif/ppp/ipcp.c \
- lwip/src/netif/ppp/lcp.c \
- lwip/src/netif/ppp/magic.c \
- lwip/src/netif/ppp/md5.c \
- lwip/src/netif/ppp/pap.c \
- lwip/src/netif/ppp/ppp.c \
- lwip/src/netif/ppp/ppp_oe.c \
- lwip/src/netif/ppp/randm.c \
- lwip/src/netif/ppp/vj.c \
- lwip/src/netif/slipif.c
-
rpp_lib_INCLUDES = \
os/$(rpp_lib_OS)/include \
- rpp/include \
- lwip/src/include \
- lwip/src/include/ipv4 \
- lwip/src/include/ipv6
+ rpp/include
+
+++ /dev/null
-/**
- *
- * @file Fr_GeneralTypes.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef FR_GENERALTYPES_H_
-#define FR_GENERALTYPES_H_
-
-#include "types.h"
-/* Macro definitions */
-
-/* Configuration indexes:
- * Can be passed into API function Fr_ReadCCConfig as parameter Fr_ConfigParamIdx.
- */
-#define FR_CIDX_GDCYCLE 0
-#define FR_CIDX_PMICROPERCYCLE 1
-#define FR_CIDX_PDLISTENTIMEOUT 2
-#define FR_CIDX_GMACROPERCYCLE 3
-#define FR_CIDX_GDMACROTICK 4
-#define FR_CIDX_GNUMBEROFMINISLOTS 5
-#define FR_CIDX_GNUMBEROFSTATICSLOTS 6
-#define FR_CIDX_GDNIT 7
-#define FR_CIDX_GDSTATICSLOT 8
-#define FR_CIDX_GDWAKEUPRXWINDOW 9
-#define FR_CIDX_PKEYSLOTID 10
-#define FR_CIDX_PLATESTTX 11
-#define FR_CIDX_POFFSETCORRECTIONOUT 12
-#define FR_CIDX_POFFSETCORRECTIONSTART 13
-#define FR_CIDX_PRATECORRECTIONOUT 14
-#define FR_CIDX_PSECONDKEYSLOTID 15
-#define FR_CIDX_PDACCEPTEDSTARTUPRANGE 16
-#define FR_CIDX_GCOLDSTARTATTEMPTS 17
-#define FR_CIDX_GCYCLECOUNTMAX 18
-#define FR_CIDX_GLISTENNOISE 19
-#define FR_CIDX_GMAXWITHOUTCLOCKCORRECTFATAL 20
-#define FR_CIDX_GMAXWITHOUTCLOCKCORRECTPASSIVE 21
-#define FR_CIDX_GNETWORKMANAGEMENTVECTORLENGTH 22
-#define FR_CIDX_GPAYLOADLENGTHSTATIC 23
-#define FR_CIDX_GSYNCFRAMEIDCOUNTMAX 24
-#define FR_CIDX_GDACTIONPOINTOFFSET 25
-#define FR_CIDX_GDBIT 26
-#define FR_CIDX_GDCASRXLOWMAX 27
-#define FR_CIDX_GDDYNAMICSLOTIDLEPHASE 28
-#define FR_CIDX_GDMINISLOTACTIONPOINTOFFSET 29
-#define FR_CIDX_GDMINISLOT 30
-#define FR_CIDX_GDSAMPLECLOCKPERIOD 31
-#define FR_CIDX_GDSYMBOLWINDOW 32
-#define FR_CIDX_GDSYMBOLWINDOWACTIONPOINTOFFSET 33
-#define FR_CIDX_GDTSSTRANSMITTER 34
-#define FR_CIDX_GDWAKEUPRXIDLE 35
-#define FR_CIDX_GDWAKEUPRXLOW 36
-#define FR_CIDX_GDWAKEUPTXACTIVE 37
-#define FR_CIDX_GDWAKEUPTXIDLE 38
-#define FR_CIDX_PALLOWPASSIVETOACTIVE 39
-#define FR_CIDX_PCHANNELS 40
-#define FR_CIDX_PCLUSTERDRIFTDAMPING 41
-#define FR_CIDX_PDECODINGCORRECTION 42
-#define FR_CIDX_PDELAYCOMPENSATIONA 43
-#define FR_CIDX_PDELAYCOMPENSATIONB 44
-#define FR_CIDX_PMACROINITIALOFFSETA 45
-#define FR_CIDX_PMACROINITIALOFFSETB 46
-#define FR_CIDX_PMICROINITIALOFFSETA 47
-#define FR_CIDX_PMICROINITIALOFFSETB 48
-#define FR_CIDX_PPAYLOADLENGTHDYNMAX 49
-#define FR_CIDX_PSAMPLESPERMICROTICK 50
-#define FR_CIDX_PWAKEUPCHANNEL 51
-#define FR_CIDX_PWAKEUPPATTERN 52
-#define FR_CIDX_PDMICROTICK 53
-#define FR_CIDX_GDIGNOREAFTERTX 54
-#define FR_CIDX_PALLOWHALTDUETOCLOCK 55
-#define FR_CIDX_PEXTERNALSYNC 56
-#define FR_CIDX_PFALLBACKINTERNAL 57
-#define FR_CIDX_PKEYSLOTONLYENABLED 58
-#define FR_CIDX_PKEYSLOTUSEDFORSTARTUP 59
-#define FR_CIDX_PKEYSLOTUSEDFORSYNC 60
-#define FR_CIDX_PNMVECTOREARLYUPDATE 61
-#define FR_CIDX_PTWOKEYSLOTMODE 62
-#define FR_CIDX_CNT 63
-
-/* Enumerations */
-typedef enum {
- FR_POCSTATE_CONFIG,
- FR_POCSTATE_DEFAULT_CONFIG,
- FR_POCSTATE_HALT,
- FR_POCSTATE_NORMAL_ACTIVE,
- FR_POCSTATE_NORMAL_PASSIVE,
- FR_POCSTATE_READY,
- FR_POCSTATE_STARTUP,
- FR_POCSTATE_LOOPBACK,
- FR_POCSTATE_MONITOR,
- FR_POCSTATE_WAKEUP,
- FR_POCSTATE_INVALID
-} Fr_POCStateType;
-
-typedef enum {
- FR_SLOTMODE_KEYSLOT,
- FR_SLOTMODE_ALL_PENDING,
- FR_SLOTMODE_ALL,
- FR_SLOTMODE_INVALID
-} Fr_SlotModeType;
-
-typedef enum {
- FR_ERRORMODE_ACTIVE,
- FR_ERRORMODE_PASSIVE,
- FR_ERRORMODE_COMM_HALT,
- FR_ERRORMODE_INVALID
-} Fr_ErrorModeType;
-
-typedef enum {
- FR_WAKEUP_UNDEFINED,
- FR_WAKEUP_RECEIVED_HEADER,
- FR_WAKEUP_RECEIVED_WUP,
- FR_WAKEUP_COLLISION_HEADER,
- FR_WAKEUP_COLLISION_WUP,
- FR_WAKEUP_COLLISION_UNKNOWN,
- FR_WAKEUP_TRANSMITTED,
- FR_WAKEUP_INVALID
-} Fr_WakeupStatusType;
-
-typedef enum {
- FR_STARTUP_UNDEFINED,
- FR_STARTUP_COLDSTART_LISTEN,
- FR_STARTUP_INTEGRATION_COLDSTART_CHECK,
- FR_STARTUP_COLDSTART_JOIN,
- FR_STARTUP_COLDSTART_CONSISTENCY_CHECK,
- FR_STARTUP_INTEGRATION_LISTEN,
- FR_STARTUP_INITIALIZE_SCHEDULE,
- FR_STARTUP_INTEGRATION_CONSISTENCY_CHECK,
- FR_STARTUP_COLDSTART_GAP,
- FR_STARTUP_EXTERNAL_STARTUP,
- FR_STARTUP_ABORT,
- FR_STARTUP_COLDSTART_COLLISION_RESOLUTION,
- FR_STARTUP_PREPARE
-} Fr_StartupStateType;
-
-/*
- * These values are used to determine whether a LPdu has been transmitted or not.
- */
-typedef enum {
- FR_TRANSMITTED, /* LPdu has been transmitted */
- FR_NOT_TRANSMITTED /* LPdu has not been transmitted */
-} Fr_TxLPduStatusType;
-
-/*
- * These values are used to determine if a LPdu has been received or not.
- */
-typedef enum {
- FR_RECEIVED, /* LPdu has been received */
- FR_NOT_RECEIVED, /* LPdu has not been received */
- FR_RECEIVED_MORE_DATA_AVAILABLE /* LPdu has been received. More instances of this LPdu are available (FIFO usage). */
-} Fr_RxLPduStatusType;
-
-/*
- * The values are used to reference channels on a CC.
- */
-
-typedef enum {
- FR_CHANNEL_A, /* Refers to channel A of a CC. */
- FR_CHANNEL_B, /* Refers to channel A of a CC. */
- FR_CHANNEL_AB /* Refers to both channel (A and B) of a CC. */
-} Fr_ChannelType;
-
-/* Data structures */
-/**
- * In order for the host to react to POC state changes, this structure provides basic POC states
- */
-typedef struct Fr_POCStatusType_st {
- boolean_t CHIHaltRequest; /**< is used to indicate that a request has been received from the CHI to halt the POC at the end of the communication cycle */
- boolean_t ColdstartNoise; /**< is used to indicate that the STARTUP mechanism completed under noisy channel conditions */
- Fr_ErrorModeType ErrorMode; /**< is used to indicate what error mode the POC is in */
- boolean_t Freeze; /**< is used to indicate that the POC has entered the POC:halt state due to an error condition requiring an immediate halt */
- Fr_SlotModeType SlotMode; /**< is used to indicate what slot mode the POC is in */
- Fr_StartupStateType StartupState; /**< is used to indicate the current substate of the startup procedure */
- Fr_POCStateType State; /**< is used to indicate current state of POC */
- Fr_WakeupStatusType WakeupStatus; /**< is used to indicate the outcome of the execution of the WAKEUP mechanism */
- boolean_t CHIReadyRequest; /**< */
-} Fr_POCStatusType;
-
-#endif /* FR_GENERALTYPES_H_ */
+++ /dev/null
-/**
- * RPP driver implementation for ADC header file.
- *
- * @file adc.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn
- * @author Carlos Jenkins <carlos@jenkins.co.cr>
- */
-
-
-#ifndef __DRV_DAC_H
-#define __DRV_DAC_H
-
-#include "hal/hal.h"
-
-
-/**
- * Send SPI command to DAC.
- *
- * This function translates parameters into a command and sends it through SPI.
- *
- * @param[in] pin The DAC pin number [0-3].
- *
- * @return SPI response if successful.
- * -1 if pin out of range.
- * -2 if value out of range.
- */
-int drv_dac_spi_transfer(uint8_t pin, boolean_t enabled, uint16_t value);
-
-
-#endif /* __DRV_DAC_H */
#include "hal/hal.h"
#include "drv/adc.h"
-#include "drv/dac.h"
#include "drv/din.h"
-#include "drv/fray.h"
-#include "drv/fr_tms570.h"
-#include "drv/hbridge.h"
-#include "drv/hout.h"
-#include "drv/lout.h"
-#include "drv/mout.h"
#include "drv/sci.h"
+++ /dev/null
-#ifndef EMAC_H_
-#define EMAC_H_
-
-#include "netif/etharp.h"
-#include "lwip/sys.h"
-#include "sys/hw_emac.h"
-
-#define EMAC_CTRL_RAM_BASE_m(x) EMAC_CTRL_RAM_ ## x ## _BASE
-#define EMAC_BASE_m(x) EMAC_ ## x ## _BASE
-#define EMAC_CTRL_BASE_m(x) EMAC_CTRL_ ## x ## _BASE
-#define MDIO_BASE_m(x) MDIO_ ## x ## _BASE
-/* -EMAC0- */
-#define EMAC_CTRL_RAM_0_BASE EMAC_CTRL_RAM_BASE
-#define EMAC_0_BASE EMAC_BASE
-#define EMAC_CTRL_0_BASE EMAC_CTRL_BASE
-#define MDIO_0_BASE MDIO_BASE
-/* -EMAC0- end */
-/* EMAC Control RAM size in bytes */
-#ifndef SIZE_EMAC_CTRL_RAM
-#define SIZE_EMAC_CTRL_RAM 0x2000U
-#endif
-
-#define MAC_ADDR_LEN ETHARP_HWADDR_LEN
-
-/* Packet Flags EMAC_Desc - tx and rx */
-#define EMAC_DSC_FLAG_SOP 0x80000000u
-#define EMAC_DSC_FLAG_EOP 0x40000000u
-#define EMAC_DSC_FLAG_OWNER 0x20000000u
-#define EMAC_DSC_FLAG_EOQ 0x10000000u
-#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u
-#define EMAC_DSC_FLAG_PASSCRC 0x04000000u
-/* Packet Flags - in addition to rx */
-#define EMAC_DSC_FLAG_JABBER 0x02000000u
-#define EMAC_DSC_FLAG_OVERSIZE 0x01000000u
-#define EMAC_DSC_FLAG_FRAGMENT 0x00800000u
-#define EMAC_DSC_FLAG_UNDERSIZED 0x00400000u
-#define EMAC_DSC_FLAG_CONTROL 0x00200000u
-#define EMAC_DSC_FLAG_OVERRUN 0x00100000u
-#define EMAC_DSC_FLAG_CODEERROR 0x00080000u
-#define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u
-#define EMAC_DSC_FLAG_CRCERROR 0x00020000u
-#define EMAC_DSC_FLAG_NOMATCH 0x00010000u
-
-/********** TI structs ***********/
-
-/* EMAC TX Buffer descriptor data structure */
-struct emac_tx_bd {
- volatile struct emac_tx_bd *next;
- volatile u8_t *bufptr;
- volatile u32_t bufoff_len;
- volatile u32_t flags_pktlen;
-
- /* helper to know which pbuf this tx bd corresponds to */
- volatile struct pbuf *pbuf;
-};
-
-/* EMAC RX Buffer descriptor data structure */
-struct emac_rx_bd {
- volatile struct emac_rx_bd *next;
- volatile u8_t *bufptr;
- volatile u32_t bufoff_len;
- volatile u32_t flags_pktlen;
-
- /* helper to know which pbuf this rx bd corresponds to */
- volatile struct pbuf *pbuf;
-};
-
-/**
- * Helper struct to hold the data used to operate on a particular
- * receive channel
- */
-struct rxch {
- volatile struct emac_rx_bd *free_head; /* pointer to buffer descriptor which will be associated with new pbuf when new pbuf is obtained */
- volatile struct emac_rx_bd *active_head; /* pointer to buffer descriptor which will be filled by EMAC this pointer is written to HDP (header descriptor pointer) */
- volatile struct emac_rx_bd *active_tail; /* pointer to buffer descriptor which is the last one which has associated pbuf, next bd is NULL */
- u32_t freed_pbuf_len; /* number of bytes which were freed (pbuf_free()) and so we need to allocate them again */
-};
-
-/**
- * Helper struct to hold the data used to operate on a particular
- * transmit channel
- */
-struct txch {
- volatile struct emac_tx_bd *free_head; /* pointer to buffer descriptor ready to be filled and sent */
- volatile struct emac_tx_bd *active_tail; /* pointer to buffer descriptor which is end of packet */
- volatile struct emac_tx_bd *next_bd_to_process; /* pointer to buffer descriptor which will be handled (cleared) when it's been processed (sent) by EMAC */
-};
-
-/**
- * Helper struct to hold private data used to operate the ethernet interface.
- */
-struct hdkif {
- /* emac instance number */
- u32_t inst_num;
-
- u8_t mac_addr[MAC_ADDR_LEN];
-
- /* emac base address */
- u32_t emac_base;
-
- /* emac controller base address */
- volatile u32_t emac_ctrl_base;
- volatile u32_t emac_ctrl_ram;
-
- /* mdio base address */
- volatile u32_t mdio_base;
-
- /* phy parameters for this instance - for future use */
- u32_t phy_addr;
- u32_t (*phy_autoneg)(u32_t, u32_t, u16_t);
- u32_t (*phy_autoneg_start)(u32_t, u32_t, u16_t);
- u32_t (*phy_autoneg_is_done)(u32_t, u32_t);
- u32_t (*phy_partnerability)(u32_t, u32_t, u16_t *);
-
- /* The tx/rx channels for the interface */
- struct txch txch;
- struct rxch rxch;
-#if !NO_SYS
- sys_sem_t goRX;
- sys_sem_t goTX;
-#if PHY_LINK_MONITOR_INT
- sys_sem_t goLink;
-#endif
- uint32_t waitTicksForPHYAneg;
-#endif
-};
-
-/********** end of TI structs ***********/
-
-
-/********************************************** Statistics and Debugging **********************************************/
-#define RPP_ETH_STATS 0
-
-#if RPP_ETH_STATS
-
-#include "types.h"
-
-struct eth_bd {
- volatile unsigned portBASE_TYPE filledTX, handledTX;
- volatile unsigned portBASE_TYPE filledRX, handledRX;
-};
-
-/* pkt means chain of buffer descriptors */
-struct eth_pkt {
- volatile unsigned portBASE_TYPE filledTX, handledTX;
- volatile unsigned portBASE_TYPE filledRX, handledRX;
-};
-
-struct eth_chan {
- volatile struct txch beforeHandled, afterHandled; /* Transmit channel. */
- volatile struct rxch beforeRecv, afterRecv; /* Receive channel. */
-};
-
-struct eth_stats {
- struct eth_bd eth_bd;
- struct eth_pkt eth_pkt;
- struct eth_chan eth_chan;
-};
-
-extern struct eth_stats rpp_eth_stats;
-
-/* notification.c */
-extern volatile int countEMACCore0TxIsr = 0;
-extern volatile int countEMACCore0RxIsr = 0;
-
-void print_tx_channel_stat();
-void print_rx_channel_stat();
-void printStatistics();
-
-#endif /* if RPP_ETH_STATS */
-
-/*
- * checks whether address is in range of CPPI RAM
- */
-boolean_t inCPPI(uint32_t spot);
-
-/********************************************** End of Statistics **********************************************/
-
-#endif /* EMAC_H_ */
+++ /dev/null
-/**
- * FlexRay Communication driver for TMS570 header file.
- *
- * @file fr_tms570.h
- *
- * @copyright Copyright (C) 2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef FR_H_
-#define FR_H_
-
-#include "drv/Std_Types.h"
-#include "drv/Fr_GeneralTypes.h"
-
-/* Protocol constants specific for TMS570 */
-#define cCASActionPointOffset 1 /**< Initialization value of the CAS action point offset timer. Units MT */
-#define cChannelIdleDelimiter 11 /**< Duration of the channel idle delimiter. Units gdBit */
-#define cClockDeviationMax 0.0015 /**< Maximum clock frequency deviation, equivalent to 1500ppm (1500ppm = 1500/1000000 = 0.0015). */
-#define cCrcInitA 0xFEDCBA /**< Initialization vector for the calculation of the frame CRC on channel A (hexadecimal). */
-#define cCrcInitB 0xABCDEF /**< Initialization vector for the calculation of the frame CRC on channel B (hexadecimal). */
-#define cCrcPolynomial 0x5D6DCB /**< Frame CRC polynomial (hexadecimal).*/
-#define cCrcSize 24 /**< Size of the frame CRC calculation register. Units bits. */
-#define cCycleCountMax 63 /**< Maximum cycle counter value in a cluster. */
-#define cdBSS 2 /**< Duration of the Byte Start Sequence. Units gdBit.*/
-#define cdCAS 30 /**< Duration of the logical low portion of the collision avoidance symbol (CAS) and media access test symbol (MTS). Units gdBit. */
-#define cdCASRxLowMin 29 /**< Lower limit of the CAS acceptance window. Units gdBit.*/
-#define cdCycleMax 16000 /**< Maximum cycle length. Units us. */
-#define cdFES 2 /**< Duration of the Frame End Sequence. Units gdBit. */
-#define cdFSS 1 /**< Duration of the Frame Start Sequence. Units gdBit. */
-#define cdMaxMTNom 6 /**< Maximum duration of a nominal macrotick. Each implementation must be able to support macroticks of at least this length. Different implementations may support higher values. Units us. */
-#define cdMinMTNom 1 /**< Minimum duration of a nominal macrotick. Each implementation must be able to support macroticks of at least this length. Different implementations may support lower values. Units us. */
-#define cdWakeupMaxCollision 5 /**< Number of continuous bit times at LOW during the idle phase of a WUS that will cause a sending node to detect a wakeup collision. Units gdBit. */
-#define cdWakeupSymbolTxLow 6 /**< Duration of low phase of a transmitted wakeup symbol. Units us.*/
-#define cdWakeupSymbolTxIdle 18 /**< Duration of the idle phase between two low phases inside a wakeup pattern. Units 18.*/
-#define cHCrcInit 0x01A /**< Initialization vector for the calculation of the header CRC on channel A or channel B (hexadecimal). */
-#define cHCrcPolynomial 0x385 /**< Header CRC polynomial (hexadecimal). */
-#define cHCrcSize 11 /**< Size of header CRC calculation register. Units bit.*/
-#define cPayloadLengthMax 127 /**< Maximum length of the payload segment of a frame. Units two-byte-words.*/
-#define cMicroPerMacroMin 20 /**< Minimum number of microticks per macrotick during the offset correction phase. Units uT.*/
-#define cMicroPerMacroNomMin 40 /**< Minimum number of microticks in a nominal (uncorrected) macrotick. Units uT. */
-#define cMicroPerMacroNomMax 240 /**< Maximum number of microticks in a nominal (uncorrected) macrotick. Units uT. */
-#define cSamplesPerBit 8 /**< Number of samples taken in the determination of a bit value. */
-#define cSlotIDMax 2047 /**< Highest slot ID number. */
-#define cStaticSlotIDMax 1023 /**< Highest static slot ID number. */
-#define cStrobeOffset 5 /**< Sample where bit strobing is performed (first sample of a bit is considered as sample 1). */
-#define cSyncNodeMax 15 /**< Maximum number of sync nodes in a cluster. */
-#define cVotingSamples 5 /**< Numbers of samples in the voting window used for majority voting of the RxD input. */
-#define cVotingDelay (cVotingSamples-1)/2 /**< Number of samples of delay between the RxD input and the majority voted output in the glitch-free case. */
-
-#define FR_MAX_SYNC_FRAME_LIST_SIZE 15
-
-/* Flags for indicating error during parameters check */
-#define ERR_PARAM_NO_ERROR 0
-
-/* Global parameters errors */
-#define ERR_PARAM_gColdStartAttempts (1 << 1)
-#define ERR_PARAM_gdActionPointOffset (1 << 2)
-#define ERR_PARAM_gdCASRxLowMax (1 << 3)
-#define ERR_PARAM_gdDynamicSlotIdlePhase (1 << 4)
-#define ERR_PARAM_gdMinislot (1 << 5)
-#define ERR_PARAM_gdMinislotActionPointOffset (1 << 6)
-#define ERR_PARAM_gdStaticSlot (1 << 7)
-#define ERR_PARAM_gdTSSTransmitter (1 << 8)
-#define ERR_PARAM_gdWakeupSymbolRxIdle (1 << 9)
-#define ERR_PARAM_gdWakeupSymbolRxLow (1 << 10)
-#define ERR_PARAM_gdWakeupSymbolRxWindow (1 << 11)
-#define ERR_PARAM_gdWakeupSymbolTxIdle (1 << 12)
-#define ERR_PARAM_gdWakeupSymbolTxLow (1 << 13)
-#define ERR_PARAM_gListenNoise (1 << 14)
-#define ERR_PARAM_gMacroPerCycle (1 << 15)
-#define ERR_PARAM_gMaxWithoutClockCorrectionFatal (1 << 16)
-#define ERR_PARAM_gMaxWithoutClockCorrectionPassive (1 << 17)
-#define ERR_PARAM_gNumberOfMinislots (1 << 18)
-#define ERR_PARAM_gNumberOfStaticSlots (1 << 19)
-#define ERR_PARAM_gOffsetCorrectionStart (1 << 20)
-#define ERR_PARAM_gPayloadLengthStatic (1 << 21)
-#define ERR_PARAM_gSyncNodeMax (1 << 22)
-#define ERR_PARAM_gdNIT (1 << 23)
-#define ERR_PARAM_gdSampleClockPeriod (1 << 24)
-#define ERR_PARAM_gNetworkManagementVectorLength (1 << 25)
-
-/* Local parameters errors */
-#define ERR_PARAM_pAllowHaltDueToClock (1 << 1)
-#define ERR_PARAM_pAllowPassiveToActive (1 << 2)
-#define ERR_PARAM_pChannels (1 << 3)
-#define ERR_PARAM_pdAcceptedStartupRange (1 << 4)
-#define ERR_PARAM_pClusterDriftDamping (1 << 5)
-#define ERR_PARAM_pDelayCompensationA (1 << 6)
-#define ERR_PARAM_pDelayCompensationB (1 << 7)
-#define ERR_PARAM_pdListenTimeout (1 << 8)
-#define ERR_PARAM_pdMaxDrift (1 << 9)
-#define ERR_PARAM_pExternOffsetCorrection (1 << 10)
-#define ERR_PARAM_pExternRateCorrection (1 << 11)
-#define ERR_PARAM_pKeySlotUsedForStartup (1 << 12)
-#define ERR_PARAM_pKeySlotUsedForSync (1 << 13)
-#define ERR_PARAM_pLatestTx (1 << 14)
-#define ERR_PARAM_pMacroInitialOffsetA (1 << 15)
-#define ERR_PARAM_pMacroInitialOffsetB (1 << 16)
-#define ERR_PARAM_pMicroInitialOffsetA (1 << 17)
-#define ERR_PARAM_pMicroInitialOffsetB (1 << 18)
-#define ERR_PARAM_pMicroPerCycle (1 << 19)
-#define ERR_PARAM_pRateCorrectionOut (1 << 20)
-#define ERR_PARAM_pSingleSlotEnabled (1 << 21)
-#define ERR_PARAM_pWakeupChannel (1 << 22)
-#define ERR_PARAM_pWakeupPattern (1 << 23)
-#define ERR_PARAM_pSamplesPerMicrotick (1 << 24)
-#define ERR_PARAM_pDecodingCorrection (1 << 25)
-#define ERR_PARAM_pOffsetCorrectionOut (1 << 26)
-
-/* Message RAM parameters errors */
-#define ERR_PARAM_statSegmentBufferCount (1 << 1)
-#define ERR_PARAM_dynSegmentBufferCount (1 << 2)
-#define ERR_PARAM_fifoBufferCount (1 << 3)
-#define ERR_PARAM_maxBuffLimit (1 << 4)
-
-/* Buffer configuration parameters errors */
-#define ERR_PARAM_BUFFIFO_NOT_RX (1 << 1)
-#define ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS (1 << 2)
-#define ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS (1 << 3)
-#define ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS (1 << 4)
-#define ERR_PARAM_BUFDYN_FRAMEID_INVALID (1 << 5)
-#define ERR_PARAM_BUFDYN_PAYLOAD_HIGH (1 << 6)
-#define ERR_PARAM_BUFSTAT_FRAMEID_INVALID (1 << 7)
-#define ERR_PARAM_BUFSTAT_PAYLOAD_HIGH (1 << 8)
-#define ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH (1 << 9)
-#define ERR_PARAM_BUFDYN_CHANNELS (1 << 10)
-#define ERR_PARAM_BUFFIFO_PAYLOAD_HIGH (1 << 12)
-#define ERR_PARAM_BUFFIFO_FIDMASK_DIFFERS (1 << 13)
-#define ERR_PARAM_BUFFIFO_PPIT (1 << 14)
-#define ERR_PARAM_BUFFIFO_REJNULLFR_DIFFERS (1 << 15)
-#define ERR_PARAM_BUFFIFO_REJSTATFR_DIFFERS (1 << 16)
-#define ERR_PARAM_BUFFIFO_SLOTID_DIFFERS (1 << 17)
-
-/* Buffer reconfiguration parameters errors */
-#define ERR_PARAM_INVALID_FRAME_ID (1 << 1)
-#define ERR_PARAM_INVALID_CHANNEL (1 << 2)
-#define ERR_PARAM_RECONFIG_NOT_ALLOWED (1 << 3)
-#define ERR_PARAM_NO_BUFFER_FOUND (1 << 4)
-#define ERR_PARAM_PAYLOAD_TOO_BIG (1 << 5)
-
-
-/* Error codes for controller initialization */
-#define FR_INIT_ERR_BAD_PARAM (1 << 26)
-#define FR_INIT_ERR_CLUSTER_CONFIG (1 << 27)
-#define FR_INIT_ERR_NODE_CONFIG (1 << 28)
-#define FR_INIT_ERR_MSGRAM_CONFIG (1 << 29)
-#define FR_INIT_ERR_BUFFPARAM_CONFIG (1 << 30)
-#define FR_INIT_ERR_BUFF_CONFIG (1 << 31)
-
-/* Error flags for startup failures */
-#define FR_STARTUP_ERR_SW_STUP_FOLLOW (1 << 26)
-#define FR_STARTUP_ERR_CSINH_DIS (1 << 27)
-#define FR_STARTUP_ERR_SW_STUP_READY (1 << 28)
-#define FR_STARTUP_ERR_SW_STUP_AS_NCOLD (1 << 29)
-
-/* TMS570 FlexRay related constants */
-#define FR_MAX_BUFFERS_CNT 128
-#define FR_FCS_LISTEN_TIMEOUT 10000000U
-
-/* Macros with constants for FlexRay POC status, read from CCEV register */
-#define FR_POCS_DEFAULT_CONFIG 0x0
-#define FR_POCS_READY 0x1
-#define FR_POCS_NORMAL_ACTIVE 0x2
-#define FR_POCS_NORMAL_PASSIVE 0x3
-#define FR_POCS_HALT 0x4
-#define FR_POCS_MONITOR_MODE 0x5
-#define FR_POCS_LOOPBACK 0xD
-#define FR_POCS_CONFIG 0xF
-#define FR_POCS_WAKEUP_STANDBY 0x10
-#define FR_POCS_WAKEUP_LISTEN 0x11
-#define FR_POCS_WAKEUP_SEND 0x12
-#define FR_POCS_WAKEUP_DETECT 0x13
-#define FR_POCS_STARTUP_PREPARE 0x20
-#define FR_POCS_COLDSTART_LISTEN 0x21
-#define FR_POCS_COLDSTART_COLLISION_RESOLUTION 0x22
-#define FR_POCS_COLDSTART_CONSISTENCY_CHECK 0x23
-#define FR_POCS_COLDSTART_GAP 0x24
-#define FR_POCS_COLDSTART_JOIN 0x25
-#define FR_POCS_INTEGRATION_COLDSTART_CHECK 0x26
-#define FR_POCS_INTEGRATION_LISTEN 0x27
-#define FR_POCS_INTEGRATION_CONSISTENCY_CHECK 0x28
-#define FR_POCS_INITIALIZE_SCHEDULE 0x29
-#define FR_POCS_ABORT_STARTUP 0x2A
-
-/* Macros with constants for Wakeup status read from CCEV register */
-#define FR_WSV_UNDEFINED 0x0
-#define FR_WSV_RECEIVED_HEADER 0x1
-#define FR_WSV_RECEIVED_WUP 0x2
-#define FR_WSV_COLLISION_HEADER 0x3
-#define FR_WSV_COLLISION_WUP 0x4
-#define FR_WSV_COLLISION_UNKNOWN 0x5
-#define FR_WSV_TRANSMITTED 0x6
-
-/* Macros with constants for SPI communication with the bus controller */
-#define FRAY_SPICMD_INIT_VAL 0xFFFF
-#define FRAY_NUM_PORTS 2
-
-/* Macros with flags for buffers configuration */
-#define FRAY_BUF_MBI_EN 0x01
-#define FRAY_BUF_MBI_DIS 0x00
-#define FRAY_BUF_TX_MODE_CONTINUOUS 0x02
-#define FRAY_BUF_TX_MODE_SINGLE 0x00
-#define FRAY_BUF_NM_EN 0x04
-#define FRAY_BUF_NM_DIS 0x00
-#define FRAY_BUF_TX 0x08
-#define FRAY_BUF_RX 0x00
-#define FRAY_BUF_CHB_EN 0x10
-#define FRAY_BUF_CHB_DIS 0x00
-#define FRAY_BUF_CHA_EN 0x20
-#define FRAY_BUF_CHA_DIS 0x00
-#define FRAY_BUF_SFI_EN 0x40
-#define FRAY_BUF_SFI_DIS 0x00
-#define FRAY_BUF_SYNC_EN 0x80
-#define FRAY_BUF_SYNC_DIS 0x00
-#define FRAY_BUF_REJECT_NULL_FRAMES 0x100
-#define FRAY_BUF_ACCEPT_NULL_FRAMES 0x000
-#define FRAY_BUF_REJECT_STATIC_SEGMENT 0x200
-#define FRAY_BUF_ACCEPT_STATIC_SEGMENT 0x000
-#define FRAY_BUF_TXREQ_EN 0x800
-#define FRAY_BUF_TXREQ_DIS 0x000
-
-#define FR_CLUSTER_PARAMS_CNT 25
-#define FR_NODE_PARAMS_CNT 26
-#define FR_MSGRAM_PARAMS_CNT 5
-#define FR_STATIC_BUF_PARAMS_CNT 8
-#define FR_DYNAMIC_BUF_PARAMS_CNT 7
-#define FR_FIFO_BUF_PARAMS_CNT 6
-/**
- * This structure represents global FlexRay cluster parameters.
- * Values of all those parameters have to be equal for all nodes in cluster.
- */
-typedef struct Fr_TMS570LS_ClusterConfigType_st {
- /* Protocol relevant parameters */
- uint8_t gColdStartAttempts; /**< Maximum number of times a node in the cluster is permitted to attempt to start the cluster by initiating schedule synchronization. Range 2-31. */
- uint8_t gdActionPointOffset; /**< Number of macroticks the action point is offset from the beginning of a static slot or symbol window. Range 1-63 MT. */
- uint8_t gdCASRxLowMax; /**< Upper limit of the CAS acceptance window. Range 67-99 MT. */
- uint8_t gdDynamicSlotIdlePhase; /**< Duration of the idle phase within a dynamic slot. Range 0-2 Minislots. */
- uint8_t gdMinislot; /**< Duration of a minislot. Range 2-63 MT */
- uint8_t gdMinislotActionPointOffset; /**< Number of macroticks the minislot action point is offset from the beginning of a minislot. Range 1-31 MT. */
- uint16_t gdStaticSlot; /**< Duration of a static slot. Range 4-661 MT. */
- uint8_t gdTSSTransmitter; /**< Number of bits in the Transmission Start Sequence. Range 3-15 gdBit. */
- uint8_t gdWakeupSymbolRxIdle; /**< Number of bits used by the node to test the duration of the 'idle' portion of a received wakeup symbol. Duration is equal to (gdWakeupSymbolTxIdle - gdWakeupSymbolTxLow)/2 minus a safe part. (Collisions, clock differences, and other effects can deform the Tx-wakeup pattern.) 14-59 gdBit.*/
- uint8_t gdWakeupSymbolRxLow; /**< Number of bits used by the node to test the LOW portion of a received wakeup symbol. This lower limit of zero bits has to be received to detect the LOW portion by the receiver. The duration is equal to gdWakeupSymbolTxLow minus a safe part. (Active stars, clock differences, and other effects can deform the Tx-wakeup pattern.). Range 11-59. */
- uint16_t gdWakeupSymbolRxWindow; /**< The size of the window used to detect wakeups. Detection of a wakeup requires a low and idle period (from one WUS) and a low period (from another WUS) to be detected entirely within a window of this size. The duration is equal to gdWakeupSymbolTxIdle + 2 * gdWakeupSymbolTxLow plus a safe part. (Clock differences and other effects can deform the Tx-wakeup pattern.). Range 76-301 gdBit. */
- uint8_t gdWakeupSymbolTxIdle; /**< Number of bits used by the node to transmit the 'idle' part of a wakeup symbol. The duration is equal to cdWakeupSymbolTxIdle. 45-180 gdBit. */
- uint8_t gdWakeupSymbolTxLow; /**< Number of bits used by the node to transmit the LOW part of a wakeup symbol. The duration is equal to cdWakeupSymbolTxLow. Range 15-60 gdBit. */
- uint8_t gListenNoise; /**< Upper limit for the startup listen timeout and wakeup listen timeout in the presence of noise. It is used as a multiplier of the node parameter pdListenTimeout. Range 2-16. */
- uint16_t gMacroPerCycle; /**< Number of macroticks in a communication cycle. Range 10-16000 MT. */
- uint8_t gMaxWithoutClockCorrectionFatal; /**< Threshold used for testing the vClockCorrectionFailed counter. Defines the number of consecutive even/odd cycle pairs with missing clock correction terms that will cause the protocol to transition from the POC:normal active or POC:normal passive state into the POC:halt state. Range gMaxWithoutClockCorrectionPassive - 15 even/odd cycle pairs */
- uint8_t gMaxWithoutClockCorrectionPassive; /**< Threshold used for testing the vClockCorrectionFailed counter. Defines the number of consecutive even/odd cycle pairs with missing clock correction terms that will cause the protocol to transition from the POC:normal active state to the POC:normal passive state. Note that gMaxWithoutClockCorrectionPassive <= gMaxWithoutClockCorrectionFatal <= 15. Range 1-15 even/odd cycle pairs.*/
- uint16_t gNumberOfMinislots; /**< Number of minislots in the dynamic segment. Range 0-7986. */
- uint16_t gNumberOfStaticSlots; /**< Number of static slots in the static segment. Range 2 - cStaticSlotIDMax. */
- uint16_t gOffsetCorrectionStart; /**< Start of the offset correction phase within the NIT, expressed as the number of macroticks from the start of cycle. Range 9-15999 MT. */
- uint8_t gPayloadLengthStatic; /**< Payload length of a static frame. Range 0 - cPayloadLengthMax two-byte-words. */
- uint8_t gSyncNodeMax; /**< Maximum number of nodes that may send frames with the sync frame indicator bit set to one. Range 2 - cSyncNodeMax. */
- /* Protocol related parameters */
- uint16_t gdNIT; /**< Duration of the Network Idle Time. Range 2-805 MT. */
- uint8_t gdSampleClockPeriod; /**< Sample clock period. 0 = 0.0125, 1 = 0.025, 2 = 0.05 us. */
- uint8_t gNetworkManagementVectorLength; /**< Length of the Network Management vector in a cluster. Range 0-12 bytes */
-} Fr_TMS570LS_ClusterConfigType;
-
-/**
- * This structure represents local parameters of FlexRay node.
- */
-typedef struct Fr_TMS570LS_NodeConfigType_st {
- /* Protocol relevant */
- boolean_t pAllowHaltDueToClock; /**< Boolean flag that controls the transition to the POC:halt state due to a clock synchronization errors. If set to true, the CC is allowed to transition to POC:halt. If set to false, the CC will not transition to the POC:halt state but will enter or remain in the POC:normal passive state (self healing would still be possible). */
- uint8_t pAllowPassiveToActive; /**< Number of consecutive even/odd cycle pairs that must have valid clock correction terms before the CC will be allowed to transition from the POC:normal passive state to POC:normal active state. If set to zero, the CC is not allowed to transition from POC:normal passive to POC:normal active. Range 0-31 even/odd cycle pairs. */
- Fr_ChannelType pChannels; /**< Channels to which the node is connected. */
- uint16_t pdAcceptedStartupRange; /**< Expanded range of measured clock deviation allowed for startup frames during integration. Range 0-1875 uT. */
- uint8_t pClusterDriftDamping; /**< Local cluster drift damping factor used for rate correction. Range 0-20 uT*/
- uint16_t pDelayCompensationA; /**< Value used to compensate for reception delays on the indicated channel. This covers assumed propagation delay up to cPropagationDelayMax for microticks in the range of 0.0125 μs to 0.05 μs. In practice, the minimum of the propagation delays of all sync nodes should be applied. Range 0-200 uT*/
- uint16_t pDelayCompensationB; /**< Value used to compensate for reception delays on the indicated channel. This covers assumed propagation delay up to cPropagationDelayMax for microticks in the range of 0.0125 μs to 0.05 μs. In practice, the minimum of the propagation delays of all sync nodes should be applied. Range 0-200 uT*/
- uint32_t pdListenTimeout; /**< Value for the startup listen timeout and wakeup listen timeout. Although this is a node local parameter, the real time equivalent of this value should be the same for all nodes in the cluster. Range 1284-1283846 uT. */
- uint16_t pdMaxDrift; /**< Maximum drift offset between two nodes that operate with unsynchronized clocks over one communication cycle. Range 2-1923 uT. */
- uint8_t pExternOffsetCorrection; /**< Number of microticks added or subtracted to the NIT to carry out a host-requested external offset correction. Range 0-7 uT. */
- uint8_t pExternRateCorrection; /**< Number of microticks added or subtracted to the cycle to carry out a host-requested external rate correction. Range 0-7 uT. */
- boolean_t pKeySlotUsedForStartup; /**< Flag indicating whether the Key Slot is used to transmit a startup frame. If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true. */
- boolean_t pKeySlotUsedForSync; /**< Flag indicating whether the Key Slot is used to transmit a sync frame. If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true. */
- uint16_t pLatestTx; /**< Number of the last minislot in which a frame transmission can start in the dynamic segment. Range 0-7980 Minislot. */
- uint8_t pMacroInitialOffsetA; /**< Integer number of macroticks between the static slot boundary and the following macrotick boundary of the secondary time reference point based on the nominal macrotick duration. Range 2-68 MT. */
- uint8_t pMacroInitialOffsetB; /**< Integer number of macroticks between the static slot boundary and the following macrotick boundary of the secondary time reference point based on the nominal macrotick duration. Range 2-68 MT. */
- uint8_t pMicroInitialOffsetA; /**< Number of microticks between the closest macrotick boundary described by pMacroInitialOffset[Ch] and the secondary time reference point. The parameter depends on pDelayCompensation[Ch] and therefore it has to be set independently for each channel. Range 0-239 uT. */
- uint8_t pMicroInitialOffsetB; /**< Number of microticks between the closest macrotick boundary described by pMacroInitialOffset[Ch] and the secondary time reference point. The parameter depends on pDelayCompensation[Ch] and therefore it has to be set independently for each channel. Range 0-239 uT. */
- uint32_t pMicroPerCycle; /**< Nominal number of microticks in the communication cycle of the local node. If nodes have different microtick durations this number will differ from node to node. Range 640-640000 uT */
- uint16_t pRateCorrectionOut; /**< Magnitude of the maximum permissible rate correction value. Range 2-1923 uT. */
- uint16_t pOffsetCorrectionOut; /**< Holds the maximum permitted offset correction value to be applied by the internal clock synchronization algorithm. Range 5-3BA2 uT. */
- boolean_t pSingleSlotEnabled; /**< Flag indicating whether or not the node shall enter single slot mode following startup. */
- Fr_ChannelType pWakeupChannel; /**< Channel used by the node to send a wakeup pattern. Range A, B. */
- uint8_t pWakeupPattern; /**< Number of repetitions of the wakeup symbol that are combined to form a wakeup pattern when the node enters the POC:wakeup send state. Range 2-63. */
- /* Protocol related */
- uint8_t pSamplesPerMicrotick; /**< Number of samples per microtick. Range 1,2,4. */
- uint8_t pDecodingCorrection; /**< Decoding correction (in microticks). Range 0xF - 0x8F. */
-} Fr_TMS570LS_NodeConfigType;
-
-/**
- * This structure provides parameters for buffer configuration.
- */
-typedef struct Fr_TMS570LS_BufferConfigType_st {
- uint32_t slotId; /**< Index of the slot in which this buffer will transfer or receive data. */
- uint8_t maxPayload; /**< Maximum data payload in buffer in 2-bytes-words. If lower than global payload maximum value, padding bytes are inserted (zeros). */
- Fr_ChannelType channel; /**< Channel filter control. A&B should not be seleceted for dynamic segment. */
- uint8_t cycleCounterFiltering; /**< Cycle counter filter control. */
- boolean_t isTx; /**< Tx or Rx buffer selector */
- boolean_t singleTransmit; /**< Single-shot or continuous mode selector */
- boolean_t payloadPreambleIndicatorTr; /**< For static segment - indicates that data section contains network management data. For dynamic segment - the first two data bytes can be used for message ID filtering (done manualy by MCU) */
- uint16_t fidMask; /**< USED ONLY FOR FIFO - specifies which of the corresponding frame ID filter bits are relevant for rejection filtering. 1 - ignore the fid bit, 0 - consider the fid bit */
- boolean_t rejectNullFrames; /**< USED ONLY FOR FIFO - Reject every NULL frames. */
- boolean_t rejectStaticSegment; /**< USED ONLY FOR FIFO - Accept only static segment frames. */
- boolean_t msgBufferInterrupt; /**< Enables TX/RX interrupt for corresponding buffer*/
-} Fr_TMS570LS_BufferConfigType;
-
-typedef enum {
- FR_SB_RECONFIG_ENABLED,
- FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED,
- FR_SB_ALL_REC_DISABLED,
- FR_SB_ALL_REC_DISABLED_STAT_TR_DISABLED
-} Fr_TMS570LS_SecureBuffersType;
-
-/**
- * This data type reflect state of the FlexRay driver.
- */
-typedef enum {
- FR_ST_DRV_NOT_INITIALIZED, /**< No initialization procedure was performed, Fr_Init has to be processed at first. */
- FR_ST_DRV_INITIALIZED, /**< Fr_Init procedure was performed, Fr_ControllerInit has to be processed now. */
- FR_ST_CTRL_INITIALIZED /**< Fr_ControllerInit procedure was performed, driver and controller is ready for other actions */
-} Fr_TMS570LS_DriverState;
-
-/**
- * This structure contains the definition of the message RAM
- * configuration parameters.
- */
-typedef struct Fr_TMS570LS_MsgRAMConfig_st {
- uint8_t statSegmentBufferCount; /**< Number of buffers for static segment */
- uint8_t dynSegmentBufferCount; /**< Number of bufferes for dynamic segment */
- uint8_t fifoBufferCount; /**< Number of buffers for Rx fifo */
- boolean_t syncFramePayloadMultiplexEnabled; /**< Selector of Payload multiplexing. 0 - Only message buffer 0 locked against reconfiguration; 1 - Both message buffers 0 and 1 are locked against reconfiguration. */
- Fr_TMS570LS_SecureBuffersType secureBuffers; /**< Secure buffers against reconfiguration selector */
-} Fr_TMS570LS_MsgRAMConfig;
-/*
- * This type contains the definition of the implementation-specific
- * post build configuration structure for FlexRay driver in TMS570LS MCU.
- */
-typedef struct Fr_TMS570LS_ConfigType_st {
- const Fr_TMS570LS_ClusterConfigType *clusterConfiguration;
- const Fr_TMS570LS_NodeConfigType *nodeConfiguration;
- const Fr_TMS570LS_MsgRAMConfig *msgRAMConfig;
- const Fr_TMS570LS_BufferConfigType *staticBufferConfigs;
- const Fr_TMS570LS_BufferConfigType *dynamicBufferConfigs;
- const Fr_TMS570LS_BufferConfigType *fifoBufferConfigs;
-} Fr_ConfigType;
-
-/**
- * @brief Initalizes the Fr.
- *
- * The function Fr_Init shall internally store the configuration
- * address to enable subsequent API calls to access the configuration.
- *
- * @param [in] Fr_ConfigPtr Address to an Fr dependant configuration structure
- * that contains all information for operating the Fr subsequently.
- */
-void Fr_Init(const Fr_ConfigType *Fr_ConfigPtr);
-
-/**
- * @brief Initializes a FlexRay CC.
- *
- * The function Fr_ControllerInit shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Switch CC into ‘POC:config’ (from any other POCState).
- * 2. Configure all FlexRay cluster and node configuration parameters (e.g., cycle
- * length, macrotick duration).
- * 3. Configure all transmit/receive resources (e.g., buffer initialization) according to
- * the frame triggering configuration parameters contained in the FrIf.
- * 4. Switch CC into ‘POC:ready’
- * 5. Return E_OK.
- *
- * @param [in] Fr_ConfigPtr Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Starts communication.
- *
- * The function Fr_StartCommunication shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘RUN’, which initiates the startup procedure
- * within the FlexRay CC.
- * 2. Return E_OK.
- *
- * The function call of Fr_StartCommunication changes the CC POCState to
- * POC:startup which is a transitional state. In the case when communication startup
- * succeeds, the CC wil change the POCState to ‘POC:normal active’ or ‘POC:normal
- * passive’. It is not guaranteed that the FlexRay CC will reside in the ‘POC:normal
- * active’ or ‘POC:normal passive’ state after a call of the function
- * Fr_StartCommunication.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Invokes the CC CHI command ‘ALLOW_COLDSTART’.
- *
- * The function Fr_AllowColdstart shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘ALLOW_COLDSTART’.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Invokes the CC CHI command 'ALL_SLOTS'.
- *
- * The function Fr_AllSlots shall perform the following tasks on
- * FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘ALL_SLOTS’, which requests a switch from key
- * slot only mode to all slots transmission mode at the beginning of the next
- * communication cycle.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Invokes the CC CHI command 'DEFERRED_HALT'.
- *
- * The function Fr_HaltCommunication shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘DEFERRED_HALT’.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-
-Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Invokes the CC CHI command ‘FREEZE‘.
- *
- * The function Fr_AbortCommunication shall perform the
- * following tasks on FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘FREEZE’, which immediately aborts
- * communication (if active) and changes to the POC:halt state from any
- * previous POCState.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Invokes the CC CHI command ‘WAKEUP‘.
- *
- * The function Fr_SendWUP shall perform the following tasks on
- * FlexRay CC Fr_CtrIdx:
- * 1. Invoke the CC CHI command ‘WAKEUP’, which initiates the wakeup
- * transmission procedure on the configured FlexRay channel.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx);
-
-/**
- * @brief Sets a wakeup channel.
- *
- * The function Fr_SetWakeupChannel shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Change the CC’s POCState to POC:config by invoking the CHI command
- * ‘CONFIG’.
- * 2. Configure the wakeup channel according to parameter Fr_ChnlIdx.
- * 3. Change the CC’s POCState to POC:ready again by invoking the CHI
- * command ‘CONFIG_COMPLETE’.
- * 4. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_ChnlIdx Index of FlexRay channel within the context of the FlexRay CC
- * Fr_CtrlIdx. Valid values are FR_CHANNEL_A and FR_CHANNEL_B.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- *
- */
-Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx);
-
-/**
- * @brief Gets the POC status.
- *
- * The function Fr_GetPOCStatus shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Query the CC’s actual POC status by reading the CHI variable ‘vPOC’ and
- * write the result to parameter Fr_POCStatusPtr.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_POCStatusPtr Address the output value is stored to.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType *Fr_POCStatusPtr);
-
-/**
- * @brief Transmits data on the FlexRay network.
- *
- * The function Fr_TransmitTxLPdu shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the transmission of
- * the FlexRay frame identified by Fr_LPduIdx.
- * 2. If the transmit Lpdu supports dynamic payload length (configuration parameter
- * FrIfAllowDynamicLSduLength is set to true), then the transmission
- * resource shall be reconfigured to match the payload length Fr_LsduLength
- * passed to the API. Note that the dynamic payload length is only applicable to
- * frames within the dynamic FlexRay segment.
- * 3. Copy Fr_LsduLength bytes from address Fr_LsduPtr into the FlexRay CC’s
- * transmission resource and then activate it for transmission.
- * 4. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @param [in] Fr_LSduPtr This reference points to a buffer where the assembled LSdu to be
- * transmitted within this LPdu is stored at.
- * @param [in] Fr_LSduLength Determines the length of the data (in Bytes) to be transmitted.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t *Fr_LSduPtr, uint8_t Fr_LSduLength);
-
-/**
- * @brief Cancels the already pending transmission of a LPdu contained in a controllers physical transmit resource (e.g. message buffer).
- *
- * The function Fr_CancelTxLPdu shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the transmission of
- * the FlexRay frame identified by Fr_LpduIdx.
- * 2. If the physical resource figured out is actively pending for transmission, then
- * the transmit request of this particular resource shall be terminated and E_OK
- * returned. If no transmission is pending E_NOT_OK shall be returned,
- * indicating that no such cancelation took place.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx);
-
-/**
- * @brief Receives data from the FlexRay network.
- *
- * The function Fr_ReceiveRxLPdu shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer, a receive-FIFO) mapped to the
- * reception of the FlexRay frame as identified by Fr_LpduIdx.
- * 2. Figure out whether a new FlexRay frame instance has been received within
- * the receive resource as figured in bullet 1. If the receive resource is a FIFO,
- * then consume the first element out of the FIFO.
- * 3. If a new FlexRay frame has been accepted, then copy the received payload
- * data to address Fr_LsduPtr, store the number of bytes copied to
- * Fr_LsduLengthPtr and store the status FR_RECEIVED to
- * Fr_RxLPduStatusPtr. If a FIFO is used as received resource and the FIFO is
- * not empty, then store the status FR_RECEIVED_MORE_DATA_AVAILABLE
- * to Fr_RxLPduStatusPtr.
- * 4. If no new frame has been accepted, then do not copy any payload data to
- * Fr_LsduPtr, write 0 to the parameter Fr_LsduLengthPtr and store the status
- * FR_NOT_RECEIVED to Fr_RxLPduStatusPtr.
- * 5. Return E_OK.
- *
- * Only reconfigurable message buffers can be canceled.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @param [out] Fr_LSduPtr This reference points to the buffer where the LSdu to be received shall be stored.
- * @param [out] Fr_LPduStatusPtr This reference points to the memory location where the status of the LPdu shall be stored.
- * @param [out] Fr_LSduLengthPtr This reference points to the memory location where the length
- * of the LSdu (in bytes) shall be stored. This length represents
- * the number of bytes copied to Fr_LSduPtr.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t *Fr_LSduPtr, Fr_RxLPduStatusType *Fr_LPduStatusPtr, uint8_t *Fr_LSduLengthPtr);
-
-/**
- * @brief Checks the transmit status of the LSdu.
- *
- * The function Fr_CheckTxLPduStatus shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the transmission of
- * the FlexRay frame identified by Fr_LpduIdx.
- * 2. Check whether the transmission resource as figured in bullet 1 is pending for
- * transmission.
- * 3. If a transmission request is pending, then store the status
- * FR_NOT_TRANSMITTED to Fr_TxLPduStatusPtr.
- * 4. If no transmission request is pending, then store the status
- * FR_TRANSMITTED to Fr_TxLPduStatusPtr.
- * 5. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @param [out] Fr_LPduStatusPtr This reference points to the memory location where the status of the LPdu shall be stored.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType *Fr_TxLPduStatusPtr);
-
-
-/**
- * @brief Prepares a LPdu.
- *
- * Function Fr_Init must be called at first to initialize global arrays Fr_BuffersPtrs and Fr_BufferConfigured.
- * Fr_BuffersPtrs contains configuratin data for all buffers and Fr_BufferConfigured holds flags to check if the buffer
- * was or was not configured by some previous calling of this function.
- *
- * Buffers are identified the frame ID on which they should receive or transmit data. The function has to find an index of
- * the buffer in the Fr_BuffersPtrs array. When match between FrameID in the array and Fr_LPduIdx is found, the function
- * configures this buffer and then continues to find others occurences of the same frame ID in the array of config data.
- *
- * The function controlls if the buffer was or was not configured by some previous functin call. Already configured buffers
- * are skipped. For buffer reconfiguration (if allowed) is designed fuction Fr_ReconfigLPdu.
- *
- * The right procedure to configure static/dynamic buffers or FIFO buffers is launched according to the index of the buffer and
- * data stored in message RAM configuration register.
- *
- * The function Fr_PrepareLPdu shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the processing of
- * the FlexRay frame identified by Fr_LpduIdx.
- * 2. Configure the physical resource (a buffer) appropriate for Fr_LpduIdx
- * operation (SlotId, Cycle filter, payload length, header CRC, etc.) if the MCG
- * uses the reconfiguration feature9.
- * 3. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx);
-
-/**
- * @brief Reconfigures a given LPdu according to the parameters (FrameId, Channel, CycleRepetition, CycleOffset, PayloadLength, HeaderCRC) at runtime.
- *
- * The function Fr_ReconfigLPdu shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the processing of
- * the FlexRay frame as identified by Fr_LpduIdx.
- * 2. Configure the physical resource (a buffer) according to the parameters given
- * at the API. The Lpdu direction is statically associated with the Lpdu and
- * cannot be changed by this service.
- * 3. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @param [in] Fr_FrameId FlexRay Frame ID the FrIf_LPdu shall be configured to.
- * @param [in] Fr_ChnlIdx FlexRay Channel the FrIf_LPdu shall be configured to.
- * @param [in] Fr_CycleRepetition Cycle Repetition part of the cycle filter mechanism (1,2,4,8,16,32,64 is allowed)
- * @param [in] Fr_CycleOffset Cycle Offset part of the cycle filter mechanism (0 - Fr_CycleRepetition-1 is allowed)
- * @param [in] Fr_PayloadLength Payloadlength in units of bytes the FrIf_LPduIdx shall be configured to.
- * @param [in] Fr_HeaderCRC This parameter is not used. CRC is calculated automaticaly inside the function.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC);
-
-
-/**
- * @brief Disables the hardware resource of a LPdu for transmission/reception.
- *
- * The function Fr_DisableLPdu shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Figure out the physical resource (e.g., a buffer) mapped to the processing of
- * the FlexRay frame identified by Fr_LpduIdx.
- * 2. Configure the physical resource (a buffer) in a way that it doesn’t take part in
- * the transmission/reception process.
- * 3. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx);
-
-/**
- * @brief Gets the current global FlexRay time.
- *
- * The function Fr_GetGlobalTime shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the current global FlexRay time and write it to the output parameters
- * Fr_CyclePtr and Fr_MacrotickPtr.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t *Fr_CyclePtr, uint16_t *Fr_MacroTickPtr);
-
-/**
- * @brief Gets the network management vector of the last communication cycle.
- *
- * The function Fr_GetNmVector shall perform the following tasks
- * on FlexRay CC Fr_CtrIdx:
- * 1. Read the current accrued network management vector out of the FlexRay CC
- * and then write it to the output parameter Fr_NmVectorPtr. The number of
- * bytes written to the output parameter is constant and is known at configuration
- * time (FrIf configuration parameter FrIfGNetworkManagementVectorLength).
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_NmVectorPtr Address where the NmVector of the last communication cycle shall be stored.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t *Fr_NmVectorPtr);
-
-/**
- * @brief Gets the current number of startup frames seen on the cluster.
- *
- * The function Fr_GetNumOfStartupFrames shall perform the
- * following tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the number of aligned startup frame pairs received or transmitted during
- * the previous double cycle, aggregated across both channels and write it to the
- * output parameter Fr_NumOfStartupFramesPtr.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_NumOfStartupFramesPtr Address where the number of startup frames seen within the last even/odd cycle pair shall be stored.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t *Fr_NumOfStartupFramesPtr);
-
-/**
- * @brief Gets the current number of startup frames seen on the cluster.
- *
- * The function Fr_GetChannelStatus shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the aggregated channel status, NIT status, symbol window status and
- * write it to the output parameter Fr_ChannelAStatusPtr/ Fr_ChannelBStatusPtr.
- * The value of *Fr_ChannelAStatusPtr / *Fr_ChannelBStatusPtr is bitcoded with
- * the following meaning (Bit 0 = LSB, Bit 15 = MSB)13:
- * Bit 0: Channel A/B aggregated channel status vSS!ValidFrame
- * Bit 1: Channel A/B aggregated channel status vSS!SyntaxError
- * Bit 2: Channel A/B aggregated channel status vSS!ContentError
- * Bit 3: Channel A/B aggregated channel status additional communication
- * Bit 4: Channel A/B aggregated channel status vSS!Bviolation
- * Bit 5: Channel A/B aggregated channel status vSS!TxConflict
- * Bit 6: Not used (0)
- * Bit 7: Not used (0)
- * Bit 8: Channel A/B symbol window status data vSS!ValidMTS
- * Bit 9: Channel A/B symbol window status data vSS!SyntaxError
- * Bit 10: Channel A/B symbol window status data vSS!Bviolation
- * Bit 11: Channel A/B symbol window status data vSS!TxConflict
- * Bit 12: Channel A/B NIT status data vSS!SyntaxError
- * Bit 13: Channel A/B NIT status data vSS!Bviolation
- * Bit 14: Not used (0)
- * Bit 15: Not used (0)
- * 2. Reset the aggregated channel status information within the FlexRay controller.
- * 3. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_ChannelAStatusPtr Address where the bitcoded channel A status information shall be stored.
- * @param [out] Fr_ChannelBStatusPtr Address where the bitcoded channel B status information shall be stored.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t *Fr_ChannelAStatusPtr, uint16_t *Fr_ChannelBStatusPtr);
-
-/**
- * @brief Gets the current clock correction values.
- *
- * The function Fr_GetClockCorrection shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the rate correction value (vInterimRateCorrection14) and write it as
- * signed integer to the output parameter Fr_RateCorrectionPtr. Read the offset
- * correction value (vInterimOffsetCorrection15) and write it as signed integer to
- * the output parameter Fr_OffsetCorrectionPtr
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_RateCorrectionPtr Address where the current rate correction value shall be stored.
- * @param [out] Fr_OffsetCorrectionPtr Address where the current offset correction value shall be stored.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t *Fr_RateCorrectionPtr, int32_t *Fr_OffsetCorrectionPtr);
-
-/**
- * @brief Gets a list of syncframes received or transmitted on channel A and channel B via the even and odd communication cycle.
- *
- * The function Fr_ GetSyncFrameList shall perform the following
- * tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the list of syncframes received in the last even communication cycle on
- * channel A and write it as array to the memory location
- * Fr_ChannelAEvenListPtr.
- * Read the list of syncframes received in the last even communication cycle on
- * channel B and write it as array to the memory location
- * Fr_ChannelBEvenListPtr.
- * Read the list of syncframes received in the last odd communication cycle on
- * channel A and write it as array to the memory location
- * Fr_ChannelAOddListPtr.
- * Read the list of syncframes received in the last odd communication cycle on
- * channel B and write it as array to the memory location
- * Fr_ChannelBOddListPtr.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_ListSize Size of the arrays passed via parameters:
- * Fr_ChannelAEvenListPtr
- * Fr_ChannelBEvenListPtr
- * Fr_ChannelAOddListPtr
- * Fr_ChannelBOddListPtr.
- * The service must ensure to not write more entries into those arrays than granted by this parameter.
- * @param [out] Fr_ChannelAEvenListPtr Address the list of syncframes on channel A within the
- * even communication cycle is written to. The exact
- * number of elements written to the list is limited by
- * parameter Fr_ListSize.
- * Unused list elements are filled with the value '0' to indicate that no more syncframe has been seen.
- * @param [out] Fr_ChannelBEvenListPtr Address the list of syncframes on channel B within the
- * even communication cycle is written to. The exact
- * number of elements written to the list is limited by
- * parameter Fr_ListSize.
- * @param [out] Fr_ChannelAOddListPtr Address the list of syncframes on channel A within the
- * odd communication cycle is written to. The exact number
- * of elements written to the list is limited by parameter
- * Fr_ListSize.
- * Unused list elements are filled with the value '0' to indicate that no more syncframe has been seen.
- * @param [out] Fr_ChannelBOddListPtr Address the list of syncframes on channel B within the
- * odd communication cycle is written to. The exact number
- * of elements written to the list is limited by parameter
- * Fr_ListSize.
- * Unused list elements are filled with the value '0' to indicate that no more syncframe has been seen.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t *Fr_ChannelAEvenListPtr, uint16_t *Fr_ChannelBEvenListPtr, uint16_t *Fr_ChannelAOddListPtr, uint16_t *Fr_ChannelBOddListPtr);
-
-/**
- * @brief Gets the wakeup received information from the FlexRay controller.
- *
- * The function Fr_GetWakeupRxStatus shall perform the
- * following tasks on FlexRay CC Fr_CtrIdx:
- * 1. Read the wakeup pattern received indicators for channel A and channel B and
- * write it to the output parameter Fr_WakeupRxStatusPtr. The value of
- * *Fr_WakeupRxStatusPtr is bitcoded with the following meaning (Bit 0 = LSB,
- * Bit 7 = MSB):
- * Bit 0: Wakeup pattern received on channel A (1), otherwise (0)
- * Bit 1: Wakeup pattern received on channel B (1), otherwise (0)
- * Bit 2: Not used (always 0)
- * Bit 3: Not used (always 0)
- * Bit 4: Not used (always 0)
- * Bit 5: Not used (always 0)
- * Bit 6: Not used (always 0)
- * Bit 7: Not used (always 0)
- * 2. Reset the wakeup received indication status information within the FlexRay
- * controller.
- * 3. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [out] Fr_WakeupRxStatusPtr Address where bitcoded wakeup reception status shall be stored.
- * Bit 0: Wakeup received on channel A indicator
- * Bit 1: Wakeup received on channel B indicator
- * Bit 2-7: Unused
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t *Fr_WakeupRxStatusPtr);
-
-/**
- * @brief Sets the absolute FlexRay timer.
- *
- * The function Fr_SetAbsoluteTimer shall perform the following
- * tasks:
- * 1. Program the absolute FlexRay timer Fr_AbsTimerIdx according to the
- * parameters Fr_Cycle and Fr_Offset.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @param [in] Fr_Cycle Absolute cycle the timer shall elapse in.
- * @param [in] Fr_Offset Offset within cycle Fr_Cycle in units of macrotick the timer shall elapse at.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset);
-
-
-/**
- * @brief Stops an absolute timer.
- *
- * The function Fr_CancelAbsoluteTimer shall perform the
- * following tasks:
- * 1. Stop the absolute timer Fr_AbsTimerIdx.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx);
-
-/**
- * @brief Enables the interrupt line of an absolute timer.
- *
- * The function Fr_EnableAbsoluteTimerIRQ shall perform the
- * following tasks:
- * 1. Enable the interrupt line related to timer Fr_AbsTimerIdx.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx);
-
-
-/**
- * @brief Resets the interrupt condition of an absolute timer.
- *
- * The function Fr_AckAbsoluteTimerIRQ shall perform the
- * following tasks:
- * 1. Reset the interrupt condition of absolute timer Fr_AbsTimerIdx.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx);
-
-/**
- * @brief Disables the interrupt line of an absolute timer.
- *
- * The function Fr_DisableAbsoluteTimerIRQ shall perform the
- * following tasks:
- * 1. Disable the interrupt line related to absolute timer Fr_AbsTimerIdx.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx);
-
-/**
- * @brief Gets IRQ status of an absolute timer.
- *
- * The function Fr_GetAbsoluteTimerIRQStatus shall perform the
- * following tasks:
- * 1. Check whether the interrupt of absolute timer Fr_AbsTimerIdx is pending.
- * Write TRUE to output parameter Fr_IRQStatusPtr in case the interrupt is
- * pending, FALSE otherwise.
- * 2. Return E_OK.
- *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_AbsTimerIdx Index of absolute timer within the context of the FlexRay CC.
- * @param [out] Fr_IRQStatusPtr Address the output value is stored to.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t *Fr_IRQStatusPtr);
-
-/**
- * @brief Returns the version information of this module.
- *
- * @param [out] VersioninfoPtr Pointer to where to store the version information of this module.
- */
-void Fr_GetVersionInfo(Std_VersionInfoType *VersioninfoPtr);
-
-
-/**
- * @brief Reads a FlexRay protocol configuration parameter for a particular FlexRay controller out of the module's configuration.
- *
- * The function Fr_ReadCCConfig shall perform the following tasks:
- * 1. Read the value of the configuration parameter requested by
- * Fr_ConfigParamIdx from the configuration and write it to output parameter Fr_ConfigParamValuePtr.
- * 2. Return E_OK.
-
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_ConfigParamIdx Index that identifies the configuration parameter to read. See macros FR_CIDX_<config_parameter_name>.
- * @param [out] Fr_ConfigParamValuePtr Address the output value is stored to.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t *Fr_ConfigParamValuePtr);
-
-/**
- * @brief Function sends prepared command on SPI and stores response
- *
- * @param[in] port Index of flexray 0 or 1
- * @return 0 when success, -1 when bad parameter
- */
-int Fr_spi_transfer(uint8_t port);
-
-/**
- * @brief Returns last spi response of selected fray port
- *
- * @param[in] port Index of flexray 0 or 1
- * @return spi response or -1 when bad parameter
- */
-int Fr_spi_response(uint8_t port);
-
-/**
- * @brief Returns last spi command of selected fray port
- *
- * @param[in] port Index of flexray 0 or 1
- * @return spi command or -1 when bad parameter
- */
-int Fr_spi_get_cmd(uint8_t port);
-
-#endif /* FR_H_ */
+++ /dev/null
-/**
- *
- * @file fray.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef FRAY_H_
-#define FRAY_H_
-
-
-#endif /* FRAY_SPI_H_ */
+++ /dev/null
-/**
- * RPP driver implementation for H-Bridge header file.
- *
- * @file hbridge.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn
- * @author Carlos Jenkins <carlos@jenkins.co.cr>
- */
-
-
-#ifndef __DRV_HBR_H
-#define __DRV_HBR_H
-
-#include "drv/drv.h"
-
-// Watchdog related
-int8_t drv_hbr_wdg_start();
-int8_t drv_hbr_wdg_stop();
-
-// Basic H-Bridge API
-void drv_hbr_set_en(int value);
-void drv_hbr_set_dir(int direction);
-int8_t drv_hbr_pwm_set_signal(double period, uint32_t duty);
-void drv_hbr_pwm_set_duty(uint8_t percent);
-int8_t drv_hbr_pwm_start();
-void drv_hbr_pwm_stop();
-
-// Extended H-Bridge API
-uint32_t drv_hbr_pwm_get_duty();
-double drv_hbr_pwm_get_period();
-int drv_hbr_get_dir();
-int drv_hbr_get_en();
-
-
-#endif /* __DRV_HBR_H */
+++ /dev/null
-/**
- *
- * @file hout.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef HOUT_H_
-#define HOUT_H_
-
-//#include "ti_drv_het.h"
-//#include "hal_port_def.h"
-//#include "FreeRTOS.h"
-//#include "os_task.h"
-//#include "hal_gpio_tms570.h"
-#include "drv/drv.h"
-
-#define HOUT_FAILED 1
-#define HOUT_NOT_ON 2
-#define HOUT_OK 0
-
-void hout_pwm_set_signal(uint8_t hout_id, double period, uint32_t duty);
-int hout_pwm_start(uint8_t hout_id);
-void hout_pwm_stop(uint8_t hout_id);
-uint32_t hout_pwm_get_duty(uint8_t hout_id);
-double hout_pwm_get_period(uint8_t hout_id);
-int hout_fail(uint8_t hout_id);
-
-
-#endif /* HOUT_H_ */
+++ /dev/null
-/**
- *
- * @file lout_spi.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef LOUT_SPI_H_
-#define LOUT_SPI_H_
-
-//#include "sys_common.h"
-//#include "hal_port_def.h"
-#include "drv/drv.h"
-
-// 0b01010101111111110101010111111111
-#define LOUT_SPICMD_INIT_VAL 0x55FF55FF
-
-enum LOUT_CODES {
- LOUT_CODE0 = 1, LOUT_CODE1
-};
-
-void lout_init();
-int lout_set_pin(uint32_t pin, int val);
-int lout_get_pin(uint32_t pin);
-void lout_set_word(uint8_t word);
-uint8_t lout_get_word();
-int lout_spi_transfer();
-uint32_t lout_spi_get_cmd();
-uint32_t lout_spi_get_response();
-
-#endif /* LOUT_SPI_H_ */
+++ /dev/null
-/**
- * RPP driver implementation for MOUT header file.
- *
- * @file mout.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Carlos Jenkins <carlos@jenkins.co.cr>
- */
-
-
-#ifndef __DRV_MOUT_H
-#define __DRV_MOUT_H
-
-#include "hal/hal.h"
-
-// FIXME Document.
-int8_t drv_mout_set(uint8_t pin, uint8_t val);
-int8_t drv_mout_diag(uint8_t pin);
-
-#endif /* __DRV_MOUT_H */
#include "hal/gpio_tms570.h"
#include "hal/port_def.h"
#include "hal/port_gpio.h"
-#include "hal/spi_resp_transl.h"
-#include "hal/spi_tms570.h"
-#include "hal/spi.h"
-#include "hal/port_spi.h"
#endif /* __HAL_H */
#define PORT_CFG_DINSPI { 1, 0 }
#define PORT_NV_DINSPI 3
#define PORT_GFC_DINSPI NULL
-#define PORT_SFC_DINSPI &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_DINSPI NULL
#define PORT_INT_TYPE_DINSPI PORT_INTERFACE_SPI
#define PORT_NAME_HOUTDIAG "HOUTDIAG"
#define PORT_CFG_LOUT { 1, 1 }
#define PORT_NV_LOUT 4
#define PORT_GFC_LOUT NULL
-#define PORT_SFC_LOUT &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_LOUT NULL
#define PORT_INT_TYPE_LOUT PORT_INTERFACE_SPI
#define PORT_NAME_DAC1_2 "DAC12"
#define PORT_CFG_DAC1_2 { 3, 0 }
#define PORT_NV_DAC1_2 2
#define PORT_GFC_DAC1_2 NULL
-#define PORT_SFC_DAC1_2 &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_DAC1_2 NULL
#define PORT_INT_TYPE_DAC1_2 PORT_INTERFACE_SPI
#define PORT_NAME_DAC3_4 "DAC34"
#define PORT_CFG_DAC3_4 { 3, 1 }
#define PORT_NV_DAC3_4 2
#define PORT_GFC_DAC3_4 NULL
-#define PORT_SFC_DAC3_4 &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_DAC3_4 NULL
#define PORT_INT_TYPE_DAC3_4 PORT_INTERFACE_SPI
#define PORT_NAME_DACDREF "DACDREF"
#define PORT_CFG_DACDREF { 3, 2 }
#define PORT_NV_DACDREF 2
#define PORT_GFC_DACDREF NULL
-#define PORT_SFC_DACDREF &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_DACDREF NULL
#define PORT_INT_TYPE_DACDREF PORT_INTERFACE_SPI
#define PORT_NAME_HBR "HBR"
#define PORT_CFG_HBR { 4, 0 }
#define PORT_NV_HBR 2
#define PORT_GFC_HBR NULL
-#define PORT_SFC_HBR &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_HBR NULL
#define PORT_INT_TYPE_HBR PORT_INTERFACE_SPI
#define PORT_NAME_FRAY1 "FRAY1"
#define PORT_CFG_FRAY1 { 4, 1 }
#define PORT_NV_FRAY1 2
#define PORT_GFC_FRAY1 NULL
-#define PORT_SFC_FRAY1 &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_FRAY1 NULL
#define PORT_INT_TYPE_FRAY1 PORT_INTERFACE_SPI
#define PORT_NAME_FRAY2 "FRAY2"
#define PORT_CFG_FRAY2 { 4, 2 }
#define PORT_NV_FRAY2 2
#define PORT_GFC_FRAY2 NULL
-#define PORT_SFC_FRAY2 &hal_spi_port_transfer_command
+/* FIXME: redefine ports */
+#define PORT_SFC_FRAY2 NULL
#define PORT_INT_TYPE_FRAY2 PORT_INTERFACE_SPI
#define PORT_NAME_MOUTEN "MOUTEN"
+++ /dev/null
-/**
- *
- * @file port_spi.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef PORT_SPI_H_
-#define PORT_SPI_H_
-
-//#include "sys_common.h"
-#include "hal/hal.h"
-
-uint32_t hal_spi_port_transfer_command(uint32_t *config, uint32_t num_bytes, const uint32_t *commands);
-
-
-#endif /* PORT_SPI_H_ */
+++ /dev/null
-/**
- *
- * @file spi.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- */
-
-#ifndef _SPI_DRV_H_
-#define _SPI_DRV_H_
-
-//#include "sys_common.h"
-//#include "string.h"
-//#include "cpu_def.h"
-#include "hal/hal.h"
-
-
-UL_LIST_CUST_DEC(spi_rq_queue, spi_drv_t, spi_msg_head_t, rq_queue, node)
-
-/* ------------------------------------------------------------------------- */
-
-//typedef unsigned long spi_isr_lock_level_t;
-//#define spi_isr_lock save_and_cli
-//#define spi_isr_unlock restore_flags
-
-/* ------------------------------------------------------------------------- */
-int spi_transfer(spi_drv_t *ifc, int addr, int rq_len, const void *tx_buf, void *rx_buf);
-//spi_drv_t *spi_find_drv(char *name, int number);
-int spi_msg_rq_ins(spi_drv_t *ifc, spi_msg_head_t *msg);
-
-#endif /* _SPI_DRV_H_ */
+++ /dev/null
-/**
- *
- * @file spi_resp_transl.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef SPI_RESP_TRANSL_H_
-#define SPI_RESP_TRANSL_H_
-
-//#include "hal_port_def.h"
-//#include "cmdproc_utils.h"
-#include "hal/hal.h"
-
-#define NUM_SPI_DEVICES 7
-#define DIN_NUM_GLOB_FD 24
-#define LOUT_NUM_GLOB_FD 28
-#define DAC_NUM_GLOB_FD 1
-#define FRAY_NUM_GLOB_FD 12
-#define HBR_NUM_STATREG_FD 14
-#define HBR_NUM_APPLREG1_FD 15
-#define HBR_NUM_APPLREG2_FD 13
-#define HBR_NUM_APPLREG3_FD 16
-#define HBR_NUM_DIADDR0_FD 10
-#define HBR_NUM_DIADDR1_FD 9
-#define HBR_NUM_DIADDR2_FD 9
-#define HBR_NUM_DIADDR3_FD 16
-
-#define DIN_NUM_CMD_D 1
-#define LOUT_NUM_CMD_D 1
-#define DAC_NUM_CMD_D 1
-#define FRAY_NUM_CMD_D 1
-#define HBR_NUM_CMD_D 12
-
-#define MAX_NUM_ROWS 32
-
-/*masked fields macros*/
-//#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-//#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-
-typedef struct spitr_field_desc_st {
- const char *field_name;
- uint32_t mask;
-} spitr_field_desc_t;
-
-typedef struct spitr_cmd_map_st {
- uint32_t cmd_msk;
- uint32_t command;
- const spitr_field_desc_t *field_desc;
- uint32_t num_fields;
-} spitr_cmd_map_t;
-
-typedef struct spitr_name_map_st {
- const char *spi_name;
- const spitr_cmd_map_t *cmd_map;
- uint32_t num_cmd;
-} spitr_name_map_t;
-
-typedef struct spitr_reg_translate_table_row_st {
- const char *field_name;
- uint32_t value;
-} spitr_reg_translate_table_row_t;
-
-typedef struct spitr_reg_translate_table_st {
- spitr_reg_translate_table_row_t row[MAX_NUM_ROWS];
- uint32_t num_rows;
-} spitr_reg_translate_table_t;
-
-
-const spitr_cmd_map_t *get_spi_cmd_map(const char *spi_port_name, int len, uint32_t *num_cmdDesc);
-const spitr_field_desc_t *get_spi_field_desc(const spitr_cmd_map_t *cmd_map, uint32_t num_cmd, uint32_t cmd, uint32_t *num_fdDesc);
-int spitr_fill_tr_table(const spitr_field_desc_t *fd, uint32_t num_fields, uint32_t value, spitr_reg_translate_table_t *table);
-
-#endif /* SPI_RESP_TRANSL_H_ */
+++ /dev/null
-/**
- *
- * @file spi_resp_transl.h
- *
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * @author Michal Horn <hornmich@fel.cvut.cz>
- */
-
-#ifndef _MYSPI_H_
-#define _MYSPI_H_
-
-//#include "sys_common.h"
-//#include "drv_spi.h"
-#include "ul/ul_list.h"
-#include "hal/hal.h"
-
-#define SPI_IFC_ON 1
-#define SPI_CTRL_WAKE_RQ 1
-
-/* ------------------------------------------------------------------------- */
-
-#define SPI_MSG_FINISHED 0x040
-#define SPI_MSG_ABORT 0x020
-#define SPI_MSG_FAIL 0x010
-
-#define SPI_BR_FORMAT0 1000000 /**< Clock rate for data format 0 in Hz. */
-#define SPI_BR_FORMAT1 1000000 /**< Clock rate for data format 0 in Hz. */
-#define SPI_BR_FORMAT2 1000000 /**< Clock rate for data format 0 in Hz. */
-#define SPI_BR_FORMAT3 1000000 /**< Clock rate for data format 0 in Hz. */
-
-
-struct spi_drv;
-
-typedef int (spi_ctrl_fnc_t)(struct spi_drv *ifc, int ctrl, void *p);
-
-typedef struct spi_msg_head {
- uint16_t flags; // message flags
- uint16_t addr; // message destination address -- used as index into the "address translation table"*/
-
- //uint16_t size_mode; // message frame len and mode
- uint16_t rq_len; // requested transfer length
- const uint8_t *tx_buf; // pointer to TX data
- uint8_t *rx_buf; // pointer to RX data
-
- ul_list_node_t node;
- //struct spi_drv *ifc;
- int (*callback)(struct spi_drv *ifc, int code, struct spi_msg_head *msg); // Called when whole transfer is finished
- long private; // If set -- msg is processed by HW
-} spi_msg_head_t;
-
-typedef struct spi_drv {
- uint16_t flags; // Flags
- //uint16_t self_addr;
- ul_list_head_t rq_queue; // Queue containing MSG requests to process
- spi_msg_head_t *msg_act; // MSG being actually processed
- spi_ctrl_fnc_t *ctrl_fnc; // Device dependent function responsible for sending data
- //long private;
-} spi_drv_t;
-
-/* ------------------------------------------------------------------------- */
-
-typedef unsigned long spi_isr_lock_level_t;
-#define spi_isr_lock save_and_cli
-#define spi_isr_unlock restore_flags
-
-/* ------------------------------------------------------------------------- */
-
-#define spi_compat_REG2 ((spiBASE_compat_t *)0xFFF7F600U)
-#define spi_compat_REG4 ((spiBASE_compat_t *)0xFFF7FA00U)
-#define mibspi_compat_REG1 ((spiBASE_compat_t *)0xFFF7F400U)
-#define mibspi_compat_REG3 ((spiBASE_compat_t *)0xFFF7F800U)
-#define mibspi_compat_REG5 ((spiBASE_compat_t *)0xFFF7FC00U) /* NOT USED ON RPP BOARD */
-
-
-#define SPI_FLG_TXINT_m (1 << 9)
-#define SPI_FLG_RXINT_m (1 << 8)
-
-#define SPI_INT0_TXINTENA_m (1 << 9)
-#define SPI_INT0_RXINTENA_m (1 << 8)
-
-#define SPI_DAT1_CSHOLD_m (1 << 28)
-
-/* Used as CSNR in DATA1 reg */
-enum spiChipSelect {
- SPI_CS_NONE = 0x00FF,
- SPI_CS_0 = 0x00FE,
- SPI_CS_1 = 0x00FD,
- SPI_CS_2 = 0x00FB,
- SPI_CS_3 = 0x00F7,
- SPI_CS_4 = 0x00EF,
- SPI_CS_5 = 0x00DF,
- SPI_CS_6 = 0x00BF,
- SPI_CS_7 = 0x007F,
- SPI_CS_DMM0 = 0x0100,
- SPI_CS_DMM1 = 0x0200,
- SPI_CS_DMM2 = 0x0400
-};
-
-
-
-typedef volatile struct spiBase {
- uint32_t GCR0; /**< 0x0000: Global Control 0 */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
- uint32_t PD : 1U; /**< 0x0006: Power down bit */
- uint32_t : 7U;
- uint32_t LB : 1U; /**< 0x0005: Loop back bit */
- uint32_t : 7U;
- uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
- uint32_t : 7U;
- uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
- uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
- uint32_t : 7U;
- uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
- uint32_t : 7U;
-#else
- uint32_t : 7U;
- uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
- uint32_t : 7U;
- uint32_t LB : 1U; /**< 0x0005: Loop back bit */
- uint32_t : 7U;
- uint32_t PD : 1U; /**< 0x0006: Power down bit */
- uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
- uint32_t : 7U;
- uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
- uint32_t : 7U;
- uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
- uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
-#endif
- uint32_t LVL; /**< 0x000C: Interrupt Level */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
- uint32_t : 8U;
- uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
- uint32_t : 7U;
-#else
- uint32_t : 7U;
- uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
- uint32_t : 8U;
- uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
-#endif
- uint32_t PCFUN; /**< 0x0014: Function Pin Enable */
- uint32_t PCDIR; /**< 0x0018: Pin Direction */
- uint32_t PCDIN; /**< 0x001C: Pin Input Latch */
- uint32_t PCDOUT; /**< 0x0020: Pin Output Latch */
- uint32_t PCSET; /**< 0x0024: Output Pin Set */
- uint32_t PCCLR; /**< 0x0028: Output Pin Clr */
- uint32_t PCPDR; /**< 0x002C: Open Drain Output Enable */
- uint32_t PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
- uint32_t PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
- uint32_t DAT0; /**< 0x0038: Transmit Data */
- uint32_t DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
- uint32_t BUF; /**< 0x0040: Receive Buffer */
- uint32_t EMU; /**< 0x0044: Emulation Receive Buffer */
- uint32_t DELAY; /**< 0x0048: Delays */
- uint32_t CSDEF; /**< 0x004C: Default Chip Select */
- uint32_t FMT0; /**< 0x0050: Data Format 0 */
- uint32_t FMT1; /**< 0x0054: Data Format 1 */
- uint32_t FMT2; /**< 0x0058: Data Format 2 */
- uint32_t FMT3; /**< 0x005C: Data Format 3 */
- uint32_t INTVECT0; /**< 0x0060: Interrupt Vector 0 */
- uint32_t INTVECT1; /**< 0x0064: Interrupt Vector 1 */
- uint32_t SRSEL; /**< 0x0068: Slew Rate Select */
-
- uint32_t PMCTRL; /**< 0x006C: Parallel Mode Control */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
- uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
-#else
- uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
- uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
-#endif
-
- uint32_t RESERVED[48U]; /**< 0x006C to 0x0130: Reserved */
- uint32_t IOLPKTSTCR; /**< 0x0134: IO loopback */
-} spiBASE_compat_t;
-
-
-/* SPI devices connected to SPI interface */
-typedef struct spi_dev {
- unsigned int cs; /* Combination of CS (+GPIO CS) necessary to enable the device */
- unsigned char dfsel; /* Data word format */
- unsigned char wdel; /* Enable the delay counter at the end of the current transaction */
- unsigned char cshold; /* Chip select hold mode */
- unsigned int dlen; /* Data len needed for one complete transfer */
-} spi_dev_t;
-
-/* SPI interface */
-typedef struct spi_tms570_drv {
- spi_drv_t spi_drv;
- spiBASE_compat_t *spi; /* Base Reg. for SPI device register array */
- unsigned txcnt; /* No. of transfered bytes for msg_act */
- unsigned rxcnt; /* No. of received bytes for msg_act */
- spi_dev_t *spi_devs; /* Pointer to table holding information about SPI devices bound to the interface */
- uint32_t transfer_ctrl; /* Transfer configuration -- upper 16 bits of SPIDAT1 register */
-} spi_tms570_drv_t;
-
-//extern spi_tms570_drv_t spi_tms570_ifcs[4];
-//extern spi_dev_t spi_devs[];
-int spi_tms570_init(void);
-
-spi_drv_t *spi_find_drv(char *name, int number);
-
-
-#endif /* _MYSPI_H_ */
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn
- * - Carlos Jenkins <carlos@jenkins.co.cr>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : dac.c
- * Abstract:
- * RPP driver implementation for DAC.
- *
- * References:
- * None
- */
-
-
-#include "drv/dac.h"
-
-#define DAC_PIN_NUM 4
-
-// See mcp4922.pdf p. 24
-// Options:
-// Bit 13: Output Gain Selection bit set = 1x (VOUT = VREF * D/4096)
-// Bit 15: DACA (0) or DACB (1) Selection bit.
-#define DAC1_INIT_VAL (_BV(13) )
-#define DAC2_INIT_VAL (_BV(13) | _BV(15))
-#define DAC3_INIT_VAL (_BV(13) )
-#define DAC4_INIT_VAL (_BV(13) | _BV(15))
-
-/**
- * Pin status for each DAC pin, the structure of each field is defined
- * as spi command structure.
- */
-uint16_t dac_pin_stat[DAC_PIN_NUM] = {
- DAC1_INIT_VAL,
- DAC2_INIT_VAL,
- DAC3_INIT_VAL,
- DAC4_INIT_VAL
-};
-
-/**
- * Port names for each DAC port, to be easily accessible by indexing
- */
-const char *dac_port_names[DAC_PIN_NUM] = {
- PORT_NAME_DAC1_2,
- PORT_NAME_DAC1_2,
- PORT_NAME_DAC3_4,
- PORT_NAME_DAC3_4
-};
-
-/**
- * Command for SPI
- */
-static uint32_t dac_spi_cmd;
-/**
- * Shadow variable of SPI command
- */
-static uint32_t dac_spi_cmd_sh;
-
-int drv_dac_spi_transfer(uint8_t pin, boolean_t enabled, uint16_t value)
-{
- // Check pin range
- if (pin >= DAC_PIN_NUM)
- return -1;
-
- // Check value range
- if (value > 4095)
- return -2;
-
- // Prepare command
- if (enabled)
- bit_set(dac_pin_stat[pin], 12);
- else
- bit_clear(dac_pin_stat[pin], 12);
-
- dac_pin_stat[pin] = dac_pin_stat[pin] & 0xF000;
- dac_pin_stat[pin] |= (value & 0xFFF);
-
- uint32_t commands[2];
-
- // Warning!!! Can be "optimized" by compiler
- dac_spi_cmd = dac_pin_stat[pin];
- dac_spi_cmd_sh = dac_spi_cmd;
- //--
- port_desc_t *desc;
- desc = hal_port_get_dsc(dac_port_names[pin], -1);
- commands[0] = (dac_spi_cmd_sh & 0xFF00) >> 8;
- commands[1] = (dac_spi_cmd_sh & 0xFF);
-
- return desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Created on: Aug 23, 2013
- *
- * Authors:
- * - Jan Dolezal
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : emac.c
- *
- * Abstract:
- * This file contains functions and shared variables for Statistics
- *
- */
-
-#include "drv/emac.h"
-
-#if RPP_ETH_STATS
-
-/**
- * when true, bd was already handled after sent
- * when false, bd wasn't sent yet or it wasn't handled yet
- */
-volatile boolean_t tx_bd_handled = FALSE, received = FALSE;
-
-struct eth_stats rpp_eth_stats;
-
-void print_tx_channel_stat()
-{
- rpp_sci_printf("Transmit:\n");
- rpp_sci_printf("\t\tbeforeHandled\tafterHandled\n");
- rpp_sci_printf("active_tail:\t0x%08x\t0x%08x\n", rpp_eth_stats.eth_chan.beforeHandled.active_tail, rpp_eth_stats.eth_chan.afterHandled.active_tail);
- rpp_sci_printf("free_head:\t0x%08x\t0x%08x\n", rpp_eth_stats.eth_chan.beforeHandled.free_head, rpp_eth_stats.eth_chan.afterHandled.free_head);
- rpp_sci_printf("nxt_bd_to_proc:\t0x%08x\t0x%08x\n\n", rpp_eth_stats.eth_chan.beforeHandled.next_bd_to_process, rpp_eth_stats.eth_chan.afterHandled.next_bd_to_process);
-}
-
-void print_rx_channel_stat()
-{
- rpp_sci_printf("Receive:\n");
- rpp_sci_printf("\t\tbeforeRecv\tafterRecv\n");
- rpp_sci_printf("active_head:\t0x%08x\t0x%08x\n", rpp_eth_stats.eth_chan.beforeRecv.active_head, rpp_eth_stats.eth_chan.afterRecv.active_head);
- rpp_sci_printf("active_tail:\t0x%08x\t0x%08x\n", rpp_eth_stats.eth_chan.beforeRecv.active_tail, rpp_eth_stats.eth_chan.afterRecv.active_tail);
- rpp_sci_printf("free_head:\t0x%08x\t0x%08x\n", rpp_eth_stats.eth_chan.beforeRecv.free_head, rpp_eth_stats.eth_chan.afterRecv.free_head);
- rpp_sci_printf("freed_pbuf_len:\t%d\t\t%d\n\n", rpp_eth_stats.eth_chan.beforeRecv.freed_pbuf_len, rpp_eth_stats.eth_chan.afterRecv.freed_pbuf_len);
-}
-
-void printStatistics()
-{
- rpp_sci_printf("BDs:\t\tTX\tRX\n");
- rpp_sci_printf("NO of filled PKTs:\t%d\t%d\n", rpp_eth_stats.eth_pkt.filledTX, rpp_eth_stats.eth_pkt.filledRX);
- rpp_sci_printf("NO of sent PKTs:\t%d\t%d\n", rpp_eth_stats.eth_pkt.handledTX, rpp_eth_stats.eth_pkt.handledRX);
- rpp_sci_printf("NO of filled BDs:\t%d\t%d\n", rpp_eth_stats.eth_pkt.filledTX, rpp_eth_stats.eth_pkt.filledRX);
- rpp_sci_printf("NO of sent BDs:\t%d\t%d\n", rpp_eth_stats.eth_pkt.handledTX, rpp_eth_stats.eth_pkt.handledRX);
- rpp_sci_printf("\n");
-}
-
-#endif /* if RPP_ETH_STATS */
-
-boolean_t inCPPI(uint32_t spot)
-{
- if ((uint32_t)spot >= EMAC_CTRL_RAM_BASE_m(0) && (uint32_t)spot < EMAC_CTRL_RAM_BASE_m(0)+SIZE_EMAC_CTRL_RAM)
- return TRUE;
- else
- return FALSE;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : fr_rms570.c
- *
- * Abstract:
- * FlexRay Communication driver for TMS570 source file.
- */
-
-#include "drv/fr_tms570.h"
-#include "sys/ti_drv_fray.h"
-#include "binary.h"
-#include "hal/port_def.h"
-
-/**
- * The structure maps a RX/TX buffer to a slot in the communication cycle.
- * Each buffer has its default values, which are defined in buffer_ptr during
- * initialization. Those values are here for reinitialization of the driver
- * after HALT or to provide some maximum for reconfiguration functions.
- */
-typedef struct Fr_slot_buffer_map_st {
- const Fr_TMS570LS_BufferConfigType *buffer_ptr; /**< Address of a buffer configuration assigned to the slot slot_id */
- /*
- * TODO:
- * slot_id is not unique enough. It should be implemented to not only recognize a slot id, but even to count with cycle period (cyc_filter) of
- * the messages and maybe with the channel.
- *
- * Now the user is not able to configure and use more than one buffer in one slot, which is acceptable for period (cyc_filter) 1.
- * But sometimes user may want to configure the first buffer to send messages in slot 1 with period 2 and the second buffer to
- * send messages in slot 1 with period 2 and offset 1 (interleaved messages from two buffers), which is not possible now.
- *
- * When the identifier slot_id will count with cycle period, channel and slot id, everything should be OK and no further patches
- * to the software should be needed.
- *
- */
- uint16_t slot_id; /**< An ID of the slot in the communication cycle. The value may not be equal to the slot_id value in the buffer configuration, after reconfiguration is done. */
- uint8_t act_payload; /**< The actual maximum payload, that was set for the buffer by reconfiguration function. The value can be equal or lower than max_payload in buffer_ptr. */
- uint32_t act_cyc_filter; /**< Actual cycle set filter. */
- Fr_ChannelType act_ch_filter; /**< Actual channel filter. */
-} Fr_slot_buffer_map_t;
-
-static Std_VersionInfoType Fr_versionInfo = {
- .vendorID = 0x00000001,
- .moduleID = 0x00000002,
- .sw_major_version = 0,
- .sw_minor_version = 1,
- .sw_patch_version = 0
-};
-
-/** Prepared spi command */
-static uint32_t fray_spi_cmd = FRAY_SPICMD_INIT_VAL;
-/** Shadow variable used during command sending */
-static uint32_t fray_spi_cmd_sh;
-/** Array of responses for each fray driver */
-static uint32_t fray_spi_resp[FRAY_NUM_PORTS];
-/** Array of port names to be easily accessible by indexing */
-static const char *fray_port_names[FRAY_NUM_PORTS] = { PORT_NAME_FRAY1, PORT_NAME_FRAY2 };
-/** Array of integers, where FlexRay cluster and node configuration
- * parameters are stored to be accessible by indexes defined in Fr_GeneralTypes.h.
- */
-static uint32_t Fr_ConfigParPtrs[FR_CIDX_CNT];
-/**
- * Address of the unified structure with complete configuration of
- * the FlexRay node (cluster, node, message RAM and buffer configuration)
- */
-static const Fr_ConfigType *Fr_Config;
-/** Map of the buffers to their slot ID */
-static Fr_slot_buffer_map_t Fr_buffer_slot_map[FR_MAX_BUFFERS_CNT];
-/** Array of flags to determine if the buffer was or was not configured. */
-static boolean_t Fr_BuffersConfigured[FR_MAX_BUFFERS_CNT];
-/** Array of computed data pointers addresses for each buffer. */
-static int Fr_MsgRAMDataPtrs[FR_MAX_BUFFERS_CNT];
-/**
- * Address of the next free position in message RAM, which can be assigned
- * to configured buffer. Addresses 32b words.
- */
-static uint32_t Fr_MsgRAMDataOffset;
-/**
- * Address of the first free position in message RAM, which can be assigned
- * to the first configured buffer. Addresses 32b words.
- */
-static uint32_t Fr_MsgRAMDataStartAddress;
-
-/**
- * Development error detection.
- * Comment this line to disable error detection and make function processing
- * faster, but more dangerous.
- */
-#define DET_ACTIVATED
-
-/**
- * How much times should be the CC test repeated
- *
- * The CC test verifies the values written to the FlexRay configuration registers.
- */
-uint32_t FrCtrlTestCount = 50;
-
-/**
- * Fr_PrepareLPdu and Fr_ReconfigLPdu functions enabled
- *
- * If the value of this variable is false, the only one API function that is allowed to configure buffers is the Fr_ControllerInit.
- */
-boolean_t FrBufferReconfig = TRUE;
-
-#ifdef DET_ACTIVATED
-/**
- * A variable for driver state monitoring. The state value is used in several
- * functions to determine if they are called in right order.
- */
-static Fr_TMS570LS_DriverState Fr_DrvState = FR_ST_DRV_NOT_INITIALIZED;
-#endif
-
-/**
- * Create flags according to the index of the buffer, its configuration and node configuration.
- * Flags created by this function are used in buffer configuration and reconfiguration functions.
- *
- * @param[in] buffer_cfg_ptr Address of the buffer configuration parameters
- * @param[in] index of the buffer to which belong the parameters
- *
- * @return Buffer configuration flags. Their definition can be found in fr_tms570.h file as macros with prefixes FRAY_BUF_
- */
-uint32_t Fr_buffer_config_flags(const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr, uint8_t bufferIndex)
-{
- uint32_t mode = 0;
-
- mode = (buffer_cfg_ptr->msgBufferInterrupt == TRUE) ? FRAY_BUF_MBI_EN : FRAY_BUF_MBI_DIS;
- mode |= (buffer_cfg_ptr->singleTransmit == TRUE) ? FRAY_BUF_TX_MODE_SINGLE : FRAY_BUF_TX_MODE_CONTINUOUS;
- mode |= (buffer_cfg_ptr->payloadPreambleIndicatorTr == TRUE) ? FRAY_BUF_NM_EN : FRAY_BUF_NM_DIS;
- mode |= (buffer_cfg_ptr->isTx == TRUE) ? FRAY_BUF_TX : FRAY_BUF_RX;
- mode |= (buffer_cfg_ptr->channel == FR_CHANNEL_A || buffer_cfg_ptr->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHA_EN : FRAY_BUF_CHA_DIS;
- mode |= (buffer_cfg_ptr->channel == FR_CHANNEL_B || buffer_cfg_ptr->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHB_EN : FRAY_BUF_CHB_DIS;
- mode |= (buffer_cfg_ptr->rejectNullFrames == TRUE) ? FRAY_BUF_REJECT_NULL_FRAMES : FRAY_BUF_ACCEPT_NULL_FRAMES;
- mode |= (buffer_cfg_ptr->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
- mode |= FRAY_BUF_TXREQ_DIS;
- if (bufferIndex == 0 || (bufferIndex == 1 && Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled == TRUE)) { // Buffer 0 is always a key slot, if payload multiplexing is enabled, then buffer 1 serves for key slot as well.
- if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] == 1)
- mode |= FRAY_BUF_SFI_EN;
- if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] == 1)
- mode |= FRAY_BUF_SYNC_EN;
- }
- return mode;
-}
-
-/**
- * Buffer is reconfigurable if it is not assigned to the key slot (slot for
- * synchronization and startup) and reconfiguration is enabled in ode configuration
- * parameters.
- * RX FIFO buffer is never configurable.
- *
- * @return -1 if buffer reconfiguration is prohibited, otherwise returns index of the first buffer, which is reconfigurable.
- */
-int Fr_reconfigurable_buffer_index()
-{
- int lowest_index = -1;
-
- if (Fr_Config->msgRAMConfig->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
- lowest_index = frayREG->MRC_UN.MRC_ST.fdb_B8;
- else if (Fr_Config->msgRAMConfig->secureBuffers == FR_SB_RECONFIG_ENABLED) {
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE ||
- Fr_Config->nodeConfiguration->pSingleSlotEnabled == TRUE
- ) {
- if (Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled)
- lowest_index = 2;
- else
- lowest_index = 1;
- }
- else
- lowest_index = 0;
- }
- else
- lowest_index = -1;
- return lowest_index;
-}
-
-/**
- * Compute CRC for message RAM header data
- *
- * @param[in] Fr_LPduPtr Pointer to header data
- * @return CRC code
- */
-static int Fr_header_crc_calc(const wrhs *Fr_LPduPtr)
-{
- unsigned int header;
-
- int CrcInit = 0x1A;
- int length = 20;
- int CrcNext;
- unsigned long CrcPoly = 0x385;
- unsigned long CrcReg_X = CrcInit;
- unsigned long header_temp, reg_temp;
-
- header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
- header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
-
- header <<= 11;
- CrcReg_X <<= 21;
- CrcPoly <<= 21;
-
- while (length--) {
- header <<= 1;
- header_temp = header & 0x80000000;
- reg_temp = CrcReg_X & 0x80000000;
-
- if (header_temp ^ reg_temp) // Step 1
- CrcNext = 1;
- else
- CrcNext = 0;
-
- CrcReg_X <<= 1; // Step 2
-
- if (CrcNext)
- CrcReg_X ^= CrcPoly; // Step 3
- }
-
- CrcReg_X >>= 21;
-
- return CrcReg_X;
-}
-
-/**
- * Retrieve data and header from message buffer into output buffer.
- *
- * Upper software layers have to read the header and data from RDDS and RDHS registers.
- * @param[in] buf_num Number of buffer
- */
-static void Fr_buffer_receive_data_header(uint32_t buf_num)
-{
- bc read_buffer;
-
- read_buffer.obrs = buf_num; // output buffer number
- read_buffer.rdss = 1; // read data section
- read_buffer.rhss = 1; // read header section
-
- // ensure no transfer in progress on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0) ;
- frayREG->OBCM_UN.OBCM_UL = (((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL = ((1 << 9) | (read_buffer.obrs & 0x3F)); //req=1, view=0
- // wait for completion on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0) ;
-
- frayREG->OBCM_UN.OBCM_UL = (((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL = ((1 << 8) | (read_buffer.obrs & 0x3F)); //req=0, view=1
-}
-
-/**
- * Transfer data to the message RAM using the input buffer
- *
- * @param[in] Fr_LSduPtr Pointer to data structure with input buffer settings
- */
-inline void Fr_transmit_tx_LPdu(const bc *Fr_LSduPtr)
-{
- // ensure nothing is pending
- while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0) ;
- frayREG->IBCM_UN.IBCM_UL = ((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
- frayREG->IBCR_UN.IBCR_UL = (Fr_LSduPtr->ibrh & 0x3F);
- // optimization possible for future by not gating like below
- // wait for completion on host registers
- while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0)) ;
- // wait for completion on shadow registers
- while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0)) ;
-}
-
-/**
- * Fill the buffer configuration data structure with given data and transfer it to the message RAM header using the input buffer.
- *
- * @param[in] buf_num number of buffer to be configured (0-128)
- * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
- * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
- * @param[in] frame_id Id of the frame to be associated with the buffer
- * @param[in] payload Maximum data size in half-word
- * @param[in] data_pointer Address of the first word of data in buffer
- */
-static void Fr_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer)
-{
- wrhs Fr_LPdu;
- bc Fr_LSdu;
- int wrhs1;
- int wrhs2;
-
- Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
- Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 0 : 1; // transmission mode(0=continuous mode, 1=single mode)
- Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
- Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
- Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
- Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
- Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
- Fr_LPdu.fid = frame_id; // Frame ID
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.pl = payload; // Payload Length
-
- // Write Header Section 3 (WRHS3)
- Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
-
- Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
- Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? Fr_header_crc_calc(&Fr_LPdu) : 0;
-
- // Input buffer configuration
- Fr_LSdu.ibrh = buf_num; // input buffer number
- Fr_LSdu.ibsyh = 1; // check for input buffer busy host
- Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
-
- Fr_LSdu.stxrh = (mode&FRAY_BUF_TXREQ_EN) ? 1 : 0; // set transmission request
- Fr_LSdu.ldsh = 0; // load data section
- Fr_LSdu.lhsh = 1; // load header section
- Fr_LSdu.obrs = 0; // output buffer number
- Fr_LSdu.rdss = 0; // read data section
- Fr_LSdu.rhss = 0; // read header section
-
- wrhs1 = ((Fr_LPdu.mbi) & 0x1) <<29;
- wrhs1 |= (Fr_LPdu.txm & 0x1) << 28;
- wrhs1 |= (Fr_LPdu.ppit & 0x1) << 27;
- wrhs1 |= (Fr_LPdu.cfg & 0x1) << 26;
- wrhs1 |= (Fr_LPdu.chb & 0x1) << 25;
- wrhs1 |= (Fr_LPdu.cha & 0x1) << 24;
- wrhs1 |= (Fr_LPdu.cyc & 0x7F) << 16;
- wrhs1 |= (Fr_LPdu.fid & 0x7FF);
- frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
-
- wrhs2 = ((Fr_LPdu.pl & 0x7F) << 16) | (Fr_LPdu.crc & 0x7FF);
- frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
-
- frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPdu.dp & 0x7FF);
-
- Fr_transmit_tx_LPdu(&Fr_LSdu);
-}
-
-/**
- * Fill FIFO filter rejection configuration and configure the buffer.
- *
- * @param[in] buf_num number of buffer to be configured (0-128)
- * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
- * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
- * @param[in] frame_id Id of the frame to be associated with the buffer
- * @param[in] payload Maximum data size in half-word
- * @param[in] data_pointer Address of the first word of data in buffer
- */
-static void Fr_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint16_t fidMask, uint32_t payload, uint32_t data_pointer)
-{
- frayREG->FRF_UN.FRF_ST.rnf = (mode&FRAY_BUF_REJECT_NULL_FRAMES) ? 1 : 0;
- frayREG->FRF_UN.FRF_ST.rss = (mode&FRAY_BUF_REJECT_STATIC_SEGMENT) ? 1 : 0;
- frayREG->FRF_UN.FRF_ST.fid_B11 = frame_id;
- frayREG->FRFM_UN.FRFM_ST.mfid_B11 = fidMask;
- frayREG->FRF_UN.FRF_ST.cyf_B7 = cyc_filter;
- if (mode&FRAY_BUF_CHB_EN && mode&FRAY_BUF_CHA_EN)
- frayREG->FRF_UN.FRF_ST.ch_B2 = 0;
- else if (mode&FRAY_BUF_CHB_EN)
- frayREG->FRF_UN.FRF_ST.ch_B2 = 1;
- else if (mode&FRAY_BUF_CHA_EN)
- frayREG->FRF_UN.FRF_ST.ch_B2 = 2;
- else
- frayREG->FRF_UN.FRF_ST.ch_B2 = 3;
- Fr_config_buffer(buf_num, mode, cyc_filter, frame_id, payload, data_pointer);
-}
-
-/**
- * Load data to message buffer. Data must be copied into WRDS register before this function is called.
- *
- * @param[in] buf_num Number of buffer
- * @param[in] len Number of words to be loaded from data to buffer
- */
-static void Fr_buffer_transmit_data(uint32_t buf_num)
-{
- bc write_buffer;
-
- write_buffer.ibrh = buf_num; // input buffer number
- write_buffer.stxrh = 1; // set transmission request
- write_buffer.ldsh = 1; // load data section
- write_buffer.lhsh = 0; // load header section
- write_buffer.ibsys = 0; // check for input buffer busy shadow
- write_buffer.ibsyh = 1; // check for input buffer busy host
- Fr_transmit_tx_LPdu(&write_buffer);
-}
-
-
-/** @fn wait_for_POC_ready(void)
- * @brief Wait until POC is not busy
- */
-inline void Fr_wait_for_POC_ready()
-{
- // Wait for PBSY bit to clear - POC not busy.
- // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
- while (((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0) ;
-}
-
-/** @fn clear_msg_ram(void)
- * @brief Clears FRAY message RAMs
- *
- * Send command to POC to set all bits of message RAM to 0.
- * @return SUCCESS or FAILURE when command was not accepted
- */
-static int Fr_clear_msg_RAM()
-{
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return FAILURE;
- Fr_wait_for_POC_ready();
- return SUCCESS;
-}
-
-
-/**
- * @brief Switch POC to config state from any other state
- *
- * After command to switch into config state is passed into CHI,
- * the response is checked and if POC has reacted on the command,
- * the function is waiting until POC is ready
- *
- * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
- */
-static Std_ReturnType Fr_POC_go_to_config()
-{
- // write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CONFIG;
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0)
- return E_NOT_OK;
- // Wait for PBSY bit to clear - POC not busy
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-/**
- * @brief Switch POC to ready state from config state
- *
- * After command to switch into ready state is passed into CHI,
- * the response is checked and if POC has reacted on the command,
- * the function is waiting until POC is ready
- *
- * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
- */
-static Std_ReturnType Fr_POC_go_to_ready_from_config()
-{
- Fr_wait_for_POC_ready();
- // For CHA and CHB network
- if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1) {
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- // For CHA network
- else if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1) {
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- }
- // For CHB network
- else if (frayREG->SUCC1_UN.SUCC1_ST.cchb_B1) {
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
-
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
-
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01)
- ; // Waiting for READY state
- return E_OK;
-}
-
-/**
- * @brief Switch POC to ready state from startup state
- *
- * After command to switch into ready state is passed into CHI,
- * the response is checked and if POC has reacted on the command,
- * the function is waiting until POC is ready
- *
- * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
- */
-static Std_ReturnType Fr_POC_go_to_ready_from_startup()
-{
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01) ; // Wait until POC is not in ready state
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-/**
- * @brief Switch POC to startup state from ready state
- *
- * After command to switch into startup state is passed into CHI,
- * the response is checked and if POC has reacted on the command,
- * the function is waiting until POC is ready
- *
- * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
- */
-static Std_ReturnType Fr_POC_go_to_startup()
-{
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (E_NOT_OK);
- Fr_wait_for_POC_ready();
- return (E_OK);
-}
-
-/**
- * @brief Copy cluster config parameters into FlexRay configuration registers.
- *
- * This function does not check values ranges. This is a responsibility of higher
- * layers. Cluster configuration parameters are copied from data structure
- * into right bit position in configuration registers.
- *
- * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
- */
-void Fr_config_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr)
-{
- frayREG->SUCC1_UN.SUCC1_ST.csa_B5 = clusterConfigPtr->gColdStartAttempts;
- frayREG->GTUC9_UN.GTUC9_ST.apo_B5 = clusterConfigPtr->gdActionPointOffset;
- frayREG->PRTC1_UN.PRTC1_ST.casm_B7 = clusterConfigPtr->gdCASRxLowMax;
- frayREG->GTUC9_UN.GTUC9_ST.dsi_B2 = clusterConfigPtr->gdDynamicSlotIdlePhase;
- frayREG->GTUC8_UN.GTUC8_ST.msl_B6 = clusterConfigPtr->gdMinislot;
- frayREG->GTUC9_UN.GTUC9_ST.mapo_B5 = clusterConfigPtr->gdMinislotActionPointOffset;
- frayREG->GTUC7_UN.GTUC7_ST.ssl_B10 = clusterConfigPtr->gdStaticSlot;
- frayREG->PRTC1_UN.PRTC1_ST.tsst_B4 = clusterConfigPtr->gdTSSTransmitter;
- frayREG->PRTC2_UN.PRTC2_ST.rxi_B6 = clusterConfigPtr->gdWakeupSymbolRxIdle;
- frayREG->PRTC2_UN.PRTC2_ST.rxl_B6 = clusterConfigPtr->gdWakeupSymbolRxLow;
- frayREG->PRTC1_UN.PRTC1_ST.rxw_B9 = clusterConfigPtr->gdWakeupSymbolRxWindow;
- frayREG->PRTC2_UN.PRTC2_ST.txi_B8 = clusterConfigPtr->gdWakeupSymbolTxIdle;
- frayREG->PRTC2_UN.PRTC2_ST.txl_B6 = clusterConfigPtr->gdWakeupSymbolTxLow;
- frayREG->SUCC2_UN.SUCC2_ST.ltn_B4 = clusterConfigPtr->gListenNoise;
- frayREG->GTUC2_UN.GTUC2_ST.mpc_B14 = clusterConfigPtr->gMacroPerCycle;
- frayREG->SUCC3_UN.SUCC3_ST.wcf_B4 = clusterConfigPtr->gMaxWithoutClockCorrectionFatal;
- frayREG->SUCC3_UN.SUCC3_ST.wcp_B4 = clusterConfigPtr->gMaxWithoutClockCorrectionPassive;
- frayREG->GTUC8_UN.GTUC8_ST.nms_B13 = clusterConfigPtr->gNumberOfMinislots;
- frayREG->GTUC7_UN.GTUC7_ST.nss_B10 = clusterConfigPtr->gNumberOfStaticSlots;
- frayREG->GTUC4_UN.GTUC4_ST.ocs_B14 = clusterConfigPtr->gOffsetCorrectionStart;
- frayREG->MHDC_UN.MHDC_ST.sfdl_B7 = clusterConfigPtr->gPayloadLengthStatic;
- frayREG->GTUC2_UN.GTUC2_ST.snm_B4 = clusterConfigPtr->gSyncNodeMax;
- frayREG->GTUC4_UN.GTUC4_ST.nit_B14 = clusterConfigPtr->gdNIT;
- frayREG->PRTC1_UN.PRTC1_ST.brp_B2 = clusterConfigPtr->gdSampleClockPeriod;
- frayREG->NEMC_UN.NEMC_ST.nml_B4 = clusterConfigPtr->gNetworkManagementVectorLength;
-}
-
-Std_ReturnType Fr_verify_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr)
-{
- boolean_t error = FALSE;
-
- error |= frayREG->SUCC1_UN.SUCC1_ST.csa_B5 == clusterConfigPtr->gColdStartAttempts;
- error |= frayREG->GTUC9_UN.GTUC9_ST.apo_B5 == clusterConfigPtr->gdActionPointOffset;
- error |= frayREG->PRTC1_UN.PRTC1_ST.casm_B7 == clusterConfigPtr->gdCASRxLowMax;
- error |= frayREG->GTUC9_UN.GTUC9_ST.dsi_B2 == clusterConfigPtr->gdDynamicSlotIdlePhase;
- error |= frayREG->GTUC8_UN.GTUC8_ST.msl_B6 == clusterConfigPtr->gdMinislot;
- error |= frayREG->GTUC9_UN.GTUC9_ST.mapo_B5 == clusterConfigPtr->gdMinislotActionPointOffset;
- error |= frayREG->GTUC7_UN.GTUC7_ST.ssl_B10 == clusterConfigPtr->gdStaticSlot;
- error |= frayREG->PRTC1_UN.PRTC1_ST.tsst_B4 == clusterConfigPtr->gdTSSTransmitter;
- error |= frayREG->PRTC2_UN.PRTC2_ST.rxi_B6 == clusterConfigPtr->gdWakeupSymbolRxIdle;
- error |= frayREG->PRTC2_UN.PRTC2_ST.rxl_B6 == clusterConfigPtr->gdWakeupSymbolRxLow;
- error |= frayREG->PRTC1_UN.PRTC1_ST.rxw_B9 == clusterConfigPtr->gdWakeupSymbolRxWindow;
- error |= frayREG->PRTC2_UN.PRTC2_ST.txi_B8 == clusterConfigPtr->gdWakeupSymbolTxIdle;
- error |= frayREG->PRTC2_UN.PRTC2_ST.txl_B6 == clusterConfigPtr->gdWakeupSymbolTxLow;
- error |= frayREG->SUCC2_UN.SUCC2_ST.ltn_B4 == clusterConfigPtr->gListenNoise;
- error |= frayREG->GTUC2_UN.GTUC2_ST.mpc_B14 == clusterConfigPtr->gMacroPerCycle;
- error |= frayREG->SUCC3_UN.SUCC3_ST.wcf_B4 == clusterConfigPtr->gMaxWithoutClockCorrectionFatal;
- error |= frayREG->SUCC3_UN.SUCC3_ST.wcp_B4 == clusterConfigPtr->gMaxWithoutClockCorrectionPassive;
- error |= frayREG->GTUC8_UN.GTUC8_ST.nms_B13 == clusterConfigPtr->gNumberOfMinislots;
- error |= frayREG->GTUC7_UN.GTUC7_ST.nss_B10 == clusterConfigPtr->gNumberOfStaticSlots;
- error |= frayREG->GTUC4_UN.GTUC4_ST.ocs_B14 == clusterConfigPtr->gOffsetCorrectionStart;
- error |= frayREG->MHDC_UN.MHDC_ST.sfdl_B7 == clusterConfigPtr->gPayloadLengthStatic;
- error |= frayREG->GTUC2_UN.GTUC2_ST.snm_B4 == clusterConfigPtr->gSyncNodeMax;
- error |= frayREG->GTUC4_UN.GTUC4_ST.nit_B14 == clusterConfigPtr->gdNIT;
- error |= frayREG->PRTC1_UN.PRTC1_ST.brp_B2 == clusterConfigPtr->gdSampleClockPeriod;
- error |= frayREG->NEMC_UN.NEMC_ST.nml_B4 == clusterConfigPtr->gNetworkManagementVectorLength;
- return (error == FALSE) ? E_OK : E_NOT_OK;
-}
-
-#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
-
-/**
- * @brief Check cluster configuration parameters.
- *
- * This function checks values of the cluster configuration parameters,
- * if they are in ranges noted in FlexRay specification.
- *
- * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
- * @param [out] errCode Address where error flags will be stored.
- * We have 26 parameters to check. Every one of them has assigned its bit in this flag.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
- * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
- */
-Std_ReturnType Fr_check_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr, uint32_t *errCode)
-{
- *errCode = ERR_PARAM_NO_ERROR;
-
- if (__notInRange(clusterConfigPtr->gColdStartAttempts, 2, 31)) *errCode |= ERR_PARAM_gColdStartAttempts;
- if (__notInRange(clusterConfigPtr->gdActionPointOffset, 1, 63)) *errCode |= ERR_PARAM_gdActionPointOffset;
- if (__notInRange(clusterConfigPtr->gdCASRxLowMax, 67, 99)) *errCode |= ERR_PARAM_gdCASRxLowMax;
- if (clusterConfigPtr->gdDynamicSlotIdlePhase > 2) *errCode |= ERR_PARAM_gdDynamicSlotIdlePhase;
- if (__notInRange(clusterConfigPtr->gdMinislot, 2, 63)) *errCode |= ERR_PARAM_gdMinislot;
- if (__notInRange(clusterConfigPtr->gdMinislotActionPointOffset, 1, 31)) *errCode |= ERR_PARAM_gdMinislotActionPointOffset;
- if (__notInRange(clusterConfigPtr->gdStaticSlot, 4, 661)) *errCode |= ERR_PARAM_gdStaticSlot;
- if (__notInRange(clusterConfigPtr->gdTSSTransmitter, 3, 15)) *errCode |= ERR_PARAM_gdTSSTransmitter;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxIdle, 14, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxIdle;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxLow, 11, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxLow;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxWindow,
- 76, 301)) *errCode |= ERR_PARAM_gdWakeupSymbolRxWindow;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxIdle, 45, 180)) *errCode |= ERR_PARAM_gdWakeupSymbolTxIdle;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxLow, 15, 60)) *errCode |= ERR_PARAM_gdWakeupSymbolTxLow;
- if (__notInRange(clusterConfigPtr->gListenNoise, 2, 16)) *errCode |= ERR_PARAM_gListenNoise;
- if (__notInRange(clusterConfigPtr->gMacroPerCycle, 10, 16000)) *errCode |= ERR_PARAM_gMacroPerCycle;
- if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionFatal,
- clusterConfigPtr->gMaxWithoutClockCorrectionPassive, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionFatal;
- if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionPassive,
- 1, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionPassive;
- if (clusterConfigPtr->gNumberOfMinislots > 7986) *errCode |= ERR_PARAM_gNumberOfMinislots;
- if (__notInRange(clusterConfigPtr->gNumberOfStaticSlots,
- 2, cStaticSlotIDMax)) *errCode |= ERR_PARAM_gNumberOfStaticSlots;
- if (__notInRange(clusterConfigPtr->gOffsetCorrectionStart,
- 9, 15999)) *errCode |= ERR_PARAM_gOffsetCorrectionStart;
- if (clusterConfigPtr->gPayloadLengthStatic > cPayloadLengthMax) *errCode |= ERR_PARAM_gPayloadLengthStatic;
- if (__notInRange(clusterConfigPtr->gSyncNodeMax, 2, cSyncNodeMax)) *errCode |= ERR_PARAM_gSyncNodeMax;
- if (__notInRange(clusterConfigPtr->gdNIT, 7, 0x3E7D)) *errCode |= ERR_PARAM_gdNIT;
- if (clusterConfigPtr->gdSampleClockPeriod > 3) *errCode |= ERR_PARAM_gdSampleClockPeriod;
- if (clusterConfigPtr->gNetworkManagementVectorLength > 12) *errCode |= ERR_PARAM_gNetworkManagementVectorLength;
-
- return (*errCode == 0) ? E_OK : E_NOT_OK;
-}
-
-/**
- * @brief Copy node config parameters into FlexRay configuration registers.
- *
- * This function does not check values ranges. This is a responsibility of higher
- * layers. Node configuration parameters are copied from data structure
- * into right bit position in configuration registers.
- *
- * @param [in] nodeConfigPtr Address of structure with node configuration parameters
- */
-void Fr_config_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr)
-{
- frayREG->SUCC1_UN.SUCC1_ST.hcse_B1 = nodeConfigPtr->pAllowHaltDueToClock;
- frayREG->SUCC1_UN.SUCC1_ST.pta_B5 = nodeConfigPtr->pAllowPassiveToActive;
- if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
- frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 = 1;
- frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 = 1;
- }
- else if (nodeConfigPtr->pChannels == FR_CHANNEL_A) {
- frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 = 1;
- frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 = 0;
- }
- else {
- frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 = 0;
- frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 = 1;
- }
- frayREG->GTUC6_UN.GTUC6_ST.asr_B11 = nodeConfigPtr->pdAcceptedStartupRange;
- frayREG->GTUC5_UN.GTUC5_ST.cdd_B5 = nodeConfigPtr->pClusterDriftDamping;
- frayREG->GTUC5_UN.GTUC5_ST.dca_B8 = nodeConfigPtr->pDelayCompensationA;
- frayREG->GTUC5_UN.GTUC5_ST.dcb_B8 = nodeConfigPtr->pDelayCompensationB;
- frayREG->GTUC5_UN.GTUC5_ST.dec_B8 = nodeConfigPtr->pDecodingCorrection;
- frayREG->SUCC2_UN.SUCC2_ST.lt_B21 = nodeConfigPtr->pdListenTimeout;
- frayREG->GTUC6_UN.GTUC6_ST.mod_B11 = nodeConfigPtr->pdMaxDrift;
- frayREG->GTUC11_UN.GTUC11_ST.eoc_B3 = nodeConfigPtr->pExternOffsetCorrection;
- frayREG->GTUC11_UN.GTUC11_ST.erc_B3 = nodeConfigPtr->pExternRateCorrection;
- frayREG->SUCC1_UN.SUCC1_ST.txst_B1 = nodeConfigPtr->pKeySlotUsedForStartup;
- frayREG->SUCC1_UN.SUCC1_ST.txsy_B1 = nodeConfigPtr->pKeySlotUsedForSync;
- frayREG->MHDC_UN.MHDC_ST.slt_B13 = nodeConfigPtr->pLatestTx;
- frayREG->GTUC3_UN.GTUC3_ST.mioa_B7 = nodeConfigPtr->pMacroInitialOffsetA;
- frayREG->GTUC3_UN.GTUC3_ST.miob_B7 = nodeConfigPtr->pMacroInitialOffsetB;
- frayREG->GTUC3_UN.GTUC3_ST.uioa_B8 = nodeConfigPtr->pMicroInitialOffsetA;
- frayREG->GTUC3_UN.GTUC3_ST.uiob_B8 = nodeConfigPtr->pMicroInitialOffsetB;
- frayREG->GTUC1_UN.GTUC1_ST.ut_B20 = nodeConfigPtr->pMicroPerCycle;
- frayREG->GTUC10_UN.GTUC10_ST.moc_B13 = nodeConfigPtr->pRateCorrectionOut;
- frayREG->GTUC10_UN.GTUC10_ST.mrc_B11 = nodeConfigPtr->pOffsetCorrectionOut;
- frayREG->SUCC1_UN.SUCC1_ST.tsm_B1 = nodeConfigPtr->pSingleSlotEnabled;
- if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A)
- frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 0;
- else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B)
- frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 1;
- frayREG->PRTC1_UN.PRTC1_ST.rwp_B6 = nodeConfigPtr->pWakeupPattern;
- frayREG->PRTC1_UN.PRTC1_ST.brp_B2 = nodeConfigPtr->pSamplesPerMicrotick;
- frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF;
-}
-
-Std_ReturnType Fr_verify_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr)
-{
- boolean_t error = FALSE;
-
- error |= frayREG->SUCC1_UN.SUCC1_ST.hcse_B1 == nodeConfigPtr->pAllowHaltDueToClock;
- error |= frayREG->SUCC1_UN.SUCC1_ST.pta_B5 == nodeConfigPtr->pAllowPassiveToActive;
- if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
- error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 1;
- error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 1;
- }
- else if (nodeConfigPtr->pChannels == FR_CHANNEL_A) {
- error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 1;
- error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 0;
- }
- else {
- error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 0;
- error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 1;
- }
- error |= frayREG->GTUC6_UN.GTUC6_ST.asr_B11 == nodeConfigPtr->pdAcceptedStartupRange;
- error |= frayREG->GTUC5_UN.GTUC5_ST.cdd_B5 == nodeConfigPtr->pClusterDriftDamping;
- error |= frayREG->GTUC5_UN.GTUC5_ST.dca_B8 == nodeConfigPtr->pDelayCompensationA;
- error |= frayREG->GTUC5_UN.GTUC5_ST.dcb_B8 == nodeConfigPtr->pDelayCompensationB;
- error |= frayREG->GTUC5_UN.GTUC5_ST.dec_B8 == nodeConfigPtr->pDecodingCorrection;
- error |= frayREG->SUCC2_UN.SUCC2_ST.lt_B21 == nodeConfigPtr->pdListenTimeout;
- error |= frayREG->GTUC6_UN.GTUC6_ST.mod_B11 == nodeConfigPtr->pdMaxDrift;
- error |= frayREG->GTUC11_UN.GTUC11_ST.eoc_B3 == nodeConfigPtr->pExternOffsetCorrection;
- error |= frayREG->GTUC11_UN.GTUC11_ST.erc_B3 == nodeConfigPtr->pExternRateCorrection;
- error |= frayREG->SUCC1_UN.SUCC1_ST.txst_B1 == nodeConfigPtr->pKeySlotUsedForStartup;
- error |= frayREG->SUCC1_UN.SUCC1_ST.txsy_B1 == nodeConfigPtr->pKeySlotUsedForSync;
- error |= frayREG->MHDC_UN.MHDC_ST.slt_B13 == nodeConfigPtr->pLatestTx;
- error |= frayREG->GTUC3_UN.GTUC3_ST.mioa_B7 == nodeConfigPtr->pMacroInitialOffsetA;
- error |= frayREG->GTUC3_UN.GTUC3_ST.miob_B7 == nodeConfigPtr->pMacroInitialOffsetB;
- error |= frayREG->GTUC3_UN.GTUC3_ST.uioa_B8 == nodeConfigPtr->pMicroInitialOffsetA;
- error |= frayREG->GTUC3_UN.GTUC3_ST.uiob_B8 == nodeConfigPtr->pMicroInitialOffsetB;
- error |= frayREG->GTUC1_UN.GTUC1_ST.ut_B20 == nodeConfigPtr->pMicroPerCycle;
- error |= frayREG->GTUC10_UN.GTUC10_ST.moc_B13 == nodeConfigPtr->pRateCorrectionOut;
- error |= frayREG->GTUC10_UN.GTUC10_ST.mrc_B11 == nodeConfigPtr->pOffsetCorrectionOut;
- error |= frayREG->SUCC1_UN.SUCC1_ST.tsm_B1 == nodeConfigPtr->pSingleSlotEnabled;
- if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A)
- error |= frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 == 0;
- else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B)
- error |= frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 == 1;
- error |= frayREG->PRTC1_UN.PRTC1_ST.rwp_B6 == nodeConfigPtr->pWakeupPattern;
- error |= frayREG->PRTC1_UN.PRTC1_ST.brp_B2 == nodeConfigPtr->pSamplesPerMicrotick;
- return (error == FALSE) ? E_OK : E_NOT_OK;
-}
-
-
-/**
- * @brief Check node configuration parameters.
- *
- * This function checks values of the node configuration parameters,
- * if they are in ranges noted in FlexRay specification.
- *
- * @param [in] nodeConfigPtr Address of structure with node configuration parameters
- * @param [out] errCode Address where error flags will be stored.
- * We have 24 parameters to check. Every one of them has assigned its bit in this flag.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
- * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
- */
-Std_ReturnType Fr_check_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr, uint32_t *errCode)
-{
- *errCode = ERR_PARAM_NO_ERROR;
-
- if (nodeConfigPtr->pAllowPassiveToActive > 31) *errCode |= ERR_PARAM_pAllowPassiveToActive;
- if (nodeConfigPtr->pChannels != FR_CHANNEL_A &&
- nodeConfigPtr->pChannels != FR_CHANNEL_B &&
- nodeConfigPtr->pChannels != FR_CHANNEL_AB ) *errCode |= ERR_PARAM_pChannels;
- if (nodeConfigPtr->pdAcceptedStartupRange > 1875) *errCode |= ERR_PARAM_pdAcceptedStartupRange;
- if (nodeConfigPtr->pClusterDriftDamping > 20) *errCode |= ERR_PARAM_pClusterDriftDamping;
- if (nodeConfigPtr->pDelayCompensationA > 200) *errCode |= ERR_PARAM_pDelayCompensationA;
- if (nodeConfigPtr->pDelayCompensationB > 200) *errCode |= ERR_PARAM_pDelayCompensationB;
- if (__notInRange(nodeConfigPtr->pdListenTimeout, 1284, 1283846)) *errCode |= ERR_PARAM_pdListenTimeout;
- if (__notInRange(nodeConfigPtr->pdMaxDrift, 2, 1923)) *errCode |= ERR_PARAM_pdMaxDrift;
- if (nodeConfigPtr->pExternOffsetCorrection > 7) *errCode |= ERR_PARAM_pExternOffsetCorrection;
- if (nodeConfigPtr->pExternRateCorrection > 7) *errCode |= ERR_PARAM_pExternRateCorrection;
- if (nodeConfigPtr->pKeySlotUsedForStartup == TRUE &&
- nodeConfigPtr->pKeySlotUsedForSync == FALSE) *errCode |= ERR_PARAM_pKeySlotUsedForSync
- | ERR_PARAM_pKeySlotUsedForStartup; // If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true.
- if (nodeConfigPtr->pLatestTx > 7980) *errCode |= ERR_PARAM_pLatestTx;
- if (__notInRange(nodeConfigPtr->pMacroInitialOffsetA, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetA;
- if (__notInRange(nodeConfigPtr->pMacroInitialOffsetB, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetB;
- if (nodeConfigPtr->pMicroInitialOffsetA > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetA;
- if (nodeConfigPtr->pMicroInitialOffsetB > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetB;
- if (__notInRange(nodeConfigPtr->pMicroPerCycle, 640, 640000)) *errCode |= ERR_PARAM_pMicroPerCycle;
- if (__notInRange(nodeConfigPtr->pRateCorrectionOut, 2, 1923)) *errCode |= ERR_PARAM_pRateCorrectionOut;
- if (__notInRange(nodeConfigPtr->pOffsetCorrectionOut, 5, 0x3BA2)) *errCode |= ERR_PARAM_pOffsetCorrectionOut;
- if (nodeConfigPtr->pWakeupChannel != FR_CHANNEL_A &&
- nodeConfigPtr->pWakeupChannel != FR_CHANNEL_B ) *errCode |= ERR_PARAM_pWakeupChannel;
- if (__notInRange(nodeConfigPtr->pWakeupPattern, 2, 63)) *errCode |= ERR_PARAM_pWakeupPattern;
- if (nodeConfigPtr->pSamplesPerMicrotick > 3) *errCode |= ERR_PARAM_pSamplesPerMicrotick;
- if (__notInRange(nodeConfigPtr->pDecodingCorrection, 0xF, 0x8F)) *errCode |= ERR_PARAM_pDecodingCorrection;
-
- return (*errCode == 0) ? E_OK : E_NOT_OK;
-}
-
-/**
- * @brief Check Configuration parameters for all buffers
- *
- * This function checks configuration parameters.
- * For FIFO buffers:
- * - All of them have to be RX
- * - All of them have the same payload <= 256B
- * - Same channels active
- * - Same cycle counter filter
- * - not coldstart
- * - not single/auto
- * - not reconfigurable
- * - frame ID can be 0, which means that all messages not received by others buffers are received in FIFO.
- * For dynamic segment buffers and static segment buffers:
- * - frame ID must not be 0
- * - payload <= 256B
- * The sum of all configured payloads must be <= 8KB.
- *
- * @param [in] statBufCfgPtr Address of structure with static buffers configuration parameters
- * @param [in] dynBufCfgPtr Address of structure with dynamic buffers configuration parameters
- * @param [in] fifoBufCfgPtr Address of structure with fifo buffers configuration parameters
- * @param [in] statBufCnt Number of static buffers to be configured
- * @param [in] dynBufCnt Number of dynamic buffers to be configured
- * @param [in] fifoBufCnt Number of fifo buffers to be configured
- * @param [out] errCode Address where error flags will be stored.
- * Flags are defined as ERR_PARAM_BUF.....
- * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
- */
-Std_ReturnType Fr_check_buffer_parameters(const Fr_TMS570LS_BufferConfigType *statBufCfgPtr, const Fr_TMS570LS_BufferConfigType *dynBufCfgPtr, const Fr_TMS570LS_BufferConfigType *fifoBufCfgPtr,
- uint8_t statBufCnt, uint8_t dynBufCnt, uint8_t fifoBufCnt, uint32_t *errCode)
-{
- uint32_t payloadTotal = 0;
-
- *errCode = ERR_PARAM_NO_ERROR;
- uint8_t fifoPayload, fifoCycleCounterFiltering;
- Fr_ChannelType fifoChannels;
- uint16_t fifoFidMask, fifoSlotId;
- boolean_t fifoRejNullFr, fifoRejStatFr;
- const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr = NULL;
-
- /* Check FIFO buffer parameters */
- if (fifoBufCnt != 0 && fifoBufCfgPtr != NULL) {
- fifoChannels = fifoBufCfgPtr[0].channel;
- fifoCycleCounterFiltering = fifoBufCfgPtr[0].cycleCounterFiltering;
- fifoFidMask = fifoBufCfgPtr[0].fidMask;
- fifoSlotId = fifoBufCfgPtr[0].slotId;
- fifoPayload = fifoBufCfgPtr[0].maxPayload;
- fifoRejNullFr = fifoBufCfgPtr[0].rejectNullFrames;
- fifoRejStatFr = fifoBufCfgPtr[0].rejectStaticSegment;
- if (fifoPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_HIGH;
- for (buffer_cfg_ptr = &fifoBufCfgPtr[0]; buffer_cfg_ptr < &fifoBufCfgPtr[fifoBufCnt]; buffer_cfg_ptr++) {
- if (buffer_cfg_ptr->channel != fifoChannels) *errCode |= ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS;
- if (buffer_cfg_ptr->cycleCounterFiltering != fifoCycleCounterFiltering) *errCode |= ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS;
- if (buffer_cfg_ptr->fidMask != fifoFidMask) *errCode |= ERR_PARAM_BUFFIFO_FIDMASK_DIFFERS;
- if (buffer_cfg_ptr->isTx == TRUE) *errCode |= ERR_PARAM_BUFFIFO_NOT_RX;
- if (buffer_cfg_ptr->maxPayload != fifoPayload) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS;
- if (buffer_cfg_ptr->payloadPreambleIndicatorTr == TRUE) *errCode |= ERR_PARAM_BUFFIFO_PPIT;
- if (buffer_cfg_ptr->rejectNullFrames != fifoRejNullFr) *errCode |= ERR_PARAM_BUFFIFO_REJNULLFR_DIFFERS;
- if (buffer_cfg_ptr->rejectStaticSegment != fifoRejStatFr) *errCode |= ERR_PARAM_BUFFIFO_REJSTATFR_DIFFERS;
- if (buffer_cfg_ptr->slotId != fifoSlotId) *errCode |= ERR_PARAM_BUFFIFO_SLOTID_DIFFERS;
- payloadTotal += buffer_cfg_ptr->maxPayload;
- }
- }
- if (dynBufCfgPtr != NULL)
- for (buffer_cfg_ptr = &dynBufCfgPtr[0]; buffer_cfg_ptr < &dynBufCfgPtr[dynBufCnt]; buffer_cfg_ptr++) {
- if (buffer_cfg_ptr->slotId == 0) *errCode |= ERR_PARAM_BUFDYN_FRAMEID_INVALID;
- if (buffer_cfg_ptr->maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFDYN_PAYLOAD_HIGH;
- if (buffer_cfg_ptr->channel == FR_CHANNEL_AB) *errCode |= ERR_PARAM_BUFDYN_CHANNELS;
- payloadTotal += buffer_cfg_ptr->maxPayload;
- }
-
- if (statBufCfgPtr != NULL)
- for (buffer_cfg_ptr = &statBufCfgPtr[0]; buffer_cfg_ptr < &statBufCfgPtr[statBufCnt]; buffer_cfg_ptr++) {
- if (buffer_cfg_ptr->slotId == 0) *errCode |= ERR_PARAM_BUFSTAT_FRAMEID_INVALID;
- if (buffer_cfg_ptr->maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFSTAT_PAYLOAD_HIGH;
- payloadTotal += buffer_cfg_ptr->maxPayload;
- }
-
- if (payloadTotal > 8192/2) *errCode |= ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH;
-
- return (*errCode == 0) ? E_OK : E_NOT_OK;
-}
-
-/**
- * @brief Compute and set message RAM config parameters into FlexRay configuration registers.
- *
- * This function does not check values ranges. This is a responsibility of other functions.
- * Message RAM configuration parameters are computed from data in the structure and
- * written into right bit position in configuration registers.
- *
- * @param [in] msgRAMConfigPtr Address of structure with message RAM configuration parameters
- * @return Number of configured buffers
- */
-uint8_t Fr_config_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr)
-{
- /* If dynSegmentBufferCount is not 0 then first dynamic buffer = statSegmentBufferCount.
- * If dynSegmentBufferCount is 0 then first dynamic buffer is 0x80 (see TMS570LS31x documentation)
- */
- if (msgRAMConfigPtr->dynSegmentBufferCount == 0)
- frayREG->MRC_UN.MRC_ST.fdb_B8 = 0x80;
- else
- frayREG->MRC_UN.MRC_ST.fdb_B8 = msgRAMConfigPtr->statSegmentBufferCount;
- /* If fifoBufferCount is not 0 then first fifo buffer = statSegmentBufferCount + dynSegmentBufferCount
- * If fifoBufferCount is 0 then first fifo buffer is 0x80 (see TMS570LS31x documentation)
- */
- if (msgRAMConfigPtr->fifoBufferCount == 0)
- frayREG->MRC_UN.MRC_ST.ffb_B8 = 0x80;
- else
- frayREG->MRC_UN.MRC_ST.ffb_B8 = msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount;
- /* Last configured buffer = statSegmentBufferCount + dynSegmentBufferCount + fifoBufferCount - 1 */
- frayREG->MRC_UN.MRC_ST.lcb_B8 = msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1;
-
- /* Secure buffers setting */
- if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED)
- frayREG->MRC_UN.MRC_ST.sec_B2 = 0;
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
- frayREG->MRC_UN.MRC_ST.sec_B2 = 1;
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED)
- frayREG->MRC_UN.MRC_ST.sec_B2 = 2;
- else
- frayREG->MRC_UN.MRC_ST.sec_B2 = 3;
-
- /* Sync frame payload multiplex setting */
- if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE)
- frayREG->MRC_UN.MRC_ST.splm_B1 = 1;
- else
- frayREG->MRC_UN.MRC_ST.splm_B1 = 0;
-
- return msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount;
-}
-
-Std_ReturnType Fr_verify_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr)
-{
- boolean_t error = FALSE;
-
- if (msgRAMConfigPtr->dynSegmentBufferCount == 0)
- error |= frayREG->MRC_UN.MRC_ST.fdb_B8 == 0x80;
- else
- error |= frayREG->MRC_UN.MRC_ST.fdb_B8 == msgRAMConfigPtr->statSegmentBufferCount;
-
- if (msgRAMConfigPtr->fifoBufferCount == 0)
- error |= frayREG->MRC_UN.MRC_ST.ffb_B8 == 0x80;
- else
- error |= frayREG->MRC_UN.MRC_ST.ffb_B8 == msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount;
-
- error |= frayREG->MRC_UN.MRC_ST.lcb_B8 == msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1;
- if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED)
- error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 0;
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
- error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 1;
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED)
- error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 2;
- else
- error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 3;
-
- if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE)
- error |= frayREG->MRC_UN.MRC_ST.splm_B1 == 1;
- else
- error |= frayREG->MRC_UN.MRC_ST.splm_B1 == 0;
-
- return (error == FALSE) ? E_OK : E_NOT_OK;
-}
-
-
-#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
-
-/**
- * @brief Check message RAM configuration parameters.
- *
- * This function checks values of the message RAM configuration parameters.
- * FlexRay implementation in TMS570 can have up to 128 buffers configured, so
- * the sum of all values buffer count must not exceed this ceiling.
- *
- *
- * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
- * @param [out] errCode Address where error flags will be stored.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
- * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
- */
-Std_ReturnType Fr_check_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr, uint32_t *errCode)
-{
- *errCode = ERR_PARAM_NO_ERROR;
-
- if (__notInRange(msgRAMConfigPtr->statSegmentBufferCount, 1, 127)) *errCode |= ERR_PARAM_statSegmentBufferCount;
- if (msgRAMConfigPtr->dynSegmentBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_dynSegmentBufferCount;
- if (msgRAMConfigPtr->fifoBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_fifoBufferCount;
- if ((msgRAMConfigPtr->statSegmentBufferCount +
- msgRAMConfigPtr->dynSegmentBufferCount +
- msgRAMConfigPtr->fifoBufferCount) >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_maxBuffLimit;
-
- return (*errCode == 0) ? E_OK : E_NOT_OK;
-}
-
-/**
- * @brief Master function to prepare buffers for communication
- * *
- * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
- * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame.
- * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
- */
-Std_ReturnType Fr_PrepareLPdu_master(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
-{
- uint32_t bufferIndex;
- uint32_t mode;
- const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_DRV_INITIALIZED)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
-
-#endif
- /* Find the index of the buffer in configuration data array */
- for (bufferIndex = 0; bufferIndex <= frayREG->MRC_UN.MRC_ST.lcb_B8; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx)
- if (Fr_BuffersConfigured[bufferIndex] == FALSE) { // Buffer was not yet configured
- buffer_cfg_ptr = Fr_buffer_slot_map[bufferIndex].buffer_ptr;
- mode = Fr_buffer_config_flags(buffer_cfg_ptr, bufferIndex);
- Fr_MsgRAMDataPtrs[bufferIndex] = Fr_MsgRAMDataOffset;
- if (bufferIndex >= frayREG->MRC_UN.MRC_ST.ffb_B8) // This is RX FIFO buffer
- Fr_configure_fifo_buffer(bufferIndex, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->fidMask, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[bufferIndex]);
- else // Static/dynamic segment buffer
- Fr_config_buffer(bufferIndex, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[bufferIndex]);
- /*
- * Calculate new address.
- * Payload contains the number of two-bytes words, Fr_MsgRAMDataPtrs contains addresses of 4B words in message RAM, all msgRAM addresses have
- * to be 4B aligned.
- * Offset has to be divided by two each time because payload is in 2B words and msgRAM addresses are in 4B words.
- */
- Fr_MsgRAMDataOffset += ((buffer_cfg_ptr->maxPayload)%2U == 0U ? (buffer_cfg_ptr->maxPayload) : ((buffer_cfg_ptr->maxPayload)+1U))/2;
- Fr_BuffersConfigured[bufferIndex] = TRUE;
- }
- }
- return E_OK;
-}
-
-void Fr_Init(const Fr_ConfigType *Fr_ConfigPtr)
-{
- Fr_slot_buffer_map_t *buffer_slot_map_ptr;
- uint8_t buffer_last_index;
- boolean_t *buffers_configured_ptr;
- const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
-
-#ifdef DET_ACTIVATED
- if (Fr_ConfigPtr == NULL)
- return;
- if (Fr_DrvState != FR_ST_DRV_NOT_INITIALIZED)
- return;
-
-#endif
- /* Save pointers for parameters indexed by CIDX indexes
- * This array representation is used by Fr_ReadCCConfig function.
- * Parameter thet are not configurable in tms570 FlexRay implementation
- * are set as NULL.
- */
- Fr_ConfigParPtrs[FR_CIDX_GDCYCLE] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PMICROPERCYCLE] = Fr_ConfigPtr->nodeConfiguration->pMicroPerCycle;
- Fr_ConfigParPtrs[FR_CIDX_PDLISTENTIMEOUT] = Fr_ConfigPtr->clusterConfiguration->gMacroPerCycle;
- Fr_ConfigParPtrs[FR_CIDX_GDMACROTICK] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFMINISLOTS] = Fr_ConfigPtr->clusterConfiguration->gNumberOfMinislots;
- Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFSTATICSLOTS] = Fr_ConfigPtr->clusterConfiguration->gNumberOfStaticSlots;
- Fr_ConfigParPtrs[FR_CIDX_GDNIT] = Fr_ConfigPtr->clusterConfiguration->gdNIT;
- Fr_ConfigParPtrs[FR_CIDX_GDSTATICSLOT] = Fr_ConfigPtr->clusterConfiguration->gdNIT;
- Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXWINDOW] = Fr_ConfigPtr->clusterConfiguration->gdWakeupSymbolRxWindow;
- Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTID] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PLATESTTX] = Fr_ConfigPtr->nodeConfiguration->pLatestTx;
- Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONOUT] = 0;
- Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONSTART] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PRATECORRECTIONOUT] = Fr_ConfigPtr->nodeConfiguration->pRateCorrectionOut;
- Fr_ConfigParPtrs[FR_CIDX_PSECONDKEYSLOTID] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PDACCEPTEDSTARTUPRANGE] = Fr_ConfigPtr->nodeConfiguration->pdAcceptedStartupRange;
- Fr_ConfigParPtrs[FR_CIDX_GCOLDSTARTATTEMPTS] = Fr_ConfigPtr->clusterConfiguration->gColdStartAttempts;
- Fr_ConfigParPtrs[FR_CIDX_GCYCLECOUNTMAX] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GLISTENNOISE] = Fr_ConfigPtr->clusterConfiguration->gListenNoise;
- Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTFATAL] = Fr_ConfigPtr->clusterConfiguration->gMaxWithoutClockCorrectionFatal;
- Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTPASSIVE] = Fr_ConfigPtr->clusterConfiguration->gMaxWithoutClockCorrectionPassive;
- Fr_ConfigParPtrs[FR_CIDX_GNETWORKMANAGEMENTVECTORLENGTH] = Fr_ConfigPtr->clusterConfiguration->gNetworkManagementVectorLength;
- Fr_ConfigParPtrs[FR_CIDX_GPAYLOADLENGTHSTATIC] = Fr_ConfigPtr->clusterConfiguration->gPayloadLengthStatic;
- Fr_ConfigParPtrs[FR_CIDX_GSYNCFRAMEIDCOUNTMAX] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDACTIONPOINTOFFSET] = Fr_ConfigPtr->clusterConfiguration->gdActionPointOffset;
- Fr_ConfigParPtrs[FR_CIDX_GDBIT] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDCASRXLOWMAX] = Fr_ConfigPtr->clusterConfiguration->gdCASRxLowMax;
- Fr_ConfigParPtrs[FR_CIDX_GDDYNAMICSLOTIDLEPHASE] = Fr_ConfigPtr->clusterConfiguration->gdDynamicSlotIdlePhase;
- Fr_ConfigParPtrs[FR_CIDX_GDMINISLOTACTIONPOINTOFFSET] = Fr_ConfigPtr->clusterConfiguration->gdMinislotActionPointOffset;
- Fr_ConfigParPtrs[FR_CIDX_GDMINISLOT] = Fr_ConfigPtr->clusterConfiguration->gdMinislot;
- Fr_ConfigParPtrs[FR_CIDX_GDSAMPLECLOCKPERIOD] = Fr_ConfigPtr->clusterConfiguration->gdSampleClockPeriod;
- Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOW] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOWACTIONPOINTOFFSET] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDTSSTRANSMITTER] = Fr_ConfigPtr->clusterConfiguration->gdTSSTransmitter;
- Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXIDLE] = Fr_ConfigPtr->clusterConfiguration->gdWakeupSymbolRxIdle;
- Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXLOW] = Fr_ConfigPtr->clusterConfiguration->gdWakeupSymbolRxLow;
- Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXACTIVE] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXIDLE] = Fr_ConfigPtr->clusterConfiguration->gdWakeupSymbolTxIdle;
- Fr_ConfigParPtrs[FR_CIDX_PALLOWPASSIVETOACTIVE] = Fr_ConfigPtr->nodeConfiguration->pAllowPassiveToActive;
- Fr_ConfigParPtrs[FR_CIDX_PCHANNELS] = Fr_ConfigPtr->nodeConfiguration->pChannels;
- Fr_ConfigParPtrs[FR_CIDX_PCLUSTERDRIFTDAMPING] = Fr_ConfigPtr->nodeConfiguration->pClusterDriftDamping;
- Fr_ConfigParPtrs[FR_CIDX_PDECODINGCORRECTION] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONA] = Fr_ConfigPtr->nodeConfiguration->pDelayCompensationA;
- Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONB] = Fr_ConfigPtr->nodeConfiguration->pDelayCompensationB;
- Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETA] = Fr_ConfigPtr->nodeConfiguration->pMacroInitialOffsetA;
- Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETB] = Fr_ConfigPtr->nodeConfiguration->pMacroInitialOffsetB;
- Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETA] = Fr_ConfigPtr->nodeConfiguration->pMicroInitialOffsetA;
- Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETB] = Fr_ConfigPtr->nodeConfiguration->pMicroInitialOffsetB;
- Fr_ConfigParPtrs[FR_CIDX_PPAYLOADLENGTHDYNMAX] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PSAMPLESPERMICROTICK] = Fr_ConfigPtr->nodeConfiguration->pSamplesPerMicrotick;
- Fr_ConfigParPtrs[FR_CIDX_PWAKEUPCHANNEL] = Fr_ConfigPtr->nodeConfiguration->pWakeupChannel;
- Fr_ConfigParPtrs[FR_CIDX_PWAKEUPPATTERN] = Fr_ConfigPtr->nodeConfiguration->pWakeupPattern;
- Fr_ConfigParPtrs[FR_CIDX_PDMICROTICK] = 0;
- Fr_ConfigParPtrs[FR_CIDX_GDIGNOREAFTERTX] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PALLOWHALTDUETOCLOCK] = Fr_ConfigPtr->nodeConfiguration->pAllowHaltDueToClock;
- Fr_ConfigParPtrs[FR_CIDX_PEXTERNALSYNC] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PFALLBACKINTERNAL] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTONLYENABLED] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] = Fr_ConfigPtr->nodeConfiguration->pKeySlotUsedForStartup;
- Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] = Fr_ConfigPtr->nodeConfiguration->pKeySlotUsedForSync;
- Fr_ConfigParPtrs[FR_CIDX_PNMVECTOREARLYUPDATE] = 0;
- Fr_ConfigParPtrs[FR_CIDX_PTWOKEYSLOTMODE] = 0;
-
- /* Store whole configuration address
- * This structured representation is used by other function in API.
- */
- Fr_Config = Fr_ConfigPtr;
-
- /* Store pointers to structures with configuration parameters of buffers
- * Reset configured flags for all buffers */
- buffer_last_index = Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount;
- for (buffer_slot_map_ptr = Fr_buffer_slot_map, buffers_configured_ptr = Fr_BuffersConfigured, buffer_cfg_ptr = Fr_ConfigPtr->staticBufferConfigs;
- buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
- buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
- ) { // Static segment buffers
- buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
- buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
- buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
- buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
- buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
- *buffers_configured_ptr = FALSE;
- }
- buffer_last_index += Fr_ConfigPtr->msgRAMConfig->dynSegmentBufferCount;
- for (buffer_cfg_ptr = Fr_ConfigPtr->dynamicBufferConfigs;
- buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
- buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
- ) { // Dynamic segment buffers
- buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
- buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
- buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
- buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
- buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
- *buffers_configured_ptr = FALSE;
- }
- buffer_last_index += Fr_ConfigPtr->msgRAMConfig->fifoBufferCount;
- for (buffer_cfg_ptr = Fr_ConfigPtr->fifoBufferConfigs;
- buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
- buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
- ) { // Fifo buffrers
- buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
- buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
- buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
- buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
- buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
- *buffers_configured_ptr = FALSE;
- }
-
-#ifdef DET_ACTIVATED
- Fr_DrvState = FR_ST_DRV_INITIALIZED;
-#endif
-}
-
-Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx)
-{
- uint32_t errCode = ERR_PARAM_NO_ERROR;
- uint32_t i;
- uint8_t totalBufferCount;
-
-#ifdef DET_ACTIVATED
- if (Fr_DrvState < FR_ST_DRV_INITIALIZED)
- return E_NOT_OK;
-
-#endif
-
- /* Switch CC into ‘POC:config’ (from any other POCState) */
- while (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_CONFIG)
- if (Fr_POC_go_to_config() == E_NOT_OK)
- return E_NOT_OK;
- /* Now no TX request is pending, no RX is pending, all buffers looks like disabled */
- /* Disable all interrupts */
- frayREG->EIES_UN.EIES_UL = 0;
- frayREG->SIES_UN.SIES_UL = 0;
- /* Clear all pending interrupts */
- frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF;
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF;
- /* Disable all timers */
- frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
- frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
- /* Check Cluster config parameters */
- if (Fr_check_cluster_parameters(Fr_Config->clusterConfiguration, &errCode) == E_NOT_OK)
- return E_NOT_OK | errCode | FR_INIT_ERR_CLUSTER_CONFIG;
- /* Check node config parameters */
- if (Fr_check_node_parameters(Fr_Config->nodeConfiguration, &errCode) == E_NOT_OK)
- return E_NOT_OK | errCode | FR_INIT_ERR_NODE_CONFIG;
- /* Check msgRAM config parameters */
- if (Fr_check_msgRAM_parameters(Fr_Config->msgRAMConfig, &errCode) == E_NOT_OK)
- return E_NOT_OK | errCode | FR_INIT_ERR_MSGRAM_CONFIG;
- /* Check buffers parameters */
- if (Fr_check_buffer_parameters(Fr_Config->staticBufferConfigs, Fr_Config->dynamicBufferConfigs, Fr_Config->fifoBufferConfigs,
- Fr_Config->msgRAMConfig->statSegmentBufferCount, Fr_Config->msgRAMConfig->dynSegmentBufferCount, Fr_Config->msgRAMConfig->fifoBufferCount, &errCode) == E_NOT_OK)
- return E_NOT_OK | errCode | FR_INIT_ERR_BUFFPARAM_CONFIG;
-
- /* Clear message RAM */
- if (Fr_clear_msg_RAM() == FAILURE)
- return E_NOT_OK;
-
- /* Configure all FlexRay cluster, node and msgRAM parameters */
- Fr_config_cluster_parameters(Fr_Config->clusterConfiguration);
- Fr_config_node_parameters(Fr_Config->nodeConfiguration);
-
- // Wait until CLEAR_RAMS command is complete
- while (frayREG->MHDS_UN.MHDS_ST.cram_B1 == 1)
- ;
-
- totalBufferCount = Fr_config_msgRAM_parameters(Fr_Config->msgRAMConfig);
-
- /* Repeat the parameter verification procedure */
- boolean_t passed = TRUE;
- for (i = 0; i < FrCtrlTestCount; i++) {
- if (Fr_verify_cluster_parameters(Fr_Config->clusterConfiguration) == E_OK &&
- Fr_verify_node_parameters(Fr_Config->nodeConfiguration) == E_OK &&
- Fr_verify_msgRAM_parameters(Fr_Config->msgRAMConfig) == E_OK) {
- passed = TRUE;
- break;
- }
- }
-
- Fr_MsgRAMDataStartAddress = totalBufferCount*4U; // First data section after headers sections in message RAM.
- Fr_MsgRAMDataOffset = Fr_MsgRAMDataStartAddress;
-
- /* Reset configured flags and map */
- for (i = 0; i < totalBufferCount; i++) {
- Fr_BuffersConfigured[i] = FALSE;
- Fr_buffer_slot_map[i].slot_id = Fr_buffer_slot_map[i].buffer_ptr->slotId;
- Fr_buffer_slot_map[i].act_payload = Fr_buffer_slot_map[i].buffer_ptr->maxPayload;
- Fr_buffer_slot_map[i].act_ch_filter = Fr_buffer_slot_map[i].buffer_ptr->channel;
- Fr_buffer_slot_map[i].act_cyc_filter = Fr_buffer_slot_map[i].buffer_ptr->cycleCounterFiltering;
- }
-
- /* Configure all transmit/receive resources */
- for (i = 0; i < totalBufferCount; i++) {
- if (Fr_PrepareLPdu_master(Fr_CtrlIdx, Fr_buffer_slot_map[i].buffer_ptr->slotId) == E_NOT_OK)
- return E_NOT_OK | FR_INIT_ERR_BUFF_CONFIG;
- }
- if (passed == FALSE)
- return E_NOT_OK;
-
- /* Switch POC to ready state */
- if (Fr_POC_go_to_ready_from_config() == E_NOT_OK)
- return E_NOT_OK;
- /* Enable all interrupts */
- frayREG->EIES_UN.EIES_UL = 0xFFFFFFFF;
- frayREG->SIES_UN.SIES_UL = 0xFFFFFFFF;
-
-#ifdef DET_ACTIVATED
- Fr_DrvState = FR_ST_CTRL_INITIALIZED;
-#endif
- return E_OK;
-}
-
-Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx)
-{
- uint32_t counter;
- uint32_t state_value;
- uint32_t csa;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
- return E_NOT_OK;
-
-#endif
- // Node is configured as coldstart
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForStartup == TRUE)
- // Start up loop
- while (1) {
- counter = 0;
- // Try to integrate into an existing network as following coldstarter
- if (Fr_POC_go_to_startup() == E_NOT_OK)
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_FOLLOW; // Switch to run state error
-
- do { // Wait until NORMAL_ACTIVE state or timeout
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- counter++;
- } while ((state_value != FR_POCS_NORMAL_ACTIVE) && (counter < FR_FCS_LISTEN_TIMEOUT));
-
- // No success in integration, try to initiate FlexRay network as leading coldstarter.
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_INTEGRATION_LISTEN) {
- csa = frayREG->CCSV_UN.CCSV_ST.rca_B5;
- if (csa != 0) // Some cold start attempts remaining
- if (Fr_AllowColdstart(Fr_CtrlIdx) == E_NOT_OK)
- return E_NOT_OK | FR_STARTUP_ERR_CSINH_DIS; // Cold start inhibit disabled error
- }
- do { // Wait until NORMAL_ACTIVE or INTEGRATION_LISTEN state
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while ( (state_value != FR_POCS_NORMAL_ACTIVE) && (state_value != FR_POCS_INTEGRATION_LISTEN));
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_NORMAL_ACTIVE) // Success, break the start up loop
- break;
- if (Fr_POC_go_to_ready_from_startup() == E_NOT_OK) // No success. Switch back to READY state
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_READY;
- }
- // The node is not coldstarter, try to integrate into an existing network.
- else {
- if (Fr_POC_go_to_startup() == E_NOT_OK)
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_AS_NCOLD; // Switching to startup state as non-cold start node
- else {
- // Wait until NORMAL_ACTIVE
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while (state_value != FR_POCS_NORMAL_ACTIVE);
- }
- }
- return E_OK;
-}
-
-Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
-
-#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALLOW_COLDSTART;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALL_SLOTS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_HALT;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
-
-#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_FREEZE;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
- return E_NOT_OK;
-
-#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_WAKEUP;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
-Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx)
-{
- Std_ReturnType retVal = E_OK;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_ChnlIdx == FR_CHANNEL_AB)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
- return E_NOT_OK;
-
-#endif
- if (Fr_POC_go_to_config() == E_NOT_OK)
- return E_NOT_OK;
- if (Fr_ChnlIdx == FR_CHANNEL_A) {
- frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 0;
- retVal = E_OK;
- }
- else if (Fr_ChnlIdx == FR_CHANNEL_B) {
- frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 1;
- retVal = E_OK;
- }
- else
- retVal = E_NOT_OK;
- if (Fr_POC_go_to_ready_from_config() == E_NOT_OK)
- retVal = E_NOT_OK;
-
- return retVal;
-}
-
-Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType *Fr_POCStatusPtr)
-{
- static const Fr_SlotModeType slot_mode[4] = {FR_SLOTMODE_KEYSLOT, FR_SLOTMODE_INVALID, FR_SLOTMODE_ALL_PENDING, FR_SLOTMODE_ALL};
- static const Fr_ErrorModeType error_mode[4] = {FR_ERRORMODE_ACTIVE, FR_ERRORMODE_PASSIVE, FR_ERRORMODE_COMM_HALT, FR_ERRORMODE_INVALID};
- static const Fr_POCStateType poc_state[9] = {
- FR_POCSTATE_DEFAULT_CONFIG, FR_POCSTATE_READY, FR_POCSTATE_NORMAL_ACTIVE, FR_POCSTATE_NORMAL_PASSIVE,
- FR_POCSTATE_HALT, FR_POCSTATE_MONITOR, FR_POCSTATE_LOOPBACK, FR_POCSTATE_INVALID, FR_POCSTATE_CONFIG
- };
- static const Fr_WakeupStatusType wup_state[8] = {
- FR_WAKEUP_UNDEFINED, FR_WAKEUP_RECEIVED_HEADER, FR_WAKEUP_RECEIVED_WUP, FR_WAKEUP_COLLISION_HEADER,
- FR_WAKEUP_COLLISION_WUP, FR_WAKEUP_COLLISION_UNKNOWN, FR_WAKEUP_TRANSMITTED, FR_WAKEUP_INVALID
- };
- static const Fr_StartupStateType startup_state[11] = {
- FR_STARTUP_PREPARE, FR_STARTUP_COLDSTART_LISTEN, FR_STARTUP_COLDSTART_COLLISION_RESOLUTION,
- FR_STARTUP_COLDSTART_CONSISTENCY_CHECK, FR_STARTUP_COLDSTART_GAP, FR_STARTUP_COLDSTART_JOIN, FR_STARTUP_INTEGRATION_COLDSTART_CHECK,
- FR_STARTUP_INTEGRATION_LISTEN, FR_STARTUP_INTEGRATION_CONSISTENCY_CHECK, FR_STARTUP_INITIALIZE_SCHEDULE, FR_STARTUP_ABORT
- };
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_POCStatusPtr == NULL)
- return E_NOT_OK;
-
-#endif
- Fr_POCStatusPtr->SlotMode = slot_mode[frayREG->CCSV_UN.CCSV_ST.slm_B2]; /* Slot mode detection */
- Fr_POCStatusPtr->Freeze = (frayREG->CCSV_UN.CCSV_ST.fsi_B1 == 1) ? TRUE : FALSE; /* Freeze request detection */
- Fr_POCStatusPtr->CHIHaltRequest = (frayREG->CCSV_UN.CCSV_ST.hrq_B1 == 1) ? TRUE : FALSE; /* Halt request detection */
- Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE; /* Coldstart noise detection */
- Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE; /* Coldstart noise detection */
- Fr_POCStatusPtr->ErrorMode = error_mode[frayREG->CCEV_UN.CCEV_ST.errm_B2]; /* Error mode detection */
-
- /* POC state detection */
- /* Startup substate detection */
- uint16_t pocs = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- Fr_POCStatusPtr->StartupState = FR_STARTUP_UNDEFINED;
- if (pocs > FR_POCSTATE_DEFAULT_CONFIG && pocs <= FR_POCSTATE_MONITOR)
- Fr_POCStatusPtr->State = poc_state[pocs];
- else if (pocs >= FR_POCSTATE_LOOPBACK && pocs <= FR_POCSTATE_CONFIG)
- Fr_POCStatusPtr->State = poc_state[pocs-7];
- else if (pocs >= FR_POCS_WAKEUP_STANDBY && pocs <= FR_POCS_WAKEUP_DETECT)
- Fr_POCStatusPtr->State = FR_POCSTATE_WAKEUP;
- else if (pocs >= FR_POCS_STARTUP_PREPARE && pocs <= FR_POCS_ABORT_STARTUP) {
- Fr_POCStatusPtr->State = FR_POCSTATE_STARTUP;
- Fr_POCStatusPtr->StartupState = startup_state[frayREG->CCSV_UN.CCSV_ST.pocs_B6 - FR_POCS_STARTUP_PREPARE];
- }
- else
- Fr_POCStatusPtr->State = FR_POCSTATE_INVALID;
-
- /* Wakeup substate detection */
- Fr_POCStatusPtr->WakeupStatus = wup_state[frayREG->CCSV_UN.CCSV_ST.wsv_B3];
-
- return E_OK;
-}
-
-Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t *Fr_LSduPtr, uint8_t Fr_LSduLength)
-{
- uint32_t word, buffer, index, bufferIndex, mode;
- uint8_t actualPayload = (Fr_LSduLength+1)/2;
- Fr_TMS570LS_BufferConfigType tmp_buffer;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
- if (Fr_LSduPtr == NULL)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
-
-#endif
- /* Find the index of the buffer in configuration data array */
- for (bufferIndex = 0; bufferIndex <= frayREG->MRC_UN.MRC_ST.lcb_B8; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx)
- if (Fr_BuffersConfigured[bufferIndex] == TRUE && Fr_buffer_slot_map[bufferIndex].buffer_ptr->isTx == TRUE) { // Buffer was configured already and is TX
- memset((void *)frayREG->WRDS, 0, sizeof(frayREG->WRDS));
- if (bufferIndex >= frayREG->MRC_UN.MRC_ST.fdb_B8) { // It is a dynamic segment buffer, reconfigure its payload to match with Fr_LSduLength
- if (actualPayload > Fr_buffer_slot_map[bufferIndex].act_payload)
- actualPayload = Fr_buffer_slot_map[bufferIndex].act_payload;
- // Reconfigure buffer to send just the minimum possible payload
- tmp_buffer = *Fr_buffer_slot_map[bufferIndex].buffer_ptr;
- tmp_buffer.channel = Fr_buffer_slot_map[bufferIndex].act_ch_filter;
- tmp_buffer.cycleCounterFiltering = Fr_buffer_slot_map[bufferIndex].act_cyc_filter;
- tmp_buffer.slotId = Fr_buffer_slot_map[bufferIndex].slot_id;
- tmp_buffer.maxPayload = actualPayload;
- mode = Fr_buffer_config_flags(&tmp_buffer, bufferIndex);
- Fr_config_buffer(bufferIndex, mode, tmp_buffer.cycleCounterFiltering, tmp_buffer.slotId, tmp_buffer.maxPayload, Fr_MsgRAMDataPtrs[bufferIndex]);
-
- }
- for (word = 0; word < (Fr_LSduLength+3)/4; word++) {
- index = word*4;
- buffer = Fr_LSduPtr[index++];
- buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 8 : 0;
- buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 16 : 0;
- buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 24 : 0;
- frayREG->WRDS[word] = buffer;
- }
- Fr_buffer_transmit_data(bufferIndex);
- return E_OK;
- }
- }
- return E_NOT_OK;
-}
-
-Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
-{
- uint8_t bufferIndex;
- uint8_t mode;
- const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
-
-#ifdef DET_ACTIVATED
- boolean_t canceled = FALSE;
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED)
- return E_NOT_OK;
-
-#endif
-
- /* If bit IBCM.STXR in the input buffer command mask register is set (STXR = 1), the transmission request
- * flag TXR of the selected message buffer is automatically set after the message buffer has been updated.
- * If bit IBCM.STXR in the input buffer command mask register is reset (STXR = 0), the transmission request
- * flag TXR of the selected message buffer is reset. This can be used to stop transmission from message
- * buffers operated in continuous mode.
- */
-
- /*
- * Write the same configuration into buffer headers with TXREQ disabled.
- */
- for (bufferIndex = 0; bufferIndex <= frayREG->MRC_UN.MRC_ST.lcb_B8; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was already configured
- buffer_cfg_ptr = Fr_buffer_slot_map[bufferIndex].buffer_ptr;
- mode = Fr_buffer_config_flags(buffer_cfg_ptr, bufferIndex);
- if (buffer_cfg_ptr->isTx == TRUE) {
- Fr_config_buffer(bufferIndex, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[bufferIndex]);
-#ifdef DET_ACTIVATED
- canceled = TRUE;
-#endif
- }
- }
- }
- }
-
-#ifdef DET_ACTIVATED
- return (canceled == TRUE) ? E_OK : E_NOT_OK;
-#else
- return E_OK;
-#endif
-}
-
-Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t *Fr_LSduPtr, Fr_RxLPduStatusType *Fr_LPduStatusPtr, uint8_t *Fr_LSduLengthPtr)
-{
- volatile unsigned long *ndat[4] = {&frayREG->NDAT1_UN.NDAT1_UL, &frayREG->NDAT2_UN.NDAT2_UL, &frayREG->NDAT3_UN.NDAT3_UL, &frayREG->NDAT4_UN.NDAT4_UL};
- uint32_t bufferIndex;
- uint8_t word, byte;
- boolean_t bufferFound = FALSE;
- const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
-
- #define fifo_not_empty (frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) // Macro that makes the code more readable, is undefined at the end of the function
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
- if (Fr_LSduPtr == NULL)
- return E_NOT_OK;
- if (Fr_LPduStatusPtr == NULL)
- return E_NOT_OK;
- if (Fr_LSduLengthPtr == NULL)
- return E_NOT_OK;
-
-#endif
- /* Find the index of the buffer in configuration data array */
- *Fr_LSduLengthPtr = 0;
- *Fr_LPduStatusPtr = FR_NOT_RECEIVED;
-
- /*
- * Try to find new message in static and dynamic segment buffers at first:
- * - Check New Data flag, if no new data received, return.
- * - Load received data and header into the output buffer.
- * - Store loaded payload from header of the output buffer.
- * - Copy data from the output buffer to the Fr_LSduPtr address.
- * If no new message has been retrieved, there is possibility that
- * RX FIFO buffer has received it (for example when static or dynamic
- * segment buffers has rejection filter for channel A, but FIFO for channel B).
- * - Check if the Fr_LPduIdx can be accepted by the RX FIFO (FID combined with the mask.
- * - Check if the FIFO is not empty
- * - Pop data and header into an output buffer.
- * - Detect if more data is available in the FIFO and set Fr_LPduStatusPtr.
- * - Store loaded payload from header of the output buffer.
- * - Copy data from the output buffer to the Fr_LSduPtr address.
- */
- for (bufferIndex = 0; bufferIndex < frayREG->MRC_UN.MRC_ST.ffb_B8; bufferIndex++) { // Static and dynamic segment buffers
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx)
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was configured already
- bufferFound = TRUE;
- if (*ndat[bufferIndex/32] & (0x1 << bufferIndex%32)) { // New data received
- Fr_buffer_receive_data_header(bufferIndex); // Read data and header into output buffer
- *Fr_LPduStatusPtr = FR_RECEIVED;
- break; // Buffer which received a message has been found, other buffers are irrelevant. According the FlexRay specification the buffer with lowest index has the highest priority.
- }
- }
- }
- if (*Fr_LPduStatusPtr == FR_NOT_RECEIVED && Fr_BuffersConfigured[bufferIndex] == TRUE) { // No message was received, try the FIFO.
- bufferIndex = frayREG->MRC_UN.MRC_ST.ffb_B8;
- buffer_cfg_ptr = Fr_buffer_slot_map[bufferIndex].buffer_ptr;
- if ((Fr_LPduIdx & (~buffer_cfg_ptr->fidMask)) != (buffer_cfg_ptr->slotId & (~buffer_cfg_ptr->fidMask)) ) {
- bufferFound = TRUE;
- if (fifo_not_empty) { // The RX FIFO buffer is not empty
- Fr_buffer_receive_data_header(bufferIndex); // Consume first element from FIFO
- if (fifo_not_empty) // FIFO not empty after last pop
- *Fr_LPduStatusPtr = FR_RECEIVED_MORE_DATA_AVAILABLE;
- else // FIFO empty after last pop
- *Fr_LPduStatusPtr = FR_RECEIVED;
- }
- }
- }
-
- /*
- * Copy data from output register into address from parameter Fr_LSduPtr.
- * Data in the output register are 32b words,
- * Data in Fr_LSduPtr are 8b words.
- */
- *Fr_LSduLengthPtr = frayREG->RDHS2_UN.RDHS2_ST.plr_B7*2; // Number of bytes copied into Fr_LSduPtr
- for (byte = 0, word = 0; word < (*Fr_LSduLengthPtr+3)/4; word++) {
- Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? frayREG->RDDS[word] & 0xFF : 0;
- byte++;
- Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF00) >> 8 : 0;
- byte++;
- Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF0000) >> 16 : 0;
- byte++;
- Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF000000) >> 24 : 0;
- byte++;
- }
-
- return (bufferFound == TRUE) ? E_OK : E_NOT_OK;
- #undef fifo_not_empty
-}
-
-Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType *Fr_TxLPduStatusPtr)
-{
- volatile unsigned long *txrq[4] = {&frayREG->TXRQ1_UN.TXRQ1_UL, &frayREG->TXRQ2_UN.TXRQ2_UL, &frayREG->TXRQ3_UN.TXRQ3_UL, &frayREG->TXRQ4_UN.TXRQ4_UL};
- uint8_t bufferIndex;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
- if (Fr_TxLPduStatusPtr == NULL)
- return E_NOT_OK;
-
-#endif
- for (bufferIndex = 0; bufferIndex <= frayREG->MRC_UN.MRC_ST.lcb_B8; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) // Buffer was configured already
- if (Fr_buffer_slot_map[bufferIndex].buffer_ptr->isTx == TRUE) {
- if (*txrq[bufferIndex/32] & (0x1 << bufferIndex%32)) // Transmit request is pending
- *Fr_TxLPduStatusPtr = FR_NOT_TRANSMITTED;
- else
- *Fr_TxLPduStatusPtr = FR_TRANSMITTED;
- break;
- }
- }
- }
- return E_OK;
-}
-
-Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
-{
- if (FrBufferReconfig == TRUE)
- return Fr_PrepareLPdu_master(Fr_CtrlIdx, Fr_LPduIdx);
- else
- return E_NOT_OK;
-}
-
-Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC)
-{
- if (FrBufferReconfig == FALSE)
- return E_NOT_OK;
-
- uint32_t bufferIndex;
- int lowest_index = 0;
- uint8_t highest_index = frayREG->MRC_UN.MRC_ST.ffb_B8;
- uint32_t mode;
- Fr_TMS570LS_BufferConfigType buffer_cfg;
-
-#ifdef DET_ACTIVATED
- boolean_t reconfigured = FALSE;
- boolean_t is_pow2;
- uint8_t pow2;
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_CycleOffset >= Fr_CycleRepetition)
- return E_NOT_OK;
- for (pow2 = 1, is_pow2 = FALSE; pow2 < 128; pow2 *= 2) {
- if (Fr_CycleRepetition == pow2) {
- is_pow2 = TRUE;
- break;
- }
- }
- if (!is_pow2)
- return E_NOT_OK;
-
-#endif
- lowest_index = Fr_reconfigurable_buffer_index();
- if (lowest_index == -1)
- return E_NOT_OK | ERR_PARAM_RECONFIG_NOT_ALLOWED;
- if (Fr_FrameId == 0)
- return E_NOT_OK | ERR_PARAM_INVALID_FRAME_ID;
- if (Fr_FrameId > Fr_Config->clusterConfiguration->gNumberOfStaticSlots &&
- Fr_ChnlIdx == FR_CHANNEL_AB)
- return E_NOT_OK | ERR_PARAM_INVALID_CHANNEL;
- uint8_t payload_in_hw = (Fr_PayloadLength+1)/2;
- uint32_t cycle_filter = Fr_CycleRepetition+Fr_CycleOffset;
-
- for (bufferIndex = lowest_index; bufferIndex < highest_index; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was configured already
- buffer_cfg = *Fr_buffer_slot_map[bufferIndex].buffer_ptr;
- buffer_cfg.channel = Fr_ChnlIdx;
- buffer_cfg.cycleCounterFiltering = cycle_filter;
- buffer_cfg.slotId = Fr_FrameId;
- buffer_cfg.maxPayload = payload_in_hw;
- if (buffer_cfg.maxPayload > Fr_buffer_slot_map[bufferIndex].buffer_ptr->maxPayload)
- return E_NOT_OK | ERR_PARAM_PAYLOAD_TOO_BIG;
- Fr_buffer_slot_map[bufferIndex].act_payload = payload_in_hw;
- Fr_buffer_slot_map[bufferIndex].slot_id = Fr_FrameId;
- Fr_buffer_slot_map[bufferIndex].act_ch_filter = Fr_ChnlIdx;
- Fr_buffer_slot_map[bufferIndex].act_cyc_filter = cycle_filter;
- mode = Fr_buffer_config_flags(&buffer_cfg, bufferIndex);
- Fr_config_buffer(bufferIndex, mode, buffer_cfg.cycleCounterFiltering, buffer_cfg.slotId, buffer_cfg.maxPayload, Fr_MsgRAMDataPtrs[bufferIndex]);
-#ifdef DET_ACTIVATED
- reconfigured = TRUE;
-#endif
- }
- }
- }
-
-#ifdef DET_ACTIVATED
- if (reconfigured == FALSE)
- return E_NOT_OK | ERR_PARAM_NO_BUFFER_FOUND;
-#endif
- return E_OK;
-}
-
-Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
-{
- if (FrBufferReconfig == FALSE)
- return E_NOT_OK;
-
- uint8_t bufferIndexLimit;
- uint8_t bufferIndex;
- uint8_t mode;
- int lowest_index;
-#ifdef DET_ACTIVATED
- boolean_t disabled = FALSE;
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_LPduIdx > cSlotIDMax)
- return E_NOT_OK;
- if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED)
- return E_NOT_OK;
-
-#endif
- /* Determine reconfigurable buffers from the data in MRC.SET bits */
- switch (frayREG->MRC_UN.MRC_ST.sec_B2) {
- case 0:
- bufferIndexLimit = frayREG->MRC_UN.MRC_ST.ffb_B8;
- break;
- case 1:
- bufferIndexLimit = frayREG->MRC_UN.MRC_ST.fdb_B8;
- break;
- default:
- return E_OK; // No reconfiguration enabled
- }
-
- /* Find the index of the buffer in configuration data array */
- for (bufferIndex = 0; bufferIndex <= frayREG->MRC_UN.MRC_ST.lcb_B8; bufferIndex++) {
- if (Fr_buffer_slot_map[bufferIndex].slot_id == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was not yet configured
- lowest_index = Fr_reconfigurable_buffer_index();
- if (lowest_index == -1) // Reconfiguration disabled
- break;
- if (bufferIndex < lowest_index)
- continue;
- if (bufferIndex < bufferIndexLimit) { // Buffer is reconfigurable, reset its configuration registers.
- mode = 0;
- Fr_MsgRAMDataPtrs[bufferIndex] = 0;
- Fr_BuffersConfigured[bufferIndex] = FALSE;
- Fr_config_buffer(bufferIndex, mode, Fr_buffer_slot_map[bufferIndex].buffer_ptr->cycleCounterFiltering,
- Fr_buffer_slot_map[bufferIndex].buffer_ptr->slotId,
- Fr_buffer_slot_map[bufferIndex].buffer_ptr->maxPayload,
- Fr_MsgRAMDataPtrs[bufferIndex]);
-#ifdef DET_ACTIVATED
- disabled = TRUE;
-#endif
- }
- }
- }
- }
-#ifdef DET_ACTIVATED
- return (disabled == TRUE) ? E_OK : E_NOT_OK;
-#else
- return E_OK;
-#endif
-}
-
-Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t *Fr_CyclePtr, uint16_t *Fr_MacroTickPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_CyclePtr == NULL)
- return E_NOT_OK;
- if (Fr_MacroTickPtr == NULL)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- uint32_t time = frayREG->MTCCV_UN.MTCCV_UL;
- *Fr_CyclePtr = __mfld2val(MTCCV_CCV_MSK, time);
- *Fr_MacroTickPtr = __mfld2val(MTCCV_MTV_MSK, time);
- return E_OK;
-}
-
-static inline uint32_t swap32(uint32_t x)
-{
- return (x & 0x000000ff) << 24 |
- (x & 0x0000ff00) << 8 |
- (x & 0x00ff0000) >> 8 |
- (x & 0xff000000) >> 24;
-}
-
-Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t *Fr_NmVectorPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_NmVectorPtr == NULL)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- *((uint32_t *)(Fr_NmVectorPtr+0)) = swap32(frayREG->NMV1_UN.NMV1_UL);
- *((uint32_t *)(Fr_NmVectorPtr+4)) = swap32(frayREG->NMV2_UN.NMV2_UL);
- *((uint32_t *)(Fr_NmVectorPtr+8)) = swap32(frayREG->NMV3_UL);
- return E_OK;
-}
-
-Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t *Fr_NumOfStartupFramesPtr)
-{
- /* TODO: Implement - can not find this information in the datasheet */
- return E_OK;
-}
-
-Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t *Fr_ChannelAStatusPtr, uint16_t *Fr_ChannelBStatusPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_ChannelAStatusPtr == NULL)
- return E_NOT_OK;
- if (Fr_ChannelBStatusPtr == NULL)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- *Fr_ChannelAStatusPtr = 0;
- *Fr_ChannelBStatusPtr = 0;
-
- *Fr_ChannelAStatusPtr |= frayREG->ACS_UN.ACS_ST.vfra_B1;
- *Fr_ChannelAStatusPtr |= frayREG->ACS_UN.ACS_ST.seda_B1 << 1;
- *Fr_ChannelAStatusPtr |= frayREG->ACS_UN.ACS_ST.ceda_B1 << 2;
- *Fr_ChannelAStatusPtr |= frayREG->ACS_UN.ACS_ST.cia_B1 << 3;
- *Fr_ChannelAStatusPtr |= frayREG->ACS_UN.ACS_ST.sbva_B1 << 4;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.mtsa_B1 << 8;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sesa_B1 << 9;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sbsa_B1 << 10;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.tcsa_B1 << 11;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sena_B1 << 12;
- *Fr_ChannelAStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sbna_B1 << 13;
-
- *Fr_ChannelBStatusPtr |= frayREG->ACS_UN.ACS_ST.vfrb_B1;
- *Fr_ChannelBStatusPtr |= frayREG->ACS_UN.ACS_ST.sedb_B1 << 1;
- *Fr_ChannelBStatusPtr |= frayREG->ACS_UN.ACS_ST.cedb_B1 << 2;
- *Fr_ChannelBStatusPtr |= frayREG->ACS_UN.ACS_ST.cib_B1 << 3;
- *Fr_ChannelBStatusPtr |= frayREG->ACS_UN.ACS_ST.sbvb_B1 << 4;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.mtsb_B1 << 8;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sesb_B1 << 9;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sbsb_B1 << 10;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.tcsb_B1 << 11;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.senb_B1 << 12;
- *Fr_ChannelBStatusPtr |= frayREG->SWNIT_UN.SWNIT_ST.sbnb_B1 << 13;
-
- return E_OK;
-}
-
-Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t *Fr_RateCorrectionPtr, int32_t *Fr_OffsetCorrectionPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_RateCorrectionPtr == NULL)
- return E_NOT_OK;
- if (Fr_OffsetCorrectionPtr == NULL)
- return E_NOT_OK;
-
-#endif
- *Fr_RateCorrectionPtr = frayREG->RCV_UN.RCV_ST.rcv_B12;
- *Fr_OffsetCorrectionPtr = frayREG->OCV_UN.OCV_ST.ocv_B14;
-
- return E_OK;
-}
-
-Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t *Fr_ChannelAEvenListPtr, uint16_t *Fr_ChannelBEvenListPtr, uint16_t *Fr_ChannelAOddListPtr, uint16_t *Fr_ChannelBOddListPtr)
-{
- uint32_t esid;
- uint32_t osid;
- uint8_t i;
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_ChannelAEvenListPtr == NULL)
- return E_NOT_OK;
- if (Fr_ChannelBEvenListPtr == NULL)
- return E_NOT_OK;
- if (Fr_ChannelAOddListPtr == NULL)
- return E_NOT_OK;
- if (Fr_ChannelBOddListPtr == NULL)
- return E_NOT_OK;
-
-#endif
-
- if (Fr_ListSize > FR_MAX_SYNC_FRAME_LIST_SIZE) // Limit list size to 15
- Fr_ListSize = FR_MAX_SYNC_FRAME_LIST_SIZE;
-
- for (i = 0; i < Fr_ListSize; i++) {
- esid = frayREG->ESID_UL[i];
- osid = frayREG->OSID_UL[i];
-
- Fr_ChannelAEvenListPtr[i] = (__mfld2val(ESID_RXEA_MSK, esid) == 1) ? __mfld2val(ESID_EID_MSK, esid) : 0;
- Fr_ChannelBEvenListPtr[i] = (__mfld2val(ESID_RXEB_MSK, esid) == 1) ? __mfld2val(ESID_EID_MSK, esid) : 0;
- Fr_ChannelAOddListPtr[i] = (__mfld2val(OSID_RXOA_MSK, osid) == 1) ? __mfld2val(OSID_OID_MSK, osid) : 0;
- Fr_ChannelBOddListPtr[i] = (__mfld2val(OSID_RXOB_MSK, osid) == 1) ? __mfld2val(OSID_OID_MSK, osid) : 0;
- }
-
- for (i = Fr_ListSize; i < 15; i++) {
- Fr_ChannelAEvenListPtr[i] = 0;
- Fr_ChannelBEvenListPtr[i] = 0;
- Fr_ChannelAOddListPtr[i] = 0;
- Fr_ChannelBOddListPtr[i] = 0;
- }
-
- return E_OK;
-}
-
-Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t *Fr_WakeupRxStatusPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_WakeupRxStatusPtr == NULL)
- return E_NOT_OK;
-
-#endif
-
- *Fr_WakeupRxStatusPtr = 0;
- *Fr_WakeupRxStatusPtr |= frayREG->SIR_UN.SIR_ST.wupa_B1;
- *Fr_WakeupRxStatusPtr |= frayREG->SIR_UN.SIR_ST.wupb_B1 << 1;
- // Reset flags
- frayREG->SIR_UN.SIR_ST.wupa_B1 = 1;
- frayREG->SIR_UN.SIR_ST.wupb_B1 = 1;
- return E_OK;
-}
-
-Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
- if (Fr_Offset > Fr_Config->clusterConfiguration->gMacroPerCycle)
- return E_NOT_OK;
- if (Fr_Cycle & 0x80)
- return E_NOT_OK;
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
- return E_NOT_OK;
-
-#endif
- if (Fr_AbsTimerIdx == 0) {
- frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
- frayREG->T0C_UN.T0C_ST.t0ms_B1 = 1;
- frayREG->T0C_UN.T0C_ST.t0cc_B7 = Fr_Cycle;
- frayREG->T0C_UN.T0C_ST.t0mo_B14 = Fr_Offset;
- frayREG->SIR_UN.SIR_ST.ti0_B1 = 1; // Reset interrupt
- frayREG->T0C_UN.T0C_ST.t0rc_B1 = 1;
- }
- else if (Fr_AbsTimerIdx == 1) {
- frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
- frayREG->T1C_UN.T1C_ST.t1ms_B1 = 1;
- frayREG->T1C_UN.T1C_ST.t1mc_B14 = Fr_Cycle*Fr_Config->clusterConfiguration->gMacroPerCycle+Fr_Offset;
- frayREG->SIR_UN.SIR_ST.ti1_B1 = 1; // Reset interrupt
- frayREG->T1C_UN.T1C_ST.t1rc_B1 = 1;
- }
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
-
-#endif
- if (Fr_AbsTimerIdx == 0)
- frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
- else if (Fr_AbsTimerIdx == 1)
- frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
-
-#endif
- frayREG->ILE_UN.ILE_ST.eint0_B1 = 1;
- if (Fr_AbsTimerIdx == 0)
- frayREG->SIES_UN.SIES_ST.ti0e_B1 = 1;
- else if (Fr_AbsTimerIdx == 1)
- frayREG->SIES_UN.SIES_ST.ti0e_B1 = 1;
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
-
-#endif
- if (Fr_AbsTimerIdx == 0)
- frayREG->SIR_UN.SIR_ST.ti0_B1 = 1;
- else if (Fr_AbsTimerIdx == 1)
- frayREG->SIR_UN.SIR_ST.ti1_B1 = 1;
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
-
-#endif
- if (Fr_AbsTimerIdx == 0)
- frayREG->SIER_UN.SIER_ST.ti0e_B1 = 1;
- else if (Fr_AbsTimerIdx == 1)
- frayREG->SIER_UN.SIER_ST.ti0e_B1 = 1;
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t *Fr_IRQStatusPtr)
-{
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
- if (Fr_AbsTimerIdx > 1)
- return E_NOT_OK;
- if (Fr_IRQStatusPtr == NULL)
- return E_NOT_OK;
-
-#endif
- if (Fr_AbsTimerIdx == 0)
- *Fr_IRQStatusPtr = (frayREG->SIR_UN.SIR_ST.ti0_B1 == 1) ? TRUE : FALSE;
- else if (Fr_AbsTimerIdx == 1)
- *Fr_IRQStatusPtr = (frayREG->SIR_UN.SIR_ST.ti1_B1 == 1) ? TRUE : FALSE;
- else
- return E_NOT_OK;
- return E_OK;
-}
-
-void Fr_GetVersionInfo(Std_VersionInfoType *VersioninfoPtr)
-{
-#ifdef DET_ACTIVATED
- if (VersioninfoPtr == NULL)
- return;
-
-#endif
- VersioninfoPtr->vendorID = Fr_versionInfo.vendorID;
- VersioninfoPtr->moduleID = Fr_versionInfo.moduleID;
- VersioninfoPtr->sw_major_version = Fr_versionInfo.sw_major_version;
- VersioninfoPtr->sw_minor_version = Fr_versionInfo.sw_minor_version;
- VersioninfoPtr->sw_patch_version = Fr_versionInfo.sw_patch_version;
-}
-
-Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t *Fr_ConfigParamValuePtr)
-{
-
-#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0)
- return E_NOT_OK;
- if (Fr_ConfigParamIdx >= FR_CIDX_CNT)
- return E_NOT_OK;
- if (Fr_ConfigParamValuePtr == NULL)
- return E_NOT_OK;
- if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
- return E_NOT_OK;
-
-#endif
-
- *Fr_ConfigParamValuePtr = Fr_ConfigParPtrs[Fr_ConfigParamIdx];
- return E_OK;
-}
-
-int Fr_spi_transfer(uint8_t port)
-{
- uint32_t commands[2];
- port_desc_t *desc;
-
- if (port > FRAY_NUM_PORTS) return -1;
- desc = hal_port_get_dsc(fray_port_names[port], -1);
- fray_spi_cmd_sh = fray_spi_cmd;
- commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
- commands[1] = (fray_spi_cmd_sh & 0xFF);
-
- fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
- return 0;
-}
-
-int Fr_spi_response(uint8_t port)
-{
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_resp[port];
-}
-
-int Fr_spi_get_cmd(uint8_t port)
-{
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_cmd;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- * - Martin Zeman
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : fray.c
- *
- * Abstract:
- * This file contains function for getting fray status as spi respons
- * and functions for FlexRay initialization and usage.
- * FlexRay chips on SPI are read only.
- */
-
-//#include "drv_fray.h"
-#include "drv/drv.h"
+++ /dev/null
-/* Copyright (C) 2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn
- * - Carlos Jenkins <carlos@jenkins.co.cr>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : ain.c
- * Abstract:
- * RPP driver implementation for HBR.
- *
- * References:
- * hbridge.h
- */
-
-// This file contains functions to control H-bridge.
-// A keep-alive watchdog is implemented.
-// PWM is available for HBR control.
-#include "drv/drv.h"
-#include <os/semphr.h>
-
-//Flag variable if pwm was initialized and is ready to start.
-static boolean_t pwm_initialized = FALSE;
-
-/// Watchdog Task --------------------------------------------------------------
-static boolean_t wdg_start = FALSE;
-
-// Prepared command to be send on SPI.
-// Default value is watchdog reset command.
-uint16_t hbr_spi_wdg_tx = 0x03DB;
-
-// Shadow variable of hbr_spi_wdg_tx
-uint16_t hbr_spi_wdg_tx_shd = 0x03DB;
-
-// Response from SPI.
-uint16_t hbr_spi_wdg_rx = 0;
-
-// Shadow variable of hbr_spi_wdg_shd
-uint16_t hbr_spi_wdg_rx_shd = 0;
-
-// SPI communication result code (one of SPI_MSG_*)
-int hbr_spi_code = 0;
-
-// In certain situation the H-Bridge stops working without signaling that in
-// its status byte. This happens when the watchdog message is sent
-// approximately 25us after asserting EN signal. To prevent this situation we
-// have to synchronize EN signal with watchdog thread.
-static xSemaphoreHandle wdg_sync;
-
-/**
- * @brief SPI callback function
- *
- * This function is called each time SPI transfer finishes.
- * Gets response and prepare command for next sending.
- * Copy response from shadow variable,
- * Copy prepared command to shadow variable
- *
- * @param[in] ifc Pointer to SPI driver structure
- * @param[in] code SPI transfer status code
- * @param[in] msg Pointer to message definition structure
- *
- * @return always zero
- */
-int drv_hbr_spi_wdg_callback(struct spi_drv *ifc, int code,
- struct spi_msg_head *msg)
-{
- hbr_spi_code = code;
- if (code == SPI_MSG_FINISHED) {
- hbr_spi_wdg_rx = hbr_spi_wdg_rx_shd;
- hbr_spi_wdg_tx_shd = hbr_spi_wdg_tx;
- }
- return 0;
-}
-
-// SPI message format definition for watchdog reset command
-spi_msg_head_t hbr_spi_wdg = {
- .flags = 0,
- .addr = 0,
- .rq_len = 2,
- .tx_buf = (uint8_t *)&hbr_spi_wdg_tx_shd,
- .rx_buf = (uint8_t *)&hbr_spi_wdg_rx_shd,
- .callback = drv_hbr_spi_wdg_callback,
- .private = 1
-};
-
-/**
- * Watchdog FreeRTOS Task function.
- *
- * Select appropriate spi address
- * Initialize task timer
- * Send watchdog keep-alive command each 10ms.
- *
- * @param[in] p Pointer to parameter, unused.
- */
-void drv_hbr_wdg_task(void *p)
-{
- spi_drv_t *ifc;
-
- ifc = spi_find_drv(NULL, 4);
-
- if (ifc == NULL) {
- wdg_start = FALSE;
- vTaskDelete(NULL);
- }
-
- portTickType xLastWakeTime;
- xLastWakeTime = xTaskGetTickCount();
-
- while (TRUE) {
- vTaskDelayUntil(&xLastWakeTime, (10 / portTICK_RATE_MS));
- xSemaphoreTake(wdg_sync, portMAX_DELAY);
- if (wdg_start) {
- xLastWakeTime = xTaskGetTickCount();
- wdg_start = FALSE;
- }
- else
- spi_msg_rq_ins(ifc, &hbr_spi_wdg);
- xSemaphoreGive(wdg_sync);
- }
-}
-
-/// Watchdog API ---------------------------------------------------------------
-static xTaskHandle wdg_handle = NULL;
-
-/**
- * Start the watchdog task to send keep-alive commands periodically to H-Bridge.
- *
- * @return SUCCESS if watchdog could be started.\n
- * -RPP_EBUSY if watchdog is running already
- * -RPP_ENOMEM if the task could not be created
- */
-int8_t drv_hbr_wdg_start()
-{
- if (wdg_start)
- return -RPP_EBUSY;
-
- wdg_start = TRUE;
- // Task never started
- if (wdg_handle == NULL ) {
- wdg_sync = xSemaphoreCreateMutex();
- if (wdg_sync == NULL )
- return -RPP_ENOMEM;
- if (xTaskCreate(drv_hbr_wdg_task,
- (const signed char *)"hbr_wdg_task",
- 1024, NULL, 1, &wdg_handle) != pdPASS) {
- wdg_start = FALSE;
- return -RPP_ENOMEM;
- }
- }
- else
- // Task already created
- vTaskResume(drv_hbr_wdg_task);
-
- return SUCCESS;
-}
-
-/**
- * Stop the watchdog task.
- *
- * @return SUCCESS if watchdog could be stopped.\n
- * FAILURE if watchdog wasn't running.
- */
-int8_t drv_hbr_wdg_stop()
-{
- if (!wdg_start)
- return FAILURE;
-
- xSemaphoreTake(wdg_sync, portMAX_DELAY);
- vTaskSuspend(drv_hbr_wdg_task);
- xSemaphoreGive(wdg_sync);
- return SUCCESS;
-}
-
-/// H-Bridge API ---------------------------------------------------------------
-/**
- * @brief Set PWM period and duty cycle to HBR_PWM pin
- *
- * Set period and dutycycle to HBR_PWM pin.
- * Period is expected to be in us, duty cycle in percent of the period,
- *
- * If period is lower than 50us or duty greater than 100, function returns without having effect.
- *
- * @param[in] period Period of PWM in us
- * @param[in] duty Width of duty in %
- */
-int8_t drv_hbr_pwm_set_signal(double period, uint32_t duty)
-{
- hetSIGNAL_t tmp_signal;
-
- if (duty > 100)
- return FAILURE;
-
- if (period < 50)
- return FAILURE;
-
- tmp_signal.duty = duty;
- tmp_signal.period = period;
- pwmSetSignal(hetRAM1, pwm0, tmp_signal);
-
- pwm_initialized = TRUE;
-
- return SUCCESS;
-}
-
-/**
- * Start PWM on HBR_PWM pin
- *
- * If PWM was set previously by hbr_pwm_set_signal function, this procedure starts it.
- * Otherwise function returns and PWM is not started.
- *
- * @return 0 if success, -1 when PWM was not yes set.
- */
-int8_t drv_hbr_pwm_start()
-{
- if (pwm_initialized) {
-
- pwmStart(hetRAM1, pwm0);
- return SUCCESS;
-
- }
- else
-
- return FAILURE;
-}
-
-/**
- * @brief Stop PWM on HBR_PWM pin
- */
-void drv_hbr_pwm_stop()
-{
- pwmStop(hetRAM1, pwm0);
-}
-
-void drv_hbr_pwm_set_duty(uint8_t percent)
-{
- // Don't mind doing range check, pwmSetDuty handles this in error free
- // manner.
- pwmSetDuty(hetRAM1, pwm0, percent);
-}
-
-/**
- * @brief Get duty width of PWM on HBR_PWM pin
- *
- * @return Duty width of PWM in %
- */
-uint32_t drv_hbr_pwm_get_duty()
-{
- hetSIGNAL_t tmp_signal;
-
- tmp_signal = pwmGetSignal(hetRAM1, pwm0);
- return tmp_signal.duty;
-}
-
-/**
- * @brief Get period of PWM on HBR_PWM pin
- *
- * @return Period of PWM in us
- */
-double drv_hbr_pwm_get_period()
-{
- hetSIGNAL_t tmp_signal;
-
- tmp_signal = pwmGetSignal(hetRAM1, pwm0);
- return tmp_signal.period;
-
-}
-
-/**
- * @brief Set value to HBR_DIR pin.
- *
- * @param[in] direction If O, set hbr_dir to 0, otherwise to 1
- */
-void drv_hbr_set_dir(int direction)
-{
- hal_gpio_pin_set_value(PIN_DSC_HBRDIR, direction);
-}
-
-/**
- * @brief Get value of hbr_dir
- *
- * @return return 0 or 1 - the value of hbr_dir
- */
-int drv_hbr_get_dir()
-{
- return hal_gpio_pin_get_value(PIN_DSC_HBRDIR);
-}
-
-/**
- * @brief Set value to HBR_EN pin.
- *
- * @param[in] direction If O, set hbr_en to 0, otherwise to 1
- */
-void drv_hbr_set_en(int value)
-{
- hal_gpio_pin_set_value(PIN_DSC_HBREN, value);
-}
-
-/**
- * @brief Get value of HBR_EN
- *
- * @return return 0 or 1 - the value of hbr_en
- */
-int drv_hbr_get_en()
-{
- return hal_gpio_pin_get_value(PIN_DSC_HBREN);
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : hout.c
- *
- * Abstract:
- * This file provides functions and procedures to manipulate HOUT port.
- *
- * Functions for setting, starting and stopping PWM on selected HOUT pin.
- */
-
-//#include "drv_hout.h"
-#include "drv/drv.h"
-
-#define HOUT_PWM_INITIALIZED 0x1
-#define HOUT_PWM_RUNNING 0x100
-
-/** Map of hout_in pin descriptors to their index **/
-static uint32_t hout_pin_in_descs[PORT_NV_HOUTIN] = {PIN_DSC_HOUT1IN, PIN_DSC_HOUT2IN, PIN_DSC_HOUT3IN, PIN_DSC_HOUT4IN, PIN_DSC_HOUT5IN, PIN_DSC_HOUT6IN};
-/** Map of hout_diag pin descriptors to their index **/
-static uint32_t hout_pin_diag_descs[PORT_NV_HOUTDIAG] = {PIN_DSC_HOUT1DIAG, PIN_DSC_HOUT2DIAG, PIN_DSC_HOUT3DIAG, PIN_DSC_HOUT4DIAG, PIN_DSC_HOUT5DIAG, PIN_DSC_HOUT6DIAG};
-/** PWM modules from N2HET mapped to HOUT pin ID 0-5 **/
-static uint8_t hout_pwm_map[PORT_NV_HOUTIN] = {pwm1, pwm2, pwm3, pwm4, pwm5, pwm6};
-/** Flag variable
- * 1st byte - if pwm for each HOUT pin was set a period and duty, so it can be started.
- * 2nd byte - if pwm is currently running
- **/
-uint16_t hout_pwm_state = 0;
-
-/**
- * @brief Set PWM period and duty cycle to HOUT pin
- *
- * Set period and dutycycle to HOUT pin.
- * Period is expected to be in us, duty cycle in percent of the period,
- * hout_id is indexing HOUT pin 0-5.
- *
- * If period is lower than 1, duty greater than 100 or hout_id out of range <0;5>,
- * function returns without having effect.
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- * @param[in] period Period of PWM in us
- * @param[in] duty Width of duty in %
- */
-void hout_pwm_set_signal(uint8_t hout_id, double period, uint32_t duty)
-{
- hetSIGNAL_t tmp_signal;
-
- if (duty > 100) return;
- if (period < 1) return;
- tmp_signal.duty = duty;
- tmp_signal.period = period;
- pwmSetSignal(hetRAM1, hout_pwm_map[hout_id], tmp_signal);
- hout_pwm_state |= (HOUT_PWM_INITIALIZED << hout_id);
-}
-
-/**
- * @brief Start PWM on HOUT pin
- *
- * If PWM was set previously by hout_pwm_set_signal function, this procedure starts it.
- * Otherwise function returns and PWM is not started.
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- * @return 0 if success, -1 when PWM was not yes set.
- */
-int hout_pwm_start(uint8_t hout_id)
-{
- if (hout_pwm_state & (HOUT_PWM_INITIALIZED << hout_id)) {
- pwmStart(hetRAM1, hout_pwm_map[hout_id]);
- hout_pwm_state |= HOUT_PWM_RUNNING << hout_id;
- return 0;
- }
- else
- return -1;
-}
-
-/**
- * @brief Stop PWM on HOUT pin
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- */
-void hout_pwm_stop(uint8_t hout_id)
-{
- pwmStop(hetRAM1, hout_pwm_map[hout_id]);
- hout_pwm_state &= ~(HOUT_PWM_RUNNING << hout_id);
-}
-
-/**
- * @brief Get duty width of PWM on HOUT pin
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- * @return Duty width of PWM in %
- */
-uint32_t hout_pwm_get_duty(uint8_t hout_id)
-{
- hetSIGNAL_t tmp_signal;
-
- tmp_signal = pwmGetSignal(hetRAM1, hout_pwm_map[hout_id]);
- return tmp_signal.duty;
-}
-
-/**
- * @brief Get period of PWM on HOUT pin
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- * @return Period of PWM in us
- */
-double hout_pwm_get_period(uint8_t hout_id)
-{
- hetSIGNAL_t tmp_signal;
-
- tmp_signal = pwmGetSignal(hetRAM1, hout_pwm_map[hout_id]);
- return tmp_signal.period;
-
-}
-
-/**
- * @brief Runs test of selected HOUT pin.
- *
- * Function runs a test to check if HOUT pin is in good or fault condition.
- * When HOUT is OK, HOUT_DIAG pin has the same value as HOUT_IN pin.
- * When HOUT is in fault state, HOUT_DIAG periodically follows HOUT_PIN for 2ms and shorts to ground for 2ms.
- *
- * @param[in] hout_id ID of HOUT pin from range 0-5
- * @return 0 (HOUT_OK) - hout is in good state and is workiing
- * 1(HOUT_FAILED) - hout id in fault state and generates an error code
- * 2(HOUT_NOT_ON) - HOUT has not been activated
- * -1 when error
- */
-int hout_fail(uint8_t hout_id)
-{
-
- // FIXME This function is more test application centered and should be
- // removed from library. If user calls this function (which is blocking
- // by the intensive use of vTaskDelay) from the main working a overrun
- // is guaranteed, which, offcourse, is not desired at all.
- uint32_t i;
- uint16_t pwm_running;
- int err_cnt = 0;
-
- if (hout_id >= PORT_NV_HOUTIN) return -1; // Bad parameter
- pwm_running = hout_pwm_state & (HOUT_PWM_RUNNING << hout_id);
-
- if (!pwm_running)
- return HOUT_NOT_ON; // HOUT is not powered on
- else
- hout_pwm_stop(hout_id);
- vTaskDelay(1/portTICK_RATE_MS);
- hal_gpio_pin_set_value(hout_pin_in_descs[hout_id], 1);
- for (i = 0; i < 4; i++) {
- if (hal_gpio_pin_get_value(hout_pin_diag_descs[hout_id]) != 1)
- err_cnt++; // Input value and output value are not equal
- vTaskDelay(1/portTICK_RATE_MS);
- }
- hal_gpio_pin_set_value(hout_pin_in_descs[hout_id], 0);
- if (pwm_running) hout_pwm_start(hout_id);
- return (err_cnt == 0) ? HOUT_OK : HOUT_FAILED;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : lout.c
- *
- * Abstract:
- * This file contains functions to control LOUT port over SPI
- */
-
-//#include "drv/lout.h"
-#include "drv/drv.h"
-
-/** Prepared spi command */
-uint32_t lout_spi_cmd = LOUT_SPICMD_INIT_VAL;
-/** Shadow variable used during spi sending */
-uint32_t lout_spi_cmd_sh = LOUT_SPICMD_INIT_VAL;
-/** Spi response */
-uint32_t lout_spi_resp = 0;
-/** Pin mask definitions, those masks are used by val2mfld and mfld2val macros to set and get values into commands */
-static const uint32_t lout_pin_msk[] = {
- 0xC000, // B [0000 0000] [0000 0000] [1100 0000] [0000 0000]
- 0x3000, // B [0000 0000] [0000 0000] [0011 0000] [0000 0000]
- 0xC00, // B [0000 0000] [0000 0000] [0000 1100] [0000 0000]
- 0x300, // B [0000 0000] [0000 0000] [0000 0011] [0000 0000]
- 0xC0000000, // B [1100 0000] [0000 0000] [0000 0000] [0000 0000]
- 0x30000000, // B [0011 0000] [0000 0000] [0000 0000] [0000 0000]
- 0xC000000, // B [0000 1100] [0000 0000] [0000 0000] [0000 0000]
- 0x3000000 // B [0000 0011] [0000 0000] [0000 0000] [0000 0000]
-};
-
-void lout_init()
-{
- // FIXME: Not sure if all those are required. Also not safe for multiple calls.
- dmmInit();
- gioInit();
- hetInit();
- //spi_tms570_init();
-}
-
-/**
- * @brief Set value 0 or 1 to Lout pin
- * This function prepares command for spi, that sets value on 1 lout pin
- *
- * @param[in] pin number of the pin
- * @param[in] val value to be set
- * @return 0 when success, -1 when bad parameter
- */
-int lout_set_pin(uint32_t pin, int val)
-{
-
- int new_val;
-
- if (val == 0)
- new_val = LOUT_CODE0;
- else if (val == 1)
- new_val = LOUT_CODE1;
- else
- return -1;
-
- uint32_t msk = lout_pin_msk[pin - 1];
- uint32_t old_val = __mfld2val(msk, lout_spi_cmd);
- lout_spi_cmd ^= __val2mfld(msk, old_val); // Delete old unknown value
- lout_spi_cmd |= __val2mfld(msk, new_val); // Insert new value
- return 0;
-}
-
-/**
- * @brief Get value from lout pin
- * This function gets value of 1 lout pin. The value is read from the last spi command.
- * @param[in] pin number of the pin
- * @return 0 or 1 when succes, -1 when bad parameter
- */
-int lout_get_pin(uint32_t pin)
-{
-
- unsigned int msk = lout_pin_msk[pin - 1];
- unsigned int val = __mfld2val(msk, lout_spi_cmd);
-
- if (val == LOUT_CODE0)
- return 0;
- if (val == LOUT_CODE1)
- return 1;
-
- return -1;
-}
-
-/**
- * @brief Set values on all pins of LOUT port
- * This function prepares command for spi, that sets value on all lout pins.
- *
- * @param[in] word bits of the word are assigned to LOUT pins. 1st bit -> LOUT1, 2nd bit -> LOUT2 ...
- */
-void lout_set_word(uint8_t word)
-{
- int i;
-
- for (i = 0; i < 8; i++,word >>= 1) {
- lout_set_pin(i+1, word&0x1);
- }
-}
-
-/**
- * @brief Get values from all pins of LOUT port
- * This function gets value from all lout pins. It reads the values from last spi command.
- *
- * @return bits of the returned word are assigned to LOUT pins. 1st bit -> LOUT1, 2nd bit -> LOUT2 ...
- */
-uint8_t lout_get_word()
-{
- uint8_t word = 0;
- int i;
-
- for (i = 0; i < 8; i++) {
- word |= lout_get_pin(i+1) << i;
- }
- return word;
-}
-
-/**
- * Send prepared command to the spi, store response.
- *
- * @return spi response
- */
-int lout_spi_transfer()
-{
-
- port_desc_t *desc;
-
- desc = hal_port_get_dsc(PORT_NAME_LOUT, -1);
-
- lout_spi_cmd_sh = lout_spi_cmd;
- uint32_t commands[4];
- commands[0] = (lout_spi_cmd_sh & 0xFF000000) >> 24;
- commands[1] = (lout_spi_cmd_sh & 0xFF0000) >> 16;
- commands[2] = (lout_spi_cmd_sh & 0xFF00) >> 8;
- commands[3] = (lout_spi_cmd_sh & 0xFF);
-
- lout_spi_resp = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
- return lout_spi_resp;
-}
-
-/**
- * Returns actual spi command
- * @return actual spi command
- */
-uint32_t lout_spi_get_cmd()
-{
- return lout_spi_cmd;
-}
-
-/**
- * Returns last spi response
- * @return last spi response
- */
-uint32_t lout_spi_get_response()
-{
- return lout_spi_resp;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Carlos Jenkins <carlos@jenkins.co.cr>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : mout.c
- * Abstract:
- * RPP driver implementation for MOUT.
- *
- * References:
- * hal/gpio_tms570.h
- * hal/gpio_tms570_def.h
- */
-
-
-#include "drv/mout.h"
-
-const static uint32_t dsc_pin_map[6U][2U] = {
- {PIN_DSC_MOUT1IN, PIN_DSC_MOUT1EN},
- {PIN_DSC_MOUT2IN, PIN_DSC_MOUT2EN},
- {PIN_DSC_MOUT3IN, PIN_DSC_MOUT3EN},
- {PIN_DSC_MOUT4IN, PIN_DSC_MOUT4EN},
- {PIN_DSC_MOUT5IN, PIN_DSC_MOUT5EN},
- {PIN_DSC_MOUT6IN, PIN_DSC_MOUT6EN}
-};
-
-
-int8_t drv_mout_set(uint8_t pin, uint8_t val)
-{
- // Check range
- if (pin > 5)
- return -1;
-
- hal_gpio_pin_set_value(dsc_pin_map[pin][0], val);
- return SUCCESS;
-}
-
-
-int8_t drv_mout_diag(uint8_t pin)
-{
- // Check range
- if (pin > 5)
- return -1;
-
- if (hal_gpio_pin_get_value(dsc_pin_map[pin][1]) == 1)
- return HIGH;
- return LOW;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : port_spi.c
- *
- * Abstract:
- * This file contains getter and setter functions for SPI port type.
- */
-
-//#include "hal_port_spi.h"
-// Cannot include upper layer
-//#include "drv_spi.h"
-//#include "cmdproc.h"
-#include "hal/hal.h"
-
-#define PORT_BUF 4
-/** Buffer for spi command to be sent */
-uint8_t spi_port_buf_tx[PORT_BUF];
-/** Buffer for spi response */
-uint8_t spi_port_buf_rx[PORT_BUF];
-
-
-/**
- * Transfer command through the spi
- * @param[in] config Address of the SPI
- * @param[in] num_bytes Number of bytes to be trasfered
- * @param[in] commands SPI command to be sent
- * @return spi response
- */
-uint32_t hal_spi_port_transfer_command(uint32_t *config, uint32_t num_bytes, const uint32_t *commands)
-{
- spi_drv_t *ifc;
- int i;
- uint32_t ret;
-
- for (i = 0; i < num_bytes; i++)
- spi_port_buf_tx[i] = commands[i];
-
- ifc = spi_find_drv(NULL, config[0]);
- if (ifc == NULL)
- return 0;
-
- if (!(ifc->flags & SPI_IFC_ON))
- return 0;
-
- spi_transfer(ifc, config[1], num_bytes, spi_port_buf_tx, spi_port_buf_rx);
- ret = 0;
- for (i = 0; i < num_bytes; i++)
- ret |= spi_port_buf_rx[i] << i*8;
- return ret;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : spi.c
- */
-
-//#include "ul/ul_list.h"
-//#include "drv/spi.h"
-//#include "cpu_def.h"
-//#include "ul/ul_list.h"
-#include "hal/hal.h"
-
-int spi_msg_rq_ins(spi_drv_t *ifc, spi_msg_head_t *msg)
-{
- spi_isr_lock_level_t saveif;
-
- if (!ifc)
- return -1;
-
- if (!(ifc->flags & SPI_IFC_ON))
- return -1;
-
- spi_isr_lock(saveif);
- spi_rq_queue_insert(ifc, msg);
- spi_isr_unlock(saveif);
- ifc->ctrl_fnc(ifc, SPI_CTRL_WAKE_RQ, NULL);
- return 0;
-}
-
-int spi_transfer_callback(struct spi_drv *ifc, int code, struct spi_msg_head *msg)
-{
- if (msg->private)
- msg->private = 0;
- return 0;
-}
-
-int spi_transfer(spi_drv_t *ifc, int addr, int rq_len, const void *tx_buf, void *rx_buf)
-{
- spi_msg_head_t msg;
-
- msg.flags = 0;
- //msg.ifc = NULL;
- spi_rq_queue_init_detached(&msg);
- msg.addr = addr;
- msg.rq_len = rq_len;
- msg.tx_buf = tx_buf;
- msg.rx_buf = rx_buf;
- msg.callback = spi_transfer_callback;
- msg.private = 1;
-
- if (spi_msg_rq_ins(ifc, &msg) < 0)
- return -1;
-
- /* Wait for the request completion */
- while (msg.private)
- __memory_barrier();
-
-
- if (msg.flags & (SPI_MSG_FAIL | SPI_MSG_ABORT))
- return -1;
-
- return msg.rq_len;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * Authors:
- * - Michal Horn <hornmich@fel.cvut.cz>
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : spi_resp_transl.c
- *
- * Abstract:
- * This module provides the capability to translate pure SPI response into human readable form.
- *
- * Some SPI peripherals provides simple responses, but some others provide responses depending
- * on previous command, they have obtained.
- *
- * So we have a structure, that maps SPI peripheral names (spi port names) to arrays of another
- * structure, that maps spi commands to responses field descriptors.
- *
- * Command to response field map consists of a command mask, command, pointer to field
- * descriptor and number of fields in field descriptor.
- *
- * Each fields descriptor maps field name to field mask, that specifies the meaning of each
- * bit or group of bits in the response.
- */
-
-//#include "spi_resp_transl.h"
-//#include "cmdproc_io_tisci.h"
-#include "hal/hal.h"
-
-// Field descriptors
-static const spitr_field_desc_t din_glob_field_descs[DIN_NUM_GLOB_FD] = {
- { .field_name = "Thermal flag\t", .mask = (1 << 23) },
- { .field_name = "INT flag\t", .mask = (1 << 22) },
- { .field_name = "SP0 - DIN0\t", .mask = (1 << 14) },
- { .field_name = "SP1 - DIN1\t", .mask = (1 << 15) },
- { .field_name = "SP2 - DIN2\t", .mask = (1 << 16) },
- { .field_name = "SP3 - DIN3\t", .mask = (1 << 17) },
- { .field_name = "SP4 - DIN4\t", .mask = (1 << 18) },
- { .field_name = "SP5 - DIN5\t", .mask = (1 << 19) },
- { .field_name = "SP6 - DIN6\t", .mask = (1 << 20) },
- { .field_name = "SP7 - DIN7\t", .mask = (1 << 21) },
- { .field_name = "SG0 - DIN8\t", .mask = (1 << 0) },
- { .field_name = "SG1 - DIN9\t", .mask = (1 << 1) },
- { .field_name = "SG2 - DIN10\t", .mask = (1 << 2) },
- { .field_name = "SG3 - DIN11\t", .mask = (1 << 3) },
- { .field_name = "SG4 - DIN12\t", .mask = (1 << 4) },
- { .field_name = "SG5 - DIN13\t", .mask = (1 << 5) },
- { .field_name = "SG6 - DIN14\t", .mask = (1 << 6) },
- { .field_name = "SG7 - DIN15\t", .mask = (1 << 7) },
- { .field_name = "SG8 - NA\t", .mask = (1 << 8) },
- { .field_name = "SG9 - NA\t", .mask = (1 << 9) },
- { .field_name = "SG10 - NA\t", .mask = (1 << 10) },
- { .field_name = "SG11 - NA\t", .mask = (1 << 11) },
- { .field_name = "SG12 - NA\t", .mask = (1 << 12) },
- { .field_name = "SG13 - NA\t", .mask = (1 << 13) }
-};
-
-static const spitr_field_desc_t lout_glob_field_descs[LOUT_NUM_GLOB_FD] = {
- { .field_name = "U401 VS PS M", .mask = (1 << 24) },
- { .field_name = "U401 IN8 state", .mask = (1 << 27) },
- { .field_name = "U401 IN7 state", .mask = (1 << 28) },
- { .field_name = "U401 IN6 state", .mask = (1 << 29) },
- { .field_name = "U401 IN5 state", .mask = (1 << 30) },
- { .field_name = "U401 Driver 8 status", .mask = (uint32_t)(1 << 31) },
- { .field_name = "U401 Driver 7 status", .mask = (1 << 16) },
- { .field_name = "U401 Driver 6 status", .mask = (1 << 17) },
- { .field_name = "U401 Driver 5 status", .mask = (1 << 18) },
- { .field_name = "U401 Driver 4 status", .mask = (1 << 19) },
- { .field_name = "U401 Driver 3 status", .mask = (1 << 20) },
- { .field_name = "U401 Driver 2 status", .mask = (1 << 21) },
- { .field_name = "U401 Driver 1 status", .mask = (1 << 22) },
- { .field_name = "U401 Thermal warning", .mask = (1 << 23) },
- { .field_name = "U404 VS PS M", .mask = (1 << 8) },
- { .field_name = "U404 IN8 state", .mask = (1 << 11) },
- { .field_name = "U404 IN7 state", .mask = (1 << 12) },
- { .field_name = "U404 IN6 state", .mask = (1 << 13) },
- { .field_name = "U404 IN5 state", .mask = (1 << 14) },
- { .field_name = "U404 Driver 8 status", .mask = (1 << 15) },
- { .field_name = "U404 Driver 7 status", .mask = (1 << 0) },
- { .field_name = "U404 Driver 6 status", .mask = (1 << 1) },
- { .field_name = "U404 Driver 5 status", .mask = (1 << 2) },
- { .field_name = "U404 Driver 4 status", .mask = (1 << 3) },
- { .field_name = "U404 Driver 3 status", .mask = (1 << 4) },
- { .field_name = "U404 Driver 2 status", .mask = (1 << 5) },
- { .field_name = "U404 Driver 1 status", .mask = (1 << 6) },
- { .field_name = "U404 Thermal warning", .mask = (1 << 7) }
-};
-
-static const spitr_field_desc_t dac_glob_field_descs[DAC_NUM_GLOB_FD] = {
- { .field_name = "Provides no informations", .mask = 0 }
-};
-
-static const spitr_field_desc_t fray_glob_field_descs[FRAY_NUM_GLOB_FD] = {
- { .field_name = "Parity bit", .mask = (1 << 0) },
- { .field_name = "SPI error", .mask = (1 << 5) },
- { .field_name = "UVVIO", .mask = (1 << 6) },
- { .field_name = "UVVCC", .mask = (1 << 7) },
- { .field_name = "TXEN clamped", .mask = (1 << 8) },
- { .field_name = "Temp high", .mask = (1 << 9) },
- { .field_name = "Bus error", .mask = (1 << 10) },
- { .field_name = "Pwon", .mask = (1 << 11) },
- { .field_name = "BGE clamped", .mask = (1 << 12) },
- { .field_name = "Transmiter enabled", .mask = (1 << 13) },
- { .field_name = "Normal mode", .mask = (1 << 14) },
- { .field_name = "Bus wake", .mask = (1 << 15) }
-};
-
-static const spitr_field_desc_t hbr_statreg0_field_descs[HBR_NUM_STATREG_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "DS_MON_3", .mask = (1 << 7) },
- { .field_name = "DS_MON_2", .mask = (1 << 6) },
- { .field_name = "DS_MON_1", .mask = (1 << 5) },
- { .field_name = "DS_MON_0", .mask = (1 << 4) },
- { .field_name = "OT_EXT", .mask = (1 << 1) },
- { .field_name = "CP_LOW", .mask = (1 << 0) }
-};
-
-static const spitr_field_desc_t hbr_applreg1_field_descs[HBR_NUM_APPLREG1_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "RWD", .mask = (1 << 7) },
- { .field_name = "FW_PAS", .mask = (1 << 6) },
- { .field_name = "OFF_CAL", .mask = (1 << 5) },
- { .field_name = "CLK_SPCTR", .mask = (1 << 4) },
- { .field_name = "OVT", .mask = (1 << 3) },
- { .field_name = "OV_UV_RD", .mask = (1 << 2) },
- { .field_name = "DIAG", .mask = (3 << 0) }
-};
-
-static const spitr_field_desc_t hbr_applreg2_field_descs[HBR_NUM_APPLREG2_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "RWD", .mask = (1 << 7) },
- { .field_name = "COPT", .mask = (7 << 4) },
- { .field_name = "FW", .mask = (1 << 3) },
- { .field_name = "MCSA", .mask = (1 << 2) },
- { .field_name = "GCSA", .mask = (3 << 0) }
-};
-
-static const spitr_field_desc_t hbr_applreg3_field_descs[HBR_NUM_APPLREG3_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "RWD", .mask = (1 << 7) },
- { .field_name = "EXT_TS", .mask = (1 << 6) },
- { .field_name = "EXT_TH_5", .mask = (1 << 5) },
- { .field_name = "EXT_TH_4", .mask = (1 << 4) },
- { .field_name = "EXT_TH_3", .mask = (1 << 3) },
- { .field_name = "EXT_TH_2", .mask = (1 << 2) },
- { .field_name = "EXT_TH_1", .mask = (1 << 1) },
- { .field_name = "EXT_TH_0", .mask = (1 << 0) }
-};
-
-static const spitr_field_desc_t hbr_diaddr0_field_descs[HBR_NUM_DIADDR0_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "FAM", .mask = (3 << 6) },
- { .field_name = "NR_PI", .mask = (0x3F << 0) }
-};
-
-static const spitr_field_desc_t hbr_diaddr1_field_descs[HBR_NUM_DIADDR1_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "PRD_ID", .mask = (0xFF << 0) }
-};
-
-static const spitr_field_desc_t hbr_diaddr2_field_descs[HBR_NUM_DIADDR2_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "PRD_ID", .mask = (0xFF << 0) }
-};
-
-static const spitr_field_desc_t hbr_diaddr3_field_descs[HBR_NUM_DIADDR3_FD] = {
- { .field_name = "GL_ER", .mask = (1 << 15) },
- { .field_name = "Frame Error", .mask = (1 << 14) },
- { .field_name = "STK_RESET_Q", .mask = (1 << 13) },
- { .field_name = "TSD", .mask = (1 << 12) },
- { .field_name = "TW", .mask = (1 << 11) },
- { .field_name = "UV", .mask = (1 << 10) },
- { .field_name = "OV", .mask = (1 << 9) },
- { .field_name = "WDTO", .mask = (1 << 8) },
- { .field_name = "BR", .mask = (1 << 7) },
- { .field_name = "AR5", .mask = (1 << 6) },
- { .field_name = "AR4", .mask = (1 << 5) },
- { .field_name = "AR3", .mask = (1 << 4) },
- { .field_name = "32-bits", .mask = (1 << 3) },
- { .field_name = "24-bits", .mask = (1 << 2) },
- { .field_name = "16-bits", .mask = (1 << 1) },
- { .field_name = "8-bits", .mask = (1 << 0) }
-};
-
-/* Map register descriptors to spi commands */
-static const spitr_cmd_map_t din_cmd_map[DIN_NUM_CMD_D] = {
- { .cmd_msk = 0, .command = 0, .field_desc = din_glob_field_descs, .num_fields = DIN_NUM_GLOB_FD}
-};
-
-static const spitr_cmd_map_t lout_cmd_map[LOUT_NUM_CMD_D] = {
- { .cmd_msk = 0, .command = 0, .field_desc = lout_glob_field_descs, .num_fields = LOUT_NUM_GLOB_FD }
-};
-
-static const spitr_cmd_map_t dac_cmd_map[DAC_NUM_CMD_D] = {
- { .cmd_msk = 0, .command = 0, .field_desc = dac_glob_field_descs, .num_fields = DAC_NUM_GLOB_FD }
-};
-
-static const spitr_cmd_map_t fray_cmd_map[FRAY_NUM_CMD_D] = {
- { .cmd_msk = 0, .command = 0, .field_desc = fray_glob_field_descs, .num_fields = FRAY_NUM_GLOB_FD }
-};
-
-static const spitr_cmd_map_t hbr_cmd_map[HBR_NUM_CMD_D] = {
- { .cmd_msk = 0x0000FF00, .command = 0xC000, .field_desc = hbr_diaddr0_field_descs, .num_fields = HBR_NUM_DIADDR0_FD },
- { .cmd_msk = 0x0000FF00, .command = 0xC100, .field_desc = hbr_diaddr1_field_descs, .num_fields = HBR_NUM_DIADDR1_FD },
- { .cmd_msk = 0x0000FF00, .command = 0xC200, .field_desc = hbr_diaddr2_field_descs, .num_fields = HBR_NUM_DIADDR2_FD },
- { .cmd_msk = 0x0000FF00, .command = 0xC300, .field_desc = hbr_diaddr3_field_descs, .num_fields = HBR_NUM_DIADDR3_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x8000, .field_desc = hbr_statreg0_field_descs, .num_fields = HBR_NUM_STATREG_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x4000, .field_desc = hbr_statreg0_field_descs, .num_fields = HBR_NUM_STATREG_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x4100, .field_desc = hbr_applreg1_field_descs, .num_fields = HBR_NUM_APPLREG1_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x4200, .field_desc = hbr_applreg2_field_descs, .num_fields = HBR_NUM_APPLREG2_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x4300, .field_desc = hbr_applreg3_field_descs, .num_fields = HBR_NUM_APPLREG3_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x0100, .field_desc = hbr_applreg1_field_descs, .num_fields = HBR_NUM_APPLREG1_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x0200, .field_desc = hbr_applreg2_field_descs, .num_fields = HBR_NUM_APPLREG2_FD },
- { .cmd_msk = 0x0000FF00, .command = 0x0300, .field_desc = hbr_applreg3_field_descs, .num_fields = HBR_NUM_APPLREG3_FD },
-};
-
-/* Map command maps to SPI peripheral name */
-static const spitr_name_map_t spitr_map[NUM_SPI_DEVICES] = {
- { .spi_name = PORT_NAME_DINSPI, .cmd_map = din_cmd_map, .num_cmd = DIN_NUM_CMD_D},
- { .spi_name = PORT_NAME_LOUT, .cmd_map = lout_cmd_map, .num_cmd = LOUT_NUM_CMD_D },
- { .spi_name = PORT_NAME_DAC1_2, .cmd_map = dac_cmd_map, .num_cmd = DAC_NUM_CMD_D },
- { .spi_name = PORT_NAME_DAC3_4, .cmd_map = dac_cmd_map, .num_cmd = DAC_NUM_CMD_D },
- { .spi_name = PORT_NAME_HBR, .cmd_map = hbr_cmd_map, .num_cmd = HBR_NUM_CMD_D },
- { .spi_name = PORT_NAME_FRAY1, .cmd_map = fray_cmd_map, .num_cmd = FRAY_NUM_CMD_D },
- { .spi_name = PORT_NAME_FRAY2, .cmd_map = fray_cmd_map, .num_cmd = FRAY_NUM_CMD_D }
-};
-
-
-
-/**
- * Get the map spi command to spi response.
- * @param[in] spi_port_name String of the port name
- * @param[in] len Length of the port name string, if terminated by '/0', then len = -1
- * @param[out] num_cmdDesc returns number of command->fieldDesc fields assigned to the map
- * @return command to field_desc map or NULL if not found
- */
-const spitr_cmd_map_t *get_spi_cmd_map(const char *spi_port_name, int len, uint32_t *num_cmdDesc)
-{
- uint32_t i;
- const char *spi_port_name_ptr;
- char port_name_term[32];
-
- if (len != -1) { // port name not terminated by '\0'
- strncpy(port_name_term, spi_port_name, len);
- port_name_term[len] = '\0';
- spi_port_name_ptr = port_name_term;
- }
- else spi_port_name_ptr = spi_port_name;
-
- for (i = 0; i < NUM_SPI_DEVICES; i++) {
- if (strcmp(spi_port_name_ptr, spitr_map[i].spi_name) == 0) {
- *num_cmdDesc = spitr_map[i].num_cmd;
- return spitr_map[i].cmd_map;
- }
- }
- *num_cmdDesc = 0;
- return NULL;
-}
-
-/**
- * Get fields descriptor according to the field descriptor map and command.
- * @param[in] cmd_map pointer to structure, that maps commands to their field descriptors
- * @param[in] num_cmd Number of fields in the cmd_map
- * @param[in] cmd Command used as a key value in the cmd_map. We are searching for the field descriptors assigned to this command
- * @param[out] num_fdDesc Number of fields in field descriptors structure, that was found
- * @return pointer to the structure that maps field names to field masks or NULL, when not found
- */
-const spitr_field_desc_t *get_spi_field_desc(const spitr_cmd_map_t *cmd_map, uint32_t num_cmd, uint32_t cmd, uint32_t *num_fdDesc)
-{
- if (cmd_map == NULL) {
- *num_fdDesc = 0;
- return NULL;
- }
-
- uint32_t i;
- for (i = 0; i < num_cmd; i++) {
- uint32_t mskcmd = cmd & cmd_map[i].cmd_msk;
- uint32_t tmpCmd = cmd_map[i].command;
- if (mskcmd == tmpCmd) {
- *num_fdDesc = cmd_map[i].num_fields;
- return cmd_map[i].field_desc;
- }
- }
- *num_fdDesc = cmd_map[i].num_fields;
- return NULL;
-}
-
-/**
- * Translate spi response into human readable form
- * @param[in] fd Pointer to structure that maps Field names to field value masks
- * @param[in] num_fields Number of fields in fd
- * @param[in] value spi response to be traslated
- * @param[out] table The result is stored in this table, where each row consists of the value name and the value
- * @return number of rows in the translated table
- */
-int spitr_fill_tr_table(const spitr_field_desc_t *fd, uint32_t num_fields, uint32_t value, spitr_reg_translate_table_t *table)
-{
- uint32_t i;
-
- for (i = 0; i < num_fields; i++) {
- table->row[i].field_name = fd[i].field_name;
- table->row[i].value = __mfld2val(fd[i].mask, value);
- }
- table->num_rows = num_fields;
- return i;
-}
+++ /dev/null
-/* Copyright (C) 2012-2013 Czech Technical University in Prague
- *
- * This document contains proprietary information belonging to Czech
- * Technical University in Prague. Passing on and copying of this
- * document, and communication of its contents is not permitted
- * without prior written authorization.
- *
- * File : spi_tms570.c
- *
- * Code based on Halcogen generated source code
- */
-
-//#include "spi_tms570.h"
-//#include "drv_spi.h"
-//#include "sys_common.h"
-//#include "ti_drv_dmm.h"
-#include "hal/hal.h"
-
-static int spi_tms570_ctrl_fnc(spi_drv_t *ifc, int ctrl, void *p);
-
-
-/* Each SPI interface has its own static spi_tms570_drv_t struct
- Index to this array is "SPI Interface ID -1" */
-spi_tms570_drv_t spi_tms570_ifcs[4];
-
-/* Addresses of SPI devices (=chips) bound to particular interfaces */
-enum spi_ifc1_devices {
- SPIDEV_MC33972 = 0, SPIDEV_NCV7608_2x
-};
-enum spi_ifc2_devices {
- SPIDEV_SDCARD = 0
-};
-enum spi_ifc3_devices {
- SPIDEV_MCP4922_1 = 0, SPIDEV_MCP4922_2, SPIDEV_MCP4922_3
-};
-enum spi_ifc4_devices {
- SPIDEV_L99H01 = 0, SPIDEV_TJA1082_1, SPIDEV_TJA1082_2
-};
-
-spi_dev_t spi_ifc1_devs[] = {
- [SPIDEV_MC33972] = {
- .cs = SPI_CS_3,
- .dfsel = 0,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- },
- [SPIDEV_NCV7608_2x] = {
- .cs = SPI_CS_4,
- .dfsel = 0,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- }
-};
-
-spi_dev_t spi_ifc2_devs[] = {
- [SPIDEV_SDCARD] = {
- .cs = SPI_CS_0,
- .dfsel = 0,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- }
-};
-
-spi_dev_t spi_ifc3_devs[] = {
- [SPIDEV_MCP4922_1] = {
- .cs = SPI_CS_0,
- .dfsel = 1,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- },
- [SPIDEV_MCP4922_2] = {
- .cs = SPI_CS_4,
- .dfsel = 1,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- },
- [SPIDEV_MCP4922_3] = {
- .cs = SPI_CS_5,
- .dfsel = 1,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- }
-};
-
-spi_dev_t spi_ifc4_devs[] = {
- [SPIDEV_L99H01] = {
- .cs = SPI_CS_0 | SPI_CS_DMM0,
- .dfsel = 1,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- },
- [SPIDEV_TJA1082_1] = {
- .cs = SPI_CS_0 | SPI_CS_DMM1,
- .dfsel = 0,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- },
- [SPIDEV_TJA1082_2] = {
- .cs = SPI_CS_0 | SPI_CS_DMM2,
- .dfsel = 0,
- .wdel = 0,
- .cshold = 1,
- .dlen = 0
- }
-};
-
-/*
- Universal piece of code initializing SPI or MibSPI
- devices in "compatibility" mode.
- 8 CS pins are initialized on each device -- even if
- it does not have so much of them.
- ENA register is set even on SPI devices which do not have it --
- this should not be an issue
- */
-void spiInit(spiBASE_compat_t *spiREG)
-{
- /** bring SPI out of reset */
- spiREG->GCR0 = 1U;
-
- /** SPI master mode and clock configuration */
- spiREG->GCR1 = (1 << 1) /* CLOKMOD */
- |1; /* MASTER */
-
- /** SPI enable pin configuration */
- spiREG->ENAHIGHZ = 0; /* ENABLE HIGHZ */
-
- /** - Delays */
- spiREG->DELAY = (0 << 24) /* C2TDELAY */
- | (0 << 16) /* T2CDELAY */
- | (0 << 8) /* T2EDELAY */
- | 0; /* C2EDELAY */
-
- /** - Data Format 0 */
- spiREG->FMT0 = (0 << 24) /* wdelay */
- | (0 << 23) /* parity Polarity */
- | (0 << 22) /* parity enable */
- | (0 << 21) /* wait on enable */
- | (0 << 20) /* shift direction */
- | (0 << 17) /* clock polarity */
- | (0 << 16) /* clock phase */
- | ((RPP_VCLK1_FREQ / SPI_BR_FORMAT0 - 1 ) << 8) /* baudrate prescale */
- | 8; /* data word length */
-
- /** - Data Format 1 */
- spiREG->FMT1 = (0 << 24) /* wdelay */
- | (0 << 23) /* parity Polarity */
- | (0 << 22) /* parity enable */
- | (0 << 21) /* wait on enable */
- | (0 << 20) /* shift direction */
- | (0 << 17) /* clock polarity */
- | (1 << 16) /* clock phase */
- | ((RPP_VCLK1_FREQ / SPI_BR_FORMAT1 - 1 ) << 8) /* baudrate prescale */
- | 8; /* data word length */
-
- /** - Data Format 2 */
- spiREG->FMT2 = (0 << 24) /* wdelay */
- | (0 << 23) /* parity Polarity */
- | (0 << 22) /* parity enable */
- | (0 << 21) /* wait on enable */
- | (0 << 20) /* shift direction */
- | (0 << 17) /* clock polarity */
- | (0 << 16) /* clock phase */
- | ((RPP_VCLK1_FREQ / SPI_BR_FORMAT2 - 1 ) << 8) /* baudrate prescale */
- | 8; /* data word length */
-
- /** - Data Format 3 */
- spiREG->FMT3 = (0 << 24) /* wdelay */
- | (0 << 23) /* parity Polarity */
- | (0 << 22) /* parity enable */
- | (0 << 21) /* wait on enable */
- | (0 << 20) /* shift direction */
- | (0 << 17) /* clock polarity */
- | (0 << 16) /* clock phase */
- | ((RPP_VCLK1_FREQ / SPI_BR_FORMAT3 - 1 ) << 8) /* baudrate prescale */
- | 8; /* data word length */
-
- /** - set interrupt levels */
- spiREG->LVL = (0 << 9) /* TXINT */
- | (0 << 8) /* RXINT */
- | (0 << 6) /* OVRNINT */
- | (0 << 4) /* BITERR */
- | (0 << 3) /* DESYNC */
- | (0 << 2) /* PARERR */
- | (0 << 1) /* TIMEOUT */
- | (0); /* DLENERR */
-
- /** - clear any pending interrupts */
- spiREG->FLG = 0xFFFFU;
-
- /** - enable interrupts */
- spiREG->INT0 = (0 << 9) /* TXINT */
- | (0 << 8) /* RXINT */
- | (0 << 6) /* OVRNINT */
- | (0 << 4) /* BITERR */
- | (0 << 3) /* DESYNC */
- | (0 << 2) /* PARERR */
- | (0 << 1) /* TIMEOUT */
- | (0); /* DLENERR */
-
- /** initialize SPI Port */
-
- /** - SPI Port output values */
- spiREG->PCDOUT = 1 /* SCS[0] */
- | (1 << 1) /* SCS[1] */
- | (1 << 2) /* SCS[2] */
- | (1 << 3) /* SCS[3] */
- | (1 << 4) /* SCS[4] */
- | (1 << 5) /* SCS[5] */
- | (1 << 6) /* SCS[6] */
- | (1 << 7) /* SCS[7] */
- | (0 << 8) /* ENA */
- | (0 << 9) /* CLK */
- | (0 << 10) /* SIMO */
- | (0 << 11); /* SOMI */
-
- /** - SPI Port direction */
- spiREG->PCDIR = 1 /* SCS[0] */
- | (1 << 1) /* SCS[1] */
- | (1 << 2) /* SCS[2] */
- | (1 << 3) /* SCS[3] */
- | (1 << 4) /* SCS[4] */
- | (1 << 5) /* SCS[5] */
- | (1 << 6) /* SCS[6] */
- | (1 << 7) /* SCS[7] */
- | (0 << 8) /* ENA */
- | (1 << 9) /* CLK */
- | (1 << 10) /* SIMO */
- | (0 << 11); /* SOMI */
-
- /** - SPI Port open drain enable */
- spiREG->PCPDR = 0 /* SCS[0] */
- | (0 << 1) /* SCS[1] */
- | (0 << 2) /* SCS[2] */
- | (0 << 3) /* SCS[3] */
- | (0 << 4) /* SCS[4] */
- | (0 << 5) /* SCS[5] */
- | (0 << 6) /* SCS[6] */
- | (0 << 7) /* SCS[7] */
- | (0 << 8) /* ENA */
- | (0 << 9) /* CLK */
- | (0 << 10) /* SIMO */
- | (0 << 11); /* SOMI */
-
- /** - SPI Port pullup / pulldown selection */
- spiREG->PCPSL = 1 /* SCS[0] */
- | (1 << 1) /* SCS[1] */
- | (1 << 2) /* SCS[2] */
- | (1 << 3) /* SCS[3] */
- | (1 << 4) /* SCS[4] */
- | (1 << 5) /* SCS[5] */
- | (1 << 6) /* SCS[6] */
- | (1 << 7) /* SCS[7] */
- | (1 << 8) /* ENA */
- | (1 << 9) /* CLK */
- | (1 << 10) /* SIMO */
- | (1 << 11); /* SOMI */
-
- /** - SPI Port pullup / pulldown enable*/
- spiREG->PCDIS = 0 /* SCS[0] */
- | (0 << 1) /* SCS[1] */
- | (0 << 2) /* SCS[2] */
- | (0 << 3) /* SCS[3] */
- | (0 << 4) /* SCS[4] */
- | (0 << 5) /* SCS[5] */
- | (0 << 6) /* SCS[6] */
- | (0 << 7) /* SCS[7] */
- | (0 << 8) /* ENA */
- | (0 << 9) /* CLK */
- | (0 << 10) /* SIMO */
- | (0 << 11); /* SOMI */
-
- /* SPI set all pins to functional */
- spiREG->PCFUN = 1 /* SCS[0] */
- | (1 << 1) /* SCS[1] */
- | (1 << 2) /* SCS[2] */
- | (1 << 3) /* SCS[3] */
- | (1 << 4) /* SCS[4] */
- | (1 << 5) /* SCS[5] */
- | (1 << 6) /* SCS[6] */
- | (1 << 7) /* SCS[7] */
- | (1 << 8) /* ENA */
- | (1 << 9) /* CLK */
- | (1 << 10) /* SIMO */
- | (1 << 11); /* SOMI */
-
- /* Default CS logic levels */
- spiREG->CSDEF = 0xFF;
-
- /** Set MibSPI devices into compatibility mode --
- "SPI" devices will hopefully ignore this */
- spiREG->MIBSPIE = 0U;
-
- /** - Finally start SPI */
- spiREG->ENA = 1U;
-}
-
-static boolean_t spi_initialized = FALSE;
-
-int spi_tms570_init(void)
-{
- if (spi_initialized == TRUE)
- return FAILURE;
- spi_initialized = TRUE;
- int i;
-
- spi_tms570_ifcs[0].spi = mibspi_compat_REG1;
- spi_tms570_ifcs[1].spi = spi_compat_REG2;
- spi_tms570_ifcs[2].spi = mibspi_compat_REG3;
- spi_tms570_ifcs[3].spi = spi_compat_REG4;
-
- spi_tms570_ifcs[0].spi_devs = spi_ifc1_devs;
- spi_tms570_ifcs[1].spi_devs = spi_ifc2_devs;
- spi_tms570_ifcs[2].spi_devs = spi_ifc3_devs;
- spi_tms570_ifcs[3].spi_devs = spi_ifc4_devs;
-
-
- for (i = 0; i <= 3; i++) {
- spiInit(spi_tms570_ifcs[i].spi);
- spi_tms570_ifcs[i].spi_drv.ctrl_fnc = spi_tms570_ctrl_fnc;
- spi_rq_queue_init_head(&(spi_tms570_ifcs[i].spi_drv));
- spi_tms570_ifcs[i].spi_drv.msg_act = NULL;
- spi_tms570_ifcs[i].spi_drv.flags = SPI_IFC_ON;
- }
-
- //dmmREG->PC5 = (1 << DMM_DATA5); /* Set to L */
- //dmmREG->PC5 = (1 << DMM_DATA6); /* Set to L */
-
- return SUCCESS;
-}
-
-
-static int spi_tms570_ctrl_fnc(spi_drv_t *ifc, int ctrl, void *p)
-{
- spi_tms570_drv_t *tms570_drv =
- UL_CONTAINEROF(ifc, spi_tms570_drv_t, spi_drv);
-
- switch (ctrl) {
- case SPI_CTRL_WAKE_RQ:
- if (!(ifc->flags & SPI_IFC_ON))
- return -1;
- if (spi_rq_queue_is_empty(ifc))
- return 0;
-
- tms570_drv->spi->INT0 = SPI_INT0_TXINTENA_m;
- // Enable TXINT (Causes an interrupt
- // to be generated every time data is written to the shift
- // register, so that the next word can be written to TXBUF.
- // (=transmitter empty interrupt)
- // Setting this bit will generate an interrupt if the
- // TXINTFLG bit (SPI Flag Register (SPIFLG)[9]) is set to 1.;
- // An interrupt request will be generated as soon as this
- // bit is set to 1.
- return 0;
-
- default:
- return -1;
- }
-}
-
-
-
-/* -------------------------------------------------------------------------- */
-
-
-
-void spi_tms570_isr(int spi_ifc, uint32_t flags)
-{
- spi_msg_head_t *msg;
- spi_tms570_drv_t *spi_tms570_drv;
-
- spi_tms570_drv = &spi_tms570_ifcs[spi_ifc];
- spi_isr_lock_level_t saveif;
- uint8_t val_to_wr;
- uint32_t cs;
- unsigned int rxcnt;
- unsigned int txcnt;
- unsigned int rq_len;
- unsigned int rx_data;
- int stop_fl;
-
- if (flags & SPI_FLG_TXINT_m) {
- do {
- msg = spi_tms570_drv->spi_drv.msg_act;
- if (!msg) { /* Is there any MSG being processed? */
- /* If not, get one from a queue */
- spi_isr_lock(saveif);
- msg = spi_tms570_drv->spi_drv.msg_act =
- spi_rq_queue_first(&spi_tms570_drv->spi_drv);
- spi_isr_unlock(saveif);
-
- if (!msg) { /* Nothing to process */
- volatile unsigned int dummy_read;
- /* Disable TXEMPTY IRQ */
- spi_tms570_drv->spi->INT0 = 0x00;
- spi_tms570_drv->spi->FLG = 0x00;
- dummy_read = spi_tms570_drv->spi->BUF;
- // FIXME "INT |= " with disabled IRQ ??
- return;
- }
-
- spi_tms570_drv->txcnt = 0;
- spi_tms570_drv->rxcnt = 0;
- cs = spi_tms570_drv->spi_devs[msg->addr].cs;
- spi_tms570_drv->transfer_ctrl =
- (cs & 0xff) << 16
- | (spi_tms570_drv->spi_devs[msg->addr].wdel & 0x1) << 26
- | (spi_tms570_drv->spi_devs[msg->addr].cshold & 0x1) << 28
- | (spi_tms570_drv->spi_devs[msg->addr].dfsel & 0x3) << 24;
-
- /* GPIO CS -- setting the multiplexer */
- if (cs > 0xff) {
- switch (cs & 0xFF00) {
- case SPI_CS_DMM0:
- dmmREG->PC5 = (1 << DMM_DATA5); /* Set to L */
- dmmREG->PC5 = (1 << DMM_DATA6); /* Set to L */
- break;
- case SPI_CS_DMM1:
- dmmREG->PC4 = (1 << DMM_DATA5); /* Set to H */
- dmmREG->PC5 = (1 << DMM_DATA6); /* Set to L */
- break;
- case SPI_CS_DMM2:
- dmmREG->PC5 = (1 << DMM_DATA5); /* Set to L */
- dmmREG->PC4 = (1 << DMM_DATA6); /* Set to H */
- break;
- }
- }
- }
-
- rq_len = msg->rq_len;
- rxcnt = spi_tms570_drv->rxcnt;
- txcnt = spi_tms570_drv->txcnt;
- /* RX/TX transfers */
- do {
- /* Receive all the incoming data */
- while (spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m) {
- rx_data = spi_tms570_drv->spi->BUF;
-
- if (msg->rx_buf && (rxcnt < rq_len))
- msg->rx_buf[rxcnt++] = rx_data & 0xFF;
- //FIXME how to make sure we got only 8 bits
- else
- rxcnt++;
- }
-
- /* Send some data */
- while (1) {
- /* Tx buffer full or nothing to send */
- stop_fl = ((txcnt >= rq_len) ||
- (!(spi_tms570_drv->spi->FLG & SPI_FLG_TXINT_m)));
-
- if (stop_fl)
- break;
- /* Make it possible to write "empty data"
- for "read transfers" */
- if (msg->tx_buf)
- val_to_wr = msg->tx_buf[txcnt++];
- else {
- val_to_wr = 0x00;
- txcnt++;
- }
-
- if (txcnt == rq_len) /* Disable CS for the last byte of the transfer */
- spi_tms570_drv->transfer_ctrl &= ~SPI_DAT1_CSHOLD_m;
-
- spi_tms570_drv->spi->DAT1 =
- (uint32_t)(spi_tms570_drv->transfer_ctrl | val_to_wr);
-
- /* We just received something */
- if (spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m)
- break;
- }
- } while (!stop_fl);
- spi_tms570_drv->rxcnt = rxcnt;
- spi_tms570_drv->txcnt = txcnt;
-
- if ((rxcnt >= rq_len) ||
- (!msg->rx_buf && (txcnt >= rq_len) &&
- !(spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m))) { // FIXME
-
- /* Sending of the message successfully finished */
- spi_isr_lock(saveif);
- spi_rq_queue_del_item(msg);
- msg->flags |= SPI_MSG_FINISHED;
- spi_tms570_drv->spi_drv.msg_act = NULL;
- spi_isr_unlock(saveif);
- if (msg->callback)
- msg->callback(&spi_tms570_drv->spi_drv,
- SPI_MSG_FINISHED, msg);
-
- continue;
- }
- if (txcnt < rq_len)
- spi_tms570_drv->spi->INT0 = SPI_INT0_TXINTENA_m;
- else
- spi_tms570_drv->spi->INT0 = SPI_INT0_RXINTENA_m;
-
- } while (1);
- }
-}
-
-spi_drv_t *spi_find_drv(char *name, int number)
-{
- if (number < 1 || number > (sizeof(spi_tms570_ifcs)/sizeof(spi_tms570_ifcs[0])))
- return NULL;
-
- return &spi_tms570_ifcs[number - 1].spi_drv;
-}
-
-#pragma INTERRUPT(spi2LowLevelInterrupt, IRQ)
-void spi2LowLevelInterrupt(void)
-{
- uint32_t flags = spi_compat_REG2->FLG; // & (~spiREG2->LVL & 0x035F);
-
- spi_tms570_isr(2 - 1, flags);
-}
-
-#pragma INTERRUPT(spi2HighLevelInterrupt, IRQ)
-void spi2HighLevelInterrupt(void)
-{
- uint32_t flags = spi_compat_REG2->FLG; // & (~spiREG2->LVL & 0x035F);
-
- spi_tms570_isr(2 - 1, flags);
-}
-
-#pragma INTERRUPT(spi4LowLevelInterrupt, IRQ)
-void spi4LowLevelInterrupt(void)
-{
- uint32_t flags = spi_compat_REG4->FLG; // & (~spiREG4->LVL & 0x035F);
-
- spi_tms570_isr(4 - 1, flags);
-}
-
-#pragma INTERRUPT(spi4HighLevelInterrupt, IRQ)
-void spi4HighLevelInterrupt(void)
-{
- uint32_t flags = spi_compat_REG4->FLG; // & (~spiREG4->LVL & 0x035F);
-
- spi_tms570_isr(4 - 1, flags);
-}
-
-#pragma INTERRUPT(mibspi1HighLevelInterrupt, IRQ)
-void mibspi1HighLevelInterrupt(void)
-{
- uint32_t flags = mibspi_compat_REG1->FLG; // & (~mibspiREG1->LVL & 0x035F);
-
- spi_tms570_isr(1 - 1, flags);
-}
-
-#pragma INTERRUPT(mibspi1LowLevelInterrupt, IRQ)
-void mibspi1LowLevelInterrupt(void)
-{
- uint32_t flags = mibspi_compat_REG1->FLG; // & (~mibspiREG1->LVL & 0x035F);
-
- spi_tms570_isr(1 - 1, flags);
-}
-
-#pragma INTERRUPT(mibspi3HighInterruptLevel, IRQ)
-void mibspi3HighInterruptLevel(void)
-{
- uint32_t flags = mibspi_compat_REG3->FLG; // & (~mibspiREG3->LVL & 0x035F);
-
- spi_tms570_isr(3 - 1, flags);
-}
-
-#pragma INTERRUPT(mibspi3LowLevelInterrupt, IRQ)
-void mibspi3LowLevelInterrupt(void)
-{
- uint32_t flags = mibspi_compat_REG3->FLG; // & (~mibspiREG3->LVL & 0x035F);
-
- spi_tms570_isr(3 - 1, flags);
-}
dmmInit();
gioInit();
hetInit();
- spi_tms570_init();
#endif
return SUCCESS;
gioInit();
hetInit();
linInit();
- spi_tms570_init();
#endif
rpp_din_init();
&phantomInterrupt,
&phantomInterrupt, // 10
&phantomInterrupt,
- &mibspi1HighLevelInterrupt,
+ &phantomInterrupt,
/*#if serialLine == scilinREG
&sciHighLevelinterrupt,
#else
&phantomInterrupt,
&adc1Group1Interrupt, // 15
&phantomInterrupt,
- &spi2HighLevelInterrupt,
+ &phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt, // 20
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt, // 25
- &mibspi1LowLevelInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
- &spi2LowLevelInterrupt, // 30
+ &phantomInterrupt,
+ &phantomInterrupt, // 30
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt, // 35
&phantomInterrupt,
- &mibspi3HighInterruptLevel,
- &mibspi3LowLevelInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt, // 40
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
- &spi4HighLevelInterrupt,
+ &phantomInterrupt,
&phantomInterrupt, // 50
&adc2Group1Interrupt,
&phantomInterrupt,
&phantomInterrupt,
- &spi4LowLevelInterrupt,
+ &phantomInterrupt,
&phantomInterrupt, // 55
&phantomInterrupt,
&phantomInterrupt,
projects / pes-rpp / rpp-lib.git / commitdiff