/**
* MCU endianity. Define the constant as 1 for little endian.
*/
-#define __LITTLE_ENDIAN__ 0
+#define __LITTLE_ENDIAN__ 1
/*
* Clock configuration.
*
* PLL1 configuration.
*/
#define RPP_PLL1_REF_CLK_DIV 6 /**< PLL1 Frequency clock divider. */
-#define RPP_PLL1_CLK_MUL 120 /**< PLL1 Frequency multiplier. */
+#define RPP_PLL1_CLK_MUL 165 /**< PLL1 Frequency multiplier. */
#define RPP_PLL1_CLK_OUT_DIV 2 /**< PLL1 output frequency internal divider. */
#define RPP_PLL1_CLK_DIV 1 /**< PLL1 final clock divider. */
-#define RPP_PLL1_FREQ 160000000 /**< Desired frequency of PLL1 in Hz. Make sure this value is the result
+#define RPP_PLL1_FREQ 220000000 /**< Desired frequency of PLL1 in Hz. Make sure this value is the result
RPP_OSC_FR / RPP_PLL1_REF_CLK_DIV * RPP_PLL1_CLK_MUL / RPP_PLL1_CLK_OUT_DIV / RPP_PLL1_CLK_DIV
because it is used in the code as a reference clock value.
*/
* PLL2 configuration.
*/
#define RPP_PLL2_REF_CLK_DIV 6 /**< PLL2 Frequency clock divider. */
-#define RPP_PLL2_CLK_MUL 120 /**< PLL2 Frequency multiplier. */
+#define RPP_PLL2_CLK_MUL 165 /**< PLL2 Frequency multiplier. */
#define RPP_PLL2_CLK_OUT_DIV 2 /**< PLL2 output frequency internal divider. */
#define RPP_PLL2_CLK_DIV 1 /**< PLL2 final clock divider. */
-#define RPP_PLL2_FREQ 160000000 /**< Desired frequency of PLL2 in Hz. Make sure this value is the result
+#define RPP_PLL2_FREQ 220000000 /**< Desired frequency of PLL2 in Hz. Make sure this value is the result
RPP_OSC_FR / RPP_PLL1_REF_CLK_DIV * RPP_PLL1_CLK_MUL / RPP_PLL1_CLK_OUT_DIV / RPP_PLL1_CLK_DIV
because it is used in the code as a reference clock value.
*/
*/
#define RPP_GHVSRC_CLK_SOURCE SYS_PLL1 /**< Clock source for GCLK, HCLK and VCLK peripherals */
#define RPP_VCLK1_CLK_DIV 2 /**< Clock divider for VCLK1 */
-#define RPP_VCLK1_FREQ 80000000 /**< Desired frequency of the VCLK1 in Hz. Make sure this value is the result
+#define RPP_VCLK1_FREQ 110000000 /**< Desired frequency of the VCLK1 in Hz. Make sure this value is the result
RPP_GHVSRC_CLK_SOURCE / RPP_VCLK1_CLK_DIV
because it is used in the code as a reference clock value.
*/
#define RPP_VCLK2_CLK_DIV 2 /**< Clock divider for VCLK2 */
-#define RPP_VCLK2_FREQ 80000000 /**< Desired frequency of the VCLK2 in Hz. Make sure this value is the result
+#define RPP_VCLK2_FREQ 110000000 /**< Desired frequency of the VCLK2 in Hz. Make sure this value is the result
RPP_GHVSRC_CLK_SOURCE / RPP_VCLK2_CLK_DIV
because it is used in the code as a reference clock value.
*/
#define RPP_VCLK3_CLK_DIV 2 /**< Clock divider for VCLK3 */
-#define RPP_VCLK3_FREQ 80000000 /**< Desired frequency of the VCLK3 in Hz. Make sure this value is the result
+#define RPP_VCLK3_FREQ 110000000 /**< Desired frequency of the VCLK3 in Hz. Make sure this value is the result
RPP_GHVSRC_CLK_SOURCE / RPP_VCLK3_CLK_DIV
because it is used in the code as a reference clock value.
*/
#define RPP_RCLK_CLK_SRC SYS_VCLK /**< Clock source for RTI */
#define RPP_RCLK_CLK_DIV 1 /**< Clock divider for RTI. Value between 0-3. RTI1DIV=2^RPP_RCLK_CLK_DIV */
-#define RPP_RCLK_FREQ 80000000 /**< Desired RTI clock in Hz. Make sure this value is the result
+#define RPP_RCLK_FREQ 110000000 /**< Desired RTI clock in Hz. Make sure this value is the result
RPP_RCLK_CLK_SRC / RPP_RCLK_CLK_DIV
because it is used in the code as a reference clock value.
*/
#define RPP_VCLKA1_CLK_SRC SYS_VCLK /**< Clock source for VCLKA1 */
-#define RPP_VCLKA1_FREQ 80000000 /**< Desired VCLKA1 clock in Hz. Make sure this value is the result
+#define RPP_VCLKA1_FREQ 110000000 /**< Desired VCLKA1 clock in Hz. Make sure this value is the result
RPP_VCLKA1_CLK_SRC
because it is used in the code as a reference clock value.
*/
#define RPP_VCLKA2_CLK_SRC SYS_VCLK /**< Clock source for VCLKA2 */
-#define RPP_VCLKA2_FREQ 80000000 /**< Desired VCLKA2 clock in Hz. Make sure this value is the result
+#define RPP_VCLKA2_FREQ 110000000 /**< Desired VCLKA2 clock in Hz. Make sure this value is the result
RPP_VCLKA2_CLK_SRC
because it is used in the code as a reference clock value.
*/
#define RPP_VCLKA3_CLK_SRC SYS_VCLK /**< Clock source for VCLKA3 */
#define RPP_VCLKA3_DIV_OUT_DIS 0 /**< Disable the VCLKA3 divider output */
#define RPP_VCLKA3_CLK_DIV 2 /**< Clock divider for the VCLKA3 source */
-#define RPP_VCLKA3_FREQ 80000000 /**< Desired VCLKA3 clock in Hz. Make sure this value is the result
+#define RPP_VCLKA3_FREQ 110000000 /**< Desired VCLKA3 clock in Hz. Make sure this value is the result
RPP_VCLKA3_CLK_SRC / RPP_VCLKA3_CLK_DIV if the divider is used, else RPP_VCLKA3_CLK_SRC
because it is used in the code as a reference clock value.
*/
#define RPP_VCLKA4_CLK_SRC SYS_VCLK /**< Clock source for VCLKA4 */
#define RPP_VCLKA4_DIV_OUT_DIS 0 /**< Disable the VCLKA4 divider output */
#define RPP_VCLKA4_CLK_DIV 2 /**< Clock divider for the VCLKA4 source */
-#define RPP_VCLKA4_FREQ 80000000 /**< Desired VCLKA4 clock in Hz. Make sure this value is the result
+#define RPP_VCLKA4_FREQ 110000000 /**< Desired VCLKA4 clock in Hz. Make sure this value is the result
RPP_VCLKA4_CLK_SRC / RPP_VCLKA4_CLK_DIV if the divider is used, else RPP_VCLKA4_CLK_SRC
because it is used in the code as a reference clock value.
*/
projects / pes-rpp / rpp-lib.git / commitdiff