Enable response to ECC errors before Flash ECC enabling

The response has to be enabled before the Flash ECC. See description of
EDACEN field of FEDACCTRL1 register.

diff --git a/rpp/src/sys/sys_startup.c b/rpp/src/sys/sys_startup.c
index 15c9574276f2690c0d48e422147209c4c136a182..eff24d2f6f75291bf234ec38574b8627537b27aa 100644 (file)
--- a/rpp/src/sys/sys_startup.c
+++ b/rpp/src/sys/sys_startup.c
@@ -297,12 +297,12 @@ void _c_int00()
      */
     _coreEnableEventBusExport_();
 
-    /* Enable CPU ECC checking for ATCM (flash accesses) */
-    _coreEnableFlashEcc_();
-
     /* Enable response to ECC errors indicated by CPU for accesses to flash */
     flashWREG->FEDACCTRL1 = 0x000A060A;
 
+    /* Enable CPU ECC checking for ATCM (flash accesses) */
+    _coreEnableFlashEcc_();
+
 /* USER CODE BEGIN (9) */
 /* USER CODE END */