+
+#define CTR_MODE_COUNT_DIR_mask 0x00000001
+enum {CTR_MODE_COUNT_DIR_DOWN, CTR_MODE_COUNT_DIR_UP};
+#define CTR_MODE_REPETITION_mask 0x00000002
+enum {CTR_MODE_REPETITION_DISABLED, CTR_MODE_REPETITION_ENABLED};
+#define CTR_MODE_LOAD_TOGGLE_mask 0x00000004
+enum {CTR_MODE_LOAD_TOGGLE_DISABLED /* reload from A only */,
+ CTR_MODE_LOAD_TOGGLE_ENABLED /* alter A and B */};
+#define CTR_MODE_OUTPUT_TOGGLE_mask 0x00000008
+enum {CTR_MODE_OUTPUT_TOGGLE_DISABLED /* output changed at terminal count */,
+ CTR_MODE_OUTPUT_TOGGLE_ENABLED /* output is toggled at terminal count */};
+#define CTR_MODE_OUTPUT_CONTROL_mask 0x00000030
+enum {CTR_MODE_OUTPUT_CONTROL_DIRECT /* direct output */,
+ CTR_MODE_OUTPUT_CONTROL_INVERTED /* inverted output */,
+ CTR_MODE_OUTPUT_CONTROL_FORCE_LO /* force output low */,
+ CTR_MODE_OUTPUT_CONTROL_FORCE_HI /* force output high */};
+#define CTR_MODE_TRIGGER_SOURCE_mask 0x000000C0
+enum {CTR_MODE_TRIGGER_SOURCE_DISABLED /* trigger disabled */,
+ CTR_MODE_TRIGGER_SOURCE_TXIN /* trigger by counter input (TxIN) */,
+ CTR_MODE_TRIGGER_SOURCE_BY_PREV /* trigger by counter n-1 output */,
+ CTR_MODE_TRIGGER_SOURCE_BY_NEXT /* trigger by counter n+1 output */};
+#define CTR_MODE_TRIGGER_TYPE_mask 0x00000300
+enum {CTR_MODE_TRIGGER_TYPE_DISABLED /* trigger disabled */,
+ CTR_MODE_TRIGGER_TYPE_BY_RE /* by rising edge of trigger signal */,
+ CTR_MODE_TRIGGER_TYPE_BY_FE /* by falling edge of trigger signal */,
+ CTR_MODE_TRIGGER_TYPE_BY_BOTH /* by either edge of trigger signal */};
+#define CTR_MODE_RETRIGGER_mask 0x00000400
+enum {CTR_MODE_RETRIGGER_DISABLED /* counter can be triggered only when stopped */,
+ CTR_MODE_RETRIGGER_ENABLED /* counter can be retriggered when running */};
+#define CTR_MODE_GATE_SOURCE_mask 0x00001800
+enum {CTR_MODE_GATE_SOURCE_SET_HIGH /* gate set high/not gated */,
+ CTR_MODE_GATE_SOURCE_BY_TXIN /* gated by counter input (TxIN) */,
+ CTR_MODE_GATE_SOURCE_BY_PREV /* gated by counter n-1 output */,
+ CTR_MODE_GATE_SOURCE_BY_NEXT /* gated by counter n+1 output */};
+#define CTR_MODE_GATE_POLARITY_mask 0x00002000
+enum {CTR_MODE_GATE_POLARITY_LOW /* low level of gate signal disables counting */,
+ CTR_MODE_GATE_POLARITY_HIGH /* high level of gate signal disables counting */};
+#define CTR_MODE_CLOCK_SOURCE_mask 0x0003C000
+enum {CTR_MODE_CLOCK_SOURCE_50MHZ /* 50 MHz internal clock */,
+ CTR_MODE_CLOCK_SOURCE_10MHZ /* 10 MHz internal clock */,
+ CTR_MODE_CLOCK_SOURCE_1MHZ /* 1 MHz internal clock */,
+ CTR_MODE_CLOCK_SOURCE_100KHZ /* 100 kHz internal clock */,
+ CTR_MODE_CLOCK_SOURCE_res1 /* reserved */,
+ CTR_MODE_CLOCK_SOURCE_TXIN_RE /* counter input (TxIN) rising edge */,
+ CTR_MODE_CLOCK_SOURCE_TXIN_FE /* counter input (TxIN) falling edge */,
+ CTR_MODE_CLOCK_SOURCE_TXIN_BOTH /* counter input (TxIN) either edge */,
+ CTR_MODE_CLOCK_SOURCE_res2 /* reserved */,
+ CTR_MODE_CLOCK_SOURCE_PREV_RE /* counter n-1 output rising edge */,
+ CTR_MODE_CLOCK_SOURCE_PREV_FE /* counter n-1 output falling edge */,
+ CTR_MODE_CLOCK_SOURCE_PREV_BOTH /* counter n-1 output either edge */,
+ CTR_MODE_CLOCK_SOURCE_res3 /* reserved */,
+ CTR_MODE_CLOCK_SOURCE_NEXT_RE /* counter n+1 output rising edge */,
+ CTR_MODE_CLOCK_SOURCE_NEXT_FE /* counter n+1 output falling edge */,
+ CTR_MODE_CLOCK_SOURCE_NEXT_BOTH /* counter n+1 output either edge */};
+#define CTR_MODE_ADTRIGSRC_mask 0x40000000 /* Implemented in CTR4MODE register only */
+enum {CTR_MODE_ADTRIGSRC_OUTPUT_FE /* ADC triggers by falling edge of counter 4 output */,
+ CTR_MODE_ADTRIGSRC_EXTERNAL_INPUT /* triggers by falling edge of external trigger input. */};
+#define CTR_MODE_CTR4INTSRC_mask 0x80000000 /* Implemented in CTR4MODE register only */
+enum {CTR_MODE_CTR4INTSRC_OUTPUT_FE /* interrupts by falling edge of counter 4 output */,
+ CTR_MODE_CTR4INTSRC_EXTERNAL_INPUT/* interrupts by falling edge of external trigger input */};
+