extern struct console mcfrs_console;
extern unsigned long availmem;
-#if CONFIG_UBOOT
+#ifdef CONFIG_UBOOT
extern char m68k_command_line[CL_SIZE];
struct mem_info m68k_ramdisk;
#endif
static void coldfire_get_model(char *model)
{
- sprintf(model, "Version 4 ColdFire");
+ sprintf(model, "Version 4e ColdFire");
}
static void __init
}
//no special boot record
-int coldfire_parse_bootinfo(const struct bi_record *)
+int coldfire_parse_bootinfo(const struct bi_record * record)
{
return 1;
}
/*
* IRQ Handler lists.
*/
-static struct irq_node *irq_list[SYS_IRQS];
-static struct irq_controller *irq_controller[SYS_IRQS];
-static int irq_depth[SYS_IRQS];
+static struct irq_node *irq_list[NR_IRQS];
+static struct irq_controller *irq_controller[NR_IRQS];
+static int irq_depth[NR_IRQS];
/*
* IRQ Controller
# error No IRQ controller defined
#endif
-#define POOL_SIZE SYS_IRQS
+#define POOL_SIZE NR_IRQS
static struct irq_node pool[POOL_SIZE];
static struct irq_node *get_irq_node(void);
int i;
#if defined(CONFIG_M5445X)
- for (i = 0; i < SYS_IRQS; i++)
+ for (i = 0; i < NR_IRQS; i++)
irq_controller[i] = &m5445x_irq_controller;
#elif defined(CONFIG_M547X_8X)
- for (i = 0; i < SYS_IRQS; i++)
+ for (i = 0; i < NR_IRQS; i++)
irq_controller[i] = &m547x_8x_irq_controller;
#endif
}
#include <linux/binfmts.h>
#include <asm/setup.h>
-#include <asm/cf_uaccess.h>
-#include <asm/cf_pgtable.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
#include <asm/traps.h>
#include <asm/ucontext.h>
#include <asm/cacheflush.h>
return c != 0;
}
+static inline int atomic_dec_and_test_lt(volatile atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "=m" (*v));
+ return c != 0;
+}
+
static inline int atomic_inc_and_test(atomic_t *v)
{
char c;
return c != 0;
}
+static inline int atomic_inc_and_test_lt(volatile atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "=m" (*v));
+ return c != 0;
+}
+
#ifdef CONFIG_RMW_INSNS
static inline int atomic_add_return(int i, atomic_t *v)
*********************************************************************/
/* Register read/write macros */
-#define MCF_GPT_GMS0 0x000800
-#define MCF_GPT_GCIR0 0x000804
-#define MCF_GPT_GPWM0 0x000808
-#define MCF_GPT_GSR0 0x00080C
-#define MCF_GPT_GMS1 0x000810
-#define MCF_GPT_GCIR1 0x000814
-#define MCF_GPT_GPWM1 0x000818
-#define MCF_GPT_GSR1 0x00081C
-#define MCF_GPT_GMS2 0x000820
-#define MCF_GPT_GCIR2 0x000824
-#define MCF_GPT_GPWM2 0x000828
-#define MCF_GPT_GSR2 0x00082C
-#define MCF_GPT_GMS3 0x000830
-#define MCF_GPT_GCIR3 0x000834
-#define MCF_GPT_GPWM3 0x000838
-#define MCF_GPT_GSR3 0x00083C
-#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0 MCF_REG32(0x000800)
+#define MCF_GPT_GCIR0 MCF_REG32(0x000804)
+#define MCF_GPT_GPWM0 MCF_REG32(0x000808)
+#define MCF_GPT_GSR0 MCF_REG32(0x00080C)
+#define MCF_GPT_GMS1 MCF_REG32(0x000810)
+#define MCF_GPT_GCIR1 MCF_REG32(0x000814)
+#define MCF_GPT_GPWM1 MCF_REG32(0x000818)
+#define MCF_GPT_GSR1 MCF_REG32(0x00081C)
+#define MCF_GPT_GMS2 MCF_REG32(0x000820)
+#define MCF_GPT_GCIR2 MCF_REG32(0x000824)
+#define MCF_GPT_GPWM2 MCF_REG32(0x000828)
+#define MCF_GPT_GSR2 MCF_REG32(0x00082C)
+#define MCF_GPT_GMS3 MCF_REG32(0x000830)
+#define MCF_GPT_GCIR3 MCF_REG32(0x000834)
+#define MCF_GPT_GPWM3 MCF_REG32(0x000838)
+#define MCF_GPT_GSR3 MCF_REG32(0x00083C)
+#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010))
+#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010))
+#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010))
+#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
+/*
+ * System Integration Unit Registers
+ */
+#define MCF_SDRAMDS MCF_REG32(0x000004) /* SDRAM Drive Strength */
+#define MCF_SBCR MCF_REG32(0x000010) /* System Breakpoint Control */
+#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))/* SDRAM Chip Select X */
+#define MCF_SECSACR MCF_REG32(0x000038) /* Sequential Access Control */
+#define MCF_RSR MCF_REG32(0x000044) /* Reset Status */
+#define MCF_JTAGID MCF_REG32(0x000050) /* JTAG Device Identification */
+
+/*
+ * FlexBus Chip Selects Registers
+ */
+#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC))
+#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC))
+#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC))
+
+/*
+ * Interrupt Controller Registers
+ */
+#define MCF_IPRH MCF_REG32(0x000700)
+#define MCF_IPRL MCF_REG32(0x000704)
+#define MCF_IMRH MCF_REG32(0x000708)
+#define MCF_IMRL MCF_REG32(0x00070C)
+#define MCF_INTFRCH MCF_REG32(0x000710)
+#define MCF_INTFRCL MCF_REG32(0x000714)
+#define MCF_IRLR MCF_REG08(0x000718)
+#define MCF_IACKLPR MCF_REG08(0x000719)
+#define MCF_SWIACK MCF_REG08(0x0007E0)
+#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004))
+#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001))
+
+/*
+ * Slice Timers Registers
+ */
+#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010))
+#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010))
+#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010))
+#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010))
+
+/*
+ * Interrupt sources
+ */
+#define ISC_EPORT_Fn(x) (x) /* EPORT Interrupts */
+#define ISC_USB_EPn(x) (15+(x)) /* USB Endopint */
+#define ISC_USB_ISR (22) /* USB General source */
+#define ISC_USB_AISR (22) /* USB core source */
+#define ISC_DSPI_OVRFW (25) /* DSPI overflow */
+#define ISC_DSPI_RFOF (26)
+#define ISC_DSPI_RFDF (27)
+#define ISC_DSPI_TFUF (28)
+#define ISC_DSPI_TCF (29)
+#define ISC_DSPI_TFFF (30)
+#define ISC_DSPI_EOQF (31)
+#define ISC_PSCn(x) (35-(x))
+#define ISC_COMM_TIM (36)
+#define ISC_SEC (37)
+#define ISC_FEC1 (38)
+#define ISC_FEC0 (39)
+#define ISC_I2C (40)
+#define ISC_PCI_ARB (41)
+#define ISC_PCI_CB (42)
+#define ISC_PCI_XLB (43)
+#define ISC_DMA (48)
+#define ISC_CANn_ERR(x) (49+(6*(x)))
+#define ISC_CANn_BUSOFF(x) (50+(6*(x)))
+#define ISC_CANn_MBOR(x) (51+(6*(x)))
+#define ISC_CAN0_WAKEIN (52)
+#define ISC_SLTn(x) (54-(x))
+#define ISC_GPTn(x) (62-(x))
+
+/*
+ * Interrupt level and priorities
+ */
+#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3))
+#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2))
+#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1))
+#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0))
+#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7))
+#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6))
+#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5))
+#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4))
+#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3))
+#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2))
+#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1))
+
+#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x)))
+#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7))
+#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6))
+#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5))
+#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4))
+#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3))
+#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2))
+#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1))
+#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0))
+
+#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7))
+#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6))
+#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5))
+#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4))
+#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3))
+#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2))
+#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1))
+#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0))
+
+#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7))
+#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3)))
+#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3))
+#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2))
+#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1))
+#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0))
+
+
+
+
+
+/********************************************************************/
+
+/*
+ * System Integration Unit Bitfields
+ */
+
+/* SBCR */
+#define MCF_SBCR_PIN2DSPI (0x08000000)
+#define MCF_SBCR_DMA2CPU (0x10000000)
+#define MCF_SBCR_CPU2DMA (0x20000000)
+#define MCF_SBCR_PIN2DMA (0x40000000)
+#define MCF_SBCR_PIN2CPU (0x80000000)
+
+/* SECSACR */
+#define MCF_SECSACR_SEQEN (0x00000001)
+
+/* RSR */
+#define MCF_RSR_RST (0x00000001)
+#define MCF_RSR_RSTWD (0x00000002)
+#define MCF_RSR_RSTJTG (0x00000008)
+
+/* JTAGID */
+#define MCF_JTAGID_REV (0xF0000000)
+#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF)
+#define MCF_JTAGID_MCF5485 (0x0800C01D)
+#define MCF_JTAGID_MCF5484 (0x0800D01D)
+#define MCF_JTAGID_MCF5483 (0x0800E01D)
+#define MCF_JTAGID_MCF5482 (0x0800F01D)
+#define MCF_JTAGID_MCF5481 (0x0801001D)
+#define MCF_JTAGID_MCF5480 (0x0801101D)
+#define MCF_JTAGID_MCF5475 (0x0801201D)
+#define MCF_JTAGID_MCF5474 (0x0801301D)
+#define MCF_JTAGID_MCF5473 (0x0801401D)
+#define MCF_JTAGID_MCF5472 (0x0801501D)
+#define MCF_JTAGID_MCF5471 (0x0801601D)
+#define MCF_JTAGID_MCF5470 (0x0801701D)
+
+
+/*
+ * Interrupt Controller Bitfields
+ */
+#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1)
+#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0)
+#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
+#define MCF_ICR_IP(x) (((x)&0x07)<<0)
+#define MCF_ICR_IL(x) (((x)&0x07)<<3)
+
+/*
+ * Slice Timers Bitfields
+ */
+#define MCF_SCR_TEN (0x01000000)
+#define MCF_SCR_IEN (0x02000000)
+#define MCF_SCR_RUN (0x04000000)
+#define MCF_SSR_ST (0x01000000)
+#define MCF_SSR_BE (0x02000000)
+
+
+/*
+ * Some needed coldfire registers
+ */
+#define MCF_PAR_PCIBG MCF_REG16(0x000A48)
+#define MCF_PAR_PCIBR MCF_REG16(0x000A4A)
+#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3))
+#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44)
+#define MCF_PAR_DSPI MCF_REG16(0x000A50)
+#define MCF_PAR_TIMER MCF_REG08(0X000A52)
+#define MCF_EPPAR MCF_REG16(0x000F00)
+#define MCF_EPIER MCF_REG08(0x000F05)
+#define MCF_EPFR MCF_REG08(0x000F0C)
+
+/*
+ * Some GPIO bitfields
+ */
+#define MCF_PAR_SDA (0x0008)
+#define MCF_PAR_SCL (0x0004)
+#define MCF_PAR_PSC_TXD (0x04)
+#define MCF_PAR_PSC_RXD (0x08)
+#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
+#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
+#define MCF_PAR_PSC_CTS_GPIO (0x00)
+#define MCF_PAR_PSC_CTS_BCLK (0x80)
+#define MCF_PAR_PSC_CTS_CTS (0xC0)
+#define MCF_PAR_PSC_RTS_GPIO (0x00)
+#define MCF_PAR_PSC_RTS_FSYNC (0x20)
+#define MCF_PAR_PSC_RTS_RTS (0x30)
+#define MCF_PAR_PSC_CANRX (0x40)
+
+
+/*
+ * Some used coldfire values
+ */
+#define MCF_EPIER_EPIE(x) (0x01 << (x))
+#define MCF_EPPAR_EPPAx_FALLING (2)
+#define MCF_EPPAR_EPPA(n,x) (((x)&0x0003) << (2*n))
+
#endif /* m548xsim_h */
extern void config_BSP(char *command, int len);
extern void do_IRQ(int irq, struct pt_regs *fp);
+#ifdef CONFIG_COLDFIRE
+extern void __init config_coldfire(void);
+extern void __init mmu_context_init(void);
+extern irq_handler_t mach_default_handler;
+extern void (*mach_tick)(void);
+#endif
+
#endif /* _M68K_MACHDEP_H */
#include <asm/coldfire.h>
#include <asm/page.h>
-#include <asm/mcf_tlbflush.h>
+#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
#define pmd_set(pmdp, ptep) do {} while (0)
-extern inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
+static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
{
pgd_val(*pgdp) = virt_to_phys(pmdp);
}
#include <asm/m548xgpt.h>
#endif
+/*
+ * Define the base address of the SIM within the MBAR address space.
+ */
+#define MCFSIM_BASE 0x0 /* Base address of SIM */
+
+/*
+ * Bit definitions for the ICR family of registers.
+ */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+/*
+ * Bit definitions for the Interrupt Mask register (IMR).
+ */
+#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
+#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
+#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
+#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
+#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
+#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
+#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
+
+#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
+#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
+#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
+#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
+#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
+#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
+
+/*
+ * Mask for all of the SIM devices. Some parts have more or less
+ * SIM devices. This is a catchall for the sandard set.
+ */
+#ifndef MCFSIM_IMR_MASKALL
+#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
+#endif
+
+
+/*
+ * PIT interrupt settings, if not found in mXXXXsim.h file.
+ */
+#ifndef ICR_INTRCONF
+#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
+#endif
+#ifndef MCFPIT_IMR
+#define MCFPIT_IMR MCFINTC_IMRH
+#endif
+#ifndef MCFPIT_IMR_IBIT
+#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
+#endif
+
+
+#ifndef __ASSEMBLY__
+/*
+ * Definition for the interrupt auto-vectoring support.
+ */
+extern void mcf_autovector(unsigned int vec);
+#endif /* __ASSEMBLY__ */
+
/****************************************************************************/
#endif /* mcfsim_h */
}
#ifdef CONFIG_MMU
-#ifndef CONFIG_SUN3 && !defined(CONFIG_COLDFIRE)
+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
#include <asm/setup.h>
#include <asm/page.h>
#define deactivate_mm(tsk, mm) do { } while (0)
extern void mmu_context_init(void);
-#if defined(CONFIG_M547X_8X)
+#ifdef CONFIG_M547X_8X
#define prepare_arch_switch(next) load_ksp_mmu(next)
//FIXME: Don't use TLB here for kernel stacks
#endif /* CONFIG_M547X_8X */
+#endif /* CONFIG_COLDFIRE */
+
#else /* !CONFIG_MMU */
static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
#include <asm/virtconvert.h>
#ifdef CONFIG_SUN3
#include <asm/sun3_pgalloc.h>
+#elif defined CONFIG_COLDFIRE
+#include <asm/mcf_pgalloc.h>
#else
#include <asm/motorola_pgalloc.h>
#endif
#ifdef CONFIG_SUN3
#include <asm/sun3_pgtable.h>
-#elif CONFIG_COLDFIRE
+#elif defined(CONFIG_COLDFIRE)
#include <asm/mcf_pgtable.h>
#else
#include <asm/motorola_pgtable.h>
#define MACH_HP300 9
#define MACH_Q40 10
#define MACH_SUN3X 11
+#define MACH_CFMMU 12
#define COMMAND_LINE_SIZE 256
#include <asm/sigcontext.h>
#if !defined(__uClinux__)
+#ifndef CONFIG_COLDFIRE
#define __HAVE_ARCH_SIG_BITOPS
static inline void sigaddset(sigset_t *set, int _sig)
#undef __HAVE_ARCH_SIG_BITOPS
#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+#endif /* CONFIG_COLDFIRE */
#endif /* __uClinux__ */
#endif /* __KERNEL__ */
#define _M68K_TLBFLUSH_H
#ifdef CONFIG_MMU
-#ifndef CONFIG_SUN3
+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
#include <asm/current.h>
flush_tlb_all();
}
-#else
+#elif defined(CONFIG_SUN3)
/* Reserved PMEGs. */
sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG);
}
+#else /* CONFIG_COLDFIRE */
+#include <asm/mcf_tlbflush.h>
#endif
#else /* !CONFIG_MMU */
BUG();
}
+
#endif /* CONFIG_MMU */
#endif /* _M68K_TLBFLUSH_H */
#ifdef __uClinux__
#include "uaccess_no.h"
+#elif defined(CONFIG_COLDFIRE)
+#include "uaccess_coldfire.h"
#else
#include "uaccess_mm.h"
#endif
--- /dev/null
+#ifndef __M68K_UACCESS_H
+#define __M68K_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+
+/* The "moves" command is not available in the CF instruction set. */
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <asm/segment.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/* We let the MMU do all checking */
+#define access_ok(type, addr, size) 1
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+ unsigned long insn, fixup;
+};
+
+extern int __put_user_bad(void);
+extern int __get_user_bad(void);
+
+#define __put_user_asm(res, x, ptr, bwl, reg, err) \
+asm volatile ("\n" \
+ "1: move."#bwl" %2,%1\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: moveq.l %3,%0\n" \
+ " jra 2b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .previous" \
+ : "+d" (res), "=m" (*(ptr)) \
+ : #reg (x), "i" (err))
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define __put_user(x, ptr) \
+({ \
+ typeof(*(ptr)) __pu_val = (x); \
+ int __pu_err = 0; \
+ __chk_user_ptr(ptr); \
+ switch (sizeof (*(ptr))) { \
+ case 1: \
+ __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
+ break; \
+ case 2: \
+ __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \
+ break; \
+ case 4: \
+ __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
+ break; \
+ case 8: \
+ { \
+ const void __user *__pu_ptr = (ptr); \
+ asm volatile ("\n" \
+ "1: move.l %2,(%1)+\n" \
+ "2: move.l %R2,(%1)\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: movel %3,%0\n" \
+ " jra 3b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .long 3b,10b\n" \
+ " .previous" \
+ : "+d" (__pu_err), "+a" (__pu_ptr) \
+ : "r" (__pu_val), "i" (-EFAULT) \
+ : "memory"); \
+ break; \
+ } \
+ default: \
+ __pu_err = __put_user_bad(); \
+ break; \
+ } \
+ __pu_err; \
+})
+#define put_user(x, ptr) __put_user(x, ptr)
+
+
+#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
+ type __gu_val; \
+ asm volatile ("\n" \
+ "1: move."#bwl" %2,%1\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: move.l %3,%0\n" \
+ " subl %1,%1\n" \
+ " jra 2b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .previous" \
+ : "+d" (res), "=&" #reg (__gu_val) \
+ : "m" (*(ptr)), "i" (err)); \
+ (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \
+})
+
+#define __get_user(x, ptr) \
+({ \
+ int __gu_err = 0; \
+ __chk_user_ptr(ptr); \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \
+ break; \
+ case 2: \
+ __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \
+ break; \
+ case 4: \
+ __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \
+ break; \
+/* case 8: disabled because gcc-4.1 has a broken typeof \
+ { \
+ const void *__gu_ptr = (ptr); \
+ u64 __gu_val; \
+ asm volatile ("\n" \
+ "1: move.l (%2)+,%1\n" \
+ "2: move.l (%2),%R1\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: move.l %3,%0\n" \
+ " subl %1,%1\n" \
+ " subl %R1,%R1\n" \
+ " jra 3b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .previous" \
+ : "+d" (__gu_err), "=&r" (__gu_val), \
+ "+a" (__gu_ptr) \
+ : "i" (-EFAULT) \
+ : "memory"); \
+ (x) = (typeof(*(ptr)))__gu_val; \
+ break; \
+ } */ \
+ default: \
+ __gu_err = __get_user_bad(); \
+ break; \
+ } \
+ __gu_err; \
+})
+#define get_user(x, ptr) __get_user(x, ptr)
+
+unsigned long __generic_copy_from_user(void *to, const void __user *from,
+ unsigned long n);
+unsigned long __generic_copy_to_user(void __user *to, const void *from,
+ unsigned long n);
+
+#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\
+ asm volatile ("\n" \
+ "1: move."#s1" (%2)+,%3\n" \
+ " move."#s1" %3,(%1)+\n" \
+ "2: move."#s2" (%2)+,%3\n" \
+ " move."#s2" %3,(%1)+\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ "3: move."#s3" (%2)+,%3\n" \
+ " move."#s3" %3,(%1)+\n" \
+ " .endif\n" \
+ "4:\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10f\n" \
+ " .long 2b,20f\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " .long 3b,30f\n" \
+ " .endif\n" \
+ " .previous\n" \
+ "\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: clr."#s1" (%1)+\n" \
+ "20: clr."#s2" (%1)+\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ "30: clr."#s3" (%1)+\n" \
+ " .endif\n" \
+ " moveq.l #"#n",%0\n" \
+ " jra 4b\n" \
+ " .previous\n" \
+ : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \
+ : : "memory")
+
+static __always_inline unsigned long
+__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ unsigned long res = 0, tmp;
+
+ switch (n) {
+ case 1:
+ __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1);
+ break;
+ case 2:
+ __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w,
+ d, 2);
+ break;
+ case 3:
+ __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,);
+ break;
+ case 4:
+ __get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l,
+ r, 4);
+ break;
+ case 5:
+ __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,);
+ break;
+ case 6:
+ __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,);
+ break;
+ case 7:
+ __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b);
+ break;
+ case 8:
+ __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,);
+ break;
+ case 9:
+ __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b);
+ break;
+ case 10:
+ __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w);
+ break;
+ case 12:
+ __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l);
+ break;
+ default:
+ /* we limit the inlined version to 3 moves */
+ return __generic_copy_from_user(to, from, n);
+ }
+
+ return res;
+}
+
+#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
+ asm volatile ("\n" \
+ " move."#s1" (%2)+,%3\n" \
+ "11: move."#s1" %3,(%1)+\n" \
+ "12: move."#s2" (%2)+,%3\n" \
+ "21: move."#s2" %3,(%1)+\n" \
+ "22:\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " move."#s3" (%2)+,%3\n" \
+ "31: move."#s3" %3,(%1)+\n" \
+ "32:\n" \
+ " .endif\n" \
+ "4:\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 11b,5f\n" \
+ " .long 12b,5f\n" \
+ " .long 21b,5f\n" \
+ " .long 22b,5f\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " .long 31b,5f\n" \
+ " .long 32b,5f\n" \
+ " .endif\n" \
+ " .previous\n" \
+ "\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "5: moveq.l #"#n",%0\n" \
+ " jra 4b\n" \
+ " .previous\n" \
+ : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \
+ : : "memory")
+
+static __always_inline unsigned long
+__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ unsigned long res = 0, tmp;
+
+ switch (n) {
+ case 1:
+ __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
+ break;
+ case 2:
+ __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2);
+ break;
+ case 3:
+ __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
+ break;
+ case 4:
+ __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4);
+ break;
+ case 5:
+ __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,);
+ break;
+ case 6:
+ __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,);
+ break;
+ case 7:
+ __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b);
+ break;
+ case 8:
+ __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,);
+ break;
+ case 9:
+ __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b);
+ break;
+ case 10:
+ __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w);
+ break;
+ case 12:
+ __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l);
+ break;
+ default:
+ /* limit the inlined version to 3 moves */
+ return __generic_copy_to_user(to, from, n);
+ }
+
+ return res;
+}
+
+#define __copy_from_user(to, from, n) \
+(__builtin_constant_p(n) ? \
+ __constant_copy_from_user(to, from, n) : \
+ __generic_copy_from_user(to, from, n))
+
+#define __copy_to_user(to, from, n) \
+(__builtin_constant_p(n) ? \
+ __constant_copy_to_user(to, from, n) : \
+ __generic_copy_to_user(to, from, n))
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+#define copy_from_user(to, from, n) __copy_from_user(to, from, n)
+#define copy_to_user(to, from, n) __copy_to_user(to, from, n)
+
+long strncpy_from_user(char *dst, const char __user *src, long count);
+long strnlen_user(const char __user *src, long n);
+unsigned long __clear_user(void __user *to, unsigned long n);
+
+#define clear_user __clear_user
+
+#define strlen_user(str) strnlen_user(str, 32767)
+
+#endif /* _M68K_UACCESS_H */
#define VERIFY_READ 0
#define VERIFY_WRITE 1
-/* Coldifre doesn't have moves instruction; use move. */
-#ifdef CONFIG_COLDFIRE
-#define moves move
-#endif
-
/* We let the MMU do all checking */
static inline int access_ok(int type, const void __user *addr,
unsigned long size)
/*
* Change virtual addresses to physical addresses and vv.
*/
+
static inline unsigned long virt_to_phys(void *address)
{
return __pa(address);
extern int apollo_parse_bootinfo(const struct bi_record *);
extern int coldfire_parse_bootinfo(const struct bi_record *);
+#ifdef CONFIG_COLDFIRE
+void coldfire_sort_memrec(void);
+#endif
+
extern void config_amiga(void);
extern void config_atari(void);
extern void config_mac(void);
unknown = apollo_parse_bootinfo(record);
else if (MACH_IS_COLDFIRE)
unknown = coldfire_parse_bootinfo(record);
- else if
+ else
unknown = 1;
}
if (unknown)
break;
#endif
#ifdef CONFIG_COLDFIRE
- case MACH_COLDFIRE:
+ case MACH_CFMMU:
config_coldfire();
break;
#endif
#define LOOP_CYCLES_68030 (8)
#define LOOP_CYCLES_68040 (3)
#define LOOP_CYCLES_68060 (1)
+#define LOOP_CYCLES_COLDFIRE (2)
if (CPU_IS_020) {
cpu = "68020";
else
flush_dcache();
- ret = 0;
+ ret = 0;
+#endif
out:
return ret;
}
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
-#include <asm/mcf_pgalloc.h>
+#include <asm/pgalloc.h>
#include <asm/coldfire.h>
#include <asm/tlbflush.h>
return 0;
}
+#ifndef CONFIG_COLDFIRE
/* invalidate page in both caches */
static inline void clear040(unsigned long paddr)
{
}
EXPORT_SYMBOL(cache_push);
+#else
+
+//Not the best idea ...
+void cache_clear (unsigned long paddr, int len)
+{
+ flush_bcache();
+}
+EXPORT_SYMBOL(cache_clear);
+
+void cache_push (unsigned long paddr, int len)
+{
+ flush_bcache();
+}
+EXPORT_SYMBOL(cache_push);
+
+#endif /* CONFIG_COLDFIRE */
+
projects / mcf548x / linux.git / commitdiff