--- /dev/null
+/*
+ * arch/m68k/include/asm/cache_coldfire_m547x_8x.h - Coldfire Cache Controller
+ *
+ * Kurt Mahan kmahan@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _M68K_CACHE_COLDFIRE_M547X_8X_H
+#define _M68K_CACHE_COLDFIRE_M547X_8X_H
+
+#ifndef __ARCH_M68K_CACHE_H
+#error only <asm/cache.h> can be included directly
+#endif
+
+/*
+ * CACR Cache Control Register
+ */
+#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
+#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
+#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
+#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
+#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
+#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
+#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
+#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
+#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
+#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
+#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
+#define CF_CACR_IVO (0x00100000) /* Invalidate only */
+#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
+#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
+#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
+#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
+#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
+#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
+#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
+#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
+#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
+#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
+#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
+
+/*
+ * M547x/M548x Cache Configuration
+ * - cache line size is 16 bytes
+ * - cache is 4-way set associative
+ * - each cache has 512 sets (128k / 16bytes / 4way)
+ * - I-Cache size is 32KB
+ * - D-Cache size is 32KB
+ */
+#define ICACHE_SIZE 0x8000 /* instruction - 32k */
+#define DCACHE_SIZE 0x8000 /* data - 32k */
+
+#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
+#define CACHE_SETS 0x0200 /* 512 sets */
+#define CACHE_WAYS 0x0004 /* 4 way */
+
+/* in for the old cpushl caching code */
+#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
+#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
+#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
+#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
+
+#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
+ CF_CACR_BCINVA+ \
+ CF_CACR_ICINVA)
+
+#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
+ CF_CACR_BEC+ \
+ CF_CACR_IEC+ \
+ CF_CACR_DESB+ \
+ CF_CACR_EUSP)
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long shadow_cacr;
+extern void cacr_set(unsigned long x);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _M68K_CACHE_COLDFIRE_M547X_8X_H */
--- /dev/null
+/*
+ * arch/m68k/include/asm/cacheflush_coldfire_m547x_8x.h - Coldfire 547x/548x Cache
+ *
+ * Based on arch/m68k/include/asm/cacheflush.h
+ *
+ * Coldfire pieces by:
+ * Kurt Mahan kmahan@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007, 2008
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _M68K_CACHEFLUSH_CODLFIRE_M547X_8X_H
+#define _M68K_CACHEFLUSH_CODLFIRE_M547X_8X_H
+
+/*
+ * Cache handling functions
+ */
+
+#define flush_icache() \
+({ \
+ unsigned long set; \
+ unsigned long start_set; \
+ unsigned long end_set; \
+ \
+ start_set = 0; \
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
+ \
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
+ asm volatile("cpushl %%ic,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%ic,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%ic,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
+ } \
+})
+
+#define flush_dcache() \
+({ \
+ unsigned long set; \
+ unsigned long start_set; \
+ unsigned long end_set; \
+ \
+ start_set = 0; \
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
+ \
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
+ asm volatile("cpushl %%dc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%dc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%dc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
+ } \
+})
+
+#define flush_bcache() \
+({ \
+ unsigned long set; \
+ unsigned long start_set; \
+ unsigned long end_set; \
+ \
+ start_set = 0; \
+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
+ \
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
+ asm volatile("cpushl %%bc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%bc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%bc,(%0)\n" \
+ "\taddq%.l #1,%0\n" \
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
+ } \
+})
+
+/*
+ * invalidate the cache for the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_clear(unsigned long paddr, int len);
+/*
+ * push any dirty cache in the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_push(unsigned long paddr, int len);
+
+/*
+ * push and invalidate pages in the specified user virtual
+ * memory range.
+ */
+extern void cache_push_v(unsigned long vaddr, int len);
+
+/* This is needed whenever the virtual mapping of the current
+ process changes. */
+
+/**
+ * flush_cache_mm - Flush an mm_struct
+ * @mm: mm_struct to flush
+ */
+static inline void flush_cache_mm(struct mm_struct *mm)
+{
+ if (mm == current->mm)
+ flush_bcache();
+}
+
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+
+#define flush_cache_all() flush_bcache()
+
+/**
+ * flush_cache_range - Flush a cache range
+ * @vma: vma struct
+ * @start: Starting address
+ * @end: Ending address
+ *
+ * flush_cache_range must be a macro to avoid a dependency on
+ * linux/mm.h which includes this file.
+ */
+static inline void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (vma->vm_mm == current->mm)
+ flush_bcache();
+// cf_cache_flush_range(start, end);
+}
+
+/**
+ * flush_cache_page - Flush a page of the cache
+ * @vma: vma struct
+ * @vmaddr:
+ * @pfn: page numer
+ *
+ * flush_cache_page must be a macro to avoid a dependency on
+ * linux/mm.h which includes this file.
+ */
+static inline void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long vmaddr, unsigned long pfn)
+{
+ if (vma->vm_mm == current->mm)
+ flush_bcache();
+// cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
+}
+
+/* Push the page at kernel virtual address and clear the icache */
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
+#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
+extern inline void __flush_page_to_ram(void *address)
+{
+ unsigned long set;
+ unsigned long start_set;
+ unsigned long end_set;
+ unsigned long addr = (unsigned long) address;
+
+ addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
+
+ start_set = addr & _ICACHE_SET_MASK;
+ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
+
+ if (start_set > end_set) {
+ /* from the begining to the lowest address */
+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
+ asm volatile("cpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
+ }
+ /* next loop will finish the cache ie pass the hole */
+ end_set = LAST_ICACHE_ADDR;
+ }
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
+ asm volatile("cpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
+ }
+}
+
+/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
+#define flush_dcache_page(page) \
+ __flush_page_to_ram((void *) page_address(page))
+#define flush_icache_page(vma,pg) \
+ __flush_page_to_ram((void *) page_address(pg))
+#define flush_icache_user_range(adr,len) do { } while (0)
+/* NL */
+#define flush_icache_user_page(vma,page,addr,len) do { } while (0)
+
+/* Push n pages at kernel virtual address and clear the icache */
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
+extern inline void flush_icache_range (unsigned long address,
+ unsigned long endaddr)
+{
+ unsigned long set;
+ unsigned long start_set;
+ unsigned long end_set;
+
+ start_set = address & _ICACHE_SET_MASK;
+ end_set = endaddr & _ICACHE_SET_MASK;
+
+ if (start_set > end_set) {
+ /* from the begining to the lowest address */
+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
+ asm volatile("cpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
+ }
+ /* next loop will finish the cache ie pass the hole */
+ end_set = LAST_ICACHE_ADDR;
+ }
+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
+ asm volatile("cpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)\n"
+ "\taddq%.l #1,%0\n"
+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
+ }
+}
+
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ memcpy(dst, src, len);
+ flush_icache_user_page(vma, page, vaddr, len);
+}
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ memcpy(dst, src, len);
+}
+
+#define flush_cache_vmap(start, end) flush_cache_all()
+#define flush_cache_vunmap(start, end) flush_cache_all()
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+
+#endif /* _M68K_CACHEFLUSH_CODLFIRE_M547X_8X_H */
projects / mcf548x / linux.git / commitdiff