2 * head.S is the MMU enabled ColdFire specific initial boot code
4 * Ported to ColdFire by
5 * Matt Waddel Matt.Waddel@freescale.com
6 * Kurt Mahan kmahan@freescale.com
7 * Copyright Freescale Semiconductor, Inc. 2007, 2008
8 * Phys kernel mapping Copyright Daniel Krueger, SYSTEC electornic GmbH 2008
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * Parts of this code came from arch/m68k/kernel/head.S
17 #include <linux/linkage.h>
18 #include <linux/init.h>
19 #include <asm/bootinfo.h>
20 #include <asm/setup.h>
21 #include <asm/entry.h>
22 #include <asm/pgtable.h>
24 #include <asm/coldfire.h>
25 #include <asm/mcfuart.h>
26 #include <asm/mcfcache.h>
27 #include <asm/thread_info.h>
35 #if defined(CONFIG_UBOOT)
41 /* When debugging use readable names for labels */
43 #define L(name) .head.S.##name
45 #define L(name) .head.S./**/name
49 #define L(name) .L##name
51 #define L(name) .L/**/name
55 /* The __INITDATA stuff is a no-op when ftrace or kgdb are turned on */
57 #define __INITDATA .data
58 #define __FINIT .previous
61 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
63 * Kernel mapped to virtual ram address.
66 * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
67 * Data[1]: 0xA0000000 -> 0xAFFFFFFF PCI
72 * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
77 #if defined(CONFIG_M5445X)
78 #define ACR0_DEFAULT #0xF00FA048 /* System regs */
79 #define ACR1_DEFAULT #0xA00FA048 /* PCI */
80 #define ACR2_DEFAULT #0x00000000 /* Not Mapped */
81 #define ACR3_DEFAULT #0x00000000 /* Not Mapped */
82 #elif defined(CONFIG_M547X_8X)
83 #define ACR0_DEFAULT #0xF00FA048 /* System Regs */
84 #define ACR1_DEFAULT #0x00000000 /* Not Mapped */
85 #define ACR2_DEFAULT #0x00000000 /* Not Mapped */
86 #define ACR3_DEFAULT #0x00000000 /* Not Mapped */
89 #else /* CONFIG_SDRAM_BASE = PAGE_OFFSET */
91 * Kernel mapped to physical ram address.
94 * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
95 * Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - uncached
97 * Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached
100 * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
101 * Data[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - uncached
102 * Code[0]: Not Mapped
103 * Code[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - cached
105 #if defined(CONFIG_M5445X)
106 #define ACR0_DEFAULT #0xF00FA048 /* System Regs */
107 #define ACR1_DEFAULT #0x400FA048 /* SDRAM uncached */
108 #define ACR2_DEFAULT #0x00000000 /* Not mapped */
109 #define ACR3_DEFAULT #0x400FA008 /* SDRAM cached */
110 #elif defined(CONFIG_M547X_8X)
111 #define ACR0_DEFAULT #0xF00FA048 /* System Regs */
112 #define ACR1_DEFAULT #0x000FA048 /* SDRAM uncached */
113 #define ACR2_DEFAULT #0x00000000 /* Not mapped */
114 #define ACR3_DEFAULT #0x000FA008 /* SDRAM cached */
118 /* Several macros to make the writing of subroutines easier:
119 * - func_start marks the beginning of the routine which setups the frame
120 * register and saves the registers, it also defines another macro
121 * to automatically restore the registers again.
122 * - func_return marks the end of the routine and simply calls the prepared
123 * macro to restore registers and jump back to the caller.
124 * - func_define generates another macro to automatically put arguments
125 * onto the stack call the subroutine and cleanup the stack again.
128 .macro load_symbol_address symbol,register
129 movel #\symbol,\register
132 .macro func_start name,saveregs,savesize,stack=0
135 subal #(\savesize),%sp
136 moveml \saveregs,%sp@
137 .set stackstart,-\stack
139 .macro func_return_\name
140 moveml %sp@,\saveregs
141 addal #(\savesize),%sp
147 .macro func_return name
151 .macro func_call name
155 .macro move_stack nr,arg1,arg2,arg3,arg4
157 move_stack "(\nr-1)",\arg2,\arg3,\arg4
162 .macro func_define name,nr=0
163 .macro \name arg1,arg2,arg3,arg4
164 move_stack \nr,\arg1,\arg2,\arg3,\arg4
172 func_define serial_putc,1
176 func_call serial_putc
194 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
196 mmu_map - creates a new TLB entry
198 virt_addr Must be on proper boundary
199 phys_addr Must be on proper boundary
200 itlb MMUOR_ITLB if instruction TLB or 0
201 asid address space ID
202 shared_global MMUTR_SG if shared between different ASIDs or 0
203 size_code MMUDR_SZ1M 1 MB
207 cache_mode MMUDR_INC instruction non-cacheable
208 MMUDR_IC instruction cacheable
209 MMUDR_DWT data writethrough
210 MMUDR_DCB data copyback
211 MMUDR_DNCP data non-cacheable, precise
212 MMUDR_DNCIP data non-cacheable, imprecise
213 super_prot MMUDR_SP if user mode generates exception or 0
214 readable MMUDR_R if permits read access (data TLB) or 0
215 writable MMUDR_W if permits write access (data TLB) or 0
216 executable MMUDR_X if permits execute access (instruction TLB) or 0
217 locked MMUDR_LK prevents TLB entry from being replaced or 0
218 temp_data_reg a data register to use for temporary values
220 .macro mmu_map virt_addr,phys_addr,itlb,asid,shared_global,size_code,cache_mode,super_prot,readable,writable,executable,locked,temp_data_reg
221 /* Set up search of TLB. */
222 movel #(\virt_addr+1), \temp_data_reg
223 movel \temp_data_reg, MMUAR
225 movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
226 movew \temp_data_reg, (MMUOR)
227 /* Set up tag value. */
228 movel #(\virt_addr + \asid + \shared_global + MMUTR_V), \temp_data_reg
229 movel \temp_data_reg, MMUTR
230 /* Set up data value. */
231 movel #(\phys_addr + \size_code + \cache_mode + \super_prot + \readable + \writable + \executable + \locked), \temp_data_reg
232 movel \temp_data_reg, MMUDR
234 movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
235 movew \temp_data_reg, (MMUOR)
238 .macro mmu_unmap virt_addr,itlb,temp_data_reg
239 /* Set up search of TLB. */
240 movel #(\virt_addr+1), \temp_data_reg
241 movel \temp_data_reg, MMUAR
243 movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
244 movew \temp_data_reg, (MMUOR)
246 movel MMUSR,\temp_data_reg
247 btst #MMUSR_HITN,\temp_data_reg
250 movel #(MMUOR_RW + MMUOR_ACC +\itlb), \temp_data_reg
251 movew \temp_data_reg, (MMUOR)
252 movel MMUSR,\temp_data_reg
253 /* Set up tag value. */
254 movel #0, \temp_data_reg
255 movel \temp_data_reg, MMUTR
256 /* Set up data value. */
257 movel #0, \temp_data_reg
258 movel \temp_data_reg, MMUDR
260 movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
261 movew \temp_data_reg, (MMUOR)
263 .endm /* mmu_unmap */
264 #endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
267 .section ".text.head","ax"
269 /* Version numbers of the bootinfo interface -- if we later pass info
270 * from boot ROM we might want to put something real here.
272 * The area from _stext to _start will later be used as kernel pointer table
274 bras 1f /* Jump over bootinfo version numbers */
276 .long BOOTINFOV_MAGIC
278 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
279 1: jmp __start-(0xc0000000-CONFIG_SDRAM_BASE)
284 .equ kernel_pg_dir,_stext
291 movew #0x2700,%sr /* no interrupts */
292 #if defined(CONFIG_UBOOT)
293 movel %sp,%a4 /* save initial stack pointer */
294 addl #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4 /* high mem offset */
295 movel %a4, uboot_init_sp /*this will be used by C code after turning on MMU*/
298 /* Setup initial stack pointer */
299 movel #CONFIG_SDRAM_BASE+0x1000,%sp
305 #if defined(CONFIG_M5445X)
306 movel #0x80000000, %d0
308 #elif defined(CONFIG_M547X_8X)
311 move.l #(MCF_RAMBAR0 + 0x21), %d0
313 move.l #(MCF_RAMBAR1 + 0x21), %d0
318 movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0
321 movel #(MMU_BASE+1),%d0
323 movel #MMUOR_CA,%a0 /* Clear tlb entries */
325 movel #(MMUOR_CA + MMUOR_ITLB),%a0 /* Use ITLB for searches */
327 movel #0,%a0 /* Clear Addr Space User ID */
331 movel ACR0_DEFAULT, %d0 /* ACR0 (DATA) setup */
334 movel ACR1_DEFAULT, %d0 /* ACR1 (DATA) setup */
337 movel ACR2_DEFAULT, %d0 /* ACR2 (CODE) setup */
340 movel ACR3_DEFAULT, %d0 /* ACR3 (CODE) setup */
344 /* If you change the memory size to another value make a matching
345 change in paging_init(cf-mmu.c) to zones_size[]. */
347 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
348 #if defined(CONFIG_M5445X)
349 /* Map 256MB as code */
350 mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
351 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
352 0, 0, MMUDR_X, MMUDR_LK, %d0
353 mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), \
354 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
355 0, 0, MMUDR_X, MMUDR_LK, %d0
356 mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), \
357 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
358 0, 0, MMUDR_X, MMUDR_LK, %d0
359 mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), \
360 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
361 0, 0, MMUDR_X, MMUDR_LK, %d0
362 mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), \
363 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
364 0, 0, MMUDR_X, MMUDR_LK, %d0
365 mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), \
366 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
367 0, 0, MMUDR_X, MMUDR_LK, %d0
368 mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), \
369 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
370 0, 0, MMUDR_X, MMUDR_LK, %d0
371 mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), \
372 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
373 0, 0, MMUDR_X, MMUDR_LK, %d0
374 mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), \
375 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
376 0, 0, MMUDR_X, MMUDR_LK, %d0
377 mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), \
378 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
379 0, 0, MMUDR_X, MMUDR_LK, %d0
380 mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), \
381 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
382 0, 0, MMUDR_X, MMUDR_LK, %d0
383 mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), \
384 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
385 0, 0, MMUDR_X, MMUDR_LK, %d0
386 mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), \
387 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
388 0, 0, MMUDR_X, MMUDR_LK, %d0
389 mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), \
390 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
391 0, 0, MMUDR_X, MMUDR_LK, %d0
392 mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), \
393 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
394 0, 0, MMUDR_X, MMUDR_LK, %d0
395 mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), \
396 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
397 0, 0, MMUDR_X, MMUDR_LK, %d0
399 /* Map 256MB as data also */
400 mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
401 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
403 mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), 0, 0, \
404 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
406 mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), 0, 0, \
407 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
409 mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), 0, 0, \
410 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
412 mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), 0, 0, \
413 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
415 mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), 0, 0, \
416 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
418 mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), 0, 0, \
419 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
421 mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), 0, 0, \
422 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
424 mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), 0, 0, \
425 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
427 mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), 0, 0, \
428 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
430 mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), 0, 0, \
431 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
433 mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), 0, 0, \
434 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
436 mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), 0, 0, \
437 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
439 mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), 0, 0, \
440 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
442 mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), 0, 0, \
443 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
445 mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), 0, 0, \
446 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
449 /* Map ATA registers -- sacrifice a data TLB due to the hw design */
450 mmu_map (0x90000000), (0x90000000), 0, 0, \
451 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
454 #elif defined(CONFIG_M547X_8X)
456 /* Map first 8 MB as code */
457 mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
458 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
460 mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
461 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
463 mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
464 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
466 mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
467 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
469 mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), MMUOR_ITLB, 0, \
470 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
472 mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), MMUOR_ITLB, 0, \
473 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
475 mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), MMUOR_ITLB, 0, \
476 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
478 mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), MMUOR_ITLB, 0, \
479 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
482 /* Map first 8 MB as data */
483 mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), 0, 0, \
484 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
485 MMUDR_W, 0, MMUDR_LK, %d0
486 mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), 0, 0, \
487 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
488 MMUDR_W, 0, MMUDR_LK, %d0
489 mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), 0, 0, \
490 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
491 MMUDR_W, 0, MMUDR_LK, %d0
492 mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), 0, 0, \
493 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
494 MMUDR_W, 0, MMUDR_LK, %d0
495 mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), 0, 0, \
496 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
497 MMUDR_W, 0, MMUDR_LK, %d0
498 mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), 0, 0, \
499 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
500 MMUDR_W, 0, MMUDR_LK, %d0
501 mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), 0, 0, \
502 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
503 MMUDR_W, 0, MMUDR_LK, %d0
504 mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), 0, 0, \
505 MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
506 MMUDR_W, 0, MMUDR_LK, %d0
509 * Do unity mapping to enable the MMU. Map first chunk of memory
510 * in place as code/data. The TLBs will be deleted after the MMU is
511 * enabled and we are executing in high memory.
514 #if defined(CONFIG_M5445X)
515 /* Map first 16 MB as code */
516 mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
517 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \
519 /* Map first 16 MB as data too */
520 mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
521 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
523 #elif defined(CONFIG_M547X_8X)
524 /* Map first 4 MB as code */
525 mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
526 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
528 mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
529 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
531 mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
532 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
534 mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
535 MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
538 /* Map first 4 MB as data too */
539 mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \
540 MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
542 mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \
543 MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
545 mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \
546 MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
548 mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \
549 MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
552 #endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
555 movel #(MMUCR_EN),%a0
557 nop /* This synchs the pipeline after a write to MMUCR */
559 movel #__running_high,%a0 /* Get around PC-relative addressing. */
562 ENTRY(__running_high)
563 load_symbol_address _stext,%sp
564 movel L(memory_start),%a0
566 load_symbol_address L(phys_kernel_start),%a0
567 load_symbol_address _stext,%a1
569 addl #PAGE_OFFSET,%a1
581 /* Unmap unity mappings */
582 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
583 #if defined(CONFIG_M5445X)
584 mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
585 mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
586 #elif defined(CONFIG_M547X_8X)
587 mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
588 mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0
589 mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0
590 mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0
591 mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
592 mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0
593 mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0
594 mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0
596 #endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
599 * Load the current task pointer and stack.
601 lea init_thread_union,%a0
602 lea THREAD_SIZE(%a0),%sp
604 #ifdef CONFIG_MCF_USER_HALT
605 /* Setup debug control reg to allow halts from user space */
610 /* Continuing in C code */
614 .section ".text.head","ax"
616 func_start set_context,%d0,(1*4)
619 func_return set_context
623 * set_fpga(addr,val) on the M5445X
625 * Map in 0x00000000 -> 0x0fffffff and then do the write.
636 movel ACR0_DEFAULT, %d0
649 L(phys_kernel_start):
654 .long PAGE_OFFSET_RAW
656 #if defined(CONFIG_UBOOT)
661 #ifdef CONFIG_MCF_USER_HALT
663 * Enable User Halt Enable in the debug control register.
666 .word 0x2c80 /* DR0 */
667 .word 0x00b0 /* 31:16 */
668 .word 0x0400 /* 15:0 -- enable UHE */
669 .word 0x0000 /* unused */