drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  52                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  53                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  54                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  62                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  63                 } else if (a2 > a1) {
  64                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  65                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = radeon_crtc->h_border;
  71                 args.usOverscanLeft = radeon_crtc->h_border;
  72                 args.usOverscanBottom = radeon_crtc->v_border;
  73                 args.usOverscanTop = radeon_crtc->v_border;
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86
  87         /* fixme - fill in enc_priv for atom dac */
  88         enum radeon_tv_std tv_std = TV_STD_NTSC;
  89         bool is_tv = false, is_cv = false;
  90         struct drm_encoder *encoder;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  96                 /* find tv std */
  97                 if (encoder->crtc == crtc) {
  98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 101                                 tv_std = tv_dac->tv_std;
 102                                 is_tv = true;
 103                         }
 104                 }
 105         }
 106
 107         memset(&args, 0, sizeof(args));
 108
 109         args.ucScaler = radeon_crtc->crtc_id;
 110
 111         if (is_tv) {
 112                 switch (tv_std) {
 113                 case TV_STD_NTSC:
 114                 default:
 115                         args.ucTVStandard = ATOM_TV_NTSC;
 116                         break;
 117                 case TV_STD_PAL:
 118                         args.ucTVStandard = ATOM_TV_PAL;
 119                         break;
 120                 case TV_STD_PAL_M:
 121                         args.ucTVStandard = ATOM_TV_PALM;
 122                         break;
 123                 case TV_STD_PAL_60:
 124                         args.ucTVStandard = ATOM_TV_PAL60;
 125                         break;
 126                 case TV_STD_NTSC_J:
 127                         args.ucTVStandard = ATOM_TV_NTSCJ;
 128                         break;
 129                 case TV_STD_SCART_PAL:
 130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 131                         break;
 132                 case TV_STD_SECAM:
 133                         args.ucTVStandard = ATOM_TV_SECAM;
 134                         break;
 135                 case TV_STD_PAL_CN:
 136                         args.ucTVStandard = ATOM_TV_PALCN;
 137                         break;
 138                 }
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else if (is_cv) {
 141                 args.ucTVStandard = ATOM_TV_CV;
 142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 143         } else {
 144                 switch (radeon_crtc->rmx_type) {
 145                 case RMX_FULL:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 case RMX_CENTER:
 149                         args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 case RMX_ASPECT:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 default:
 155                         if (ASIC_IS_AVIVO(rdev))
 156                                 args.ucEnable = ATOM_SCALER_DISABLE;
 157                         else
 158                                 args.ucEnable = ATOM_SCALER_CENTER;
 159                         break;
 160                 }
 161         }
 162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 163         if ((is_tv || is_cv)
 164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 166         }
 167 }
 168
 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 170 {
 171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         int index =
 175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 176         ENABLE_CRTC_PS_ALLOCATION args;
 177
 178         memset(&args, 0, sizeof(args));
 179
 180         args.ucCRTC = radeon_crtc->crtc_id;
 181         args.ucEnable = lock;
 182
 183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 184 }
 185
 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 192         ENABLE_CRTC_PS_ALLOCATION args;
 193
 194         memset(&args, 0, sizeof(args));
 195
 196         args.ucCRTC = radeon_crtc->crtc_id;
 197         args.ucEnable = state;
 198
 199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 200 }
 201
 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 203 {
 204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 205         struct drm_device *dev = crtc->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 208         ENABLE_CRTC_PS_ALLOCATION args;
 209
 210         memset(&args, 0, sizeof(args));
 211
 212         args.ucCRTC = radeon_crtc->crtc_id;
 213         args.ucEnable = state;
 214
 215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 216 }
 217
 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221         struct drm_device *dev = crtc->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 224         BLANK_CRTC_PS_ALLOCATION args;
 225
 226         memset(&args, 0, sizeof(args));
 227
 228         args.ucCRTC = radeon_crtc->crtc_id;
 229         args.ucBlanking = state;
 230
 231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 235 {
 236         struct drm_device *dev = crtc->dev;
 237         struct radeon_device *rdev = dev->dev_private;
 238         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 239
 240         switch (mode) {
 241         case DRM_MODE_DPMS_ON:
 242                 radeon_crtc->enabled = true;
 243                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 244                 radeon_pm_compute_clocks(rdev);
 245                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 246                 if (ASIC_IS_DCE3(rdev))
 247                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 248                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 249                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 250                 radeon_crtc_load_lut(crtc);
 251                 break;
 252         case DRM_MODE_DPMS_STANDBY:
 253         case DRM_MODE_DPMS_SUSPEND:
 254         case DRM_MODE_DPMS_OFF:
 255                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 256                 if (radeon_crtc->enabled)
 257                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 258                 if (ASIC_IS_DCE3(rdev))
 259                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 260                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 261                 radeon_crtc->enabled = false;
 262                 /* adjust pm to dpms changes AFTER disabling crtcs */
 263                 radeon_pm_compute_clocks(rdev);
 264                 break;
 265         }
 266 }
 267
 268 static void
 269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 270                              struct drm_display_mode *mode)
 271 {
 272         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 273         struct drm_device *dev = crtc->dev;
 274         struct radeon_device *rdev = dev->dev_private;
 275         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 276         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 277         u16 misc = 0;
 278
 279         memset(&args, 0, sizeof(args));
 280         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 281         args.usH_Blanking_Time =
 282                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 283         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 284         args.usV_Blanking_Time =
 285                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 286         args.usH_SyncOffset =
 287                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 288         args.usH_SyncWidth =
 289                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 290         args.usV_SyncOffset =
 291                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 292         args.usV_SyncWidth =
 293                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 294         args.ucH_Border = radeon_crtc->h_border;
 295         args.ucV_Border = radeon_crtc->v_border;
 296
 297         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 298                 misc |= ATOM_VSYNC_POLARITY;
 299         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 misc |= ATOM_HSYNC_POLARITY;
 301         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 302                 misc |= ATOM_COMPOSITESYNC;
 303         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 304                 misc |= ATOM_INTERLACE;
 305         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 306                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 307
 308         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 309         args.ucCRTC = radeon_crtc->crtc_id;
 310
 311         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 312 }
 313
 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 315                                      struct drm_display_mode *mode)
 316 {
 317         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 318         struct drm_device *dev = crtc->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 321         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 322         u16 misc = 0;
 323
 324         memset(&args, 0, sizeof(args));
 325         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 326         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 327         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 328         args.usH_SyncWidth =
 329                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 330         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 331         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 332         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 333         args.usV_SyncWidth =
 334                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 335
 336         args.ucOverscanRight = radeon_crtc->h_border;
 337         args.ucOverscanLeft = radeon_crtc->h_border;
 338         args.ucOverscanBottom = radeon_crtc->v_border;
 339         args.ucOverscanTop = radeon_crtc->v_border;
 340
 341         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 342                 misc |= ATOM_VSYNC_POLARITY;
 343         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 344                 misc |= ATOM_HSYNC_POLARITY;
 345         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 346                 misc |= ATOM_COMPOSITESYNC;
 347         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 348                 misc |= ATOM_INTERLACE;
 349         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 350                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 351
 352         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 353         args.ucCRTC = radeon_crtc->crtc_id;
 354
 355         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 356 }
 357
 358 static void atombios_disable_ss(struct drm_crtc *crtc)
 359 {
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct drm_device *dev = crtc->dev;
 362         struct radeon_device *rdev = dev->dev_private;
 363         u32 ss_cntl;
 364
 365         if (ASIC_IS_DCE4(rdev)) {
 366                 switch (radeon_crtc->pll_id) {
 367                 case ATOM_PPLL1:
 368                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 369                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 370                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 371                         break;
 372                 case ATOM_PPLL2:
 373                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 374                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 375                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 376                         break;
 377                 case ATOM_DCPLL:
 378                 case ATOM_PPLL_INVALID:
 379                         return;
 380                 }
 381         } else if (ASIC_IS_AVIVO(rdev)) {
 382                 switch (radeon_crtc->pll_id) {
 383                 case ATOM_PPLL1:
 384                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 385                         ss_cntl &= ~1;
 386                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 387                         break;
 388                 case ATOM_PPLL2:
 389                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 390                         ss_cntl &= ~1;
 391                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 392                         break;
 393                 case ATOM_DCPLL:
 394                 case ATOM_PPLL_INVALID:
 395                         return;
 396                 }
 397         }
 398 }
 399
 400
 401 union atom_enable_ss {
 402         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 403         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 404         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 405         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 406 };
 407
 408 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
 409                                      int enable,
 410                                      int pll_id,
 411                                      struct radeon_atom_ss *ss)
 412 {
 413         struct drm_device *dev = crtc->dev;
 414         struct radeon_device *rdev = dev->dev_private;
 415         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 416         union atom_enable_ss args;
 417
 418         memset(&args, 0, sizeof(args));
 419
 420         if (ASIC_IS_DCE4(rdev)) {
 421                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 422                 args.v2.ucSpreadSpectrumType = ss->type;
 423                 switch (pll_id) {
 424                 case ATOM_PPLL1:
 425                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 426                         args.v2.usSpreadSpectrumAmount = ss->amount;
 427                         args.v2.usSpreadSpectrumStep = ss->step;
 428                         break;
 429                 case ATOM_PPLL2:
 430                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 431                         args.v2.usSpreadSpectrumAmount = ss->amount;
 432                         args.v2.usSpreadSpectrumStep = ss->step;
 433                         break;
 434                 case ATOM_DCPLL:
 435                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 436                         args.v2.usSpreadSpectrumAmount = 0;
 437                         args.v2.usSpreadSpectrumStep = 0;
 438                         break;
 439                 case ATOM_PPLL_INVALID:
 440                         return;
 441                 }
 442                 args.v2.ucEnable = enable;
 443         } else if (ASIC_IS_DCE3(rdev)) {
 444                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 445                 args.v1.ucSpreadSpectrumType = ss->type;
 446                 args.v1.ucSpreadSpectrumStep = ss->step;
 447                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 448                 args.v1.ucSpreadSpectrumRange = ss->range;
 449                 args.v1.ucPpll = pll_id;
 450                 args.v1.ucEnable = enable;
 451         } else if (ASIC_IS_AVIVO(rdev)) {
 452                 if (enable == ATOM_DISABLE) {
 453                         atombios_disable_ss(crtc);
 454                         return;
 455                 }
 456                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 457                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
 458                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 459                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 460                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 461                 args.lvds_ss_2.ucEnable = enable;
 462         } else {
 463                 if (enable == ATOM_DISABLE) {
 464                         atombios_disable_ss(crtc);
 465                         return;
 466                 }
 467                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 468                 args.lvds_ss.ucSpreadSpectrumType = ss->type;
 469                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 470                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 471                 args.lvds_ss.ucEnable = enable;
 472         }
 473         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 474 }
 475
 476 union adjust_pixel_clock {
 477         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 478         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 479 };
 480
 481 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 482                                struct drm_display_mode *mode,
 483                                struct radeon_pll *pll,
 484                                bool ss_enabled,
 485                                struct radeon_atom_ss *ss)
 486 {
 487         struct drm_device *dev = crtc->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct drm_encoder *encoder = NULL;
 490         struct radeon_encoder *radeon_encoder = NULL;
 491         u32 adjusted_clock = mode->clock;
 492         int encoder_mode = 0;
 493         u32 dp_clock = mode->clock;
 494         int bpc = 8;
 495
 496         /* reset the pll flags */
 497         pll->flags = 0;
 498
 499         if (ASIC_IS_AVIVO(rdev)) {
 500                 if ((rdev->family == CHIP_RS600) ||
 501                     (rdev->family == CHIP_RS690) ||
 502                     (rdev->family == CHIP_RS740))
 503                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 504                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 505
 506                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 507                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 508                 else
 509                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 510         } else {
 511                 pll->flags |= RADEON_PLL_LEGACY;
 512
 513                 if (mode->clock > 200000)       /* range limits??? */
 514                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 515                 else
 516                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 517
 518         }
 519
 520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 521                 if (encoder->crtc == crtc) {
 522                         radeon_encoder = to_radeon_encoder(encoder);
 523                         encoder_mode = atombios_get_encoder_mode(encoder);
 524                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
 525                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 526                                 if (connector) {
 527                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 528                                         struct radeon_connector_atom_dig *dig_connector =
 529                                                 radeon_connector->con_priv;
 530
 531                                         dp_clock = dig_connector->dp_clock;
 532                                 }
 533                         }
 534 #if 0 /* doesn't work properly on some laptops */
 535                         /* use recommended ref_div for ss */
 536                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 537                                 if (ss_enabled) {
 538                                         if (ss->refdiv) {
 539                                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 540                                                 pll->reference_div = ss->refdiv;
 541                                         }
 542                                 }
 543                         }
 544 #endif
 545                         if (ASIC_IS_AVIVO(rdev)) {
 546                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 547                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 548                                         adjusted_clock = mode->clock * 2;
 549                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 550                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 551                         } else {
 552                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 553                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 554                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 555                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 556                         }
 557                         break;
 558                 }
 559         }
 560
 561         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 562          * accordingly based on the encoder/transmitter to work around
 563          * special hw requirements.
 564          */
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 union adjust_pixel_clock args;
 567                 u8 frev, crev;
 568                 int index;
 569
 570                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 571                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 572                                            &crev))
 573                         return adjusted_clock;
 574
 575                 memset(&args, 0, sizeof(args));
 576
 577                 switch (frev) {
 578                 case 1:
 579                         switch (crev) {
 580                         case 1:
 581                         case 2:
 582                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 583                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 584                                 args.v1.ucEncodeMode = encoder_mode;
 585                                 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 586                                         if (ss_enabled)
 587                                                 args.v1.ucConfig |=
 588                                                         ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 589                                 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 590                                         args.v1.ucConfig |=
 591                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 592                                 }
 593
 594                                 atom_execute_table(rdev->mode_info.atom_context,
 595                                                    index, (uint32_t *)&args);
 596                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 597                                 break;
 598                         case 3:
 599                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 600                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 601                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 602                                 args.v3.sInput.ucDispPllConfig = 0;
 603                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 604                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 605                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 606                                                 if (ss_enabled)
 607                                                         args.v3.sInput.ucDispPllConfig |=
 608                                                                 DISPPLL_CONFIG_SS_ENABLE;
 609                                                 args.v3.sInput.ucDispPllConfig |=
 610                                                         DISPPLL_CONFIG_COHERENT_MODE;
 611                                                 /* 16200 or 27000 */
 612                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 613                                         } else {
 614                                                 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 615                                                         /* deep color support */
 616                                                         args.v3.sInput.usPixelClock =
 617                                                                 cpu_to_le16((mode->clock * bpc / 8) / 10);
 618                                                 }
 619                                                 if (dig->coherent_mode)
 620                                                         args.v3.sInput.ucDispPllConfig |=
 621                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 622                                                 if (mode->clock > 165000)
 623                                                         args.v3.sInput.ucDispPllConfig |=
 624                                                                 DISPPLL_CONFIG_DUAL_LINK;
 625                                         }
 626                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 627                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 628                                                 if (ss_enabled)
 629                                                         args.v3.sInput.ucDispPllConfig |=
 630                                                                 DISPPLL_CONFIG_SS_ENABLE;
 631                                                 args.v3.sInput.ucDispPllConfig |=
 632                                                         DISPPLL_CONFIG_COHERENT_MODE;
 633                                                 /* 16200 or 27000 */
 634                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 635                                         } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 636                                                 if (ss_enabled)
 637                                                         args.v3.sInput.ucDispPllConfig |=
 638                                                                 DISPPLL_CONFIG_SS_ENABLE;
 639                                         } else {
 640                                                 if (mode->clock > 165000)
 641                                                         args.v3.sInput.ucDispPllConfig |=
 642                                                                 DISPPLL_CONFIG_DUAL_LINK;
 643                                         }
 644                                 }
 645                                 atom_execute_table(rdev->mode_info.atom_context,
 646                                                    index, (uint32_t *)&args);
 647                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 648                                 if (args.v3.sOutput.ucRefDiv) {
 649                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 650                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 651                                 }
 652                                 if (args.v3.sOutput.ucPostDiv) {
 653                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 654                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 655                                 }
 656                                 break;
 657                         default:
 658                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 659                                 return adjusted_clock;
 660                         }
 661                         break;
 662                 default:
 663                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 664                         return adjusted_clock;
 665                 }
 666         }
 667         return adjusted_clock;
 668 }
 669
 670 union set_pixel_clock {
 671         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 672         PIXEL_CLOCK_PARAMETERS v1;
 673         PIXEL_CLOCK_PARAMETERS_V2 v2;
 674         PIXEL_CLOCK_PARAMETERS_V3 v3;
 675         PIXEL_CLOCK_PARAMETERS_V5 v5;
 676 };
 677
 678 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct radeon_device *rdev = dev->dev_private;
 682         u8 frev, crev;
 683         int index;
 684         union set_pixel_clock args;
 685
 686         memset(&args, 0, sizeof(args));
 687
 688         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 689         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 690                                    &crev))
 691                 return;
 692
 693         switch (frev) {
 694         case 1:
 695                 switch (crev) {
 696                 case 5:
 697                         /* if the default dcpll clock is specified,
 698                          * SetPixelClock provides the dividers
 699                          */
 700                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 701                         args.v5.usPixelClock = rdev->clock.default_dispclk;
 702                         args.v5.ucPpll = ATOM_DCPLL;
 703                         break;
 704                 default:
 705                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 706                         return;
 707                 }
 708                 break;
 709         default:
 710                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 711                 return;
 712         }
 713         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 714 }
 715
 716 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 717                                       int crtc_id,
 718                                       int pll_id,
 719                                       u32 encoder_mode,
 720                                       u32 encoder_id,
 721                                       u32 clock,
 722                                       u32 ref_div,
 723                                       u32 fb_div,
 724                                       u32 frac_fb_div,
 725                                       u32 post_div)
 726 {
 727         struct drm_device *dev = crtc->dev;
 728         struct radeon_device *rdev = dev->dev_private;
 729         u8 frev, crev;
 730         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 731         union set_pixel_clock args;
 732
 733         memset(&args, 0, sizeof(args));
 734
 735         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 736                                    &crev))
 737                 return;
 738
 739         switch (frev) {
 740         case 1:
 741                 switch (crev) {
 742                 case 1:
 743                         if (clock == ATOM_DISABLE)
 744                                 return;
 745                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 746                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 747                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 748                         args.v1.ucFracFbDiv = frac_fb_div;
 749                         args.v1.ucPostDiv = post_div;
 750                         args.v1.ucPpll = pll_id;
 751                         args.v1.ucCRTC = crtc_id;
 752                         args.v1.ucRefDivSrc = 1;
 753                         break;
 754                 case 2:
 755                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 756                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 757                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 758                         args.v2.ucFracFbDiv = frac_fb_div;
 759                         args.v2.ucPostDiv = post_div;
 760                         args.v2.ucPpll = pll_id;
 761                         args.v2.ucCRTC = crtc_id;
 762                         args.v2.ucRefDivSrc = 1;
 763                         break;
 764                 case 3:
 765                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 766                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 767                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 768                         args.v3.ucFracFbDiv = frac_fb_div;
 769                         args.v3.ucPostDiv = post_div;
 770                         args.v3.ucPpll = pll_id;
 771                         args.v3.ucMiscInfo = (pll_id << 2);
 772                         args.v3.ucTransmitterId = encoder_id;
 773                         args.v3.ucEncoderMode = encoder_mode;
 774                         break;
 775                 case 5:
 776                         args.v5.ucCRTC = crtc_id;
 777                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 778                         args.v5.ucRefDiv = ref_div;
 779                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 780                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 781                         args.v5.ucPostDiv = post_div;
 782                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 783                         args.v5.ucTransmitterID = encoder_id;
 784                         args.v5.ucEncoderMode = encoder_mode;
 785                         args.v5.ucPpll = pll_id;
 786                         break;
 787                 default:
 788                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 789                         return;
 790                 }
 791                 break;
 792         default:
 793                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 794                 return;
 795         }
 796
 797         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 798 }
 799
 800 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 801 {
 802         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 803         struct drm_device *dev = crtc->dev;
 804         struct radeon_device *rdev = dev->dev_private;
 805         struct drm_encoder *encoder = NULL;
 806         struct radeon_encoder *radeon_encoder = NULL;
 807         u32 pll_clock = mode->clock;
 808         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 809         struct radeon_pll *pll;
 810         u32 adjusted_clock;
 811         int encoder_mode = 0;
 812         struct radeon_atom_ss ss;
 813         bool ss_enabled = false;
 814
 815         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 816                 if (encoder->crtc == crtc) {
 817                         radeon_encoder = to_radeon_encoder(encoder);
 818                         encoder_mode = atombios_get_encoder_mode(encoder);
 819                         break;
 820                 }
 821         }
 822
 823         if (!radeon_encoder)
 824                 return;
 825
 826         switch (radeon_crtc->pll_id) {
 827         case ATOM_PPLL1:
 828                 pll = &rdev->clock.p1pll;
 829                 break;
 830         case ATOM_PPLL2:
 831                 pll = &rdev->clock.p2pll;
 832                 break;
 833         case ATOM_DCPLL:
 834         case ATOM_PPLL_INVALID:
 835         default:
 836                 pll = &rdev->clock.dcpll;
 837                 break;
 838         }
 839
 840         if (radeon_encoder->active_device &
 841             (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
 842                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 843                 struct drm_connector *connector =
 844                         radeon_get_connector_for_encoder(encoder);
 845                 struct radeon_connector *radeon_connector =
 846                         to_radeon_connector(connector);
 847                 struct radeon_connector_atom_dig *dig_connector =
 848                         radeon_connector->con_priv;
 849                 int dp_clock;
 850
 851                 switch (encoder_mode) {
 852                 case ATOM_ENCODER_MODE_DP:
 853                         /* DP/eDP */
 854                         dp_clock = dig_connector->dp_clock / 10;
 855                         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 856                                 if (ASIC_IS_DCE4(rdev))
 857                                         ss_enabled =
 858                                                 radeon_atombios_get_asic_ss_info(rdev, &ss,
 859                                                                                  dig->lcd_ss_id,
 860                                                                                  dp_clock);
 861                                 else
 862                                         ss_enabled =
 863                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 864                                                                                  dig->lcd_ss_id);
 865                         } else {
 866                                 if (ASIC_IS_DCE4(rdev))
 867                                         ss_enabled =
 868                                                 radeon_atombios_get_asic_ss_info(rdev, &ss,
 869                                                                                  ASIC_INTERNAL_SS_ON_DP,
 870                                                                                  dp_clock);
 871                                 else {
 872                                         if (dp_clock == 16200) {
 873                                                 ss_enabled =
 874                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 875                                                                                          ATOM_DP_SS_ID2);
 876                                                 if (!ss_enabled)
 877                                                         ss_enabled =
 878                                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 879                                                                                                  ATOM_DP_SS_ID1);
 880                                         } else
 881                                                 ss_enabled =
 882                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 883                                                                                          ATOM_DP_SS_ID1);
 884                                 }
 885                         }
 886                         break;
 887                 case ATOM_ENCODER_MODE_LVDS:
 888                         if (ASIC_IS_DCE4(rdev))
 889                                 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
 890                                                                               dig->lcd_ss_id,
 891                                                                               mode->clock / 10);
 892                         else
 893                                 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
 894                                                                               dig->lcd_ss_id);
 895                         break;
 896                 case ATOM_ENCODER_MODE_DVI:
 897                         if (ASIC_IS_DCE4(rdev))
 898                                 ss_enabled =
 899                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 900                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 901                                                                          mode->clock / 10);
 902                         break;
 903                 case ATOM_ENCODER_MODE_HDMI:
 904                         if (ASIC_IS_DCE4(rdev))
 905                                 ss_enabled =
 906                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 907                                                                          ASIC_INTERNAL_SS_ON_HDMI,
 908                                                                          mode->clock / 10);
 909                         break;
 910                 default:
 911                         break;
 912                 }
 913         }
 914
 915         /* adjust pixel clock as needed */
 916         adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
 917
 918         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 919                            &ref_div, &post_div);
 920
 921         atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
 922
 923         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 924                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
 925                                   ref_div, fb_div, frac_fb_div, post_div);
 926
 927         if (ss_enabled) {
 928                 /* calculate ss amount and step size */
 929                 if (ASIC_IS_DCE4(rdev)) {
 930                         u32 step_size;
 931                         u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
 932                         ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
 933                         ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
 934                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
 935                         if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
 936                                 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
 937                                         (125 * 25 * pll->reference_freq / 100);
 938                         else
 939                                 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
 940                                         (125 * 25 * pll->reference_freq / 100);
 941                         ss.step = step_size;
 942                 }
 943
 944                 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
 945         }
 946 }
 947
 948 static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
 949                                       struct drm_framebuffer *fb,
 950                                       int x, int y, int atomic)
 951 {
 952         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 953         struct drm_device *dev = crtc->dev;
 954         struct radeon_device *rdev = dev->dev_private;
 955         struct radeon_framebuffer *radeon_fb;
 956         struct drm_framebuffer *target_fb;
 957         struct drm_gem_object *obj;
 958         struct radeon_bo *rbo;
 959         uint64_t fb_location;
 960         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 961         int r;
 962
 963         /* no fb bound */
 964         if (!atomic && !crtc->fb) {
 965                 DRM_DEBUG_KMS("No FB bound\n");
 966                 return 0;
 967         }
 968
 969         if (atomic) {
 970                 radeon_fb = to_radeon_framebuffer(fb);
 971                 target_fb = fb;
 972         }
 973         else {
 974                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 975                 target_fb = crtc->fb;
 976         }
 977
 978         /* If atomic, assume fb object is pinned & idle & fenced and
 979          * just update base pointers
 980          */
 981         obj = radeon_fb->obj;
 982         rbo = obj->driver_private;
 983         r = radeon_bo_reserve(rbo, false);
 984         if (unlikely(r != 0))
 985                 return r;
 986
 987         if (atomic)
 988                 fb_location = radeon_bo_gpu_offset(rbo);
 989         else {
 990                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 991                 if (unlikely(r != 0)) {
 992                         radeon_bo_unreserve(rbo);
 993                         return -EINVAL;
 994                 }
 995         }
 996
 997         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 998         radeon_bo_unreserve(rbo);
 999
1000         switch (target_fb->bits_per_pixel) {
1001         case 8:
1002                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1003                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1004                 break;
1005         case 15:
1006                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1007                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1008                 break;
1009         case 16:
1010                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1011                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1012                 break;
1013         case 24:
1014         case 32:
1015                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1016                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1017                 break;
1018         default:
1019                 DRM_ERROR("Unsupported screen depth %d\n",
1020                           target_fb->bits_per_pixel);
1021                 return -EINVAL;
1022         }
1023
1024         if (tiling_flags & RADEON_TILING_MACRO)
1025                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1026         else if (tiling_flags & RADEON_TILING_MICRO)
1027                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1028
1029         switch (radeon_crtc->crtc_id) {
1030         case 0:
1031                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1032                 break;
1033         case 1:
1034                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1035                 break;
1036         case 2:
1037                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1038                 break;
1039         case 3:
1040                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1041                 break;
1042         case 4:
1043                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1044                 break;
1045         case 5:
1046                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1047                 break;
1048         default:
1049                 break;
1050         }
1051
1052         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1053                upper_32_bits(fb_location));
1054         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1055                upper_32_bits(fb_location));
1056         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1057                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1058         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1059                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1060         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1061
1062         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1063         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1064         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1065         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1066         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1067         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1068
1069         fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1070         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1071         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1072
1073         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1074                crtc->mode.vdisplay);
1075         x &= ~3;
1076         y &= ~1;
1077         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1078                (x << 16) | y);
1079         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1080                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1081
1082         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1083                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1084                        EVERGREEN_INTERLEAVE_EN);
1085         else
1086                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1087
1088         if (!atomic && fb && fb != crtc->fb) {
1089                 radeon_fb = to_radeon_framebuffer(fb);
1090                 rbo = radeon_fb->obj->driver_private;
1091                 r = radeon_bo_reserve(rbo, false);
1092                 if (unlikely(r != 0))
1093                         return r;
1094                 radeon_bo_unpin(rbo);
1095                 radeon_bo_unreserve(rbo);
1096         }
1097
1098         /* Bytes per pixel may have changed */
1099         radeon_bandwidth_update(rdev);
1100
1101         return 0;
1102 }
1103
1104 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1105                                   struct drm_framebuffer *fb,
1106                                   int x, int y, int atomic)
1107 {
1108         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1109         struct drm_device *dev = crtc->dev;
1110         struct radeon_device *rdev = dev->dev_private;
1111         struct radeon_framebuffer *radeon_fb;
1112         struct drm_gem_object *obj;
1113         struct radeon_bo *rbo;
1114         struct drm_framebuffer *target_fb;
1115         uint64_t fb_location;
1116         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1117         int r;
1118
1119         /* no fb bound */
1120         if (!atomic && !crtc->fb) {
1121                 DRM_DEBUG_KMS("No FB bound\n");
1122                 return 0;
1123         }
1124
1125         if (atomic) {
1126                 radeon_fb = to_radeon_framebuffer(fb);
1127                 target_fb = fb;
1128         }
1129         else {
1130                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1131                 target_fb = crtc->fb;
1132         }
1133
1134         obj = radeon_fb->obj;
1135         rbo = obj->driver_private;
1136         r = radeon_bo_reserve(rbo, false);
1137         if (unlikely(r != 0))
1138                 return r;
1139
1140         /* If atomic, assume fb object is pinned & idle & fenced and
1141          * just update base pointers
1142          */
1143         if (atomic)
1144                 fb_location = radeon_bo_gpu_offset(rbo);
1145         else {
1146                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1147                 if (unlikely(r != 0)) {
1148                         radeon_bo_unreserve(rbo);
1149                         return -EINVAL;
1150                 }
1151         }
1152         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1153         radeon_bo_unreserve(rbo);
1154
1155         switch (target_fb->bits_per_pixel) {
1156         case 8:
1157                 fb_format =
1158                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1159                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1160                 break;
1161         case 15:
1162                 fb_format =
1163                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1164                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1165                 break;
1166         case 16:
1167                 fb_format =
1168                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1169                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1170                 break;
1171         case 24:
1172         case 32:
1173                 fb_format =
1174                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1175                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1176                 break;
1177         default:
1178                 DRM_ERROR("Unsupported screen depth %d\n",
1179                           target_fb->bits_per_pixel);
1180                 return -EINVAL;
1181         }
1182
1183         if (rdev->family >= CHIP_R600) {
1184                 if (tiling_flags & RADEON_TILING_MACRO)
1185                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1186                 else if (tiling_flags & RADEON_TILING_MICRO)
1187                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1188         } else {
1189                 if (tiling_flags & RADEON_TILING_MACRO)
1190                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1191
1192                 if (tiling_flags & RADEON_TILING_MICRO)
1193                         fb_format |= AVIVO_D1GRPH_TILED;
1194         }
1195
1196         if (radeon_crtc->crtc_id == 0)
1197                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1198         else
1199                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1200
1201         if (rdev->family >= CHIP_RV770) {
1202                 if (radeon_crtc->crtc_id) {
1203                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1204                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1205                 } else {
1206                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1207                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1208                 }
1209         }
1210         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1211                (u32) fb_location);
1212         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1213                radeon_crtc->crtc_offset, (u32) fb_location);
1214         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1215
1216         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1217         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1218         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1219         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1220         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1221         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1222
1223         fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1224         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1225         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1226
1227         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1228                crtc->mode.vdisplay);
1229         x &= ~3;
1230         y &= ~1;
1231         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1232                (x << 16) | y);
1233         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1234                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1235
1236         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1237                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1238                        AVIVO_D1MODE_INTERLEAVE_EN);
1239         else
1240                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1241
1242         if (!atomic && fb && fb != crtc->fb) {
1243                 radeon_fb = to_radeon_framebuffer(fb);
1244                 rbo = radeon_fb->obj->driver_private;
1245                 r = radeon_bo_reserve(rbo, false);
1246                 if (unlikely(r != 0))
1247                         return r;
1248                 radeon_bo_unpin(rbo);
1249                 radeon_bo_unreserve(rbo);
1250         }
1251
1252         /* Bytes per pixel may have changed */
1253         radeon_bandwidth_update(rdev);
1254
1255         return 0;
1256 }
1257
1258 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1259                            struct drm_framebuffer *old_fb)
1260 {
1261         struct drm_device *dev = crtc->dev;
1262         struct radeon_device *rdev = dev->dev_private;
1263
1264         if (ASIC_IS_DCE4(rdev))
1265                 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1266         else if (ASIC_IS_AVIVO(rdev))
1267                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1268         else
1269                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1270 }
1271
1272 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1273                                   struct drm_framebuffer *fb,
1274                                   int x, int y, enum mode_set_atomic state)
1275 {
1276        struct drm_device *dev = crtc->dev;
1277        struct radeon_device *rdev = dev->dev_private;
1278
1279         if (ASIC_IS_DCE4(rdev))
1280                 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
1281         else if (ASIC_IS_AVIVO(rdev))
1282                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1283         else
1284                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1285 }
1286
1287 /* properly set additional regs when using atombios */
1288 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1289 {
1290         struct drm_device *dev = crtc->dev;
1291         struct radeon_device *rdev = dev->dev_private;
1292         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1293         u32 disp_merge_cntl;
1294
1295         switch (radeon_crtc->crtc_id) {
1296         case 0:
1297                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1298                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1299                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1300                 break;
1301         case 1:
1302                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1303                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1304                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1305                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1306                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1307                 break;
1308         }
1309 }
1310
1311 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1312 {
1313         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1314         struct drm_device *dev = crtc->dev;
1315         struct radeon_device *rdev = dev->dev_private;
1316         struct drm_encoder *test_encoder;
1317         struct drm_crtc *test_crtc;
1318         uint32_t pll_in_use = 0;
1319
1320         if (ASIC_IS_DCE4(rdev)) {
1321                 /* if crtc is driving DP and we have an ext clock, use that */
1322                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1323                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1324                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1325                                         if (rdev->clock.dp_extclk)
1326                                                 return ATOM_PPLL_INVALID;
1327                                 }
1328                         }
1329                 }
1330
1331                 /* otherwise, pick one of the plls */
1332                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1333                         struct radeon_crtc *radeon_test_crtc;
1334
1335                         if (crtc == test_crtc)
1336                                 continue;
1337
1338                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1339                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1340                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1341                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1342                 }
1343                 if (!(pll_in_use & 1))
1344                         return ATOM_PPLL1;
1345                 return ATOM_PPLL2;
1346         } else
1347                 return radeon_crtc->crtc_id;
1348
1349 }
1350
1351 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1352                            struct drm_display_mode *mode,
1353                            struct drm_display_mode *adjusted_mode,
1354                            int x, int y, struct drm_framebuffer *old_fb)
1355 {
1356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1357         struct drm_device *dev = crtc->dev;
1358         struct radeon_device *rdev = dev->dev_private;
1359         struct drm_encoder *encoder;
1360         bool is_tvcv = false;
1361
1362         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1363                 /* find tv std */
1364                 if (encoder->crtc == crtc) {
1365                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1366                         if (radeon_encoder->active_device &
1367                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1368                                 is_tvcv = true;
1369                 }
1370         }
1371
1372         /* always set DCPLL */
1373         if (ASIC_IS_DCE4(rdev)) {
1374                 struct radeon_atom_ss ss;
1375                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1376                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1377                                                                    rdev->clock.default_dispclk);
1378                 if (ss_enabled)
1379                         atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1380                 atombios_crtc_set_dcpll(crtc);
1381                 if (ss_enabled)
1382                         atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1383         }
1384         atombios_crtc_set_pll(crtc, adjusted_mode);
1385
1386         if (ASIC_IS_DCE4(rdev))
1387                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1388         else if (ASIC_IS_AVIVO(rdev)) {
1389                 if (is_tvcv)
1390                         atombios_crtc_set_timing(crtc, adjusted_mode);
1391                 else
1392                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1393         } else {
1394                 atombios_crtc_set_timing(crtc, adjusted_mode);
1395                 if (radeon_crtc->crtc_id == 0)
1396                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1397                 radeon_legacy_atom_fixup(crtc);
1398         }
1399         atombios_crtc_set_base(crtc, x, y, old_fb);
1400         atombios_overscan_setup(crtc, mode, adjusted_mode);
1401         atombios_scaler_setup(crtc);
1402         return 0;
1403 }
1404
1405 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1406                                      struct drm_display_mode *mode,
1407                                      struct drm_display_mode *adjusted_mode)
1408 {
1409         struct drm_device *dev = crtc->dev;
1410         struct radeon_device *rdev = dev->dev_private;
1411
1412         /* adjust pm to upcoming mode change */
1413         radeon_pm_compute_clocks(rdev);
1414
1415         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1416                 return false;
1417         return true;
1418 }
1419
1420 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1421 {
1422         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1423
1424         /* pick pll */
1425         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1426
1427         atombios_lock_crtc(crtc, ATOM_ENABLE);
1428         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1429 }
1430
1431 static void atombios_crtc_commit(struct drm_crtc *crtc)
1432 {
1433         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1434         atombios_lock_crtc(crtc, ATOM_DISABLE);
1435 }
1436
1437 static void atombios_crtc_disable(struct drm_crtc *crtc)
1438 {
1439         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1440         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1441
1442         switch (radeon_crtc->pll_id) {
1443         case ATOM_PPLL1:
1444         case ATOM_PPLL2:
1445                 /* disable the ppll */
1446                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1447                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1448                 break;
1449         default:
1450                 break;
1451         }
1452         radeon_crtc->pll_id = -1;
1453 }
1454
1455 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1456         .dpms = atombios_crtc_dpms,
1457         .mode_fixup = atombios_crtc_mode_fixup,
1458         .mode_set = atombios_crtc_mode_set,
1459         .mode_set_base = atombios_crtc_set_base,
1460         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1461         .prepare = atombios_crtc_prepare,
1462         .commit = atombios_crtc_commit,
1463         .load_lut = radeon_crtc_load_lut,
1464         .disable = atombios_crtc_disable,
1465 };
1466
1467 void radeon_atombios_init_crtc(struct drm_device *dev,
1468                                struct radeon_crtc *radeon_crtc)
1469 {
1470         struct radeon_device *rdev = dev->dev_private;
1471
1472         if (ASIC_IS_DCE4(rdev)) {
1473                 switch (radeon_crtc->crtc_id) {
1474                 case 0:
1475                 default:
1476                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1477                         break;
1478                 case 1:
1479                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1480                         break;
1481                 case 2:
1482                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1483                         break;
1484                 case 3:
1485                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1486                         break;
1487                 case 4:
1488                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1489                         break;
1490                 case 5:
1491                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1492                         break;
1493                 }
1494         } else {
1495                 if (radeon_crtc->crtc_id == 1)
1496                         radeon_crtc->crtc_offset =
1497                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1498                 else
1499                         radeon_crtc->crtc_offset = 0;
1500         }
1501         radeon_crtc->pll_id = -1;
1502         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1503 }