drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/slab.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 /* Here's the desired hotplug mode */
  38 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43                            ADPA_CRT_HOTPLUG_ENABLE)
  44
  45 struct intel_crt {
  46         struct intel_encoder base;
  47         bool force_hotplug_required;
  48 };
  49
  50 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  51 {
  52         return container_of(intel_attached_encoder(connector),
  53                             struct intel_crt, base);
  54 }
  55
  56 static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  57 {
  58         struct drm_device *dev = encoder->dev;
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60         u32 temp, reg;
  61
  62         if (HAS_PCH_SPLIT(dev))
  63                 reg = PCH_ADPA;
  64         else
  65                 reg = ADPA;
  66
  67         temp = I915_READ(reg);
  68         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  69         temp &= ~ADPA_DAC_ENABLE;
  70
  71         switch(mode) {
  72         case DRM_MODE_DPMS_ON:
  73                 temp |= ADPA_DAC_ENABLE;
  74                 break;
  75         case DRM_MODE_DPMS_STANDBY:
  76                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  77                 break;
  78         case DRM_MODE_DPMS_SUSPEND:
  79                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  80                 break;
  81         case DRM_MODE_DPMS_OFF:
  82                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  83                 break;
  84         }
  85
  86         I915_WRITE(reg, temp);
  87 }
  88
  89 static int intel_crt_mode_valid(struct drm_connector *connector,
  90                                 struct drm_display_mode *mode)
  91 {
  92         struct drm_device *dev = connector->dev;
  93
  94         int max_clock = 0;
  95         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  96                 return MODE_NO_DBLESCAN;
  97
  98         if (mode->clock < 25000)
  99                 return MODE_CLOCK_LOW;
 100
 101         if (IS_GEN2(dev))
 102                 max_clock = 350000;
 103         else
 104                 max_clock = 400000;
 105         if (mode->clock > max_clock)
 106                 return MODE_CLOCK_HIGH;
 107
 108         return MODE_OK;
 109 }
 110
 111 static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
 112                                  struct drm_display_mode *mode,
 113                                  struct drm_display_mode *adjusted_mode)
 114 {
 115         return true;
 116 }
 117
 118 static void intel_crt_mode_set(struct drm_encoder *encoder,
 119                                struct drm_display_mode *mode,
 120                                struct drm_display_mode *adjusted_mode)
 121 {
 122
 123         struct drm_device *dev = encoder->dev;
 124         struct drm_crtc *crtc = encoder->crtc;
 125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127         int dpll_md_reg;
 128         u32 adpa, dpll_md;
 129         u32 adpa_reg;
 130
 131         if (intel_crtc->pipe == 0)
 132                 dpll_md_reg = DPLL_A_MD;
 133         else
 134                 dpll_md_reg = DPLL_B_MD;
 135
 136         if (HAS_PCH_SPLIT(dev))
 137                 adpa_reg = PCH_ADPA;
 138         else
 139                 adpa_reg = ADPA;
 140
 141         /*
 142          * Disable separate mode multiplier used when cloning SDVO to CRT
 143          * XXX this needs to be adjusted when we really are cloning
 144          */
 145         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 146                 dpll_md = I915_READ(dpll_md_reg);
 147                 I915_WRITE(dpll_md_reg,
 148                            dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
 149         }
 150
 151         adpa = ADPA_HOTPLUG_BITS;
 152         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 153                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 154         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 155                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 156
 157         if (intel_crtc->pipe == 0) {
 158                 if (HAS_PCH_CPT(dev))
 159                         adpa |= PORT_TRANS_A_SEL_CPT;
 160                 else
 161                         adpa |= ADPA_PIPE_A_SELECT;
 162                 if (!HAS_PCH_SPLIT(dev))
 163                         I915_WRITE(BCLRPAT_A, 0);
 164         } else {
 165                 if (HAS_PCH_CPT(dev))
 166                         adpa |= PORT_TRANS_B_SEL_CPT;
 167                 else
 168                         adpa |= ADPA_PIPE_B_SELECT;
 169                 if (!HAS_PCH_SPLIT(dev))
 170                         I915_WRITE(BCLRPAT_B, 0);
 171         }
 172
 173         I915_WRITE(adpa_reg, adpa);
 174 }
 175
 176 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 177 {
 178         struct drm_device *dev = connector->dev;
 179         struct intel_crt *crt = intel_attached_crt(connector);
 180         struct drm_i915_private *dev_priv = dev->dev_private;
 181         u32 adpa;
 182         bool ret;
 183
 184         /* The first time through, trigger an explicit detection cycle */
 185         if (crt->force_hotplug_required) {
 186                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 187                 u32 save_adpa;
 188
 189                 crt->force_hotplug_required = 0;
 190
 191                 save_adpa = adpa = I915_READ(PCH_ADPA);
 192                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 193
 194                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 195                 if (turn_off_dac)
 196                         adpa &= ~ADPA_DAC_ENABLE;
 197
 198                 I915_WRITE(PCH_ADPA, adpa);
 199
 200                 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 201                              1000))
 202                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 203
 204                 if (turn_off_dac) {
 205                         I915_WRITE(PCH_ADPA, save_adpa);
 206                         POSTING_READ(PCH_ADPA);
 207                 }
 208         }
 209
 210         /* Check the status to see if both blue and green are on now */
 211         adpa = I915_READ(PCH_ADPA);
 212         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 213                 ret = true;
 214         else
 215                 ret = false;
 216         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 217
 218         return ret;
 219 }
 220
 221 /**
 222  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 223  *
 224  * Not for i915G/i915GM
 225  *
 226  * \return true if CRT is connected.
 227  * \return false if CRT is disconnected.
 228  */
 229 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 230 {
 231         struct drm_device *dev = connector->dev;
 232         struct drm_i915_private *dev_priv = dev->dev_private;
 233         u32 hotplug_en, orig, stat;
 234         bool ret = false;
 235         int i, tries = 0;
 236
 237         if (HAS_PCH_SPLIT(dev))
 238                 return intel_ironlake_crt_detect_hotplug(connector);
 239
 240         /*
 241          * On 4 series desktop, CRT detect sequence need to be done twice
 242          * to get a reliable result.
 243          */
 244
 245         if (IS_G4X(dev) && !IS_GM45(dev))
 246                 tries = 2;
 247         else
 248                 tries = 1;
 249         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
 250         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 251
 252         for (i = 0; i < tries ; i++) {
 253                 /* turn on the FORCE_DETECT */
 254                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 255                 /* wait for FORCE_DETECT to go off */
 256                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 257                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 258                              1000))
 259                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 260         }
 261
 262         stat = I915_READ(PORT_HOTPLUG_STAT);
 263         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 264                 ret = true;
 265
 266         /* clear the interrupt we just generated, if any */
 267         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 268
 269         /* and put the bits back */
 270         I915_WRITE(PORT_HOTPLUG_EN, orig);
 271
 272         return ret;
 273 }
 274
 275 static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus)
 276 {
 277         u8 buf;
 278         struct i2c_msg msgs[] = {
 279                 {
 280                         .addr = 0xA0,
 281                         .flags = 0,
 282                         .len = 1,
 283                         .buf = &buf,
 284                 },
 285         };
 286         /* DDC monitor detect: Does it ACK a write to 0xA0? */
 287         return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
 288 }
 289
 290 static bool intel_crt_detect_ddc(struct intel_crt *crt)
 291 {
 292         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 293
 294         /* CRT should always be at 0, but check anyway */
 295         if (crt->base.type != INTEL_OUTPUT_ANALOG)
 296                 return false;
 297
 298         if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) {
 299                 DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n");
 300                 return true;
 301         }
 302
 303         if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
 304                 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 305                 return true;
 306         }
 307
 308         return false;
 309 }
 310
 311 static enum drm_connector_status
 312 intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
 313 {
 314         struct drm_encoder *encoder = &crt->base.base;
 315         struct drm_device *dev = encoder->dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 318         uint32_t pipe = intel_crtc->pipe;
 319         uint32_t save_bclrpat;
 320         uint32_t save_vtotal;
 321         uint32_t vtotal, vactive;
 322         uint32_t vsample;
 323         uint32_t vblank, vblank_start, vblank_end;
 324         uint32_t dsl;
 325         uint32_t bclrpat_reg;
 326         uint32_t vtotal_reg;
 327         uint32_t vblank_reg;
 328         uint32_t vsync_reg;
 329         uint32_t pipeconf_reg;
 330         uint32_t pipe_dsl_reg;
 331         uint8_t st00;
 332         enum drm_connector_status status;
 333
 334         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 335
 336         if (pipe == 0) {
 337                 bclrpat_reg = BCLRPAT_A;
 338                 vtotal_reg = VTOTAL_A;
 339                 vblank_reg = VBLANK_A;
 340                 vsync_reg = VSYNC_A;
 341                 pipeconf_reg = PIPEACONF;
 342                 pipe_dsl_reg = PIPEADSL;
 343         } else {
 344                 bclrpat_reg = BCLRPAT_B;
 345                 vtotal_reg = VTOTAL_B;
 346                 vblank_reg = VBLANK_B;
 347                 vsync_reg = VSYNC_B;
 348                 pipeconf_reg = PIPEBCONF;
 349                 pipe_dsl_reg = PIPEBDSL;
 350         }
 351
 352         save_bclrpat = I915_READ(bclrpat_reg);
 353         save_vtotal = I915_READ(vtotal_reg);
 354         vblank = I915_READ(vblank_reg);
 355
 356         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 357         vactive = (save_vtotal & 0x7ff) + 1;
 358
 359         vblank_start = (vblank & 0xfff) + 1;
 360         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 361
 362         /* Set the border color to purple. */
 363         I915_WRITE(bclrpat_reg, 0x500050);
 364
 365         if (!IS_GEN2(dev)) {
 366                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 367                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 368                 POSTING_READ(pipeconf_reg);
 369                 /* Wait for next Vblank to substitue
 370                  * border color for Color info */
 371                 intel_wait_for_vblank(dev, pipe);
 372                 st00 = I915_READ8(VGA_MSR_WRITE);
 373                 status = ((st00 & (1 << 4)) != 0) ?
 374                         connector_status_connected :
 375                         connector_status_disconnected;
 376
 377                 I915_WRITE(pipeconf_reg, pipeconf);
 378         } else {
 379                 bool restore_vblank = false;
 380                 int count, detect;
 381
 382                 /*
 383                 * If there isn't any border, add some.
 384                 * Yes, this will flicker
 385                 */
 386                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 387                         uint32_t vsync = I915_READ(vsync_reg);
 388                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 389
 390                         vblank_start = vsync_start;
 391                         I915_WRITE(vblank_reg,
 392                                    (vblank_start - 1) |
 393                                    ((vblank_end - 1) << 16));
 394                         restore_vblank = true;
 395                 }
 396                 /* sample in the vertical border, selecting the larger one */
 397                 if (vblank_start - vactive >= vtotal - vblank_end)
 398                         vsample = (vblank_start + vactive) >> 1;
 399                 else
 400                         vsample = (vtotal + vblank_end) >> 1;
 401
 402                 /*
 403                  * Wait for the border to be displayed
 404                  */
 405                 while (I915_READ(pipe_dsl_reg) >= vactive)
 406                         ;
 407                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 408                         ;
 409                 /*
 410                  * Watch ST00 for an entire scanline
 411                  */
 412                 detect = 0;
 413                 count = 0;
 414                 do {
 415                         count++;
 416                         /* Read the ST00 VGA status register */
 417                         st00 = I915_READ8(VGA_MSR_WRITE);
 418                         if (st00 & (1 << 4))
 419                                 detect++;
 420                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 421
 422                 /* restore vblank if necessary */
 423                 if (restore_vblank)
 424                         I915_WRITE(vblank_reg, vblank);
 425                 /*
 426                  * If more than 3/4 of the scanline detected a monitor,
 427                  * then it is assumed to be present. This works even on i830,
 428                  * where there isn't any way to force the border color across
 429                  * the screen
 430                  */
 431                 status = detect * 4 > count * 3 ?
 432                          connector_status_connected :
 433                          connector_status_disconnected;
 434         }
 435
 436         /* Restore previous settings */
 437         I915_WRITE(bclrpat_reg, save_bclrpat);
 438
 439         return status;
 440 }
 441
 442 static enum drm_connector_status
 443 intel_crt_detect(struct drm_connector *connector, bool force)
 444 {
 445         struct drm_device *dev = connector->dev;
 446         struct intel_crt *crt = intel_attached_crt(connector);
 447         struct drm_crtc *crtc;
 448         int dpms_mode;
 449         enum drm_connector_status status;
 450
 451         if (I915_HAS_HOTPLUG(dev)) {
 452                 if (intel_crt_detect_hotplug(connector)) {
 453                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 454                         return connector_status_connected;
 455                 } else {
 456                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 457                         return connector_status_disconnected;
 458                 }
 459         }
 460
 461         if (intel_crt_detect_ddc(crt))
 462                 return connector_status_connected;
 463
 464         if (!force)
 465                 return connector->status;
 466
 467         /* for pre-945g platforms use load detect */
 468         crtc = crt->base.base.crtc;
 469         if (crtc && crtc->enabled) {
 470                 status = intel_crt_load_detect(crtc, crt);
 471         } else {
 472                 crtc = intel_get_load_detect_pipe(&crt->base, connector,
 473                                                   NULL, &dpms_mode);
 474                 if (crtc) {
 475                         if (intel_crt_detect_ddc(crt))
 476                                 status = connector_status_connected;
 477                         else
 478                                 status = intel_crt_load_detect(crtc, crt);
 479                         intel_release_load_detect_pipe(&crt->base,
 480                                                        connector, dpms_mode);
 481                 } else
 482                         status = connector_status_unknown;
 483         }
 484
 485         return status;
 486 }
 487
 488 static void intel_crt_destroy(struct drm_connector *connector)
 489 {
 490         drm_sysfs_connector_remove(connector);
 491         drm_connector_cleanup(connector);
 492         kfree(connector);
 493 }
 494
 495 static int intel_crt_get_modes(struct drm_connector *connector)
 496 {
 497         struct drm_device *dev = connector->dev;
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         int ret;
 500
 501         ret = intel_ddc_get_modes(connector,
 502                                  &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
 503         if (ret || !IS_G4X(dev))
 504                 return ret;
 505
 506         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 507         return intel_ddc_get_modes(connector,
 508                                    &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
 509 }
 510
 511 static int intel_crt_set_property(struct drm_connector *connector,
 512                                   struct drm_property *property,
 513                                   uint64_t value)
 514 {
 515         return 0;
 516 }
 517
 518 /*
 519  * Routines for controlling stuff on the analog port
 520  */
 521
 522 static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
 523         .dpms = intel_crt_dpms,
 524         .mode_fixup = intel_crt_mode_fixup,
 525         .prepare = intel_encoder_prepare,
 526         .commit = intel_encoder_commit,
 527         .mode_set = intel_crt_mode_set,
 528 };
 529
 530 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 531         .dpms = drm_helper_connector_dpms,
 532         .detect = intel_crt_detect,
 533         .fill_modes = drm_helper_probe_single_connector_modes,
 534         .destroy = intel_crt_destroy,
 535         .set_property = intel_crt_set_property,
 536 };
 537
 538 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 539         .mode_valid = intel_crt_mode_valid,
 540         .get_modes = intel_crt_get_modes,
 541         .best_encoder = intel_best_encoder,
 542 };
 543
 544 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 545         .destroy = intel_encoder_destroy,
 546 };
 547
 548 void intel_crt_init(struct drm_device *dev)
 549 {
 550         struct drm_connector *connector;
 551         struct intel_crt *crt;
 552         struct intel_connector *intel_connector;
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554
 555         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 556         if (!crt)
 557                 return;
 558
 559         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 560         if (!intel_connector) {
 561                 kfree(crt);
 562                 return;
 563         }
 564
 565         connector = &intel_connector->base;
 566         drm_connector_init(dev, &intel_connector->base,
 567                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 568
 569         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 570                          DRM_MODE_ENCODER_DAC);
 571
 572         intel_connector_attach_encoder(intel_connector, &crt->base);
 573
 574         crt->base.type = INTEL_OUTPUT_ANALOG;
 575         crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
 576                                 1 << INTEL_ANALOG_CLONE_BIT |
 577                                 1 << INTEL_SDVO_LVDS_CLONE_BIT);
 578         crt->base.crtc_mask = (1 << 0) | (1 << 1);
 579         connector->interlace_allowed = 1;
 580         connector->doublescan_allowed = 0;
 581
 582         drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
 583         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 584
 585         drm_sysfs_connector_add(connector);
 586
 587         if (I915_HAS_HOTPLUG(dev))
 588                 connector->polled = DRM_CONNECTOR_POLL_HPD;
 589         else
 590                 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 591
 592         /*
 593          * Configure the automatic hotplug detection stuff
 594          */
 595         crt->force_hotplug_required = 0;
 596         if (HAS_PCH_SPLIT(dev)) {
 597                 u32 adpa;
 598
 599                 adpa = I915_READ(PCH_ADPA);
 600                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 601                 adpa |= ADPA_HOTPLUG_BITS;
 602                 I915_WRITE(PCH_ADPA, adpa);
 603                 POSTING_READ(PCH_ADPA);
 604
 605                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
 606                 crt->force_hotplug_required = 1;
 607         }
 608
 609         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
 610 }