drivers/net/can/mscan/mscan.h

   1 /*
   2  * $Id$
   3  *
   4  * DESCRIPTION:
   5  *  Definitions of consts/structs to drive the Freescale MSCAN.
   6  *
   7  * AUTHOR:
   8  *  Andrey Volkov <avolkov@varma-el.com>
   9  *
  10  * COPYRIGHT:
  11  *  2004-2006, Varma Electronics Oy
  12  *
  13  * LICENCE:
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License as published by
  16  *  the Free Software Foundation; either version 2 of the License, or
  17  *  (at your option) any later version.
  18  *
  19  *  This program is distributed in the hope that it will be useful,
  20  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *  GNU General Public License for more details.
  23  *
  24  *  You should have received a copy of the GNU General Public License
  25  *  along with this program; if not, write to the Free Software
  26  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27  *
  28  */
  29
  30 #ifndef __MSCAN_H__
  31 #define __MSCAN_H__
  32
  33 #include <linux/autoconf.h>
  34 #include <linux/types.h>
  35
  36 /* MSCAN control register 0 (CANCTL0) bits */
  37 #define MSCAN_RXFRM             0x80
  38 #define MSCAN_RXACT             0x40
  39 #define MSCAN_CSWAI             0x20
  40 #define MSCAN_SYNCH             0x10
  41 #define MSCAN_TIME              0x08
  42 #define MSCAN_WUPE              0x04
  43 #define MSCAN_SLPRQ             0x02
  44 #define MSCAN_INITRQ            0x01
  45
  46 /* MSCAN control register 1 (CANCTL1) bits */
  47 #define MSCAN_CANE              0x80
  48 #define MSCAN_CLKSRC            0x40
  49 #define MSCAN_LOOPB             0x20
  50 #define MSCAN_LISTEN            0x10
  51 #define MSCAN_WUPM              0x04
  52 #define MSCAN_SLPAK             0x02
  53 #define MSCAN_INITAK            0x01
  54
  55 #ifdef  CONFIG_PPC_MPC52xx
  56 #define MSCAN_CLKSRC_BUS        0
  57 #define MSCAN_CLKSRC_XTAL       MSCAN_CLKSRC
  58 #else
  59 #define MSCAN_CLKSRC_BUS        MSCAN_CLKSRC
  60 #define MSCAN_CLKSRC_XTAL       0
  61 #endif
  62
  63 /* MSCAN receiver flag register (CANRFLG) bits */
  64 #define MSCAN_WUPIF             0x80
  65 #define MSCAN_CSCIF             0x40
  66 #define MSCAN_RSTAT1            0x20
  67 #define MSCAN_RSTAT0            0x10
  68 #define MSCAN_TSTAT1            0x08
  69 #define MSCAN_TSTAT0            0x04
  70 #define MSCAN_OVRIF             0x02
  71 #define MSCAN_RXF               0x01
  72 #define MSCAN_ERR_IF            (MSCAN_OVRIF | MSCAN_CSCIF)
  73 #define MSCAN_RSTAT_MSK         (MSCAN_RSTAT1 | MSCAN_RSTAT0)
  74 #define MSCAN_TSTAT_MSK         (MSCAN_TSTAT1 | MSCAN_TSTAT0)
  75 #define MSCAN_STAT_MSK          (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
  76
  77 #define MSCAN_STATE_BUS_OFF     (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
  78                                  MSCAN_TSTAT1 | MSCAN_TSTAT0)
  79 #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
  80 #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
  81 #define MSCAN_STATE_ACTIVE      0
  82 #define MSCAN_STATE_WARNING     1
  83 #define MSCAN_STATE_PASSIVE     2
  84 #define MSCAN_STATE_BUSOFF      3
  85
  86 /* MSCAN receiver interrupt enable register (CANRIER) bits */
  87 #define MSCAN_WUPIE             0x80
  88 #define MSCAN_CSCIE             0x40
  89 #define MSCAN_RSTATE1           0x20
  90 #define MSCAN_RSTATE0           0x10
  91 #define MSCAN_TSTATE1           0x08
  92 #define MSCAN_TSTATE0           0x04
  93 #define MSCAN_OVRIE             0x02
  94 #define MSCAN_RXFIE             0x01
  95
  96 /* MSCAN transmitter flag register (CANTFLG) bits */
  97 #define MSCAN_TXE2              0x04
  98 #define MSCAN_TXE1              0x02
  99 #define MSCAN_TXE0              0x01
 100 #define MSCAN_TXE               (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
 101
 102 /* MSCAN transmitter interrupt enable register (CANTIER) bits */
 103 #define MSCAN_TXIE2             0x04
 104 #define MSCAN_TXIE1             0x02
 105 #define MSCAN_TXIE0             0x01
 106 #define MSCAN_TXIE              (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
 107
 108 /* MSCAN transmitter message abort request (CANTARQ) bits */
 109 #define MSCAN_ABTRQ2            0x04
 110 #define MSCAN_ABTRQ1            0x02
 111 #define MSCAN_ABTRQ0            0x01
 112
 113 /* MSCAN transmitter message abort ack (CANTAAK) bits */
 114 #define MSCAN_ABTAK2            0x04
 115 #define MSCAN_ABTAK1            0x02
 116 #define MSCAN_ABTAK0            0x01
 117
 118 /* MSCAN transmit buffer selection (CANTBSEL) bits */
 119 #define MSCAN_TX2               0x04
 120 #define MSCAN_TX1               0x02
 121 #define MSCAN_TX0               0x01
 122
 123 /* MSCAN ID acceptance control register (CANIDAC) bits */
 124 #define MSCAN_IDAM1             0x20
 125 #define MSCAN_IDAM0             0x10
 126 #define MSCAN_IDHIT2            0x04
 127 #define MSCAN_IDHIT1            0x02
 128 #define MSCAN_IDHIT0            0x01
 129
 130 #define MSCAN_AF_32BIT          0x00
 131 #define MSCAN_AF_16BIT          MSCAN_IDAM0
 132 #define MSCAN_AF_8BIT           MSCAN_IDAM1
 133 #define MSCAN_AF_CLOSED         (MSCAN_IDAM0|MSCAN_IDAM1)
 134 #define MSCAN_AF_MASK           (~(MSCAN_IDAM0|MSCAN_IDAM1))
 135
 136 /* MSCAN Miscellaneous Register (CANMISC) bits */
 137 #define MSCAN_BOHOLD            0x01
 138
 139 #ifdef  CONFIG_PPC_MPC52xx
 140 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
 141 #define _MSCAN_RESERVED_DSR_SIZE        2
 142 #else
 143 #define _MSCAN_RESERVED_(n, num)
 144 #define _MSCAN_RESERVED_DSR_SIZE        0
 145 #endif
 146
 147 /* Structure of the hardware registers */
 148 struct mscan_regs {
 149         /* (see doco S12MSCANV3/D)                MPC5200    MSCAN */
 150         u8 canctl0;                             /* + 0x00     0x00 */
 151         u8 canctl1;                             /* + 0x01     0x01 */
 152         _MSCAN_RESERVED_(1, 2);                 /* + 0x02          */
 153         u8 canbtr0;                             /* + 0x04     0x02 */
 154         u8 canbtr1;                             /* + 0x05     0x03 */
 155         _MSCAN_RESERVED_(2, 2);                 /* + 0x06          */
 156         u8 canrflg;                             /* + 0x08     0x04 */
 157         u8 canrier;                             /* + 0x09     0x05 */
 158         _MSCAN_RESERVED_(3, 2);                 /* + 0x0a          */
 159         u8 cantflg;                             /* + 0x0c     0x06 */
 160         u8 cantier;                             /* + 0x0d     0x07 */
 161         _MSCAN_RESERVED_(4, 2);                 /* + 0x0e          */
 162         u8 cantarq;                             /* + 0x10     0x08 */
 163         u8 cantaak;                             /* + 0x11     0x09 */
 164         _MSCAN_RESERVED_(5, 2);                 /* + 0x12          */
 165         u8 cantbsel;                            /* + 0x14     0x0a */
 166         u8 canidac;                             /* + 0x15     0x0b */
 167         u8 reserved;                            /* + 0x16     0x0c */
 168         _MSCAN_RESERVED_(6, 5);                 /* + 0x17          */
 169 #ifndef CONFIG_PPC_MPC52xx
 170         u8 canmisc;                             /*            0x0d */
 171 #endif
 172         u8 canrxerr;                            /* + 0x1c     0x0e */
 173         u8 cantxerr;                            /* + 0x1d     0x0f */
 174         _MSCAN_RESERVED_(7, 2);                 /* + 0x1e          */
 175         u16 canidar1_0;                         /* + 0x20     0x10 */
 176         _MSCAN_RESERVED_(8, 2);                 /* + 0x22          */
 177         u16 canidar3_2;                         /* + 0x24     0x12 */
 178         _MSCAN_RESERVED_(9, 2);                 /* + 0x26          */
 179         u16 canidmr1_0;                         /* + 0x28     0x14 */
 180         _MSCAN_RESERVED_(10, 2);                /* + 0x2a          */
 181         u16 canidmr3_2;                         /* + 0x2c     0x16 */
 182         _MSCAN_RESERVED_(11, 2);                /* + 0x2e          */
 183         u16 canidar5_4;                         /* + 0x30     0x18 */
 184         _MSCAN_RESERVED_(12, 2);                /* + 0x32          */
 185         u16 canidar7_6;                         /* + 0x34     0x1a */
 186         _MSCAN_RESERVED_(13, 2);                /* + 0x36          */
 187         u16 canidmr5_4;                         /* + 0x38     0x1c */
 188         _MSCAN_RESERVED_(14, 2);                /* + 0x3a          */
 189         u16 canidmr7_6;                         /* + 0x3c     0x1e */
 190         _MSCAN_RESERVED_(15, 2);                /* + 0x3e          */
 191         struct {
 192                 u16 idr1_0;                     /* + 0x40     0x20 */
 193                  _MSCAN_RESERVED_(16, 2);       /* + 0x42          */
 194                 u16 idr3_2;                     /* + 0x44     0x22 */
 195                  _MSCAN_RESERVED_(17, 2);       /* + 0x46          */
 196                 u16 dsr1_0;                     /* + 0x48     0x24 */
 197                  _MSCAN_RESERVED_(18, 2);       /* + 0x4a          */
 198                 u16 dsr3_2;                     /* + 0x4c     0x26 */
 199                  _MSCAN_RESERVED_(19, 2);       /* + 0x4e          */
 200                 u16 dsr5_4;                     /* + 0x50     0x28 */
 201                  _MSCAN_RESERVED_(20, 2);       /* + 0x52          */
 202                 u16 dsr7_6;                     /* + 0x54     0x2a */
 203                  _MSCAN_RESERVED_(21, 2);       /* + 0x56          */
 204                 u8 dlr;                         /* + 0x58     0x2c */
 205                  u8:8;                          /* + 0x59     0x2d */
 206                  _MSCAN_RESERVED_(22, 2);       /* + 0x5a          */
 207                 u16 time;                       /* + 0x5c     0x2e */
 208         } rx;
 209          _MSCAN_RESERVED_(23, 2);               /* + 0x5e          */
 210         struct {
 211                 u16 idr1_0;                     /* + 0x60     0x30 */
 212                  _MSCAN_RESERVED_(24, 2);       /* + 0x62          */
 213                 u16 idr3_2;                     /* + 0x64     0x32 */
 214                  _MSCAN_RESERVED_(25, 2);       /* + 0x66          */
 215                 u16 dsr1_0;                     /* + 0x68     0x34 */
 216                  _MSCAN_RESERVED_(26, 2);       /* + 0x6a          */
 217                 u16 dsr3_2;                     /* + 0x6c     0x36 */
 218                  _MSCAN_RESERVED_(27, 2);       /* + 0x6e          */
 219                 u16 dsr5_4;                     /* + 0x70     0x38 */
 220                  _MSCAN_RESERVED_(28, 2);       /* + 0x72          */
 221                 u16 dsr7_6;                     /* + 0x74     0x3a */
 222                  _MSCAN_RESERVED_(29, 2);       /* + 0x76          */
 223                 u8 dlr;                         /* + 0x78     0x3c */
 224                 u8 tbpr;                        /* + 0x79     0x3d */
 225                  _MSCAN_RESERVED_(30, 2);       /* + 0x7a          */
 226                 u16 time;                       /* + 0x7c     0x3e */
 227         } tx;
 228          _MSCAN_RESERVED_(31, 2);               /* + 0x7e          */
 229 } __attribute__ ((packed));
 230
 231 #undef _MSCAN_RESERVED_
 232 #define MSCAN_REGION    sizeof(struct mscan)
 233
 234 #define MSCAN_WATCHDOG_TIMEOUT  ((500*HZ)/1000)
 235
 236 struct mscan_platform_data {
 237         u8 clock_src;           /* MSCAN_CLKSRC_BUS or MSCAN_CLKSRC_XTAL */
 238         u32 clock_frq;          /* can ref. clock, in Hz */
 239 };
 240
 241 struct net_device *alloc_mscandev(void);
 242 /* @clock_src:
 243         1 = The MSCAN clock source is the onchip Bus Clock.
 244         0 = The MSCAN clock source is the chip Oscillator Clock.
 245 */
 246 extern int register_mscandev(struct net_device *dev, int clock_src);
 247 extern void unregister_mscandev(struct net_device *dev);
 248
 249 #endif                          /* __MSCAN_H__ */