drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         /* some DCE3 boards have bad data for this entry */
 102                         if (ASIC_IS_DCE3(rdev)) {
 103                                 if ((i == 4) &&
 104                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 105                                     (gpio->sucI2cId.ucAccess == 0x94))
 106                                         gpio->sucI2cId.ucAccess = 0x14;
 107                         }
 108
 109                         if (gpio->sucI2cId.ucAccess == id) {
 110                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 111                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 112                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 113                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 114                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 115                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 116                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 117                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 118                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 119                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 120                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 121                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 122                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 123                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 124                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 125                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 126
 127                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 128                                         i2c.hw_capable = true;
 129                                 else
 130                                         i2c.hw_capable = false;
 131
 132                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 133                                         i2c.mm_i2c = true;
 134                                 else
 135                                         i2c.mm_i2c = false;
 136
 137                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 138
 139                                 if (i2c.mask_clk_reg)
 140                                         i2c.valid = true;
 141                                 break;
 142                         }
 143                 }
 144         }
 145
 146         return i2c;
 147 }
 148
 149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 150 {
 151         struct atom_context *ctx = rdev->mode_info.atom_context;
 152         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 153         struct radeon_i2c_bus_rec i2c;
 154         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 155         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 156         uint16_t data_offset, size;
 157         int i, num_indices;
 158         char stmp[32];
 159
 160         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 161
 162         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 163                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 164
 165                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 166                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 167
 168                 for (i = 0; i < num_indices; i++) {
 169                         gpio = &i2c_info->asGPIO_Info[i];
 170                         i2c.valid = false;
 171
 172                         /* some evergreen boards have bad data for this entry */
 173                         if (ASIC_IS_DCE4(rdev)) {
 174                                 if ((i == 7) &&
 175                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 176                                     (gpio->sucI2cId.ucAccess == 0)) {
 177                                         gpio->sucI2cId.ucAccess = 0x97;
 178                                         gpio->ucDataMaskShift = 8;
 179                                         gpio->ucDataEnShift = 8;
 180                                         gpio->ucDataY_Shift = 8;
 181                                         gpio->ucDataA_Shift = 8;
 182                                 }
 183                         }
 184
 185                         /* some DCE3 boards have bad data for this entry */
 186                         if (ASIC_IS_DCE3(rdev)) {
 187                                 if ((i == 4) &&
 188                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 189                                     (gpio->sucI2cId.ucAccess == 0x94))
 190                                         gpio->sucI2cId.ucAccess = 0x14;
 191                         }
 192
 193                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 194                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 195                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 196                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 197                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 198                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 199                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 200                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 201                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 202                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 203                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 204                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 205                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 206                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 207                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 208                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 209
 210                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 211                                 i2c.hw_capable = true;
 212                         else
 213                                 i2c.hw_capable = false;
 214
 215                         if (gpio->sucI2cId.ucAccess == 0xa0)
 216                                 i2c.mm_i2c = true;
 217                         else
 218                                 i2c.mm_i2c = false;
 219
 220                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 221
 222                         if (i2c.mask_clk_reg) {
 223                                 i2c.valid = true;
 224                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 225                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 226                         }
 227                 }
 228         }
 229 }
 230
 231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 232                                                         u8 id)
 233 {
 234         struct atom_context *ctx = rdev->mode_info.atom_context;
 235         struct radeon_gpio_rec gpio;
 236         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 237         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 238         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 239         u16 data_offset, size;
 240         int i, num_indices;
 241
 242         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 243         gpio.valid = false;
 244
 245         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 246                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 247
 248                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 249                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 250
 251                 for (i = 0; i < num_indices; i++) {
 252                         pin = &gpio_info->asGPIO_Pin[i];
 253                         if (id == pin->ucGPIO_ID) {
 254                                 gpio.id = pin->ucGPIO_ID;
 255                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 256                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 257                                 gpio.valid = true;
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         return gpio;
 264 }
 265
 266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 267                                                             struct radeon_gpio_rec *gpio)
 268 {
 269         struct radeon_hpd hpd;
 270         u32 reg;
 271
 272         memset(&hpd, 0, sizeof(struct radeon_hpd));
 273
 274         if (ASIC_IS_DCE4(rdev))
 275                 reg = EVERGREEN_DC_GPIO_HPD_A;
 276         else
 277                 reg = AVIVO_DC_GPIO_HPD_A;
 278
 279         hpd.gpio = *gpio;
 280         if (gpio->reg == reg) {
 281                 switch(gpio->mask) {
 282                 case (1 << 0):
 283                         hpd.hpd = RADEON_HPD_1;
 284                         break;
 285                 case (1 << 8):
 286                         hpd.hpd = RADEON_HPD_2;
 287                         break;
 288                 case (1 << 16):
 289                         hpd.hpd = RADEON_HPD_3;
 290                         break;
 291                 case (1 << 24):
 292                         hpd.hpd = RADEON_HPD_4;
 293                         break;
 294                 case (1 << 26):
 295                         hpd.hpd = RADEON_HPD_5;
 296                         break;
 297                 case (1 << 28):
 298                         hpd.hpd = RADEON_HPD_6;
 299                         break;
 300                 default:
 301                         hpd.hpd = RADEON_HPD_NONE;
 302                         break;
 303                 }
 304         } else
 305                 hpd.hpd = RADEON_HPD_NONE;
 306         return hpd;
 307 }
 308
 309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 310                                      uint32_t supported_device,
 311                                      int *connector_type,
 312                                      struct radeon_i2c_bus_rec *i2c_bus,
 313                                      uint16_t *line_mux,
 314                                      struct radeon_hpd *hpd)
 315 {
 316         struct radeon_device *rdev = dev->dev_private;
 317
 318         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 319         if ((dev->pdev->device == 0x791e) &&
 320             (dev->pdev->subsystem_vendor == 0x1043) &&
 321             (dev->pdev->subsystem_device == 0x826d)) {
 322                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 323                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 324                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 325         }
 326
 327         /* Asrock RS600 board lists the DVI port as HDMI */
 328         if ((dev->pdev->device == 0x7941) &&
 329             (dev->pdev->subsystem_vendor == 0x1849) &&
 330             (dev->pdev->subsystem_device == 0x7941)) {
 331                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 332                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 333                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 334         }
 335
 336         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 337         if ((dev->pdev->device == 0x796e) &&
 338             (dev->pdev->subsystem_vendor == 0x1462) &&
 339             (dev->pdev->subsystem_device == 0x7302)) {
 340                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 341                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 342                         return false;
 343         }
 344
 345         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 346         if ((dev->pdev->device == 0x7941) &&
 347             (dev->pdev->subsystem_vendor == 0x147b) &&
 348             (dev->pdev->subsystem_device == 0x2412)) {
 349                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 350                         return false;
 351         }
 352
 353         /* Falcon NW laptop lists vga ddc line for LVDS */
 354         if ((dev->pdev->device == 0x5653) &&
 355             (dev->pdev->subsystem_vendor == 0x1462) &&
 356             (dev->pdev->subsystem_device == 0x0291)) {
 357                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 358                         i2c_bus->valid = false;
 359                         *line_mux = 53;
 360                 }
 361         }
 362
 363         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 364         if ((dev->pdev->device == 0x7146) &&
 365             (dev->pdev->subsystem_vendor == 0x17af) &&
 366             (dev->pdev->subsystem_device == 0x2058)) {
 367                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 368                         return false;
 369         }
 370
 371         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 372         if ((dev->pdev->device == 0x7142) &&
 373             (dev->pdev->subsystem_vendor == 0x1458) &&
 374             (dev->pdev->subsystem_device == 0x2134)) {
 375                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 376                         return false;
 377         }
 378
 379
 380         /* Funky macbooks */
 381         if ((dev->pdev->device == 0x71C5) &&
 382             (dev->pdev->subsystem_vendor == 0x106b) &&
 383             (dev->pdev->subsystem_device == 0x0080)) {
 384                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 385                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 386                         return false;
 387                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 388                         *line_mux = 0x90;
 389         }
 390
 391         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 392         if ((dev->pdev->device == 0x9598) &&
 393             (dev->pdev->subsystem_vendor == 0x1043) &&
 394             (dev->pdev->subsystem_device == 0x01da)) {
 395                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 396                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 397                 }
 398         }
 399
 400         /* ASUS HD 3600 board lists the DVI port as HDMI */
 401         if ((dev->pdev->device == 0x9598) &&
 402             (dev->pdev->subsystem_vendor == 0x1043) &&
 403             (dev->pdev->subsystem_device == 0x01e4)) {
 404                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 405                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 406                 }
 407         }
 408
 409         /* ASUS HD 3450 board lists the DVI port as HDMI */
 410         if ((dev->pdev->device == 0x95C5) &&
 411             (dev->pdev->subsystem_vendor == 0x1043) &&
 412             (dev->pdev->subsystem_device == 0x01e2)) {
 413                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 414                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 415                 }
 416         }
 417
 418         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 419          * HDMI + VGA reporting as HDMI
 420          */
 421         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 422                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 423                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 424                         *line_mux = 0;
 425                 }
 426         }
 427
 428         /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
 429         if ((dev->pdev->device == 0x95c4) &&
 430             (dev->pdev->subsystem_vendor == 0x1025) &&
 431             (dev->pdev->subsystem_device == 0x013c)) {
 432                 struct radeon_gpio_rec gpio;
 433
 434                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 435                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 436                         gpio = radeon_lookup_gpio(rdev, 6);
 437                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 438                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 439                 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 440                            (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 441                         gpio = radeon_lookup_gpio(rdev, 7);
 442                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 443                 }
 444         }
 445
 446         /* XFX Pine Group device rv730 reports no VGA DDC lines
 447          * even though they are wired up to record 0x93
 448          */
 449         if ((dev->pdev->device == 0x9498) &&
 450             (dev->pdev->subsystem_vendor == 0x1682) &&
 451             (dev->pdev->subsystem_device == 0x2452)) {
 452                 struct radeon_device *rdev = dev->dev_private;
 453                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 454         }
 455         return true;
 456 }
 457
 458 const int supported_devices_connector_convert[] = {
 459         DRM_MODE_CONNECTOR_Unknown,
 460         DRM_MODE_CONNECTOR_VGA,
 461         DRM_MODE_CONNECTOR_DVII,
 462         DRM_MODE_CONNECTOR_DVID,
 463         DRM_MODE_CONNECTOR_DVIA,
 464         DRM_MODE_CONNECTOR_SVIDEO,
 465         DRM_MODE_CONNECTOR_Composite,
 466         DRM_MODE_CONNECTOR_LVDS,
 467         DRM_MODE_CONNECTOR_Unknown,
 468         DRM_MODE_CONNECTOR_Unknown,
 469         DRM_MODE_CONNECTOR_HDMIA,
 470         DRM_MODE_CONNECTOR_HDMIB,
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_Unknown,
 473         DRM_MODE_CONNECTOR_9PinDIN,
 474         DRM_MODE_CONNECTOR_DisplayPort
 475 };
 476
 477 const uint16_t supported_devices_connector_object_id_convert[] = {
 478         CONNECTOR_OBJECT_ID_NONE,
 479         CONNECTOR_OBJECT_ID_VGA,
 480         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 481         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 482         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 483         CONNECTOR_OBJECT_ID_COMPOSITE,
 484         CONNECTOR_OBJECT_ID_SVIDEO,
 485         CONNECTOR_OBJECT_ID_LVDS,
 486         CONNECTOR_OBJECT_ID_9PIN_DIN,
 487         CONNECTOR_OBJECT_ID_9PIN_DIN,
 488         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 489         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 490         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 491         CONNECTOR_OBJECT_ID_SVIDEO
 492 };
 493
 494 const int object_connector_convert[] = {
 495         DRM_MODE_CONNECTOR_Unknown,
 496         DRM_MODE_CONNECTOR_DVII,
 497         DRM_MODE_CONNECTOR_DVII,
 498         DRM_MODE_CONNECTOR_DVID,
 499         DRM_MODE_CONNECTOR_DVID,
 500         DRM_MODE_CONNECTOR_VGA,
 501         DRM_MODE_CONNECTOR_Composite,
 502         DRM_MODE_CONNECTOR_SVIDEO,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_Unknown,
 505         DRM_MODE_CONNECTOR_9PinDIN,
 506         DRM_MODE_CONNECTOR_Unknown,
 507         DRM_MODE_CONNECTOR_HDMIA,
 508         DRM_MODE_CONNECTOR_HDMIB,
 509         DRM_MODE_CONNECTOR_LVDS,
 510         DRM_MODE_CONNECTOR_9PinDIN,
 511         DRM_MODE_CONNECTOR_Unknown,
 512         DRM_MODE_CONNECTOR_Unknown,
 513         DRM_MODE_CONNECTOR_Unknown,
 514         DRM_MODE_CONNECTOR_DisplayPort,
 515         DRM_MODE_CONNECTOR_eDP,
 516         DRM_MODE_CONNECTOR_Unknown
 517 };
 518
 519 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 520 {
 521         struct radeon_device *rdev = dev->dev_private;
 522         struct radeon_mode_info *mode_info = &rdev->mode_info;
 523         struct atom_context *ctx = mode_info->atom_context;
 524         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 525         u16 size, data_offset;
 526         u8 frev, crev;
 527         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 528         ATOM_OBJECT_TABLE *router_obj;
 529         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 530         ATOM_OBJECT_HEADER *obj_header;
 531         int i, j, k, path_size, device_support;
 532         int connector_type;
 533         u16 igp_lane_info, conn_id, connector_object_id;
 534         struct radeon_i2c_bus_rec ddc_bus;
 535         struct radeon_router router;
 536         struct radeon_gpio_rec gpio;
 537         struct radeon_hpd hpd;
 538
 539         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 540                 return false;
 541
 542         if (crev < 2)
 543                 return false;
 544
 545         router.valid = false;
 546
 547         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 548         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 549             (ctx->bios + data_offset +
 550              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 551         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 552             (ctx->bios + data_offset +
 553              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 554         router_obj = (ATOM_OBJECT_TABLE *)
 555                 (ctx->bios + data_offset +
 556                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 557         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 558
 559         path_size = 0;
 560         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 561                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 562                 ATOM_DISPLAY_OBJECT_PATH *path;
 563                 addr += path_size;
 564                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 565                 path_size += le16_to_cpu(path->usSize);
 566
 567                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 568                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 569
 570                         con_obj_id =
 571                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 572                             >> OBJECT_ID_SHIFT;
 573                         con_obj_num =
 574                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 575                             >> ENUM_ID_SHIFT;
 576                         con_obj_type =
 577                             (le16_to_cpu(path->usConnObjectId) &
 578                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 579
 580                         /* TODO CV support */
 581                         if (le16_to_cpu(path->usDeviceTag) ==
 582                                 ATOM_DEVICE_CV_SUPPORT)
 583                                 continue;
 584
 585                         /* IGP chips */
 586                         if ((rdev->flags & RADEON_IS_IGP) &&
 587                             (con_obj_id ==
 588                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 589                                 uint16_t igp_offset = 0;
 590                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 591
 592                                 index =
 593                                     GetIndexIntoMasterTable(DATA,
 594                                                             IntegratedSystemInfo);
 595
 596                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 597                                                            &crev, &igp_offset)) {
 598
 599                                         if (crev >= 2) {
 600                                                 igp_obj =
 601                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 602                                                          *) (ctx->bios + igp_offset);
 603
 604                                                 if (igp_obj) {
 605                                                         uint32_t slot_config, ct;
 606
 607                                                         if (con_obj_num == 1)
 608                                                                 slot_config =
 609                                                                         igp_obj->
 610                                                                         ulDDISlot1Config;
 611                                                         else
 612                                                                 slot_config =
 613                                                                         igp_obj->
 614                                                                         ulDDISlot2Config;
 615
 616                                                         ct = (slot_config >> 16) & 0xff;
 617                                                         connector_type =
 618                                                                 object_connector_convert
 619                                                                 [ct];
 620                                                         connector_object_id = ct;
 621                                                         igp_lane_info =
 622                                                                 slot_config & 0xffff;
 623                                                 } else
 624                                                         continue;
 625                                         } else
 626                                                 continue;
 627                                 } else {
 628                                         igp_lane_info = 0;
 629                                         connector_type =
 630                                                 object_connector_convert[con_obj_id];
 631                                         connector_object_id = con_obj_id;
 632                                 }
 633                         } else {
 634                                 igp_lane_info = 0;
 635                                 connector_type =
 636                                     object_connector_convert[con_obj_id];
 637                                 connector_object_id = con_obj_id;
 638                         }
 639
 640                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 641                                 continue;
 642
 643                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 644                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 645
 646                                 grph_obj_id =
 647                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 648                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 649                                 grph_obj_num =
 650                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 651                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 652                                 grph_obj_type =
 653                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 654                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 655
 656                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 657                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 658
 659                                         radeon_add_atom_encoder(dev,
 660                                                                 encoder_obj,
 661                                                                 le16_to_cpu
 662                                                                 (path->
 663                                                                  usDeviceTag));
 664
 665                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 666                                         router.valid = false;
 667                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 668                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
 669                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 670                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 671                                                                 (ctx->bios + data_offset +
 672                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 673                                                         ATOM_I2C_RECORD *i2c_record;
 674                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 675                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 676                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 677                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 678                                                                 (ctx->bios + data_offset +
 679                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 680                                                         int enum_id;
 681
 682                                                         router.router_id = router_obj_id;
 683                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 684                                                              enum_id++) {
 685                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 686                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 687                                                                         break;
 688                                                         }
 689
 690                                                         while (record->ucRecordType > 0 &&
 691                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 692                                                                 switch (record->ucRecordType) {
 693                                                                 case ATOM_I2C_RECORD_TYPE:
 694                                                                         i2c_record =
 695                                                                                 (ATOM_I2C_RECORD *)
 696                                                                                 record;
 697                                                                         i2c_config =
 698                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 699                                                                                 &i2c_record->sucI2cId;
 700                                                                         router.i2c_info =
 701                                                                                 radeon_lookup_i2c_gpio(rdev,
 702                                                                                                        i2c_config->
 703                                                                                                        ucAccess);
 704                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 705                                                                         break;
 706                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 707                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 708                                                                                 record;
 709                                                                         router.valid = true;
 710                                                                         router.mux_type = ddc_path->ucMuxType;
 711                                                                         router.mux_control_pin = ddc_path->ucMuxControlPin;
 712                                                                         router.mux_state = ddc_path->ucMuxState[enum_id];
 713                                                                         break;
 714                                                                 }
 715                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 716                                                                         ((char *)record + record->ucRecordSize);
 717                                                         }
 718                                                 }
 719                                         }
 720                                 }
 721                         }
 722
 723                         /* look up gpio for ddc, hpd */
 724                         ddc_bus.valid = false;
 725                         hpd.hpd = RADEON_HPD_NONE;
 726                         if ((le16_to_cpu(path->usDeviceTag) &
 727                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 728                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 729                                         if (le16_to_cpu(path->usConnObjectId) ==
 730                                             le16_to_cpu(con_obj->asObjects[j].
 731                                                         usObjectID)) {
 732                                                 ATOM_COMMON_RECORD_HEADER
 733                                                     *record =
 734                                                     (ATOM_COMMON_RECORD_HEADER
 735                                                      *)
 736                                                     (ctx->bios + data_offset +
 737                                                      le16_to_cpu(con_obj->
 738                                                                  asObjects[j].
 739                                                                  usRecordOffset));
 740                                                 ATOM_I2C_RECORD *i2c_record;
 741                                                 ATOM_HPD_INT_RECORD *hpd_record;
 742                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 743
 744                                                 while (record->ucRecordType > 0
 745                                                        && record->
 746                                                        ucRecordType <=
 747                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 748                                                         switch (record->ucRecordType) {
 749                                                         case ATOM_I2C_RECORD_TYPE:
 750                                                                 i2c_record =
 751                                                                     (ATOM_I2C_RECORD *)
 752                                                                         record;
 753                                                                 i2c_config =
 754                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 755                                                                         &i2c_record->sucI2cId;
 756                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 757                                                                                                  i2c_config->
 758                                                                                                  ucAccess);
 759                                                                 break;
 760                                                         case ATOM_HPD_INT_RECORD_TYPE:
 761                                                                 hpd_record =
 762                                                                         (ATOM_HPD_INT_RECORD *)
 763                                                                         record;
 764                                                                 gpio = radeon_lookup_gpio(rdev,
 765                                                                                           hpd_record->ucHPDIntGPIOID);
 766                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 767                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 768                                                                 break;
 769                                                         }
 770                                                         record =
 771                                                             (ATOM_COMMON_RECORD_HEADER
 772                                                              *) ((char *)record
 773                                                                  +
 774                                                                  record->
 775                                                                  ucRecordSize);
 776                                                 }
 777                                                 break;
 778                                         }
 779                                 }
 780                         }
 781
 782                         /* needed for aux chan transactions */
 783                         ddc_bus.hpd = hpd.hpd;
 784
 785                         conn_id = le16_to_cpu(path->usConnObjectId);
 786
 787                         if (!radeon_atom_apply_quirks
 788                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 789                              &ddc_bus, &conn_id, &hpd))
 790                                 continue;
 791
 792                         radeon_add_atom_connector(dev,
 793                                                   conn_id,
 794                                                   le16_to_cpu(path->
 795                                                               usDeviceTag),
 796                                                   connector_type, &ddc_bus,
 797                                                   igp_lane_info,
 798                                                   connector_object_id,
 799                                                   &hpd,
 800                                                   &router);
 801
 802                 }
 803         }
 804
 805         radeon_link_encoder_connector(dev);
 806
 807         return true;
 808 }
 809
 810 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 811                                                  int connector_type,
 812                                                  uint16_t devices)
 813 {
 814         struct radeon_device *rdev = dev->dev_private;
 815
 816         if (rdev->flags & RADEON_IS_IGP) {
 817                 return supported_devices_connector_object_id_convert
 818                         [connector_type];
 819         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 820                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 821                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 822                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 823                 struct atom_context *ctx = mode_info->atom_context;
 824                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 825                 uint16_t size, data_offset;
 826                 uint8_t frev, crev;
 827                 ATOM_XTMDS_INFO *xtmds;
 828
 829                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 830                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 831
 832                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 833                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 834                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 835                                 else
 836                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 837                         } else {
 838                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 839                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 840                                 else
 841                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 842                         }
 843                 } else
 844                         return supported_devices_connector_object_id_convert
 845                                 [connector_type];
 846         } else {
 847                 return supported_devices_connector_object_id_convert
 848                         [connector_type];
 849         }
 850 }
 851
 852 struct bios_connector {
 853         bool valid;
 854         uint16_t line_mux;
 855         uint16_t devices;
 856         int connector_type;
 857         struct radeon_i2c_bus_rec ddc_bus;
 858         struct radeon_hpd hpd;
 859 };
 860
 861 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 862                                                                  drm_device
 863                                                                  *dev)
 864 {
 865         struct radeon_device *rdev = dev->dev_private;
 866         struct radeon_mode_info *mode_info = &rdev->mode_info;
 867         struct atom_context *ctx = mode_info->atom_context;
 868         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 869         uint16_t size, data_offset;
 870         uint8_t frev, crev;
 871         uint16_t device_support;
 872         uint8_t dac;
 873         union atom_supported_devices *supported_devices;
 874         int i, j, max_device;
 875         struct bios_connector *bios_connectors;
 876         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 877         struct radeon_router router;
 878
 879         router.valid = false;
 880
 881         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 882         if (!bios_connectors)
 883                 return false;
 884
 885         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 886                                     &data_offset)) {
 887                 kfree(bios_connectors);
 888                 return false;
 889         }
 890
 891         supported_devices =
 892             (union atom_supported_devices *)(ctx->bios + data_offset);
 893
 894         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 895
 896         if (frev > 1)
 897                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 898         else
 899                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 900
 901         for (i = 0; i < max_device; i++) {
 902                 ATOM_CONNECTOR_INFO_I2C ci =
 903                     supported_devices->info.asConnInfo[i];
 904
 905                 bios_connectors[i].valid = false;
 906
 907                 if (!(device_support & (1 << i))) {
 908                         continue;
 909                 }
 910
 911                 if (i == ATOM_DEVICE_CV_INDEX) {
 912                         DRM_DEBUG_KMS("Skipping Component Video\n");
 913                         continue;
 914                 }
 915
 916                 bios_connectors[i].connector_type =
 917                     supported_devices_connector_convert[ci.sucConnectorInfo.
 918                                                         sbfAccess.
 919                                                         bfConnectorType];
 920
 921                 if (bios_connectors[i].connector_type ==
 922                     DRM_MODE_CONNECTOR_Unknown)
 923                         continue;
 924
 925                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 926
 927                 bios_connectors[i].line_mux =
 928                         ci.sucI2cId.ucAccess;
 929
 930                 /* give tv unique connector ids */
 931                 if (i == ATOM_DEVICE_TV1_INDEX) {
 932                         bios_connectors[i].ddc_bus.valid = false;
 933                         bios_connectors[i].line_mux = 50;
 934                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 935                         bios_connectors[i].ddc_bus.valid = false;
 936                         bios_connectors[i].line_mux = 51;
 937                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 938                         bios_connectors[i].ddc_bus.valid = false;
 939                         bios_connectors[i].line_mux = 52;
 940                 } else
 941                         bios_connectors[i].ddc_bus =
 942                             radeon_lookup_i2c_gpio(rdev,
 943                                                    bios_connectors[i].line_mux);
 944
 945                 if ((crev > 1) && (frev > 1)) {
 946                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 947                         switch (isb) {
 948                         case 0x4:
 949                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 950                                 break;
 951                         case 0xa:
 952                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 953                                 break;
 954                         default:
 955                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 956                                 break;
 957                         }
 958                 } else {
 959                         if (i == ATOM_DEVICE_DFP1_INDEX)
 960                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 961                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 962                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 963                         else
 964                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 965                 }
 966
 967                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 968                  * shared with a DVI port, we'll pick up the DVI connector when we
 969                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 970                  */
 971                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 972                         bios_connectors[i].connector_type =
 973                             DRM_MODE_CONNECTOR_VGA;
 974
 975                 if (!radeon_atom_apply_quirks
 976                     (dev, (1 << i), &bios_connectors[i].connector_type,
 977                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 978                      &bios_connectors[i].hpd))
 979                         continue;
 980
 981                 bios_connectors[i].valid = true;
 982                 bios_connectors[i].devices = (1 << i);
 983
 984                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 985                         radeon_add_atom_encoder(dev,
 986                                                 radeon_get_encoder_enum(dev,
 987                                                                       (1 << i),
 988                                                                       dac),
 989                                                 (1 << i));
 990                 else
 991                         radeon_add_legacy_encoder(dev,
 992                                                   radeon_get_encoder_enum(dev,
 993                                                                         (1 << i),
 994                                                                         dac),
 995                                                   (1 << i));
 996         }
 997
 998         /* combine shared connectors */
 999         for (i = 0; i < max_device; i++) {
1000                 if (bios_connectors[i].valid) {
1001                         for (j = 0; j < max_device; j++) {
1002                                 if (bios_connectors[j].valid && (i != j)) {
1003                                         if (bios_connectors[i].line_mux ==
1004                                             bios_connectors[j].line_mux) {
1005                                                 /* make sure not to combine LVDS */
1006                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1007                                                         bios_connectors[i].line_mux = 53;
1008                                                         bios_connectors[i].ddc_bus.valid = false;
1009                                                         continue;
1010                                                 }
1011                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1012                                                         bios_connectors[j].line_mux = 53;
1013                                                         bios_connectors[j].ddc_bus.valid = false;
1014                                                         continue;
1015                                                 }
1016                                                 /* combine analog and digital for DVI-I */
1017                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1018                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1019                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1020                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1021                                                         bios_connectors[i].devices |=
1022                                                                 bios_connectors[j].devices;
1023                                                         bios_connectors[i].connector_type =
1024                                                                 DRM_MODE_CONNECTOR_DVII;
1025                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1026                                                                 bios_connectors[i].hpd =
1027                                                                         bios_connectors[j].hpd;
1028                                                         bios_connectors[j].valid = false;
1029                                                 }
1030                                         }
1031                                 }
1032                         }
1033                 }
1034         }
1035
1036         /* add the connectors */
1037         for (i = 0; i < max_device; i++) {
1038                 if (bios_connectors[i].valid) {
1039                         uint16_t connector_object_id =
1040                                 atombios_get_connector_object_id(dev,
1041                                                       bios_connectors[i].connector_type,
1042                                                       bios_connectors[i].devices);
1043                         radeon_add_atom_connector(dev,
1044                                                   bios_connectors[i].line_mux,
1045                                                   bios_connectors[i].devices,
1046                                                   bios_connectors[i].
1047                                                   connector_type,
1048                                                   &bios_connectors[i].ddc_bus,
1049                                                   0,
1050                                                   connector_object_id,
1051                                                   &bios_connectors[i].hpd,
1052                                                   &router);
1053                 }
1054         }
1055
1056         radeon_link_encoder_connector(dev);
1057
1058         kfree(bios_connectors);
1059         return true;
1060 }
1061
1062 union firmware_info {
1063         ATOM_FIRMWARE_INFO info;
1064         ATOM_FIRMWARE_INFO_V1_2 info_12;
1065         ATOM_FIRMWARE_INFO_V1_3 info_13;
1066         ATOM_FIRMWARE_INFO_V1_4 info_14;
1067         ATOM_FIRMWARE_INFO_V2_1 info_21;
1068 };
1069
1070 bool radeon_atom_get_clock_info(struct drm_device *dev)
1071 {
1072         struct radeon_device *rdev = dev->dev_private;
1073         struct radeon_mode_info *mode_info = &rdev->mode_info;
1074         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1075         union firmware_info *firmware_info;
1076         uint8_t frev, crev;
1077         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1078         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1079         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1080         struct radeon_pll *spll = &rdev->clock.spll;
1081         struct radeon_pll *mpll = &rdev->clock.mpll;
1082         uint16_t data_offset;
1083
1084         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1085                                    &frev, &crev, &data_offset)) {
1086                 firmware_info =
1087                         (union firmware_info *)(mode_info->atom_context->bios +
1088                                                 data_offset);
1089                 /* pixel clocks */
1090                 p1pll->reference_freq =
1091                     le16_to_cpu(firmware_info->info.usReferenceClock);
1092                 p1pll->reference_div = 0;
1093
1094                 if (crev < 2)
1095                         p1pll->pll_out_min =
1096                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1097                 else
1098                         p1pll->pll_out_min =
1099                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1100                 p1pll->pll_out_max =
1101                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1102
1103                 if (crev >= 4) {
1104                         p1pll->lcd_pll_out_min =
1105                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1106                         if (p1pll->lcd_pll_out_min == 0)
1107                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1108                         p1pll->lcd_pll_out_max =
1109                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1110                         if (p1pll->lcd_pll_out_max == 0)
1111                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1112                 } else {
1113                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1114                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1115                 }
1116
1117                 if (p1pll->pll_out_min == 0) {
1118                         if (ASIC_IS_AVIVO(rdev))
1119                                 p1pll->pll_out_min = 64800;
1120                         else
1121                                 p1pll->pll_out_min = 20000;
1122                 } else if (p1pll->pll_out_min > 64800) {
1123                         /* Limiting the pll output range is a good thing generally as
1124                          * it limits the number of possible pll combinations for a given
1125                          * frequency presumably to the ones that work best on each card.
1126                          * However, certain duallink DVI monitors seem to like
1127                          * pll combinations that would be limited by this at least on
1128                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
1129                          * family.
1130                          */
1131                         if (!radeon_new_pll)
1132                                 p1pll->pll_out_min = 64800;
1133                 }
1134
1135                 p1pll->pll_in_min =
1136                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1137                 p1pll->pll_in_max =
1138                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1139
1140                 *p2pll = *p1pll;
1141
1142                 /* system clock */
1143                 spll->reference_freq =
1144                     le16_to_cpu(firmware_info->info.usReferenceClock);
1145                 spll->reference_div = 0;
1146
1147                 spll->pll_out_min =
1148                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1149                 spll->pll_out_max =
1150                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1151
1152                 /* ??? */
1153                 if (spll->pll_out_min == 0) {
1154                         if (ASIC_IS_AVIVO(rdev))
1155                                 spll->pll_out_min = 64800;
1156                         else
1157                                 spll->pll_out_min = 20000;
1158                 }
1159
1160                 spll->pll_in_min =
1161                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1162                 spll->pll_in_max =
1163                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1164
1165                 /* memory clock */
1166                 mpll->reference_freq =
1167                     le16_to_cpu(firmware_info->info.usReferenceClock);
1168                 mpll->reference_div = 0;
1169
1170                 mpll->pll_out_min =
1171                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1172                 mpll->pll_out_max =
1173                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1174
1175                 /* ??? */
1176                 if (mpll->pll_out_min == 0) {
1177                         if (ASIC_IS_AVIVO(rdev))
1178                                 mpll->pll_out_min = 64800;
1179                         else
1180                                 mpll->pll_out_min = 20000;
1181                 }
1182
1183                 mpll->pll_in_min =
1184                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1185                 mpll->pll_in_max =
1186                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1187
1188                 rdev->clock.default_sclk =
1189                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1190                 rdev->clock.default_mclk =
1191                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1192
1193                 if (ASIC_IS_DCE4(rdev)) {
1194                         rdev->clock.default_dispclk =
1195                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1196                         if (rdev->clock.default_dispclk == 0)
1197                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1198                         rdev->clock.dp_extclk =
1199                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1200                 }
1201                 *dcpll = *p1pll;
1202
1203                 return true;
1204         }
1205
1206         return false;
1207 }
1208
1209 union igp_info {
1210         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1211         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1212 };
1213
1214 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1215 {
1216         struct radeon_mode_info *mode_info = &rdev->mode_info;
1217         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1218         union igp_info *igp_info;
1219         u8 frev, crev;
1220         u16 data_offset;
1221
1222         /* sideport is AMD only */
1223         if (rdev->family == CHIP_RS600)
1224                 return false;
1225
1226         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1227                                    &frev, &crev, &data_offset)) {
1228                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1229                                       data_offset);
1230                 switch (crev) {
1231                 case 1:
1232                         if (igp_info->info.ulBootUpMemoryClock)
1233                                 return true;
1234                         break;
1235                 case 2:
1236                         if (igp_info->info_2.ulBootUpSidePortClock)
1237                                 return true;
1238                         break;
1239                 default:
1240                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1241                         break;
1242                 }
1243         }
1244         return false;
1245 }
1246
1247 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1248                                    struct radeon_encoder_int_tmds *tmds)
1249 {
1250         struct drm_device *dev = encoder->base.dev;
1251         struct radeon_device *rdev = dev->dev_private;
1252         struct radeon_mode_info *mode_info = &rdev->mode_info;
1253         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1254         uint16_t data_offset;
1255         struct _ATOM_TMDS_INFO *tmds_info;
1256         uint8_t frev, crev;
1257         uint16_t maxfreq;
1258         int i;
1259
1260         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1261                                    &frev, &crev, &data_offset)) {
1262                 tmds_info =
1263                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1264                                                    data_offset);
1265
1266                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1267                 for (i = 0; i < 4; i++) {
1268                         tmds->tmds_pll[i].freq =
1269                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1270                         tmds->tmds_pll[i].value =
1271                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1272                         tmds->tmds_pll[i].value |=
1273                             (tmds_info->asMiscInfo[i].
1274                              ucPLL_VCO_Gain & 0x3f) << 6;
1275                         tmds->tmds_pll[i].value |=
1276                             (tmds_info->asMiscInfo[i].
1277                              ucPLL_DutyCycle & 0xf) << 12;
1278                         tmds->tmds_pll[i].value |=
1279                             (tmds_info->asMiscInfo[i].
1280                              ucPLL_VoltageSwing & 0xf) << 16;
1281
1282                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1283                                   tmds->tmds_pll[i].freq,
1284                                   tmds->tmds_pll[i].value);
1285
1286                         if (maxfreq == tmds->tmds_pll[i].freq) {
1287                                 tmds->tmds_pll[i].freq = 0xffffffff;
1288                                 break;
1289                         }
1290                 }
1291                 return true;
1292         }
1293         return false;
1294 }
1295
1296 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1297                                                           radeon_encoder
1298                                                           *encoder,
1299                                                           int id)
1300 {
1301         struct drm_device *dev = encoder->base.dev;
1302         struct radeon_device *rdev = dev->dev_private;
1303         struct radeon_mode_info *mode_info = &rdev->mode_info;
1304         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1305         uint16_t data_offset;
1306         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1307         uint8_t frev, crev;
1308         struct radeon_atom_ss *ss = NULL;
1309         int i;
1310
1311         if (id > ATOM_MAX_SS_ENTRY)
1312                 return NULL;
1313
1314         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1315                                    &frev, &crev, &data_offset)) {
1316                 ss_info =
1317                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1318
1319                 ss =
1320                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1321
1322                 if (!ss)
1323                         return NULL;
1324
1325                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1326                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1327                                 ss->percentage =
1328                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1329                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1330                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1331                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1332                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1333                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1334                                 break;
1335                         }
1336                 }
1337         }
1338         return ss;
1339 }
1340
1341 union lvds_info {
1342         struct _ATOM_LVDS_INFO info;
1343         struct _ATOM_LVDS_INFO_V12 info_12;
1344 };
1345
1346 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1347                                                               radeon_encoder
1348                                                               *encoder)
1349 {
1350         struct drm_device *dev = encoder->base.dev;
1351         struct radeon_device *rdev = dev->dev_private;
1352         struct radeon_mode_info *mode_info = &rdev->mode_info;
1353         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1354         uint16_t data_offset, misc;
1355         union lvds_info *lvds_info;
1356         uint8_t frev, crev;
1357         struct radeon_encoder_atom_dig *lvds = NULL;
1358         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1359
1360         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1361                                    &frev, &crev, &data_offset)) {
1362                 lvds_info =
1363                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1364                 lvds =
1365                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1366
1367                 if (!lvds)
1368                         return NULL;
1369
1370                 lvds->native_mode.clock =
1371                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1372                 lvds->native_mode.hdisplay =
1373                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1374                 lvds->native_mode.vdisplay =
1375                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1376                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1377                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1378                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1379                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1380                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1381                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1382                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1383                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1384                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1385                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1386                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1387                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1388                 lvds->panel_pwr_delay =
1389                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1390                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1391
1392                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1393                 if (misc & ATOM_VSYNC_POLARITY)
1394                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1395                 if (misc & ATOM_HSYNC_POLARITY)
1396                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1397                 if (misc & ATOM_COMPOSITESYNC)
1398                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1399                 if (misc & ATOM_INTERLACE)
1400                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1401                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1402                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1403
1404                 /* set crtc values */
1405                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1406
1407                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1408
1409                 if (ASIC_IS_AVIVO(rdev)) {
1410                         if (radeon_new_pll == 0)
1411                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1412                         else
1413                                 lvds->pll_algo = PLL_ALGO_NEW;
1414                 } else {
1415                         if (radeon_new_pll == 1)
1416                                 lvds->pll_algo = PLL_ALGO_NEW;
1417                         else
1418                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1419                 }
1420
1421                 encoder->native_mode = lvds->native_mode;
1422
1423                 if (encoder_enum == 2)
1424                         lvds->linkb = true;
1425                 else
1426                         lvds->linkb = false;
1427
1428         }
1429         return lvds;
1430 }
1431
1432 struct radeon_encoder_primary_dac *
1433 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1434 {
1435         struct drm_device *dev = encoder->base.dev;
1436         struct radeon_device *rdev = dev->dev_private;
1437         struct radeon_mode_info *mode_info = &rdev->mode_info;
1438         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1439         uint16_t data_offset;
1440         struct _COMPASSIONATE_DATA *dac_info;
1441         uint8_t frev, crev;
1442         uint8_t bg, dac;
1443         struct radeon_encoder_primary_dac *p_dac = NULL;
1444
1445         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1446                                    &frev, &crev, &data_offset)) {
1447                 dac_info = (struct _COMPASSIONATE_DATA *)
1448                         (mode_info->atom_context->bios + data_offset);
1449
1450                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1451
1452                 if (!p_dac)
1453                         return NULL;
1454
1455                 bg = dac_info->ucDAC1_BG_Adjustment;
1456                 dac = dac_info->ucDAC1_DAC_Adjustment;
1457                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1458
1459         }
1460         return p_dac;
1461 }
1462
1463 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1464                                 struct drm_display_mode *mode)
1465 {
1466         struct radeon_mode_info *mode_info = &rdev->mode_info;
1467         ATOM_ANALOG_TV_INFO *tv_info;
1468         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1469         ATOM_DTD_FORMAT *dtd_timings;
1470         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1471         u8 frev, crev;
1472         u16 data_offset, misc;
1473
1474         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1475                                     &frev, &crev, &data_offset))
1476                 return false;
1477
1478         switch (crev) {
1479         case 1:
1480                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1481                 if (index >= MAX_SUPPORTED_TV_TIMING)
1482                         return false;
1483
1484                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1485                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1486                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1487                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1488                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1489
1490                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1491                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1492                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1493                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1494                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1495
1496                 mode->flags = 0;
1497                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1498                 if (misc & ATOM_VSYNC_POLARITY)
1499                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1500                 if (misc & ATOM_HSYNC_POLARITY)
1501                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1502                 if (misc & ATOM_COMPOSITESYNC)
1503                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1504                 if (misc & ATOM_INTERLACE)
1505                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1506                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1507                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1508
1509                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1510
1511                 if (index == 1) {
1512                         /* PAL timings appear to have wrong values for totals */
1513                         mode->crtc_htotal -= 1;
1514                         mode->crtc_vtotal -= 1;
1515                 }
1516                 break;
1517         case 2:
1518                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1519                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1520                         return false;
1521
1522                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1523                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1524                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1525                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1526                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1527                         le16_to_cpu(dtd_timings->usHSyncOffset);
1528                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1529                         le16_to_cpu(dtd_timings->usHSyncWidth);
1530
1531                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1532                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1533                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1534                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1535                         le16_to_cpu(dtd_timings->usVSyncOffset);
1536                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1537                         le16_to_cpu(dtd_timings->usVSyncWidth);
1538
1539                 mode->flags = 0;
1540                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1541                 if (misc & ATOM_VSYNC_POLARITY)
1542                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1543                 if (misc & ATOM_HSYNC_POLARITY)
1544                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1545                 if (misc & ATOM_COMPOSITESYNC)
1546                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1547                 if (misc & ATOM_INTERLACE)
1548                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1549                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1550                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1551
1552                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1553                 break;
1554         }
1555         return true;
1556 }
1557
1558 enum radeon_tv_std
1559 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1560 {
1561         struct radeon_mode_info *mode_info = &rdev->mode_info;
1562         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1563         uint16_t data_offset;
1564         uint8_t frev, crev;
1565         struct _ATOM_ANALOG_TV_INFO *tv_info;
1566         enum radeon_tv_std tv_std = TV_STD_NTSC;
1567
1568         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1569                                    &frev, &crev, &data_offset)) {
1570
1571                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1572                         (mode_info->atom_context->bios + data_offset);
1573
1574                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1575                 case ATOM_TV_NTSC:
1576                         tv_std = TV_STD_NTSC;
1577                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1578                         break;
1579                 case ATOM_TV_NTSCJ:
1580                         tv_std = TV_STD_NTSC_J;
1581                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1582                         break;
1583                 case ATOM_TV_PAL:
1584                         tv_std = TV_STD_PAL;
1585                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1586                         break;
1587                 case ATOM_TV_PALM:
1588                         tv_std = TV_STD_PAL_M;
1589                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1590                         break;
1591                 case ATOM_TV_PALN:
1592                         tv_std = TV_STD_PAL_N;
1593                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1594                         break;
1595                 case ATOM_TV_PALCN:
1596                         tv_std = TV_STD_PAL_CN;
1597                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1598                         break;
1599                 case ATOM_TV_PAL60:
1600                         tv_std = TV_STD_PAL_60;
1601                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1602                         break;
1603                 case ATOM_TV_SECAM:
1604                         tv_std = TV_STD_SECAM;
1605                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1606                         break;
1607                 default:
1608                         tv_std = TV_STD_NTSC;
1609                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1610                         break;
1611                 }
1612         }
1613         return tv_std;
1614 }
1615
1616 struct radeon_encoder_tv_dac *
1617 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1618 {
1619         struct drm_device *dev = encoder->base.dev;
1620         struct radeon_device *rdev = dev->dev_private;
1621         struct radeon_mode_info *mode_info = &rdev->mode_info;
1622         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1623         uint16_t data_offset;
1624         struct _COMPASSIONATE_DATA *dac_info;
1625         uint8_t frev, crev;
1626         uint8_t bg, dac;
1627         struct radeon_encoder_tv_dac *tv_dac = NULL;
1628
1629         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1630                                    &frev, &crev, &data_offset)) {
1631
1632                 dac_info = (struct _COMPASSIONATE_DATA *)
1633                         (mode_info->atom_context->bios + data_offset);
1634
1635                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1636
1637                 if (!tv_dac)
1638                         return NULL;
1639
1640                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1641                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1642                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1643
1644                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1645                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1646                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1647
1648                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1649                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1650                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1651
1652                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1653         }
1654         return tv_dac;
1655 }
1656
1657 static const char *thermal_controller_names[] = {
1658         "NONE",
1659         "lm63",
1660         "adm1032",
1661         "adm1030",
1662         "max6649",
1663         "lm64",
1664         "f75375",
1665         "asc7xxx",
1666 };
1667
1668 static const char *pp_lib_thermal_controller_names[] = {
1669         "NONE",
1670         "lm63",
1671         "adm1032",
1672         "adm1030",
1673         "max6649",
1674         "lm64",
1675         "f75375",
1676         "RV6xx",
1677         "RV770",
1678         "adt7473",
1679         "External GPIO",
1680         "Evergreen",
1681         "adt7473 with internal",
1682
1683 };
1684
1685 union power_info {
1686         struct _ATOM_POWERPLAY_INFO info;
1687         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1688         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1689         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1690 };
1691
1692 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1693 {
1694         struct radeon_mode_info *mode_info = &rdev->mode_info;
1695         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1696         u16 data_offset;
1697         u8 frev, crev;
1698         u32 misc, misc2 = 0, sclk, mclk;
1699         union power_info *power_info;
1700         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1701         struct _ATOM_PPLIB_STATE *power_state;
1702         int num_modes = 0, i, j;
1703         int state_index = 0, mode_index = 0;
1704         struct radeon_i2c_bus_rec i2c_bus;
1705
1706         rdev->pm.default_power_state_index = -1;
1707
1708         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1709                                    &frev, &crev, &data_offset)) {
1710                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1711                 if (frev < 4) {
1712                         /* add the i2c bus for thermal/fan chip */
1713                         if (power_info->info.ucOverdriveThermalController > 0) {
1714                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1715                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1716                                          power_info->info.ucOverdriveControllerAddress >> 1);
1717                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1718                                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1719                                 if (rdev->pm.i2c_bus) {
1720                                         struct i2c_board_info info = { };
1721                                         const char *name = thermal_controller_names[power_info->info.
1722                                                                                     ucOverdriveThermalController];
1723                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1724                                         strlcpy(info.type, name, sizeof(info.type));
1725                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1726                                 }
1727                         }
1728                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1729                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1730                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1731                         /* last mode is usually default, array is low to high */
1732                         for (i = 0; i < num_modes; i++) {
1733                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1734                                 switch (frev) {
1735                                 case 1:
1736                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1737                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1738                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1739                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1740                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1741                                         /* skip invalid modes */
1742                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1743                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1744                                                 continue;
1745                                         rdev->pm.power_state[state_index].pcie_lanes =
1746                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1747                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1748                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1749                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1750                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1751                                                         VOLTAGE_GPIO;
1752                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1753                                                         radeon_lookup_gpio(rdev,
1754                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1755                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1756                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1757                                                                 true;
1758                                                 else
1759                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1760                                                                 false;
1761                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1762                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1763                                                         VOLTAGE_VDDC;
1764                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1765                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1766                                         }
1767                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1768                                         rdev->pm.power_state[state_index].misc = misc;
1769                                         /* order matters! */
1770                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1771                                                 rdev->pm.power_state[state_index].type =
1772                                                         POWER_STATE_TYPE_POWERSAVE;
1773                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1774                                                 rdev->pm.power_state[state_index].type =
1775                                                         POWER_STATE_TYPE_BATTERY;
1776                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1777                                                 rdev->pm.power_state[state_index].type =
1778                                                         POWER_STATE_TYPE_BATTERY;
1779                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1780                                                 rdev->pm.power_state[state_index].type =
1781                                                         POWER_STATE_TYPE_BALANCED;
1782                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1783                                                 rdev->pm.power_state[state_index].type =
1784                                                         POWER_STATE_TYPE_PERFORMANCE;
1785                                                 rdev->pm.power_state[state_index].flags &=
1786                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1787                                         }
1788                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1789                                                 rdev->pm.power_state[state_index].type =
1790                                                         POWER_STATE_TYPE_DEFAULT;
1791                                                 rdev->pm.default_power_state_index = state_index;
1792                                                 rdev->pm.power_state[state_index].default_clock_mode =
1793                                                         &rdev->pm.power_state[state_index].clock_info[0];
1794                                                 rdev->pm.power_state[state_index].flags &=
1795                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1796                                         } else if (state_index == 0) {
1797                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1798                                                         RADEON_PM_MODE_NO_DISPLAY;
1799                                         }
1800                                         state_index++;
1801                                         break;
1802                                 case 2:
1803                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1804                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1805                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1806                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1807                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1808                                         /* skip invalid modes */
1809                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1810                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1811                                                 continue;
1812                                         rdev->pm.power_state[state_index].pcie_lanes =
1813                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1814                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1815                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1816                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1817                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1818                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1819                                                         VOLTAGE_GPIO;
1820                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1821                                                         radeon_lookup_gpio(rdev,
1822                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1823                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1824                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1825                                                                 true;
1826                                                 else
1827                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1828                                                                 false;
1829                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1830                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1831                                                         VOLTAGE_VDDC;
1832                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1833                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1834                                         }
1835                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1836                                         rdev->pm.power_state[state_index].misc = misc;
1837                                         rdev->pm.power_state[state_index].misc2 = misc2;
1838                                         /* order matters! */
1839                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1840                                                 rdev->pm.power_state[state_index].type =
1841                                                         POWER_STATE_TYPE_POWERSAVE;
1842                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1843                                                 rdev->pm.power_state[state_index].type =
1844                                                         POWER_STATE_TYPE_BATTERY;
1845                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1846                                                 rdev->pm.power_state[state_index].type =
1847                                                         POWER_STATE_TYPE_BATTERY;
1848                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1849                                                 rdev->pm.power_state[state_index].type =
1850                                                         POWER_STATE_TYPE_BALANCED;
1851                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1852                                                 rdev->pm.power_state[state_index].type =
1853                                                         POWER_STATE_TYPE_PERFORMANCE;
1854                                                 rdev->pm.power_state[state_index].flags &=
1855                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1856                                         }
1857                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1858                                                 rdev->pm.power_state[state_index].type =
1859                                                         POWER_STATE_TYPE_BALANCED;
1860                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1861                                                 rdev->pm.power_state[state_index].flags &=
1862                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1863                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1864                                                 rdev->pm.power_state[state_index].type =
1865                                                         POWER_STATE_TYPE_DEFAULT;
1866                                                 rdev->pm.default_power_state_index = state_index;
1867                                                 rdev->pm.power_state[state_index].default_clock_mode =
1868                                                         &rdev->pm.power_state[state_index].clock_info[0];
1869                                                 rdev->pm.power_state[state_index].flags &=
1870                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1871                                         } else if (state_index == 0) {
1872                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1873                                                         RADEON_PM_MODE_NO_DISPLAY;
1874                                         }
1875                                         state_index++;
1876                                         break;
1877                                 case 3:
1878                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1879                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1880                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1881                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1882                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1883                                         /* skip invalid modes */
1884                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1885                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1886                                                 continue;
1887                                         rdev->pm.power_state[state_index].pcie_lanes =
1888                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1889                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1890                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1891                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1892                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1893                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1894                                                         VOLTAGE_GPIO;
1895                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1896                                                         radeon_lookup_gpio(rdev,
1897                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1898                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1899                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1900                                                                 true;
1901                                                 else
1902                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1903                                                                 false;
1904                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1905                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1906                                                         VOLTAGE_VDDC;
1907                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1908                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1909                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1910                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1911                                                                 true;
1912                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1913                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1914                                                 }
1915                                         }
1916                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1917                                         rdev->pm.power_state[state_index].misc = misc;
1918                                         rdev->pm.power_state[state_index].misc2 = misc2;
1919                                         /* order matters! */
1920                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1921                                                 rdev->pm.power_state[state_index].type =
1922                                                         POWER_STATE_TYPE_POWERSAVE;
1923                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1924                                                 rdev->pm.power_state[state_index].type =
1925                                                         POWER_STATE_TYPE_BATTERY;
1926                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1927                                                 rdev->pm.power_state[state_index].type =
1928                                                         POWER_STATE_TYPE_BATTERY;
1929                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1930                                                 rdev->pm.power_state[state_index].type =
1931                                                         POWER_STATE_TYPE_BALANCED;
1932                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1933                                                 rdev->pm.power_state[state_index].type =
1934                                                         POWER_STATE_TYPE_PERFORMANCE;
1935                                                 rdev->pm.power_state[state_index].flags &=
1936                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1937                                         }
1938                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1939                                                 rdev->pm.power_state[state_index].type =
1940                                                         POWER_STATE_TYPE_BALANCED;
1941                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1942                                                 rdev->pm.power_state[state_index].type =
1943                                                         POWER_STATE_TYPE_DEFAULT;
1944                                                 rdev->pm.default_power_state_index = state_index;
1945                                                 rdev->pm.power_state[state_index].default_clock_mode =
1946                                                         &rdev->pm.power_state[state_index].clock_info[0];
1947                                         } else if (state_index == 0) {
1948                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1949                                                         RADEON_PM_MODE_NO_DISPLAY;
1950                                         }
1951                                         state_index++;
1952                                         break;
1953                                 }
1954                         }
1955                         /* last mode is usually default */
1956                         if (rdev->pm.default_power_state_index == -1) {
1957                                 rdev->pm.power_state[state_index - 1].type =
1958                                         POWER_STATE_TYPE_DEFAULT;
1959                                 rdev->pm.default_power_state_index = state_index - 1;
1960                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
1961                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
1962                                 rdev->pm.power_state[state_index].flags &=
1963                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1964                                 rdev->pm.power_state[state_index].misc = 0;
1965                                 rdev->pm.power_state[state_index].misc2 = 0;
1966                         }
1967                 } else {
1968                         int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1969                         uint8_t fw_frev, fw_crev;
1970                         uint16_t fw_data_offset, vddc = 0;
1971                         union firmware_info *firmware_info;
1972                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1973
1974                         if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1975                                                    &fw_frev, &fw_crev, &fw_data_offset)) {
1976                                 firmware_info =
1977                                         (union firmware_info *)(mode_info->atom_context->bios +
1978                                                                 fw_data_offset);
1979                                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1980                         }
1981
1982                         /* add the i2c bus for thermal/fan chip */
1983                         if (controller->ucType > 0) {
1984                                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
1985                                         DRM_INFO("Internal thermal controller %s fan control\n",
1986                                                  (controller->ucFanParameters &
1987                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1988                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1989                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1990                                         DRM_INFO("Internal thermal controller %s fan control\n",
1991                                                  (controller->ucFanParameters &
1992                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1993                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1994                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1995                                         DRM_INFO("Internal thermal controller %s fan control\n",
1996                                                  (controller->ucFanParameters &
1997                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1998                                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
1999                                 } else if ((controller->ucType ==
2000                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2001                                            (controller->ucType ==
2002                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2003                                         DRM_INFO("Special thermal controller config\n");
2004                                 } else {
2005                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2006                                                  pp_lib_thermal_controller_names[controller->ucType],
2007                                                  controller->ucI2cAddress >> 1,
2008                                                  (controller->ucFanParameters &
2009                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2010                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2011                                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2012                                         if (rdev->pm.i2c_bus) {
2013                                                 struct i2c_board_info info = { };
2014                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2015                                                 info.addr = controller->ucI2cAddress >> 1;
2016                                                 strlcpy(info.type, name, sizeof(info.type));
2017                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2018                                         }
2019
2020                                 }
2021                         }
2022                         /* first mode is usually default, followed by low to high */
2023                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2024                                 mode_index = 0;
2025                                 power_state = (struct _ATOM_PPLIB_STATE *)
2026                                         (mode_info->atom_context->bios +
2027                                          data_offset +
2028                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2029                                          i * power_info->info_4.ucStateEntrySize);
2030                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2031                                         (mode_info->atom_context->bios +
2032                                          data_offset +
2033                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2034                                          (power_state->ucNonClockStateIndex *
2035                                           power_info->info_4.ucNonClockSize));
2036                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2037                                         if (rdev->flags & RADEON_IS_IGP) {
2038                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2039                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2040                                                         (mode_info->atom_context->bios +
2041                                                          data_offset +
2042                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2043                                                          (power_state->ucClockStateIndices[j] *
2044                                                           power_info->info_4.ucClockInfoSize));
2045                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2046                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
2047                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2048                                                 /* skip invalid modes */
2049                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2050                                                         continue;
2051                                                 /* voltage works differently on IGPs */
2052                                                 mode_index++;
2053                                         } else if (ASIC_IS_DCE4(rdev)) {
2054                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2055                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2056                                                         (mode_info->atom_context->bios +
2057                                                          data_offset +
2058                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2059                                                          (power_state->ucClockStateIndices[j] *
2060                                                           power_info->info_4.ucClockInfoSize));
2061                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2062                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2063                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2064                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2065                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2066                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2067                                                 /* skip invalid modes */
2068                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2069                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2070                                                         continue;
2071                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2072                                                         VOLTAGE_SW;
2073                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2074                                                         clock_info->usVDDC;
2075                                                 /* XXX usVDDCI */
2076                                                 mode_index++;
2077                                         } else {
2078                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2079                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2080                                                         (mode_info->atom_context->bios +
2081                                                          data_offset +
2082                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2083                                                          (power_state->ucClockStateIndices[j] *
2084                                                           power_info->info_4.ucClockInfoSize));
2085                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2086                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2087                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2088                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2089                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2090                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2091                                                 /* skip invalid modes */
2092                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2093                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2094                                                         continue;
2095                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2096                                                         VOLTAGE_SW;
2097                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2098                                                         clock_info->usVDDC;
2099                                                 mode_index++;
2100                                         }
2101                                 }
2102                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2103                                 if (mode_index) {
2104                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2105                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
2106                                         rdev->pm.power_state[state_index].misc = misc;
2107                                         rdev->pm.power_state[state_index].misc2 = misc2;
2108                                         rdev->pm.power_state[state_index].pcie_lanes =
2109                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2110                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2111                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2112                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2113                                                 rdev->pm.power_state[state_index].type =
2114                                                         POWER_STATE_TYPE_BATTERY;
2115                                                 break;
2116                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2117                                                 rdev->pm.power_state[state_index].type =
2118                                                         POWER_STATE_TYPE_BALANCED;
2119                                                 break;
2120                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2121                                                 rdev->pm.power_state[state_index].type =
2122                                                         POWER_STATE_TYPE_PERFORMANCE;
2123                                                 break;
2124                                         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2125                                                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2126                                                         rdev->pm.power_state[state_index].type =
2127                                                                 POWER_STATE_TYPE_PERFORMANCE;
2128                                                 break;
2129                                         }
2130                                         rdev->pm.power_state[state_index].flags = 0;
2131                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2132                                                 rdev->pm.power_state[state_index].flags |=
2133                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2134                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2135                                                 rdev->pm.power_state[state_index].type =
2136                                                         POWER_STATE_TYPE_DEFAULT;
2137                                                 rdev->pm.default_power_state_index = state_index;
2138                                                 rdev->pm.power_state[state_index].default_clock_mode =
2139                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2140                                                 /* patch the table values with the default slck/mclk from firmware info */
2141                                                 for (j = 0; j < mode_index; j++) {
2142                                                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2143                                                                 rdev->clock.default_mclk;
2144                                                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2145                                                                 rdev->clock.default_sclk;
2146                                                         if (vddc)
2147                                                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2148                                                                         vddc;
2149                                                 }
2150                                         }
2151                                         state_index++;
2152                                 }
2153                         }
2154                         /* if multiple clock modes, mark the lowest as no display */
2155                         for (i = 0; i < state_index; i++) {
2156                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2157                                         rdev->pm.power_state[i].clock_info[0].flags |=
2158                                                 RADEON_PM_MODE_NO_DISPLAY;
2159                         }
2160                         /* first mode is usually default */
2161                         if (rdev->pm.default_power_state_index == -1) {
2162                                 rdev->pm.power_state[0].type =
2163                                         POWER_STATE_TYPE_DEFAULT;
2164                                 rdev->pm.default_power_state_index = 0;
2165                                 rdev->pm.power_state[0].default_clock_mode =
2166                                         &rdev->pm.power_state[0].clock_info[0];
2167                         }
2168                 }
2169         } else {
2170                 /* add the default mode */
2171                 rdev->pm.power_state[state_index].type =
2172                         POWER_STATE_TYPE_DEFAULT;
2173                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2174                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2175                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2176                 rdev->pm.power_state[state_index].default_clock_mode =
2177                         &rdev->pm.power_state[state_index].clock_info[0];
2178                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2179                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2180                 rdev->pm.default_power_state_index = state_index;
2181                 rdev->pm.power_state[state_index].flags = 0;
2182                 state_index++;
2183         }
2184
2185         rdev->pm.num_power_states = state_index;
2186
2187         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2188         rdev->pm.current_clock_mode_index = 0;
2189         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2190 }
2191
2192 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2193 {
2194         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2195         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2196
2197         args.ucEnable = enable;
2198
2199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2200 }
2201
2202 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2203 {
2204         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2205         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2206
2207         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2208         return args.ulReturnEngineClock;
2209 }
2210
2211 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2212 {
2213         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2214         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2215
2216         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2217         return args.ulReturnMemoryClock;
2218 }
2219
2220 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2221                                   uint32_t eng_clock)
2222 {
2223         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2224         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2225
2226         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2227
2228         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2229 }
2230
2231 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2232                                   uint32_t mem_clock)
2233 {
2234         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2235         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2236
2237         if (rdev->flags & RADEON_IS_IGP)
2238                 return;
2239
2240         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2241
2242         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2243 }
2244
2245 union set_voltage {
2246         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2247         struct _SET_VOLTAGE_PARAMETERS v1;
2248         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2249 };
2250
2251 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2252 {
2253         union set_voltage args;
2254         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2255         u8 frev, crev, volt_index = level;
2256
2257         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2258                 return;
2259
2260         switch (crev) {
2261         case 1:
2262                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2263                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2264                 args.v1.ucVoltageIndex = volt_index;
2265                 break;
2266         case 2:
2267                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2268                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2269                 args.v2.usVoltageLevel = cpu_to_le16(level);
2270                 break;
2271         default:
2272                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2273                 return;
2274         }
2275
2276         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2277 }
2278
2279
2280
2281 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2282 {
2283         struct radeon_device *rdev = dev->dev_private;
2284         uint32_t bios_2_scratch, bios_6_scratch;
2285
2286         if (rdev->family >= CHIP_R600) {
2287                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2288                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2289         } else {
2290                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2291                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2292         }
2293
2294         /* let the bios control the backlight */
2295         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2296
2297         /* tell the bios not to handle mode switching */
2298         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2299
2300         if (rdev->family >= CHIP_R600) {
2301                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2302                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2303         } else {
2304                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2305                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2306         }
2307
2308 }
2309
2310 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2311 {
2312         uint32_t scratch_reg;
2313         int i;
2314
2315         if (rdev->family >= CHIP_R600)
2316                 scratch_reg = R600_BIOS_0_SCRATCH;
2317         else
2318                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2319
2320         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2321                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2322 }
2323
2324 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2325 {
2326         uint32_t scratch_reg;
2327         int i;
2328
2329         if (rdev->family >= CHIP_R600)
2330                 scratch_reg = R600_BIOS_0_SCRATCH;
2331         else
2332                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2333
2334         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2335                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2336 }
2337
2338 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2339 {
2340         struct drm_device *dev = encoder->dev;
2341         struct radeon_device *rdev = dev->dev_private;
2342         uint32_t bios_6_scratch;
2343
2344         if (rdev->family >= CHIP_R600)
2345                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2346         else
2347                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2348
2349         if (lock)
2350                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2351         else
2352                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2353
2354         if (rdev->family >= CHIP_R600)
2355                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2356         else
2357                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2358 }
2359
2360 /* at some point we may want to break this out into individual functions */
2361 void
2362 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2363                                        struct drm_encoder *encoder,
2364                                        bool connected)
2365 {
2366         struct drm_device *dev = connector->dev;
2367         struct radeon_device *rdev = dev->dev_private;
2368         struct radeon_connector *radeon_connector =
2369             to_radeon_connector(connector);
2370         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2371         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2372
2373         if (rdev->family >= CHIP_R600) {
2374                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2375                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2376                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2377         } else {
2378                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2379                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2380                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2381         }
2382
2383         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2384             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2385                 if (connected) {
2386                         DRM_DEBUG_KMS("TV1 connected\n");
2387                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2388                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2389                 } else {
2390                         DRM_DEBUG_KMS("TV1 disconnected\n");
2391                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2392                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2393                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2394                 }
2395         }
2396         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2397             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2398                 if (connected) {
2399                         DRM_DEBUG_KMS("CV connected\n");
2400                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2401                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2402                 } else {
2403                         DRM_DEBUG_KMS("CV disconnected\n");
2404                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2405                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2406                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2407                 }
2408         }
2409         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2410             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2411                 if (connected) {
2412                         DRM_DEBUG_KMS("LCD1 connected\n");
2413                         bios_0_scratch |= ATOM_S0_LCD1;
2414                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2415                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2416                 } else {
2417                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2418                         bios_0_scratch &= ~ATOM_S0_LCD1;
2419                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2420                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2421                 }
2422         }
2423         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2424             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2425                 if (connected) {
2426                         DRM_DEBUG_KMS("CRT1 connected\n");
2427                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2428                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2429                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2430                 } else {
2431                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2432                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2433                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2434                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2435                 }
2436         }
2437         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2438             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2439                 if (connected) {
2440                         DRM_DEBUG_KMS("CRT2 connected\n");
2441                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2442                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2443                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2444                 } else {
2445                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2446                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2447                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2448                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2449                 }
2450         }
2451         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2452             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2453                 if (connected) {
2454                         DRM_DEBUG_KMS("DFP1 connected\n");
2455                         bios_0_scratch |= ATOM_S0_DFP1;
2456                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2457                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2458                 } else {
2459                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2460                         bios_0_scratch &= ~ATOM_S0_DFP1;
2461                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2462                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2463                 }
2464         }
2465         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2466             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2467                 if (connected) {
2468                         DRM_DEBUG_KMS("DFP2 connected\n");
2469                         bios_0_scratch |= ATOM_S0_DFP2;
2470                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2471                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2472                 } else {
2473                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2474                         bios_0_scratch &= ~ATOM_S0_DFP2;
2475                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2476                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2477                 }
2478         }
2479         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2480             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2481                 if (connected) {
2482                         DRM_DEBUG_KMS("DFP3 connected\n");
2483                         bios_0_scratch |= ATOM_S0_DFP3;
2484                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2485                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2486                 } else {
2487                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2488                         bios_0_scratch &= ~ATOM_S0_DFP3;
2489                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2490                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2491                 }
2492         }
2493         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2494             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2495                 if (connected) {
2496                         DRM_DEBUG_KMS("DFP4 connected\n");
2497                         bios_0_scratch |= ATOM_S0_DFP4;
2498                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2499                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2500                 } else {
2501                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2502                         bios_0_scratch &= ~ATOM_S0_DFP4;
2503                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2504                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2505                 }
2506         }
2507         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2508             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2509                 if (connected) {
2510                         DRM_DEBUG_KMS("DFP5 connected\n");
2511                         bios_0_scratch |= ATOM_S0_DFP5;
2512                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2513                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2514                 } else {
2515                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2516                         bios_0_scratch &= ~ATOM_S0_DFP5;
2517                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2518                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2519                 }
2520         }
2521
2522         if (rdev->family >= CHIP_R600) {
2523                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2524                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2525                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2526         } else {
2527                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2528                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2529                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2530         }
2531 }
2532
2533 void
2534 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2535 {
2536         struct drm_device *dev = encoder->dev;
2537         struct radeon_device *rdev = dev->dev_private;
2538         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2539         uint32_t bios_3_scratch;
2540
2541         if (rdev->family >= CHIP_R600)
2542                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2543         else
2544                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2545
2546         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2547                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2548                 bios_3_scratch |= (crtc << 18);
2549         }
2550         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2551                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2552                 bios_3_scratch |= (crtc << 24);
2553         }
2554         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2555                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2556                 bios_3_scratch |= (crtc << 16);
2557         }
2558         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2559                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2560                 bios_3_scratch |= (crtc << 20);
2561         }
2562         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2563                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2564                 bios_3_scratch |= (crtc << 17);
2565         }
2566         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2567                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2568                 bios_3_scratch |= (crtc << 19);
2569         }
2570         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2571                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2572                 bios_3_scratch |= (crtc << 23);
2573         }
2574         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2575                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2576                 bios_3_scratch |= (crtc << 25);
2577         }
2578
2579         if (rdev->family >= CHIP_R600)
2580                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2581         else
2582                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2583 }
2584
2585 void
2586 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2587 {
2588         struct drm_device *dev = encoder->dev;
2589         struct radeon_device *rdev = dev->dev_private;
2590         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2591         uint32_t bios_2_scratch;
2592
2593         if (rdev->family >= CHIP_R600)
2594                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2595         else
2596                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2597
2598         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2599                 if (on)
2600                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2601                 else
2602                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2603         }
2604         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2605                 if (on)
2606                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2607                 else
2608                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2609         }
2610         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2611                 if (on)
2612                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2613                 else
2614                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2615         }
2616         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2617                 if (on)
2618                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2619                 else
2620                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2621         }
2622         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2623                 if (on)
2624                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2625                 else
2626                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2627         }
2628         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2629                 if (on)
2630                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2631                 else
2632                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2633         }
2634         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2635                 if (on)
2636                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2637                 else
2638                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2639         }
2640         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2641                 if (on)
2642                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2643                 else
2644                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2645         }
2646         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2647                 if (on)
2648                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2649                 else
2650                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2651         }
2652         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2653                 if (on)
2654                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2655                 else
2656                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2657         }
2658
2659         if (rdev->family >= CHIP_R600)
2660                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2661         else
2662                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2663 }