drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <asm/dmaengine.h>
  28 #include "shdma.h"
  29
  30 /* DMA descriptor control */
  31 enum sh_dmae_desc_status {
  32         DESC_IDLE,
  33         DESC_PREPARED,
  34         DESC_SUBMITTED,
  35         DESC_COMPLETED, /* completed, have to call callback */
  36         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  37 };
  38
  39 #define NR_DESCS_PER_CHANNEL 32
  40 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  41 #define LOG2_DEFAULT_XFER_SIZE  2
  42
  43 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  44 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
  45
  46 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  47
  48 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  49 {
  50         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  51 }
  52
  53 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  54 {
  55         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  56 }
  57
  58 static u16 dmaor_read(struct sh_dmae_device *shdev)
  59 {
  60         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
  61 }
  62
  63 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  64 {
  65         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
  66 }
  67
  68 /*
  69  * Reset DMA controller
  70  *
  71  * SH7780 has two DMAOR register
  72  */
  73 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
  74 {
  75         unsigned short dmaor = dmaor_read(shdev);
  76
  77         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
  78 }
  79
  80 static int sh_dmae_rst(struct sh_dmae_device *shdev)
  81 {
  82         unsigned short dmaor;
  83
  84         sh_dmae_ctl_stop(shdev);
  85         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
  86
  87         dmaor_write(shdev, dmaor);
  88         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
  89                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
  90                 return -EINVAL;
  91         }
  92         return 0;
  93 }
  94
  95 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
  96 {
  97         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
  98
  99         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 100                 return true; /* working */
 101
 102         return false; /* waiting */
 103 }
 104
 105 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 106 {
 107         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 108                                                 struct sh_dmae_device, common);
 109         struct sh_dmae_pdata *pdata = shdev->pdata;
 110         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 111                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 112
 113         if (cnt >= pdata->ts_shift_num)
 114                 cnt = 0;
 115
 116         return pdata->ts_shift[cnt];
 117 }
 118
 119 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 120 {
 121         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 122                                                 struct sh_dmae_device, common);
 123         struct sh_dmae_pdata *pdata = shdev->pdata;
 124         int i;
 125
 126         for (i = 0; i < pdata->ts_shift_num; i++)
 127                 if (pdata->ts_shift[i] == l2size)
 128                         break;
 129
 130         if (i == pdata->ts_shift_num)
 131                 i = 0;
 132
 133         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 134                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 135 }
 136
 137 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 138 {
 139         sh_dmae_writel(sh_chan, hw->sar, SAR);
 140         sh_dmae_writel(sh_chan, hw->dar, DAR);
 141         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 142 }
 143
 144 static void dmae_start(struct sh_dmae_chan *sh_chan)
 145 {
 146         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 147
 148         chcr |= CHCR_DE | CHCR_IE;
 149         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
 150 }
 151
 152 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 153 {
 154         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 155
 156         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 157         sh_dmae_writel(sh_chan, chcr, CHCR);
 158 }
 159
 160 static void dmae_init(struct sh_dmae_chan *sh_chan)
 161 {
 162         /*
 163          * Default configuration for dual address memory-memory transfer.
 164          * 0x400 represents auto-request.
 165          */
 166         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 167                                                    LOG2_DEFAULT_XFER_SIZE);
 168         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 169         sh_dmae_writel(sh_chan, chcr, CHCR);
 170 }
 171
 172 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 173 {
 174         /* When DMA was working, can not set data to CHCR */
 175         if (dmae_is_busy(sh_chan))
 176                 return -EBUSY;
 177
 178         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 179         sh_dmae_writel(sh_chan, val, CHCR);
 180
 181         return 0;
 182 }
 183
 184 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 185 {
 186         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 187                                                 struct sh_dmae_device, common);
 188         struct sh_dmae_pdata *pdata = shdev->pdata;
 189         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 190         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
 191         int shift = chan_pdata->dmars_bit;
 192
 193         if (dmae_is_busy(sh_chan))
 194                 return -EBUSY;
 195
 196         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 197                      addr);
 198
 199         return 0;
 200 }
 201
 202 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 203 {
 204         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 205         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 206         dma_async_tx_callback callback = tx->callback;
 207         dma_cookie_t cookie;
 208
 209         spin_lock_bh(&sh_chan->desc_lock);
 210
 211         cookie = sh_chan->common.cookie;
 212         cookie++;
 213         if (cookie < 0)
 214                 cookie = 1;
 215
 216         sh_chan->common.cookie = cookie;
 217         tx->cookie = cookie;
 218
 219         /* Mark all chunks of this descriptor as submitted, move to the queue */
 220         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 221                 /*
 222                  * All chunks are on the global ld_free, so, we have to find
 223                  * the end of the chain ourselves
 224                  */
 225                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 226                                       chunk->async_tx.cookie > 0 ||
 227                                       chunk->async_tx.cookie == -EBUSY ||
 228                                       &chunk->node == &sh_chan->ld_free))
 229                         break;
 230                 chunk->mark = DESC_SUBMITTED;
 231                 /* Callback goes to the last chunk */
 232                 chunk->async_tx.callback = NULL;
 233                 chunk->cookie = cookie;
 234                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 235                 last = chunk;
 236         }
 237
 238         last->async_tx.callback = callback;
 239         last->async_tx.callback_param = tx->callback_param;
 240
 241         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 242                 tx->cookie, &last->async_tx, sh_chan->id,
 243                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 244
 245         spin_unlock_bh(&sh_chan->desc_lock);
 246
 247         return cookie;
 248 }
 249
 250 /* Called with desc_lock held */
 251 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 252 {
 253         struct sh_desc *desc;
 254
 255         list_for_each_entry(desc, &sh_chan->ld_free, node)
 256                 if (desc->mark != DESC_PREPARED) {
 257                         BUG_ON(desc->mark != DESC_IDLE);
 258                         list_del(&desc->node);
 259                         return desc;
 260                 }
 261
 262         return NULL;
 263 }
 264
 265 static struct sh_dmae_slave_config *sh_dmae_find_slave(
 266         struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
 267 {
 268         struct dma_device *dma_dev = sh_chan->common.device;
 269         struct sh_dmae_device *shdev = container_of(dma_dev,
 270                                         struct sh_dmae_device, common);
 271         struct sh_dmae_pdata *pdata = shdev->pdata;
 272         int i;
 273
 274         if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
 275                 return NULL;
 276
 277         for (i = 0; i < pdata->slave_num; i++)
 278                 if (pdata->slave[i].slave_id == slave_id)
 279                         return pdata->slave + i;
 280
 281         return NULL;
 282 }
 283
 284 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 285 {
 286         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 287         struct sh_desc *desc;
 288         struct sh_dmae_slave *param = chan->private;
 289
 290         /*
 291          * This relies on the guarantee from dmaengine that alloc_chan_resources
 292          * never runs concurrently with itself or free_chan_resources.
 293          */
 294         if (param) {
 295                 struct sh_dmae_slave_config *cfg;
 296
 297                 cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
 298                 if (!cfg)
 299                         return -EINVAL;
 300
 301                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
 302                         return -EBUSY;
 303
 304                 param->config = cfg;
 305
 306                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 307                 dmae_set_chcr(sh_chan, cfg->chcr);
 308         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
 309                 dmae_init(sh_chan);
 310         }
 311
 312         spin_lock_bh(&sh_chan->desc_lock);
 313         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 314                 spin_unlock_bh(&sh_chan->desc_lock);
 315                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 316                 if (!desc) {
 317                         spin_lock_bh(&sh_chan->desc_lock);
 318                         break;
 319                 }
 320                 dma_async_tx_descriptor_init(&desc->async_tx,
 321                                         &sh_chan->common);
 322                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 323                 desc->mark = DESC_IDLE;
 324
 325                 spin_lock_bh(&sh_chan->desc_lock);
 326                 list_add(&desc->node, &sh_chan->ld_free);
 327                 sh_chan->descs_allocated++;
 328         }
 329         spin_unlock_bh(&sh_chan->desc_lock);
 330
 331         return sh_chan->descs_allocated;
 332 }
 333
 334 /*
 335  * sh_dma_free_chan_resources - Free all resources of the channel.
 336  */
 337 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 338 {
 339         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 340         struct sh_desc *desc, *_desc;
 341         LIST_HEAD(list);
 342
 343         dmae_halt(sh_chan);
 344
 345         /* Prepared and not submitted descriptors can still be on the queue */
 346         if (!list_empty(&sh_chan->ld_queue))
 347                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 348
 349         if (chan->private) {
 350                 /* The caller is holding dma_list_mutex */
 351                 struct sh_dmae_slave *param = chan->private;
 352                 clear_bit(param->slave_id, sh_dmae_slave_used);
 353         }
 354
 355         spin_lock_bh(&sh_chan->desc_lock);
 356
 357         list_splice_init(&sh_chan->ld_free, &list);
 358         sh_chan->descs_allocated = 0;
 359
 360         spin_unlock_bh(&sh_chan->desc_lock);
 361
 362         list_for_each_entry_safe(desc, _desc, &list, node)
 363                 kfree(desc);
 364 }
 365
 366 /**
 367  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 368  * @sh_chan:    DMA channel
 369  * @flags:      DMA transfer flags
 370  * @dest:       destination DMA address, incremented when direction equals
 371  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
 372  * @src:        source DMA address, incremented when direction equals
 373  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
 374  * @len:        DMA transfer length
 375  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 376  * @direction:  needed for slave DMA to decide which address to keep constant,
 377  *              equals DMA_BIDIRECTIONAL for MEMCPY
 378  * Returns 0 or an error
 379  * Locks: called with desc_lock held
 380  */
 381 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 382         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 383         struct sh_desc **first, enum dma_data_direction direction)
 384 {
 385         struct sh_desc *new;
 386         size_t copy_size;
 387
 388         if (!*len)
 389                 return NULL;
 390
 391         /* Allocate the link descriptor from the free list */
 392         new = sh_dmae_get_desc(sh_chan);
 393         if (!new) {
 394                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 395                 return NULL;
 396         }
 397
 398         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 399
 400         new->hw.sar = *src;
 401         new->hw.dar = *dest;
 402         new->hw.tcr = copy_size;
 403
 404         if (!*first) {
 405                 /* First desc */
 406                 new->async_tx.cookie = -EBUSY;
 407                 *first = new;
 408         } else {
 409                 /* Other desc - invisible to the user */
 410                 new->async_tx.cookie = -EINVAL;
 411         }
 412
 413         dev_dbg(sh_chan->dev,
 414                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 415                 copy_size, *len, *src, *dest, &new->async_tx,
 416                 new->async_tx.cookie, sh_chan->xmit_shift);
 417
 418         new->mark = DESC_PREPARED;
 419         new->async_tx.flags = flags;
 420         new->direction = direction;
 421
 422         *len -= copy_size;
 423         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
 424                 *src += copy_size;
 425         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
 426                 *dest += copy_size;
 427
 428         return new;
 429 }
 430
 431 /*
 432  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 433  *
 434  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 435  * converted to scatter-gather to guarantee consistent locking and a correct
 436  * list manipulation. For slave DMA direction carries the usual meaning, and,
 437  * logically, the SG list is RAM and the addr variable contains slave address,
 438  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
 439  * and the SG list contains only one element and points at the source buffer.
 440  */
 441 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 442         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 443         enum dma_data_direction direction, unsigned long flags)
 444 {
 445         struct scatterlist *sg;
 446         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 447         LIST_HEAD(tx_list);
 448         int chunks = 0;
 449         int i;
 450
 451         if (!sg_len)
 452                 return NULL;
 453
 454         for_each_sg(sgl, sg, sg_len, i)
 455                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 456                         (SH_DMA_TCR_MAX + 1);
 457
 458         /* Have to lock the whole loop to protect against concurrent release */
 459         spin_lock_bh(&sh_chan->desc_lock);
 460
 461         /*
 462          * Chaining:
 463          * first descriptor is what user is dealing with in all API calls, its
 464          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 465          *      number
 466          * if more than one chunk is needed further chunks have cookie = -EINVAL
 467          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 468          * all chunks are linked onto the tx_list head with their .node heads
 469          *      only during this function, then they are immediately spliced
 470          *      back onto the free list in form of a chain
 471          */
 472         for_each_sg(sgl, sg, sg_len, i) {
 473                 dma_addr_t sg_addr = sg_dma_address(sg);
 474                 size_t len = sg_dma_len(sg);
 475
 476                 if (!len)
 477                         goto err_get_desc;
 478
 479                 do {
 480                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 481                                 i, sg, len, (unsigned long long)sg_addr);
 482
 483                         if (direction == DMA_FROM_DEVICE)
 484                                 new = sh_dmae_add_desc(sh_chan, flags,
 485                                                 &sg_addr, addr, &len, &first,
 486                                                 direction);
 487                         else
 488                                 new = sh_dmae_add_desc(sh_chan, flags,
 489                                                 addr, &sg_addr, &len, &first,
 490                                                 direction);
 491                         if (!new)
 492                                 goto err_get_desc;
 493
 494                         new->chunks = chunks--;
 495                         list_add_tail(&new->node, &tx_list);
 496                 } while (len);
 497         }
 498
 499         if (new != first)
 500                 new->async_tx.cookie = -ENOSPC;
 501
 502         /* Put them back on the free list, so, they don't get lost */
 503         list_splice_tail(&tx_list, &sh_chan->ld_free);
 504
 505         spin_unlock_bh(&sh_chan->desc_lock);
 506
 507         return &first->async_tx;
 508
 509 err_get_desc:
 510         list_for_each_entry(new, &tx_list, node)
 511                 new->mark = DESC_IDLE;
 512         list_splice(&tx_list, &sh_chan->ld_free);
 513
 514         spin_unlock_bh(&sh_chan->desc_lock);
 515
 516         return NULL;
 517 }
 518
 519 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 520         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 521         size_t len, unsigned long flags)
 522 {
 523         struct sh_dmae_chan *sh_chan;
 524         struct scatterlist sg;
 525
 526         if (!chan || !len)
 527                 return NULL;
 528
 529         chan->private = NULL;
 530
 531         sh_chan = to_sh_chan(chan);
 532
 533         sg_init_table(&sg, 1);
 534         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 535                     offset_in_page(dma_src));
 536         sg_dma_address(&sg) = dma_src;
 537         sg_dma_len(&sg) = len;
 538
 539         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
 540                                flags);
 541 }
 542
 543 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 544         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 545         enum dma_data_direction direction, unsigned long flags)
 546 {
 547         struct sh_dmae_slave *param;
 548         struct sh_dmae_chan *sh_chan;
 549
 550         if (!chan)
 551                 return NULL;
 552
 553         sh_chan = to_sh_chan(chan);
 554         param = chan->private;
 555
 556         /* Someone calling slave DMA on a public channel? */
 557         if (!param || !sg_len) {
 558                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 559                          __func__, param, sg_len, param ? param->slave_id : -1);
 560                 return NULL;
 561         }
 562
 563         /*
 564          * if (param != NULL), this is a successfully requested slave channel,
 565          * therefore param->config != NULL too.
 566          */
 567         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
 568                                direction, flags);
 569 }
 570
 571 static void sh_dmae_terminate_all(struct dma_chan *chan)
 572 {
 573         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 574
 575         if (!chan)
 576                 return;
 577
 578         sh_dmae_chan_ld_cleanup(sh_chan, true);
 579 }
 580
 581 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 582 {
 583         struct sh_desc *desc, *_desc;
 584         /* Is the "exposed" head of a chain acked? */
 585         bool head_acked = false;
 586         dma_cookie_t cookie = 0;
 587         dma_async_tx_callback callback = NULL;
 588         void *param = NULL;
 589
 590         spin_lock_bh(&sh_chan->desc_lock);
 591         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 592                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 593
 594                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 595                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 596                        desc->mark != DESC_COMPLETED &&
 597                        desc->mark != DESC_WAITING);
 598
 599                 /*
 600                  * queue is ordered, and we use this loop to (1) clean up all
 601                  * completed descriptors, and to (2) update descriptor flags of
 602                  * any chunks in a (partially) completed chain
 603                  */
 604                 if (!all && desc->mark == DESC_SUBMITTED &&
 605                     desc->cookie != cookie)
 606                         break;
 607
 608                 if (tx->cookie > 0)
 609                         cookie = tx->cookie;
 610
 611                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 612                         if (sh_chan->completed_cookie != desc->cookie - 1)
 613                                 dev_dbg(sh_chan->dev,
 614                                         "Completing cookie %d, expected %d\n",
 615                                         desc->cookie,
 616                                         sh_chan->completed_cookie + 1);
 617                         sh_chan->completed_cookie = desc->cookie;
 618                 }
 619
 620                 /* Call callback on the last chunk */
 621                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 622                         desc->mark = DESC_WAITING;
 623                         callback = tx->callback;
 624                         param = tx->callback_param;
 625                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 626                                 tx->cookie, tx, sh_chan->id);
 627                         BUG_ON(desc->chunks != 1);
 628                         break;
 629                 }
 630
 631                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 632                         if (desc->mark == DESC_COMPLETED) {
 633                                 BUG_ON(tx->cookie < 0);
 634                                 desc->mark = DESC_WAITING;
 635                         }
 636                         head_acked = async_tx_test_ack(tx);
 637                 } else {
 638                         switch (desc->mark) {
 639                         case DESC_COMPLETED:
 640                                 desc->mark = DESC_WAITING;
 641                                 /* Fall through */
 642                         case DESC_WAITING:
 643                                 if (head_acked)
 644                                         async_tx_ack(&desc->async_tx);
 645                         }
 646                 }
 647
 648                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 649                         tx, tx->cookie);
 650
 651                 if (((desc->mark == DESC_COMPLETED ||
 652                       desc->mark == DESC_WAITING) &&
 653                      async_tx_test_ack(&desc->async_tx)) || all) {
 654                         /* Remove from ld_queue list */
 655                         desc->mark = DESC_IDLE;
 656                         list_move(&desc->node, &sh_chan->ld_free);
 657                 }
 658         }
 659         spin_unlock_bh(&sh_chan->desc_lock);
 660
 661         if (callback)
 662                 callback(param);
 663
 664         return callback;
 665 }
 666
 667 /*
 668  * sh_chan_ld_cleanup - Clean up link descriptors
 669  *
 670  * This function cleans up the ld_queue of DMA channel.
 671  */
 672 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 673 {
 674         while (__ld_cleanup(sh_chan, all))
 675                 ;
 676 }
 677
 678 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 679 {
 680         struct sh_desc *desc;
 681
 682         spin_lock_bh(&sh_chan->desc_lock);
 683         /* DMA work check */
 684         if (dmae_is_busy(sh_chan)) {
 685                 spin_unlock_bh(&sh_chan->desc_lock);
 686                 return;
 687         }
 688
 689         /* Find the first not transferred desciptor */
 690         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 691                 if (desc->mark == DESC_SUBMITTED) {
 692                         /* Get the ld start address from ld_queue */
 693                         dmae_set_reg(sh_chan, &desc->hw);
 694                         dmae_start(sh_chan);
 695                         break;
 696                 }
 697
 698         spin_unlock_bh(&sh_chan->desc_lock);
 699 }
 700
 701 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 702 {
 703         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 704         sh_chan_xfer_ld_queue(sh_chan);
 705 }
 706
 707 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
 708                                         dma_cookie_t cookie,
 709                                         dma_cookie_t *done,
 710                                         dma_cookie_t *used)
 711 {
 712         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 713         dma_cookie_t last_used;
 714         dma_cookie_t last_complete;
 715         enum dma_status status;
 716
 717         sh_dmae_chan_ld_cleanup(sh_chan, false);
 718
 719         last_used = chan->cookie;
 720         last_complete = sh_chan->completed_cookie;
 721         BUG_ON(last_complete < 0);
 722
 723         if (done)
 724                 *done = last_complete;
 725
 726         if (used)
 727                 *used = last_used;
 728
 729         spin_lock_bh(&sh_chan->desc_lock);
 730
 731         status = dma_async_is_complete(cookie, last_complete, last_used);
 732
 733         /*
 734          * If we don't find cookie on the queue, it has been aborted and we have
 735          * to report error
 736          */
 737         if (status != DMA_SUCCESS) {
 738                 struct sh_desc *desc;
 739                 status = DMA_ERROR;
 740                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 741                         if (desc->cookie == cookie) {
 742                                 status = DMA_IN_PROGRESS;
 743                                 break;
 744                         }
 745         }
 746
 747         spin_unlock_bh(&sh_chan->desc_lock);
 748
 749         return status;
 750 }
 751
 752 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 753 {
 754         irqreturn_t ret = IRQ_NONE;
 755         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 756         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 757
 758         if (chcr & CHCR_TE) {
 759                 /* DMA stop */
 760                 dmae_halt(sh_chan);
 761
 762                 ret = IRQ_HANDLED;
 763                 tasklet_schedule(&sh_chan->tasklet);
 764         }
 765
 766         return ret;
 767 }
 768
 769 #if defined(CONFIG_CPU_SH4)
 770 static irqreturn_t sh_dmae_err(int irq, void *data)
 771 {
 772         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
 773         int i;
 774
 775         /* halt the dma controller */
 776         sh_dmae_ctl_stop(shdev);
 777
 778         /* We cannot detect, which channel caused the error, have to reset all */
 779         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 780                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 781                 if (sh_chan) {
 782                         struct sh_desc *desc;
 783                         /* Stop the channel */
 784                         dmae_halt(sh_chan);
 785                         /* Complete all  */
 786                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 787                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 788                                 desc->mark = DESC_IDLE;
 789                                 if (tx->callback)
 790                                         tx->callback(tx->callback_param);
 791                         }
 792                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
 793                 }
 794         }
 795         sh_dmae_rst(shdev);
 796
 797         return IRQ_HANDLED;
 798 }
 799 #endif
 800
 801 static void dmae_do_tasklet(unsigned long data)
 802 {
 803         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 804         struct sh_desc *desc;
 805         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 806         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 807
 808         spin_lock(&sh_chan->desc_lock);
 809         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 810                 if (desc->mark == DESC_SUBMITTED &&
 811                     ((desc->direction == DMA_FROM_DEVICE &&
 812                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
 813                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
 814                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
 815                                 desc->async_tx.cookie, &desc->async_tx,
 816                                 desc->hw.dar);
 817                         desc->mark = DESC_COMPLETED;
 818                         break;
 819                 }
 820         }
 821         spin_unlock(&sh_chan->desc_lock);
 822
 823         /* Next desc */
 824         sh_chan_xfer_ld_queue(sh_chan);
 825         sh_dmae_chan_ld_cleanup(sh_chan, false);
 826 }
 827
 828 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 829                                         int irq, unsigned long flags)
 830 {
 831         int err;
 832         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 833         struct platform_device *pdev = to_platform_device(shdev->common.dev);
 834         struct sh_dmae_chan *new_sh_chan;
 835
 836         /* alloc channel */
 837         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
 838         if (!new_sh_chan) {
 839                 dev_err(shdev->common.dev,
 840                         "No free memory for allocating dma channels!\n");
 841                 return -ENOMEM;
 842         }
 843
 844         /* copy struct dma_device */
 845         new_sh_chan->common.device = &shdev->common;
 846
 847         new_sh_chan->dev = shdev->common.dev;
 848         new_sh_chan->id = id;
 849         new_sh_chan->irq = irq;
 850         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
 851
 852         /* Init DMA tasklet */
 853         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
 854                         (unsigned long)new_sh_chan);
 855
 856         /* Init the channel */
 857         dmae_init(new_sh_chan);
 858
 859         spin_lock_init(&new_sh_chan->desc_lock);
 860
 861         /* Init descripter manage list */
 862         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
 863         INIT_LIST_HEAD(&new_sh_chan->ld_free);
 864
 865         /* Add the channel to DMA device channel list */
 866         list_add_tail(&new_sh_chan->common.device_node,
 867                         &shdev->common.channels);
 868         shdev->common.chancnt++;
 869
 870         if (pdev->id >= 0)
 871                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 872                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
 873         else
 874                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 875                          "sh-dma%d", new_sh_chan->id);
 876
 877         /* set up channel irq */
 878         err = request_irq(irq, &sh_dmae_interrupt, flags,
 879                           new_sh_chan->dev_id, new_sh_chan);
 880         if (err) {
 881                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
 882                         "with return %d\n", id, err);
 883                 goto err_no_irq;
 884         }
 885
 886         shdev->chan[id] = new_sh_chan;
 887         return 0;
 888
 889 err_no_irq:
 890         /* remove from dmaengine device node */
 891         list_del(&new_sh_chan->common.device_node);
 892         kfree(new_sh_chan);
 893         return err;
 894 }
 895
 896 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 897 {
 898         int i;
 899
 900         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
 901                 if (shdev->chan[i]) {
 902                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 903
 904                         free_irq(sh_chan->irq, sh_chan);
 905
 906                         list_del(&sh_chan->common.device_node);
 907                         kfree(sh_chan);
 908                         shdev->chan[i] = NULL;
 909                 }
 910         }
 911         shdev->common.chancnt = 0;
 912 }
 913
 914 static int __init sh_dmae_probe(struct platform_device *pdev)
 915 {
 916         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
 917         unsigned long irqflags = IRQF_DISABLED,
 918                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
 919         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
 920         int err, i, irq_cnt = 0, irqres = 0;
 921         struct sh_dmae_device *shdev;
 922         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 923
 924         /* get platform data */
 925         if (!pdata || !pdata->channel_num)
 926                 return -ENODEV;
 927
 928         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 929         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
 930         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 931         /*
 932          * IRQ resources:
 933          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 934          *    the error IRQ, in which case it is the only IRQ in this resource:
 935          *    start == end. If it is the only IRQ resource, all channels also
 936          *    use the same IRQ.
 937          * 2. DMA channel IRQ resources can be specified one per resource or in
 938          *    ranges (start != end)
 939          * 3. iff all events (channels and, optionally, error) on this
 940          *    controller use the same IRQ, only one IRQ resource can be
 941          *    specified, otherwise there must be one IRQ per channel, even if
 942          *    some of them are equal
 943          * 4. if all IRQs on this controller are equal or if some specific IRQs
 944          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 945          *    requested with the IRQF_SHARED flag
 946          */
 947         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 948         if (!chan || !errirq_res)
 949                 return -ENODEV;
 950
 951         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
 952                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
 953                 return -EBUSY;
 954         }
 955
 956         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
 957                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
 958                 err = -EBUSY;
 959                 goto ermrdmars;
 960         }
 961
 962         err = -ENOMEM;
 963         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
 964         if (!shdev) {
 965                 dev_err(&pdev->dev, "Not enough memory\n");
 966                 goto ealloc;
 967         }
 968
 969         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
 970         if (!shdev->chan_reg)
 971                 goto emapchan;
 972         if (dmars) {
 973                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
 974                 if (!shdev->dmars)
 975                         goto emapdmars;
 976         }
 977
 978         /* platform data */
 979         shdev->pdata = pdata;
 980
 981         /* reset dma controller */
 982         err = sh_dmae_rst(shdev);
 983         if (err)
 984                 goto rst_err;
 985
 986         INIT_LIST_HEAD(&shdev->common.channels);
 987
 988         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
 989         if (dmars)
 990                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
 991
 992         shdev->common.device_alloc_chan_resources
 993                 = sh_dmae_alloc_chan_resources;
 994         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
 995         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
 996         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
 997         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
 998
 999         /* Compulsory for DMA_SLAVE fields */
1000         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1001         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1002
1003         shdev->common.dev = &pdev->dev;
1004         /* Default transfer size of 32 bytes requires 32-byte alignment */
1005         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1006
1007 #if defined(CONFIG_CPU_SH4)
1008         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1009
1010         if (!chanirq_res)
1011                 chanirq_res = errirq_res;
1012         else
1013                 irqres++;
1014
1015         if (chanirq_res == errirq_res ||
1016             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1017                 irqflags = IRQF_SHARED;
1018
1019         errirq = errirq_res->start;
1020
1021         err = request_irq(errirq, sh_dmae_err, irqflags,
1022                           "DMAC Address Error", shdev);
1023         if (err) {
1024                 dev_err(&pdev->dev,
1025                         "DMA failed requesting irq #%d, error %d\n",
1026                         errirq, err);
1027                 goto eirq_err;
1028         }
1029
1030 #else
1031         chanirq_res = errirq_res;
1032 #endif /* CONFIG_CPU_SH4 */
1033
1034         if (chanirq_res->start == chanirq_res->end &&
1035             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1036                 /* Special case - all multiplexed */
1037                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1038                         chan_irq[irq_cnt] = chanirq_res->start;
1039                         chan_flag[irq_cnt] = IRQF_SHARED;
1040                 }
1041         } else {
1042                 do {
1043                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1044                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1045                                     IORESOURCE_IRQ_SHAREABLE)
1046                                         chan_flag[irq_cnt] = IRQF_SHARED;
1047                                 else
1048                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1049                                 dev_dbg(&pdev->dev,
1050                                         "Found IRQ %d for channel %d\n",
1051                                         i, irq_cnt);
1052                                 chan_irq[irq_cnt++] = i;
1053                         }
1054                         chanirq_res = platform_get_resource(pdev,
1055                                                 IORESOURCE_IRQ, ++irqres);
1056                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1057         }
1058
1059         if (irq_cnt < pdata->channel_num)
1060                 goto eirqres;
1061
1062         /* Create DMA Channel */
1063         for (i = 0; i < pdata->channel_num; i++) {
1064                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1065                 if (err)
1066                         goto chan_probe_err;
1067         }
1068
1069         platform_set_drvdata(pdev, shdev);
1070         dma_async_device_register(&shdev->common);
1071
1072         return err;
1073
1074 chan_probe_err:
1075         sh_dmae_chan_remove(shdev);
1076 eirqres:
1077 #if defined(CONFIG_CPU_SH4)
1078         free_irq(errirq, shdev);
1079 eirq_err:
1080 #endif
1081 rst_err:
1082         if (dmars)
1083                 iounmap(shdev->dmars);
1084 emapdmars:
1085         iounmap(shdev->chan_reg);
1086 emapchan:
1087         kfree(shdev);
1088 ealloc:
1089         if (dmars)
1090                 release_mem_region(dmars->start, resource_size(dmars));
1091 ermrdmars:
1092         release_mem_region(chan->start, resource_size(chan));
1093
1094         return err;
1095 }
1096
1097 static int __exit sh_dmae_remove(struct platform_device *pdev)
1098 {
1099         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1100         struct resource *res;
1101         int errirq = platform_get_irq(pdev, 0);
1102
1103         dma_async_device_unregister(&shdev->common);
1104
1105         if (errirq > 0)
1106                 free_irq(errirq, shdev);
1107
1108         /* channel data remove */
1109         sh_dmae_chan_remove(shdev);
1110
1111         if (shdev->dmars)
1112                 iounmap(shdev->dmars);
1113         iounmap(shdev->chan_reg);
1114
1115         kfree(shdev);
1116
1117         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1118         if (res)
1119                 release_mem_region(res->start, resource_size(res));
1120         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1121         if (res)
1122                 release_mem_region(res->start, resource_size(res));
1123
1124         return 0;
1125 }
1126
1127 static void sh_dmae_shutdown(struct platform_device *pdev)
1128 {
1129         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1130         sh_dmae_ctl_stop(shdev);
1131 }
1132
1133 static struct platform_driver sh_dmae_driver = {
1134         .remove         = __exit_p(sh_dmae_remove),
1135         .shutdown       = sh_dmae_shutdown,
1136         .driver = {
1137                 .name   = "sh-dma-engine",
1138         },
1139 };
1140
1141 static int __init sh_dmae_init(void)
1142 {
1143         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1144 }
1145 module_init(sh_dmae_init);
1146
1147 static void __exit sh_dmae_exit(void)
1148 {
1149         platform_driver_unregister(&sh_dmae_driver);
1150 }
1151 module_exit(sh_dmae_exit);
1152
1153 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1154 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1155 MODULE_LICENSE("GPL");