sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  82                  "(0 = auto, 1 = none, 2 = POSBUF).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, int, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, PBG},"
 130                          "{Intel, SCH},"
 131                          "{ATI, SB450},"
 132                          "{ATI, SB600},"
 133                          "{ATI, RS600},"
 134                          "{ATI, RS690},"
 135                          "{ATI, RS780},"
 136                          "{ATI, R600},"
 137                          "{ATI, RV630},"
 138                          "{ATI, RV610},"
 139                          "{ATI, RV670},"
 140                          "{ATI, RV635},"
 141                          "{ATI, RV620},"
 142                          "{ATI, RV770},"
 143                          "{VIA, VT8251},"
 144                          "{VIA, VT8237A},"
 145                          "{SiS, SIS966},"
 146                          "{ULI, M5461}}");
 147 MODULE_DESCRIPTION("Intel HDA driver");
 148
 149 #ifdef CONFIG_SND_VERBOSE_PRINTK
 150 #define SFX     /* nop */
 151 #else
 152 #define SFX     "hda-intel: "
 153 #endif
 154
 155 /*
 156  * registers
 157  */
 158 #define ICH6_REG_GCAP                   0x00
 159 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 160 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 161 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 162 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 163 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 164 #define ICH6_REG_VMIN                   0x02
 165 #define ICH6_REG_VMAJ                   0x03
 166 #define ICH6_REG_OUTPAY                 0x04
 167 #define ICH6_REG_INPAY                  0x06
 168 #define ICH6_REG_GCTL                   0x08
 169 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 170 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 171 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 172 #define ICH6_REG_WAKEEN                 0x0c
 173 #define ICH6_REG_STATESTS               0x0e
 174 #define ICH6_REG_GSTS                   0x10
 175 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 176 #define ICH6_REG_INTCTL                 0x20
 177 #define ICH6_REG_INTSTS                 0x24
 178 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 179 #define ICH6_REG_SYNC                   0x34
 180 #define ICH6_REG_CORBLBASE              0x40
 181 #define ICH6_REG_CORBUBASE              0x44
 182 #define ICH6_REG_CORBWP                 0x48
 183 #define ICH6_REG_CORBRP                 0x4a
 184 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 185 #define ICH6_REG_CORBCTL                0x4c
 186 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 187 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 188 #define ICH6_REG_CORBSTS                0x4d
 189 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 190 #define ICH6_REG_CORBSIZE               0x4e
 191
 192 #define ICH6_REG_RIRBLBASE              0x50
 193 #define ICH6_REG_RIRBUBASE              0x54
 194 #define ICH6_REG_RIRBWP                 0x58
 195 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 196 #define ICH6_REG_RINTCNT                0x5a
 197 #define ICH6_REG_RIRBCTL                0x5c
 198 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 199 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 200 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 201 #define ICH6_REG_RIRBSTS                0x5d
 202 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 203 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 204 #define ICH6_REG_RIRBSIZE               0x5e
 205
 206 #define ICH6_REG_IC                     0x60
 207 #define ICH6_REG_IR                     0x64
 208 #define ICH6_REG_IRS                    0x68
 209 #define   ICH6_IRS_VALID        (1<<1)
 210 #define   ICH6_IRS_BUSY         (1<<0)
 211
 212 #define ICH6_REG_DPLBASE                0x70
 213 #define ICH6_REG_DPUBASE                0x74
 214 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 215
 216 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 217 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 218
 219 /* stream register offsets from stream base */
 220 #define ICH6_REG_SD_CTL                 0x00
 221 #define ICH6_REG_SD_STS                 0x03
 222 #define ICH6_REG_SD_LPIB                0x04
 223 #define ICH6_REG_SD_CBL                 0x08
 224 #define ICH6_REG_SD_LVI                 0x0c
 225 #define ICH6_REG_SD_FIFOW               0x0e
 226 #define ICH6_REG_SD_FIFOSIZE            0x10
 227 #define ICH6_REG_SD_FORMAT              0x12
 228 #define ICH6_REG_SD_BDLPL               0x18
 229 #define ICH6_REG_SD_BDLPU               0x1c
 230
 231 /* PCI space */
 232 #define ICH6_PCIREG_TCSEL       0x44
 233
 234 /*
 235  * other constants
 236  */
 237
 238 /* max number of SDs */
 239 /* ICH, ATI and VIA have 4 playback and 4 capture */
 240 #define ICH6_NUM_CAPTURE        4
 241 #define ICH6_NUM_PLAYBACK       4
 242
 243 /* ULI has 6 playback and 5 capture */
 244 #define ULI_NUM_CAPTURE         5
 245 #define ULI_NUM_PLAYBACK        6
 246
 247 /* ATI HDMI has 1 playback and 0 capture */
 248 #define ATIHDMI_NUM_CAPTURE     0
 249 #define ATIHDMI_NUM_PLAYBACK    1
 250
 251 /* TERA has 4 playback and 3 capture */
 252 #define TERA_NUM_CAPTURE        3
 253 #define TERA_NUM_PLAYBACK       4
 254
 255 /* this number is statically defined for simplicity */
 256 #define MAX_AZX_DEV             16
 257
 258 /* max number of fragments - we may use more if allocating more pages for BDL */
 259 #define BDL_SIZE                4096
 260 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 261 #define AZX_MAX_FRAG            32
 262 /* max buffer size - no h/w limit, you can increase as you like */
 263 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 264
 265 /* RIRB int mask: overrun[2], response[0] */
 266 #define RIRB_INT_RESPONSE       0x01
 267 #define RIRB_INT_OVERRUN        0x04
 268 #define RIRB_INT_MASK           0x05
 269
 270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 271 #define AZX_MAX_CODECS          8
 272 #define AZX_DEFAULT_CODECS      4
 273 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 274
 275 /* SD_CTL bits */
 276 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 277 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 278 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 279 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 280 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 281 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 282 #define SD_CTL_STREAM_TAG_SHIFT 20
 283
 284 /* SD_CTL and SD_STS */
 285 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 286 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 287 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 288 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 289                                  SD_INT_COMPLETE)
 290
 291 /* SD_STS */
 292 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 293
 294 /* INTCTL and INTSTS */
 295 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 296 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 297 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 298
 299 /* below are so far hardcoded - should read registers in future */
 300 #define ICH6_MAX_CORB_ENTRIES   256
 301 #define ICH6_MAX_RIRB_ENTRIES   256
 302
 303 /* position fix mode */
 304 enum {
 305         POS_FIX_AUTO,
 306         POS_FIX_LPIB,
 307         POS_FIX_POSBUF,
 308 };
 309
 310 /* Defines for ATI HD Audio support in SB450 south bridge */
 311 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 312 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 313
 314 /* Defines for Nvidia HDA support */
 315 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 316 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 317 #define NVIDIA_HDA_ISTRM_COH          0x4d
 318 #define NVIDIA_HDA_OSTRM_COH          0x4c
 319 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 320
 321 /* Defines for Intel SCH HDA snoop control */
 322 #define INTEL_SCH_HDA_DEVC      0x78
 323 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 324
 325 /* Define IN stream 0 FIFO size offset in VIA controller */
 326 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 327 /* Define VIA HD Audio Device ID*/
 328 #define VIA_HDAC_DEVICE_ID              0x3288
 329
 330 /* HD Audio class code */
 331 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 332
 333 /*
 334  */
 335
 336 struct azx_dev {
 337         struct snd_dma_buffer bdl; /* BDL buffer */
 338         u32 *posbuf;            /* position buffer pointer */
 339
 340         unsigned int bufsize;   /* size of the play buffer in bytes */
 341         unsigned int period_bytes; /* size of the period in bytes */
 342         unsigned int frags;     /* number for period in the play buffer */
 343         unsigned int fifo_size; /* FIFO size */
 344         unsigned long start_wallclk;    /* start + minimum wallclk */
 345         unsigned long period_wallclk;   /* wallclk for period */
 346
 347         void __iomem *sd_addr;  /* stream descriptor pointer */
 348
 349         u32 sd_int_sta_mask;    /* stream int status mask */
 350
 351         /* pcm support */
 352         struct snd_pcm_substream *substream;    /* assigned substream,
 353                                                  * set in PCM open
 354                                                  */
 355         unsigned int format_val;        /* format value to be set in the
 356                                          * controller and the codec
 357                                          */
 358         unsigned char stream_tag;       /* assigned stream */
 359         unsigned char index;            /* stream index */
 360         int device;                     /* last device number assigned to */
 361
 362         unsigned int opened :1;
 363         unsigned int running :1;
 364         unsigned int irq_pending :1;
 365         /*
 366          * For VIA:
 367          *  A flag to ensure DMA position is 0
 368          *  when link position is not greater than FIFO size
 369          */
 370         unsigned int insufficient :1;
 371 };
 372
 373 /* CORB/RIRB */
 374 struct azx_rb {
 375         u32 *buf;               /* CORB/RIRB buffer
 376                                  * Each CORB entry is 4byte, RIRB is 8byte
 377                                  */
 378         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 379         /* for RIRB */
 380         unsigned short rp, wp;  /* read/write pointers */
 381         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 382         u32 res[AZX_MAX_CODECS];        /* last read value */
 383 };
 384
 385 struct azx {
 386         struct snd_card *card;
 387         struct pci_dev *pci;
 388         int dev_index;
 389
 390         /* chip type specific */
 391         int driver_type;
 392         int playback_streams;
 393         int playback_index_offset;
 394         int capture_streams;
 395         int capture_index_offset;
 396         int num_streams;
 397
 398         /* pci resources */
 399         unsigned long addr;
 400         void __iomem *remap_addr;
 401         int irq;
 402
 403         /* locks */
 404         spinlock_t reg_lock;
 405         struct mutex open_mutex;
 406
 407         /* streams (x num_streams) */
 408         struct azx_dev *azx_dev;
 409
 410         /* PCM */
 411         struct snd_pcm *pcm[HDA_MAX_PCMS];
 412
 413         /* HD codec */
 414         unsigned short codec_mask;
 415         int  codec_probe_mask; /* copied from probe_mask option */
 416         struct hda_bus *bus;
 417         unsigned int beep_mode;
 418
 419         /* CORB/RIRB */
 420         struct azx_rb corb;
 421         struct azx_rb rirb;
 422
 423         /* CORB/RIRB and position buffers */
 424         struct snd_dma_buffer rb;
 425         struct snd_dma_buffer posbuf;
 426
 427         /* flags */
 428         int position_fix[2]; /* for both playback/capture streams */
 429         int poll_count;
 430         unsigned int running :1;
 431         unsigned int initialized :1;
 432         unsigned int single_cmd :1;
 433         unsigned int polling_mode :1;
 434         unsigned int msi :1;
 435         unsigned int irq_pending_warned :1;
 436         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_PCH,
 453         AZX_DRIVER_SCH,
 454         AZX_DRIVER_ATI,
 455         AZX_DRIVER_ATIHDMI,
 456         AZX_DRIVER_VIA,
 457         AZX_DRIVER_SIS,
 458         AZX_DRIVER_ULI,
 459         AZX_DRIVER_NVIDIA,
 460         AZX_DRIVER_TERA,
 461         AZX_DRIVER_GENERIC,
 462         AZX_NUM_DRIVERS, /* keep this as last entry */
 463 };
 464
 465 static char *driver_short_names[] __devinitdata = {
 466         [AZX_DRIVER_ICH] = "HDA Intel",
 467         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 468         [AZX_DRIVER_SCH] = "HDA Intel MID",
 469         [AZX_DRIVER_ATI] = "HDA ATI SB",
 470         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 471         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 472         [AZX_DRIVER_SIS] = "HDA SIS966",
 473         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 474         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 475         [AZX_DRIVER_TERA] = "HDA Teradici",
 476         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 477 };
 478
 479 /*
 480  * macros for easy use
 481  */
 482 #define azx_writel(chip,reg,value) \
 483         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 484 #define azx_readl(chip,reg) \
 485         readl((chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_writew(chip,reg,value) \
 487         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_readw(chip,reg) \
 489         readw((chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_writeb(chip,reg,value) \
 491         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 492 #define azx_readb(chip,reg) \
 493         readb((chip)->remap_addr + ICH6_REG_##reg)
 494
 495 #define azx_sd_writel(dev,reg,value) \
 496         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 497 #define azx_sd_readl(dev,reg) \
 498         readl((dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_writew(dev,reg,value) \
 500         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_readw(dev,reg) \
 502         readw((dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_writeb(dev,reg,value) \
 504         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 505 #define azx_sd_readb(dev,reg) \
 506         readb((dev)->sd_addr + ICH6_REG_##reg)
 507
 508 /* for pcm support */
 509 #define get_azx_dev(substream) (substream->runtime->private_data)
 510
 511 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 512 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 513 /*
 514  * Interface for HD codec
 515  */
 516
 517 /*
 518  * CORB / RIRB interface
 519  */
 520 static int azx_alloc_cmd_io(struct azx *chip)
 521 {
 522         int err;
 523
 524         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 525         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 526                                   snd_dma_pci_data(chip->pci),
 527                                   PAGE_SIZE, &chip->rb);
 528         if (err < 0) {
 529                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 530                 return err;
 531         }
 532         return 0;
 533 }
 534
 535 static void azx_init_cmd_io(struct azx *chip)
 536 {
 537         spin_lock_irq(&chip->reg_lock);
 538         /* CORB set up */
 539         chip->corb.addr = chip->rb.addr;
 540         chip->corb.buf = (u32 *)chip->rb.area;
 541         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 542         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 543
 544         /* set the corb size to 256 entries (ULI requires explicitly) */
 545         azx_writeb(chip, CORBSIZE, 0x02);
 546         /* set the corb write pointer to 0 */
 547         azx_writew(chip, CORBWP, 0);
 548         /* reset the corb hw read pointer */
 549         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 550         /* enable corb dma */
 551         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 552
 553         /* RIRB set up */
 554         chip->rirb.addr = chip->rb.addr + 2048;
 555         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 556         chip->rirb.wp = chip->rirb.rp = 0;
 557         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 558         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 559         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 560
 561         /* set the rirb size to 256 entries (ULI requires explicitly) */
 562         azx_writeb(chip, RIRBSIZE, 0x02);
 563         /* reset the rirb hw write pointer */
 564         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 565         /* set N=1, get RIRB response interrupt for new entry */
 566         azx_writew(chip, RINTCNT, 1);
 567         /* enable rirb dma and response irq */
 568         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 569         spin_unlock_irq(&chip->reg_lock);
 570 }
 571
 572 static void azx_free_cmd_io(struct azx *chip)
 573 {
 574         spin_lock_irq(&chip->reg_lock);
 575         /* disable ringbuffer DMAs */
 576         azx_writeb(chip, RIRBCTL, 0);
 577         azx_writeb(chip, CORBCTL, 0);
 578         spin_unlock_irq(&chip->reg_lock);
 579 }
 580
 581 static unsigned int azx_command_addr(u32 cmd)
 582 {
 583         unsigned int addr = cmd >> 28;
 584
 585         if (addr >= AZX_MAX_CODECS) {
 586                 snd_BUG();
 587                 addr = 0;
 588         }
 589
 590         return addr;
 591 }
 592
 593 static unsigned int azx_response_addr(u32 res)
 594 {
 595         unsigned int addr = res & 0xf;
 596
 597         if (addr >= AZX_MAX_CODECS) {
 598                 snd_BUG();
 599                 addr = 0;
 600         }
 601
 602         return addr;
 603 }
 604
 605 /* send a command */
 606 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 607 {
 608         struct azx *chip = bus->private_data;
 609         unsigned int addr = azx_command_addr(val);
 610         unsigned int wp;
 611
 612         spin_lock_irq(&chip->reg_lock);
 613
 614         /* add command to corb */
 615         wp = azx_readb(chip, CORBWP);
 616         wp++;
 617         wp %= ICH6_MAX_CORB_ENTRIES;
 618
 619         chip->rirb.cmds[addr]++;
 620         chip->corb.buf[wp] = cpu_to_le32(val);
 621         azx_writel(chip, CORBWP, wp);
 622
 623         spin_unlock_irq(&chip->reg_lock);
 624
 625         return 0;
 626 }
 627
 628 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 629
 630 /* retrieve RIRB entry - called from interrupt handler */
 631 static void azx_update_rirb(struct azx *chip)
 632 {
 633         unsigned int rp, wp;
 634         unsigned int addr;
 635         u32 res, res_ex;
 636
 637         wp = azx_readb(chip, RIRBWP);
 638         if (wp == chip->rirb.wp)
 639                 return;
 640         chip->rirb.wp = wp;
 641
 642         while (chip->rirb.rp != wp) {
 643                 chip->rirb.rp++;
 644                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 645
 646                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 647                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 648                 res = le32_to_cpu(chip->rirb.buf[rp]);
 649                 addr = azx_response_addr(res_ex);
 650                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 651                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 652                 else if (chip->rirb.cmds[addr]) {
 653                         chip->rirb.res[addr] = res;
 654                         smp_wmb();
 655                         chip->rirb.cmds[addr]--;
 656                 } else
 657                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 658                                    "last cmd=%#08x\n",
 659                                    res, res_ex,
 660                                    chip->last_cmd[addr]);
 661         }
 662 }
 663
 664 /* receive a response */
 665 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 666                                           unsigned int addr)
 667 {
 668         struct azx *chip = bus->private_data;
 669         unsigned long timeout;
 670         int do_poll = 0;
 671
 672  again:
 673         timeout = jiffies + msecs_to_jiffies(1000);
 674         for (;;) {
 675                 if (chip->polling_mode || do_poll) {
 676                         spin_lock_irq(&chip->reg_lock);
 677                         azx_update_rirb(chip);
 678                         spin_unlock_irq(&chip->reg_lock);
 679                 }
 680                 if (!chip->rirb.cmds[addr]) {
 681                         smp_rmb();
 682                         bus->rirb_error = 0;
 683
 684                         if (!do_poll)
 685                                 chip->poll_count = 0;
 686                         return chip->rirb.res[addr]; /* the last value */
 687                 }
 688                 if (time_after(jiffies, timeout))
 689                         break;
 690                 if (bus->needs_damn_long_delay)
 691                         msleep(2); /* temporary workaround */
 692                 else {
 693                         udelay(10);
 694                         cond_resched();
 695                 }
 696         }
 697
 698         if (!chip->polling_mode && chip->poll_count < 2) {
 699                 snd_printdd(SFX "azx_get_response timeout, "
 700                            "polling the codec once: last cmd=0x%08x\n",
 701                            chip->last_cmd[addr]);
 702                 do_poll = 1;
 703                 chip->poll_count++;
 704                 goto again;
 705         }
 706
 707
 708         if (!chip->polling_mode) {
 709                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 710                            "switching to polling mode: last cmd=0x%08x\n",
 711                            chip->last_cmd[addr]);
 712                 chip->polling_mode = 1;
 713                 goto again;
 714         }
 715
 716         if (chip->msi) {
 717                 snd_printk(KERN_WARNING SFX "No response from codec, "
 718                            "disabling MSI: last cmd=0x%08x\n",
 719                            chip->last_cmd[addr]);
 720                 free_irq(chip->irq, chip);
 721                 chip->irq = -1;
 722                 pci_disable_msi(chip->pci);
 723                 chip->msi = 0;
 724                 if (azx_acquire_irq(chip, 1) < 0) {
 725                         bus->rirb_error = 1;
 726                         return -1;
 727                 }
 728                 goto again;
 729         }
 730
 731         if (chip->probing) {
 732                 /* If this critical timeout happens during the codec probing
 733                  * phase, this is likely an access to a non-existing codec
 734                  * slot.  Better to return an error and reset the system.
 735                  */
 736                 return -1;
 737         }
 738
 739         /* a fatal communication error; need either to reset or to fallback
 740          * to the single_cmd mode
 741          */
 742         bus->rirb_error = 1;
 743         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 744                 bus->response_reset = 1;
 745                 return -1; /* give a chance to retry */
 746         }
 747
 748         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 749                    "switching to single_cmd mode: last cmd=0x%08x\n",
 750                    chip->last_cmd[addr]);
 751         chip->single_cmd = 1;
 752         bus->response_reset = 0;
 753         /* release CORB/RIRB */
 754         azx_free_cmd_io(chip);
 755         /* disable unsolicited responses */
 756         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 757         return -1;
 758 }
 759
 760 /*
 761  * Use the single immediate command instead of CORB/RIRB for simplicity
 762  *
 763  * Note: according to Intel, this is not preferred use.  The command was
 764  *       intended for the BIOS only, and may get confused with unsolicited
 765  *       responses.  So, we shouldn't use it for normal operation from the
 766  *       driver.
 767  *       I left the codes, however, for debugging/testing purposes.
 768  */
 769
 770 /* receive a response */
 771 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 772 {
 773         int timeout = 50;
 774
 775         while (timeout--) {
 776                 /* check IRV busy bit */
 777                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 778                         /* reuse rirb.res as the response return value */
 779                         chip->rirb.res[addr] = azx_readl(chip, IR);
 780                         return 0;
 781                 }
 782                 udelay(1);
 783         }
 784         if (printk_ratelimit())
 785                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 786                            azx_readw(chip, IRS));
 787         chip->rirb.res[addr] = -1;
 788         return -EIO;
 789 }
 790
 791 /* send a command */
 792 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 793 {
 794         struct azx *chip = bus->private_data;
 795         unsigned int addr = azx_command_addr(val);
 796         int timeout = 50;
 797
 798         bus->rirb_error = 0;
 799         while (timeout--) {
 800                 /* check ICB busy bit */
 801                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 802                         /* Clear IRV valid bit */
 803                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 804                                    ICH6_IRS_VALID);
 805                         azx_writel(chip, IC, val);
 806                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 807                                    ICH6_IRS_BUSY);
 808                         return azx_single_wait_for_response(chip, addr);
 809                 }
 810                 udelay(1);
 811         }
 812         if (printk_ratelimit())
 813                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 814                            azx_readw(chip, IRS), val);
 815         return -EIO;
 816 }
 817
 818 /* receive a response */
 819 static unsigned int azx_single_get_response(struct hda_bus *bus,
 820                                             unsigned int addr)
 821 {
 822         struct azx *chip = bus->private_data;
 823         return chip->rirb.res[addr];
 824 }
 825
 826 /*
 827  * The below are the main callbacks from hda_codec.
 828  *
 829  * They are just the skeleton to call sub-callbacks according to the
 830  * current setting of chip->single_cmd.
 831  */
 832
 833 /* send a command */
 834 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 835 {
 836         struct azx *chip = bus->private_data;
 837
 838         chip->last_cmd[azx_command_addr(val)] = val;
 839         if (chip->single_cmd)
 840                 return azx_single_send_cmd(bus, val);
 841         else
 842                 return azx_corb_send_cmd(bus, val);
 843 }
 844
 845 /* get a response */
 846 static unsigned int azx_get_response(struct hda_bus *bus,
 847                                      unsigned int addr)
 848 {
 849         struct azx *chip = bus->private_data;
 850         if (chip->single_cmd)
 851                 return azx_single_get_response(bus, addr);
 852         else
 853                 return azx_rirb_get_response(bus, addr);
 854 }
 855
 856 #ifdef CONFIG_SND_HDA_POWER_SAVE
 857 static void azx_power_notify(struct hda_bus *bus);
 858 #endif
 859
 860 /* reset codec link */
 861 static int azx_reset(struct azx *chip, int full_reset)
 862 {
 863         int count;
 864
 865         if (!full_reset)
 866                 goto __skip;
 867
 868         /* clear STATESTS */
 869         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 870
 871         /* reset controller */
 872         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 873
 874         count = 50;
 875         while (azx_readb(chip, GCTL) && --count)
 876                 msleep(1);
 877
 878         /* delay for >= 100us for codec PLL to settle per spec
 879          * Rev 0.9 section 5.5.1
 880          */
 881         msleep(1);
 882
 883         /* Bring controller out of reset */
 884         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 885
 886         count = 50;
 887         while (!azx_readb(chip, GCTL) && --count)
 888                 msleep(1);
 889
 890         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 891         msleep(1);
 892
 893       __skip:
 894         /* check to see if controller is ready */
 895         if (!azx_readb(chip, GCTL)) {
 896                 snd_printd(SFX "azx_reset: controller not ready!\n");
 897                 return -EBUSY;
 898         }
 899
 900         /* Accept unsolicited responses */
 901         if (!chip->single_cmd)
 902                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 903                            ICH6_GCTL_UNSOL);
 904
 905         /* detect codecs */
 906         if (!chip->codec_mask) {
 907                 chip->codec_mask = azx_readw(chip, STATESTS);
 908                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 909         }
 910
 911         return 0;
 912 }
 913
 914
 915 /*
 916  * Lowlevel interface
 917  */
 918
 919 /* enable interrupts */
 920 static void azx_int_enable(struct azx *chip)
 921 {
 922         /* enable controller CIE and GIE */
 923         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 924                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 925 }
 926
 927 /* disable interrupts */
 928 static void azx_int_disable(struct azx *chip)
 929 {
 930         int i;
 931
 932         /* disable interrupts in stream descriptor */
 933         for (i = 0; i < chip->num_streams; i++) {
 934                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 935                 azx_sd_writeb(azx_dev, SD_CTL,
 936                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 937         }
 938
 939         /* disable SIE for all streams */
 940         azx_writeb(chip, INTCTL, 0);
 941
 942         /* disable controller CIE and GIE */
 943         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 944                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 945 }
 946
 947 /* clear interrupts */
 948 static void azx_int_clear(struct azx *chip)
 949 {
 950         int i;
 951
 952         /* clear stream status */
 953         for (i = 0; i < chip->num_streams; i++) {
 954                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 955                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 956         }
 957
 958         /* clear STATESTS */
 959         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 960
 961         /* clear rirb status */
 962         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 963
 964         /* clear int status */
 965         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 966 }
 967
 968 /* start a stream */
 969 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 970 {
 971         /*
 972          * Before stream start, initialize parameter
 973          */
 974         azx_dev->insufficient = 1;
 975
 976         /* enable SIE */
 977         azx_writel(chip, INTCTL,
 978                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
 979         /* set DMA start and interrupt mask */
 980         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 981                       SD_CTL_DMA_START | SD_INT_MASK);
 982 }
 983
 984 /* stop DMA */
 985 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 986 {
 987         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 988                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 989         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 990 }
 991
 992 /* stop a stream */
 993 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 994 {
 995         azx_stream_clear(chip, azx_dev);
 996         /* disable SIE */
 997         azx_writel(chip, INTCTL,
 998                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
 999 }
1000
1001
1002 /*
1003  * reset and start the controller registers
1004  */
1005 static void azx_init_chip(struct azx *chip, int full_reset)
1006 {
1007         if (chip->initialized)
1008                 return;
1009
1010         /* reset controller */
1011         azx_reset(chip, full_reset);
1012
1013         /* initialize interrupts */
1014         azx_int_clear(chip);
1015         azx_int_enable(chip);
1016
1017         /* initialize the codec command I/O */
1018         if (!chip->single_cmd)
1019                 azx_init_cmd_io(chip);
1020
1021         /* program the position buffer */
1022         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1023         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1024
1025         chip->initialized = 1;
1026 }
1027
1028 /*
1029  * initialize the PCI registers
1030  */
1031 /* update bits in a PCI register byte */
1032 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1033                             unsigned char mask, unsigned char val)
1034 {
1035         unsigned char data;
1036
1037         pci_read_config_byte(pci, reg, &data);
1038         data &= ~mask;
1039         data |= (val & mask);
1040         pci_write_config_byte(pci, reg, data);
1041 }
1042
1043 static void azx_init_pci(struct azx *chip)
1044 {
1045         unsigned short snoop;
1046
1047         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1048          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1049          * Ensuring these bits are 0 clears playback static on some HD Audio
1050          * codecs
1051          */
1052         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1053
1054         switch (chip->driver_type) {
1055         case AZX_DRIVER_ATI:
1056                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1057                 update_pci_byte(chip->pci,
1058                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1059                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1060                 break;
1061         case AZX_DRIVER_NVIDIA:
1062                 /* For NVIDIA HDA, enable snoop */
1063                 update_pci_byte(chip->pci,
1064                                 NVIDIA_HDA_TRANSREG_ADDR,
1065                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1066                 update_pci_byte(chip->pci,
1067                                 NVIDIA_HDA_ISTRM_COH,
1068                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1069                 update_pci_byte(chip->pci,
1070                                 NVIDIA_HDA_OSTRM_COH,
1071                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1072                 break;
1073         case AZX_DRIVER_SCH:
1074         case AZX_DRIVER_PCH:
1075                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1076                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1077                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1078                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1079                         pci_read_config_word(chip->pci,
1080                                 INTEL_SCH_HDA_DEVC, &snoop);
1081                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1082                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1083                                 ? "Failed" : "OK");
1084                 }
1085                 break;
1086
1087         }
1088 }
1089
1090
1091 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1092
1093 /*
1094  * interrupt handler
1095  */
1096 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1097 {
1098         struct azx *chip = dev_id;
1099         struct azx_dev *azx_dev;
1100         u32 status;
1101         u8 sd_status;
1102         int i, ok;
1103
1104         spin_lock(&chip->reg_lock);
1105
1106         status = azx_readl(chip, INTSTS);
1107         if (status == 0) {
1108                 spin_unlock(&chip->reg_lock);
1109                 return IRQ_NONE;
1110         }
1111
1112         for (i = 0; i < chip->num_streams; i++) {
1113                 azx_dev = &chip->azx_dev[i];
1114                 if (status & azx_dev->sd_int_sta_mask) {
1115                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1116                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1117                         if (!azx_dev->substream || !azx_dev->running ||
1118                             !(sd_status & SD_INT_COMPLETE))
1119                                 continue;
1120                         /* check whether this IRQ is really acceptable */
1121                         ok = azx_position_ok(chip, azx_dev);
1122                         if (ok == 1) {
1123                                 azx_dev->irq_pending = 0;
1124                                 spin_unlock(&chip->reg_lock);
1125                                 snd_pcm_period_elapsed(azx_dev->substream);
1126                                 spin_lock(&chip->reg_lock);
1127                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1128                                 /* bogus IRQ, process it later */
1129                                 azx_dev->irq_pending = 1;
1130                                 queue_work(chip->bus->workq,
1131                                            &chip->irq_pending_work);
1132                         }
1133                 }
1134         }
1135
1136         /* clear rirb int */
1137         status = azx_readb(chip, RIRBSTS);
1138         if (status & RIRB_INT_MASK) {
1139                 if (status & RIRB_INT_RESPONSE)
1140                         azx_update_rirb(chip);
1141                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1142         }
1143
1144 #if 0
1145         /* clear state status int */
1146         if (azx_readb(chip, STATESTS) & 0x04)
1147                 azx_writeb(chip, STATESTS, 0x04);
1148 #endif
1149         spin_unlock(&chip->reg_lock);
1150
1151         return IRQ_HANDLED;
1152 }
1153
1154
1155 /*
1156  * set up a BDL entry
1157  */
1158 static int setup_bdle(struct snd_pcm_substream *substream,
1159                       struct azx_dev *azx_dev, u32 **bdlp,
1160                       int ofs, int size, int with_ioc)
1161 {
1162         u32 *bdl = *bdlp;
1163
1164         while (size > 0) {
1165                 dma_addr_t addr;
1166                 int chunk;
1167
1168                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1169                         return -EINVAL;
1170
1171                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1172                 /* program the address field of the BDL entry */
1173                 bdl[0] = cpu_to_le32((u32)addr);
1174                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1175                 /* program the size field of the BDL entry */
1176                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1177                 bdl[2] = cpu_to_le32(chunk);
1178                 /* program the IOC to enable interrupt
1179                  * only when the whole fragment is processed
1180                  */
1181                 size -= chunk;
1182                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1183                 bdl += 4;
1184                 azx_dev->frags++;
1185                 ofs += chunk;
1186         }
1187         *bdlp = bdl;
1188         return ofs;
1189 }
1190
1191 /*
1192  * set up BDL entries
1193  */
1194 static int azx_setup_periods(struct azx *chip,
1195                              struct snd_pcm_substream *substream,
1196                              struct azx_dev *azx_dev)
1197 {
1198         u32 *bdl;
1199         int i, ofs, periods, period_bytes;
1200         int pos_adj;
1201
1202         /* reset BDL address */
1203         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1204         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1205
1206         period_bytes = azx_dev->period_bytes;
1207         periods = azx_dev->bufsize / period_bytes;
1208
1209         /* program the initial BDL entries */
1210         bdl = (u32 *)azx_dev->bdl.area;
1211         ofs = 0;
1212         azx_dev->frags = 0;
1213         pos_adj = bdl_pos_adj[chip->dev_index];
1214         if (pos_adj > 0) {
1215                 struct snd_pcm_runtime *runtime = substream->runtime;
1216                 int pos_align = pos_adj;
1217                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1218                 if (!pos_adj)
1219                         pos_adj = pos_align;
1220                 else
1221                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1222                                 pos_align;
1223                 pos_adj = frames_to_bytes(runtime, pos_adj);
1224                 if (pos_adj >= period_bytes) {
1225                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1226                                    bdl_pos_adj[chip->dev_index]);
1227                         pos_adj = 0;
1228                 } else {
1229                         ofs = setup_bdle(substream, azx_dev,
1230                                          &bdl, ofs, pos_adj, 1);
1231                         if (ofs < 0)
1232                                 goto error;
1233                 }
1234         } else
1235                 pos_adj = 0;
1236         for (i = 0; i < periods; i++) {
1237                 if (i == periods - 1 && pos_adj)
1238                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1239                                          period_bytes - pos_adj, 0);
1240                 else
1241                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1242                                          period_bytes, 1);
1243                 if (ofs < 0)
1244                         goto error;
1245         }
1246         return 0;
1247
1248  error:
1249         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1250                    azx_dev->bufsize, period_bytes);
1251         return -EINVAL;
1252 }
1253
1254 /* reset stream */
1255 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1256 {
1257         unsigned char val;
1258         int timeout;
1259
1260         azx_stream_clear(chip, azx_dev);
1261
1262         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1263                       SD_CTL_STREAM_RESET);
1264         udelay(3);
1265         timeout = 300;
1266         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1267                --timeout)
1268                 ;
1269         val &= ~SD_CTL_STREAM_RESET;
1270         azx_sd_writeb(azx_dev, SD_CTL, val);
1271         udelay(3);
1272
1273         timeout = 300;
1274         /* waiting for hardware to report that the stream is out of reset */
1275         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1276                --timeout)
1277                 ;
1278
1279         /* reset first position - may not be synced with hw at this time */
1280         *azx_dev->posbuf = 0;
1281 }
1282
1283 /*
1284  * set up the SD for streaming
1285  */
1286 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1287 {
1288         /* make sure the run bit is zero for SD */
1289         azx_stream_clear(chip, azx_dev);
1290         /* program the stream_tag */
1291         azx_sd_writel(azx_dev, SD_CTL,
1292                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1293                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1294
1295         /* program the length of samples in cyclic buffer */
1296         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1297
1298         /* program the stream format */
1299         /* this value needs to be the same as the one programmed */
1300         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1301
1302         /* program the stream LVI (last valid index) of the BDL */
1303         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1304
1305         /* program the BDL address */
1306         /* lower BDL address */
1307         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1308         /* upper BDL address */
1309         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1310
1311         /* enable the position buffer */
1312         if (chip->position_fix[0] == POS_FIX_POSBUF ||
1313             chip->position_fix[0] == POS_FIX_AUTO ||
1314             chip->position_fix[1] == POS_FIX_POSBUF ||
1315             chip->position_fix[1] == POS_FIX_AUTO ||
1316             chip->via_dmapos_patch) {
1317                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1318                         azx_writel(chip, DPLBASE,
1319                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1320         }
1321
1322         /* set the interrupt enable bits in the descriptor control register */
1323         azx_sd_writel(azx_dev, SD_CTL,
1324                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1325
1326         return 0;
1327 }
1328
1329 /*
1330  * Probe the given codec address
1331  */
1332 static int probe_codec(struct azx *chip, int addr)
1333 {
1334         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1335                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1336         unsigned int res;
1337
1338         mutex_lock(&chip->bus->cmd_mutex);
1339         chip->probing = 1;
1340         azx_send_cmd(chip->bus, cmd);
1341         res = azx_get_response(chip->bus, addr);
1342         chip->probing = 0;
1343         mutex_unlock(&chip->bus->cmd_mutex);
1344         if (res == -1)
1345                 return -EIO;
1346         snd_printdd(SFX "codec #%d probed OK\n", addr);
1347         return 0;
1348 }
1349
1350 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1351                                  struct hda_pcm *cpcm);
1352 static void azx_stop_chip(struct azx *chip);
1353
1354 static void azx_bus_reset(struct hda_bus *bus)
1355 {
1356         struct azx *chip = bus->private_data;
1357
1358         bus->in_reset = 1;
1359         azx_stop_chip(chip);
1360         azx_init_chip(chip, 1);
1361 #ifdef CONFIG_PM
1362         if (chip->initialized) {
1363                 int i;
1364
1365                 for (i = 0; i < HDA_MAX_PCMS; i++)
1366                         snd_pcm_suspend_all(chip->pcm[i]);
1367                 snd_hda_suspend(chip->bus);
1368                 snd_hda_resume(chip->bus);
1369         }
1370 #endif
1371         bus->in_reset = 0;
1372 }
1373
1374 /*
1375  * Codec initialization
1376  */
1377
1378 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1379 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1380         [AZX_DRIVER_NVIDIA] = 8,
1381         [AZX_DRIVER_TERA] = 1,
1382 };
1383
1384 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1385 {
1386         struct hda_bus_template bus_temp;
1387         int c, codecs, err;
1388         int max_slots;
1389
1390         memset(&bus_temp, 0, sizeof(bus_temp));
1391         bus_temp.private_data = chip;
1392         bus_temp.modelname = model;
1393         bus_temp.pci = chip->pci;
1394         bus_temp.ops.command = azx_send_cmd;
1395         bus_temp.ops.get_response = azx_get_response;
1396         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1397         bus_temp.ops.bus_reset = azx_bus_reset;
1398 #ifdef CONFIG_SND_HDA_POWER_SAVE
1399         bus_temp.power_save = &power_save;
1400         bus_temp.ops.pm_notify = azx_power_notify;
1401 #endif
1402
1403         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1404         if (err < 0)
1405                 return err;
1406
1407         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1408                 chip->bus->needs_damn_long_delay = 1;
1409
1410         codecs = 0;
1411         max_slots = azx_max_codecs[chip->driver_type];
1412         if (!max_slots)
1413                 max_slots = AZX_DEFAULT_CODECS;
1414
1415         /* First try to probe all given codec slots */
1416         for (c = 0; c < max_slots; c++) {
1417                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1418                         if (probe_codec(chip, c) < 0) {
1419                                 /* Some BIOSen give you wrong codec addresses
1420                                  * that don't exist
1421                                  */
1422                                 snd_printk(KERN_WARNING SFX
1423                                            "Codec #%d probe error; "
1424                                            "disabling it...\n", c);
1425                                 chip->codec_mask &= ~(1 << c);
1426                                 /* More badly, accessing to a non-existing
1427                                  * codec often screws up the controller chip,
1428                                  * and disturbs the further communications.
1429                                  * Thus if an error occurs during probing,
1430                                  * better to reset the controller chip to
1431                                  * get back to the sanity state.
1432                                  */
1433                                 azx_stop_chip(chip);
1434                                 azx_init_chip(chip, 1);
1435                         }
1436                 }
1437         }
1438
1439         /* Then create codec instances */
1440         for (c = 0; c < max_slots; c++) {
1441                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1442                         struct hda_codec *codec;
1443                         err = snd_hda_codec_new(chip->bus, c, &codec);
1444                         if (err < 0)
1445                                 continue;
1446                         codec->beep_mode = chip->beep_mode;
1447                         codecs++;
1448                 }
1449         }
1450         if (!codecs) {
1451                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1452                 return -ENXIO;
1453         }
1454         return 0;
1455 }
1456
1457 /* configure each codec instance */
1458 static int __devinit azx_codec_configure(struct azx *chip)
1459 {
1460         struct hda_codec *codec;
1461         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1462                 snd_hda_codec_configure(codec);
1463         }
1464         return 0;
1465 }
1466
1467
1468 /*
1469  * PCM support
1470  */
1471
1472 /* assign a stream for the PCM */
1473 static inline struct azx_dev *
1474 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1475 {
1476         int dev, i, nums;
1477         struct azx_dev *res = NULL;
1478
1479         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1480                 dev = chip->playback_index_offset;
1481                 nums = chip->playback_streams;
1482         } else {
1483                 dev = chip->capture_index_offset;
1484                 nums = chip->capture_streams;
1485         }
1486         for (i = 0; i < nums; i++, dev++)
1487                 if (!chip->azx_dev[dev].opened) {
1488                         res = &chip->azx_dev[dev];
1489                         if (res->device == substream->pcm->device)
1490                                 break;
1491                 }
1492         if (res) {
1493                 res->opened = 1;
1494                 res->device = substream->pcm->device;
1495         }
1496         return res;
1497 }
1498
1499 /* release the assigned stream */
1500 static inline void azx_release_device(struct azx_dev *azx_dev)
1501 {
1502         azx_dev->opened = 0;
1503 }
1504
1505 static struct snd_pcm_hardware azx_pcm_hw = {
1506         .info =                 (SNDRV_PCM_INFO_MMAP |
1507                                  SNDRV_PCM_INFO_INTERLEAVED |
1508                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1509                                  SNDRV_PCM_INFO_MMAP_VALID |
1510                                  /* No full-resume yet implemented */
1511                                  /* SNDRV_PCM_INFO_RESUME |*/
1512                                  SNDRV_PCM_INFO_PAUSE |
1513                                  SNDRV_PCM_INFO_SYNC_START),
1514         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1515         .rates =                SNDRV_PCM_RATE_48000,
1516         .rate_min =             48000,
1517         .rate_max =             48000,
1518         .channels_min =         2,
1519         .channels_max =         2,
1520         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1521         .period_bytes_min =     128,
1522         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1523         .periods_min =          2,
1524         .periods_max =          AZX_MAX_FRAG,
1525         .fifo_size =            0,
1526 };
1527
1528 struct azx_pcm {
1529         struct azx *chip;
1530         struct hda_codec *codec;
1531         struct hda_pcm_stream *hinfo[2];
1532 };
1533
1534 static int azx_pcm_open(struct snd_pcm_substream *substream)
1535 {
1536         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1537         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1538         struct azx *chip = apcm->chip;
1539         struct azx_dev *azx_dev;
1540         struct snd_pcm_runtime *runtime = substream->runtime;
1541         unsigned long flags;
1542         int err;
1543
1544         mutex_lock(&chip->open_mutex);
1545         azx_dev = azx_assign_device(chip, substream);
1546         if (azx_dev == NULL) {
1547                 mutex_unlock(&chip->open_mutex);
1548                 return -EBUSY;
1549         }
1550         runtime->hw = azx_pcm_hw;
1551         runtime->hw.channels_min = hinfo->channels_min;
1552         runtime->hw.channels_max = hinfo->channels_max;
1553         runtime->hw.formats = hinfo->formats;
1554         runtime->hw.rates = hinfo->rates;
1555         snd_pcm_limit_hw_rates(runtime);
1556         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1557         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1558                                    128);
1559         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1560                                    128);
1561         snd_hda_power_up(apcm->codec);
1562         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1563         if (err < 0) {
1564                 azx_release_device(azx_dev);
1565                 snd_hda_power_down(apcm->codec);
1566                 mutex_unlock(&chip->open_mutex);
1567                 return err;
1568         }
1569         snd_pcm_limit_hw_rates(runtime);
1570         /* sanity check */
1571         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1572             snd_BUG_ON(!runtime->hw.channels_max) ||
1573             snd_BUG_ON(!runtime->hw.formats) ||
1574             snd_BUG_ON(!runtime->hw.rates)) {
1575                 azx_release_device(azx_dev);
1576                 hinfo->ops.close(hinfo, apcm->codec, substream);
1577                 snd_hda_power_down(apcm->codec);
1578                 mutex_unlock(&chip->open_mutex);
1579                 return -EINVAL;
1580         }
1581         spin_lock_irqsave(&chip->reg_lock, flags);
1582         azx_dev->substream = substream;
1583         azx_dev->running = 0;
1584         spin_unlock_irqrestore(&chip->reg_lock, flags);
1585
1586         runtime->private_data = azx_dev;
1587         snd_pcm_set_sync(substream);
1588         mutex_unlock(&chip->open_mutex);
1589         return 0;
1590 }
1591
1592 static int azx_pcm_close(struct snd_pcm_substream *substream)
1593 {
1594         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1595         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1596         struct azx *chip = apcm->chip;
1597         struct azx_dev *azx_dev = get_azx_dev(substream);
1598         unsigned long flags;
1599
1600         mutex_lock(&chip->open_mutex);
1601         spin_lock_irqsave(&chip->reg_lock, flags);
1602         azx_dev->substream = NULL;
1603         azx_dev->running = 0;
1604         spin_unlock_irqrestore(&chip->reg_lock, flags);
1605         azx_release_device(azx_dev);
1606         hinfo->ops.close(hinfo, apcm->codec, substream);
1607         snd_hda_power_down(apcm->codec);
1608         mutex_unlock(&chip->open_mutex);
1609         return 0;
1610 }
1611
1612 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1613                              struct snd_pcm_hw_params *hw_params)
1614 {
1615         struct azx_dev *azx_dev = get_azx_dev(substream);
1616
1617         azx_dev->bufsize = 0;
1618         azx_dev->period_bytes = 0;
1619         azx_dev->format_val = 0;
1620         return snd_pcm_lib_malloc_pages(substream,
1621                                         params_buffer_bytes(hw_params));
1622 }
1623
1624 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1625 {
1626         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1627         struct azx_dev *azx_dev = get_azx_dev(substream);
1628         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1629
1630         /* reset BDL address */
1631         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1632         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1633         azx_sd_writel(azx_dev, SD_CTL, 0);
1634         azx_dev->bufsize = 0;
1635         azx_dev->period_bytes = 0;
1636         azx_dev->format_val = 0;
1637
1638         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1639
1640         return snd_pcm_lib_free_pages(substream);
1641 }
1642
1643 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1644 {
1645         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1646         struct azx *chip = apcm->chip;
1647         struct azx_dev *azx_dev = get_azx_dev(substream);
1648         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1649         struct snd_pcm_runtime *runtime = substream->runtime;
1650         unsigned int bufsize, period_bytes, format_val, stream_tag;
1651         int err;
1652
1653         azx_stream_reset(chip, azx_dev);
1654         format_val = snd_hda_calc_stream_format(runtime->rate,
1655                                                 runtime->channels,
1656                                                 runtime->format,
1657                                                 hinfo->maxbps,
1658                                                 apcm->codec->spdif_ctls);
1659         if (!format_val) {
1660                 snd_printk(KERN_ERR SFX
1661                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1662                            runtime->rate, runtime->channels, runtime->format);
1663                 return -EINVAL;
1664         }
1665
1666         bufsize = snd_pcm_lib_buffer_bytes(substream);
1667         period_bytes = snd_pcm_lib_period_bytes(substream);
1668
1669         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1670                     bufsize, format_val);
1671
1672         if (bufsize != azx_dev->bufsize ||
1673             period_bytes != azx_dev->period_bytes ||
1674             format_val != azx_dev->format_val) {
1675                 azx_dev->bufsize = bufsize;
1676                 azx_dev->period_bytes = period_bytes;
1677                 azx_dev->format_val = format_val;
1678                 err = azx_setup_periods(chip, substream, azx_dev);
1679                 if (err < 0)
1680                         return err;
1681         }
1682
1683         /* wallclk has 24Mhz clock source */
1684         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1685                                                 runtime->rate) * 1000);
1686         azx_setup_controller(chip, azx_dev);
1687         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1688                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1689         else
1690                 azx_dev->fifo_size = 0;
1691
1692         stream_tag = azx_dev->stream_tag;
1693         /* CA-IBG chips need the playback stream starting from 1 */
1694         if (chip->driver_type == AZX_DRIVER_CTX &&
1695             stream_tag > chip->capture_streams)
1696                 stream_tag -= chip->capture_streams;
1697         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1698                                      azx_dev->format_val, substream);
1699 }
1700
1701 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1702 {
1703         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1704         struct azx *chip = apcm->chip;
1705         struct azx_dev *azx_dev;
1706         struct snd_pcm_substream *s;
1707         int rstart = 0, start, nsync = 0, sbits = 0;
1708         int nwait, timeout;
1709
1710         switch (cmd) {
1711         case SNDRV_PCM_TRIGGER_START:
1712                 rstart = 1;
1713         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1714         case SNDRV_PCM_TRIGGER_RESUME:
1715                 start = 1;
1716                 break;
1717         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1718         case SNDRV_PCM_TRIGGER_SUSPEND:
1719         case SNDRV_PCM_TRIGGER_STOP:
1720                 start = 0;
1721                 break;
1722         default:
1723                 return -EINVAL;
1724         }
1725
1726         snd_pcm_group_for_each_entry(s, substream) {
1727                 if (s->pcm->card != substream->pcm->card)
1728                         continue;
1729                 azx_dev = get_azx_dev(s);
1730                 sbits |= 1 << azx_dev->index;
1731                 nsync++;
1732                 snd_pcm_trigger_done(s, substream);
1733         }
1734
1735         spin_lock(&chip->reg_lock);
1736         if (nsync > 1) {
1737                 /* first, set SYNC bits of corresponding streams */
1738                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1739         }
1740         snd_pcm_group_for_each_entry(s, substream) {
1741                 if (s->pcm->card != substream->pcm->card)
1742                         continue;
1743                 azx_dev = get_azx_dev(s);
1744                 if (start) {
1745                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1746                         if (!rstart)
1747                                 azx_dev->start_wallclk -=
1748                                                 azx_dev->period_wallclk;
1749                         azx_stream_start(chip, azx_dev);
1750                 } else {
1751                         azx_stream_stop(chip, azx_dev);
1752                 }
1753                 azx_dev->running = start;
1754         }
1755         spin_unlock(&chip->reg_lock);
1756         if (start) {
1757                 if (nsync == 1)
1758                         return 0;
1759                 /* wait until all FIFOs get ready */
1760                 for (timeout = 5000; timeout; timeout--) {
1761                         nwait = 0;
1762                         snd_pcm_group_for_each_entry(s, substream) {
1763                                 if (s->pcm->card != substream->pcm->card)
1764                                         continue;
1765                                 azx_dev = get_azx_dev(s);
1766                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1767                                       SD_STS_FIFO_READY))
1768                                         nwait++;
1769                         }
1770                         if (!nwait)
1771                                 break;
1772                         cpu_relax();
1773                 }
1774         } else {
1775                 /* wait until all RUN bits are cleared */
1776                 for (timeout = 5000; timeout; timeout--) {
1777                         nwait = 0;
1778                         snd_pcm_group_for_each_entry(s, substream) {
1779                                 if (s->pcm->card != substream->pcm->card)
1780                                         continue;
1781                                 azx_dev = get_azx_dev(s);
1782                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1783                                     SD_CTL_DMA_START)
1784                                         nwait++;
1785                         }
1786                         if (!nwait)
1787                                 break;
1788                         cpu_relax();
1789                 }
1790         }
1791         if (nsync > 1) {
1792                 spin_lock(&chip->reg_lock);
1793                 /* reset SYNC bits */
1794                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1795                 spin_unlock(&chip->reg_lock);
1796         }
1797         return 0;
1798 }
1799
1800 /* get the current DMA position with correction on VIA chips */
1801 static unsigned int azx_via_get_position(struct azx *chip,
1802                                          struct azx_dev *azx_dev)
1803 {
1804         unsigned int link_pos, mini_pos, bound_pos;
1805         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1806         unsigned int fifo_size;
1807
1808         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1809         if (azx_dev->index >= 4) {
1810                 /* Playback, no problem using link position */
1811                 return link_pos;
1812         }
1813
1814         /* Capture */
1815         /* For new chipset,
1816          * use mod to get the DMA position just like old chipset
1817          */
1818         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1819         mod_dma_pos %= azx_dev->period_bytes;
1820
1821         /* azx_dev->fifo_size can't get FIFO size of in stream.
1822          * Get from base address + offset.
1823          */
1824         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1825
1826         if (azx_dev->insufficient) {
1827                 /* Link position never gather than FIFO size */
1828                 if (link_pos <= fifo_size)
1829                         return 0;
1830
1831                 azx_dev->insufficient = 0;
1832         }
1833
1834         if (link_pos <= fifo_size)
1835                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1836         else
1837                 mini_pos = link_pos - fifo_size;
1838
1839         /* Find nearest previous boudary */
1840         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1841         mod_link_pos = link_pos % azx_dev->period_bytes;
1842         if (mod_link_pos >= fifo_size)
1843                 bound_pos = link_pos - mod_link_pos;
1844         else if (mod_dma_pos >= mod_mini_pos)
1845                 bound_pos = mini_pos - mod_mini_pos;
1846         else {
1847                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1848                 if (bound_pos >= azx_dev->bufsize)
1849                         bound_pos = 0;
1850         }
1851
1852         /* Calculate real DMA position we want */
1853         return bound_pos + mod_dma_pos;
1854 }
1855
1856 static unsigned int azx_get_position(struct azx *chip,
1857                                      struct azx_dev *azx_dev)
1858 {
1859         unsigned int pos;
1860
1861         if (chip->via_dmapos_patch)
1862                 pos = azx_via_get_position(chip, azx_dev);
1863         else {
1864                 int stream = azx_dev->substream->stream;
1865                 if (chip->position_fix[stream] == POS_FIX_POSBUF ||
1866                     chip->position_fix[stream] == POS_FIX_AUTO) {
1867                         /* use the position buffer */
1868                         pos = le32_to_cpu(*azx_dev->posbuf);
1869                 } else {
1870                         /* read LPIB */
1871                         pos = azx_sd_readl(azx_dev, SD_LPIB);
1872                 }
1873         }
1874         if (pos >= azx_dev->bufsize)
1875                 pos = 0;
1876         return pos;
1877 }
1878
1879 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1880 {
1881         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1882         struct azx *chip = apcm->chip;
1883         struct azx_dev *azx_dev = get_azx_dev(substream);
1884         return bytes_to_frames(substream->runtime,
1885                                azx_get_position(chip, azx_dev));
1886 }
1887
1888 /*
1889  * Check whether the current DMA position is acceptable for updating
1890  * periods.  Returns non-zero if it's OK.
1891  *
1892  * Many HD-audio controllers appear pretty inaccurate about
1893  * the update-IRQ timing.  The IRQ is issued before actually the
1894  * data is processed.  So, we need to process it afterwords in a
1895  * workqueue.
1896  */
1897 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1898 {
1899         u32 wallclk;
1900         unsigned int pos;
1901         int stream;
1902
1903         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1904         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1905                 return -1;      /* bogus (too early) interrupt */
1906
1907         stream = azx_dev->substream->stream;
1908         pos = azx_get_position(chip, azx_dev);
1909         if (chip->position_fix[stream] == POS_FIX_AUTO) {
1910                 if (!pos) {
1911                         printk(KERN_WARNING
1912                                "hda-intel: Invalid position buffer, "
1913                                "using LPIB read method instead.\n");
1914                         chip->position_fix[stream] = POS_FIX_LPIB;
1915                         pos = azx_get_position(chip, azx_dev);
1916                 } else
1917                         chip->position_fix[stream] = POS_FIX_POSBUF;
1918         }
1919
1920         if (WARN_ONCE(!azx_dev->period_bytes,
1921                       "hda-intel: zero azx_dev->period_bytes"))
1922                 return -1; /* this shouldn't happen! */
1923         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1924             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1925                 /* NG - it's below the first next period boundary */
1926                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1927         azx_dev->start_wallclk += wallclk;
1928         return 1; /* OK, it's fine */
1929 }
1930
1931 /*
1932  * The work for pending PCM period updates.
1933  */
1934 static void azx_irq_pending_work(struct work_struct *work)
1935 {
1936         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1937         int i, pending, ok;
1938
1939         if (!chip->irq_pending_warned) {
1940                 printk(KERN_WARNING
1941                        "hda-intel: IRQ timing workaround is activated "
1942                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1943                        chip->card->number);
1944                 chip->irq_pending_warned = 1;
1945         }
1946
1947         for (;;) {
1948                 pending = 0;
1949                 spin_lock_irq(&chip->reg_lock);
1950                 for (i = 0; i < chip->num_streams; i++) {
1951                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1952                         if (!azx_dev->irq_pending ||
1953                             !azx_dev->substream ||
1954                             !azx_dev->running)
1955                                 continue;
1956                         ok = azx_position_ok(chip, azx_dev);
1957                         if (ok > 0) {
1958                                 azx_dev->irq_pending = 0;
1959                                 spin_unlock(&chip->reg_lock);
1960                                 snd_pcm_period_elapsed(azx_dev->substream);
1961                                 spin_lock(&chip->reg_lock);
1962                         } else if (ok < 0) {
1963                                 pending = 0;    /* too early */
1964                         } else
1965                                 pending++;
1966                 }
1967                 spin_unlock_irq(&chip->reg_lock);
1968                 if (!pending)
1969                         return;
1970                 msleep(1);
1971         }
1972 }
1973
1974 /* clear irq_pending flags and assure no on-going workq */
1975 static void azx_clear_irq_pending(struct azx *chip)
1976 {
1977         int i;
1978
1979         spin_lock_irq(&chip->reg_lock);
1980         for (i = 0; i < chip->num_streams; i++)
1981                 chip->azx_dev[i].irq_pending = 0;
1982         spin_unlock_irq(&chip->reg_lock);
1983 }
1984
1985 static struct snd_pcm_ops azx_pcm_ops = {
1986         .open = azx_pcm_open,
1987         .close = azx_pcm_close,
1988         .ioctl = snd_pcm_lib_ioctl,
1989         .hw_params = azx_pcm_hw_params,
1990         .hw_free = azx_pcm_hw_free,
1991         .prepare = azx_pcm_prepare,
1992         .trigger = azx_pcm_trigger,
1993         .pointer = azx_pcm_pointer,
1994         .page = snd_pcm_sgbuf_ops_page,
1995 };
1996
1997 static void azx_pcm_free(struct snd_pcm *pcm)
1998 {
1999         struct azx_pcm *apcm = pcm->private_data;
2000         if (apcm) {
2001                 apcm->chip->pcm[pcm->device] = NULL;
2002                 kfree(apcm);
2003         }
2004 }
2005
2006 static int
2007 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2008                       struct hda_pcm *cpcm)
2009 {
2010         struct azx *chip = bus->private_data;
2011         struct snd_pcm *pcm;
2012         struct azx_pcm *apcm;
2013         int pcm_dev = cpcm->device;
2014         int s, err;
2015
2016         if (pcm_dev >= HDA_MAX_PCMS) {
2017                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2018                            pcm_dev);
2019                 return -EINVAL;
2020         }
2021         if (chip->pcm[pcm_dev]) {
2022                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2023                 return -EBUSY;
2024         }
2025         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2026                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2027                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2028                           &pcm);
2029         if (err < 0)
2030                 return err;
2031         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2032         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2033         if (apcm == NULL)
2034                 return -ENOMEM;
2035         apcm->chip = chip;
2036         apcm->codec = codec;
2037         pcm->private_data = apcm;
2038         pcm->private_free = azx_pcm_free;
2039         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2040                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2041         chip->pcm[pcm_dev] = pcm;
2042         cpcm->pcm = pcm;
2043         for (s = 0; s < 2; s++) {
2044                 apcm->hinfo[s] = &cpcm->stream[s];
2045                 if (cpcm->stream[s].substreams)
2046                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2047         }
2048         /* buffer pre-allocation */
2049         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2050                                               snd_dma_pci_data(chip->pci),
2051                                               1024 * 64, 32 * 1024 * 1024);
2052         return 0;
2053 }
2054
2055 /*
2056  * mixer creation - all stuff is implemented in hda module
2057  */
2058 static int __devinit azx_mixer_create(struct azx *chip)
2059 {
2060         return snd_hda_build_controls(chip->bus);
2061 }
2062
2063
2064 /*
2065  * initialize SD streams
2066  */
2067 static int __devinit azx_init_stream(struct azx *chip)
2068 {
2069         int i;
2070
2071         /* initialize each stream (aka device)
2072          * assign the starting bdl address to each stream (device)
2073          * and initialize
2074          */
2075         for (i = 0; i < chip->num_streams; i++) {
2076                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2077                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2078                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2079                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2080                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2081                 azx_dev->sd_int_sta_mask = 1 << i;
2082                 /* stream tag: must be non-zero and unique */
2083                 azx_dev->index = i;
2084                 azx_dev->stream_tag = i + 1;
2085         }
2086
2087         return 0;
2088 }
2089
2090 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2091 {
2092         if (request_irq(chip->pci->irq, azx_interrupt,
2093                         chip->msi ? 0 : IRQF_SHARED,
2094                         "hda_intel", chip)) {
2095                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2096                        "disabling device\n", chip->pci->irq);
2097                 if (do_disconnect)
2098                         snd_card_disconnect(chip->card);
2099                 return -1;
2100         }
2101         chip->irq = chip->pci->irq;
2102         pci_intx(chip->pci, !chip->msi);
2103         return 0;
2104 }
2105
2106
2107 static void azx_stop_chip(struct azx *chip)
2108 {
2109         if (!chip->initialized)
2110                 return;
2111
2112         /* disable interrupts */
2113         azx_int_disable(chip);
2114         azx_int_clear(chip);
2115
2116         /* disable CORB/RIRB */
2117         azx_free_cmd_io(chip);
2118
2119         /* disable position buffer */
2120         azx_writel(chip, DPLBASE, 0);
2121         azx_writel(chip, DPUBASE, 0);
2122
2123         chip->initialized = 0;
2124 }
2125
2126 #ifdef CONFIG_SND_HDA_POWER_SAVE
2127 /* power-up/down the controller */
2128 static void azx_power_notify(struct hda_bus *bus)
2129 {
2130         struct azx *chip = bus->private_data;
2131         struct hda_codec *c;
2132         int power_on = 0;
2133
2134         list_for_each_entry(c, &bus->codec_list, list) {
2135                 if (c->power_on) {
2136                         power_on = 1;
2137                         break;
2138                 }
2139         }
2140         if (power_on)
2141                 azx_init_chip(chip, 1);
2142         else if (chip->running && power_save_controller &&
2143                  !bus->power_keep_link_on)
2144                 azx_stop_chip(chip);
2145 }
2146 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2147
2148 #ifdef CONFIG_PM
2149 /*
2150  * power management
2151  */
2152
2153 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2154 {
2155         struct hda_codec *codec;
2156
2157         list_for_each_entry(codec, &bus->codec_list, list) {
2158                 if (snd_hda_codec_needs_resume(codec))
2159                         return 1;
2160         }
2161         return 0;
2162 }
2163
2164 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2165 {
2166         struct snd_card *card = pci_get_drvdata(pci);
2167         struct azx *chip = card->private_data;
2168         int i;
2169
2170         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2171         azx_clear_irq_pending(chip);
2172         for (i = 0; i < HDA_MAX_PCMS; i++)
2173                 snd_pcm_suspend_all(chip->pcm[i]);
2174         if (chip->initialized)
2175                 snd_hda_suspend(chip->bus);
2176         azx_stop_chip(chip);
2177         if (chip->irq >= 0) {
2178                 free_irq(chip->irq, chip);
2179                 chip->irq = -1;
2180         }
2181         if (chip->msi)
2182                 pci_disable_msi(chip->pci);
2183         pci_disable_device(pci);
2184         pci_save_state(pci);
2185         pci_set_power_state(pci, pci_choose_state(pci, state));
2186         return 0;
2187 }
2188
2189 static int azx_resume(struct pci_dev *pci)
2190 {
2191         struct snd_card *card = pci_get_drvdata(pci);
2192         struct azx *chip = card->private_data;
2193
2194         pci_set_power_state(pci, PCI_D0);
2195         pci_restore_state(pci);
2196         if (pci_enable_device(pci) < 0) {
2197                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2198                        "disabling device\n");
2199                 snd_card_disconnect(card);
2200                 return -EIO;
2201         }
2202         pci_set_master(pci);
2203         if (chip->msi)
2204                 if (pci_enable_msi(pci) < 0)
2205                         chip->msi = 0;
2206         if (azx_acquire_irq(chip, 1) < 0)
2207                 return -EIO;
2208         azx_init_pci(chip);
2209
2210         if (snd_hda_codecs_inuse(chip->bus))
2211                 azx_init_chip(chip, 1);
2212
2213         snd_hda_resume(chip->bus);
2214         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2215         return 0;
2216 }
2217 #endif /* CONFIG_PM */
2218
2219
2220 /*
2221  * reboot notifier for hang-up problem at power-down
2222  */
2223 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2224 {
2225         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2226         snd_hda_bus_reboot_notify(chip->bus);
2227         azx_stop_chip(chip);
2228         return NOTIFY_OK;
2229 }
2230
2231 static void azx_notifier_register(struct azx *chip)
2232 {
2233         chip->reboot_notifier.notifier_call = azx_halt;
2234         register_reboot_notifier(&chip->reboot_notifier);
2235 }
2236
2237 static void azx_notifier_unregister(struct azx *chip)
2238 {
2239         if (chip->reboot_notifier.notifier_call)
2240                 unregister_reboot_notifier(&chip->reboot_notifier);
2241 }
2242
2243 /*
2244  * destructor
2245  */
2246 static int azx_free(struct azx *chip)
2247 {
2248         int i;
2249
2250         azx_notifier_unregister(chip);
2251
2252         if (chip->initialized) {
2253                 azx_clear_irq_pending(chip);
2254                 for (i = 0; i < chip->num_streams; i++)
2255                         azx_stream_stop(chip, &chip->azx_dev[i]);
2256                 azx_stop_chip(chip);
2257         }
2258
2259         if (chip->irq >= 0)
2260                 free_irq(chip->irq, (void*)chip);
2261         if (chip->msi)
2262                 pci_disable_msi(chip->pci);
2263         if (chip->remap_addr)
2264                 iounmap(chip->remap_addr);
2265
2266         if (chip->azx_dev) {
2267                 for (i = 0; i < chip->num_streams; i++)
2268                         if (chip->azx_dev[i].bdl.area)
2269                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2270         }
2271         if (chip->rb.area)
2272                 snd_dma_free_pages(&chip->rb);
2273         if (chip->posbuf.area)
2274                 snd_dma_free_pages(&chip->posbuf);
2275         pci_release_regions(chip->pci);
2276         pci_disable_device(chip->pci);
2277         kfree(chip->azx_dev);
2278         kfree(chip);
2279
2280         return 0;
2281 }
2282
2283 static int azx_dev_free(struct snd_device *device)
2284 {
2285         return azx_free(device->device_data);
2286 }
2287
2288 /*
2289  * white/black-listing for position_fix
2290  */
2291 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2292         SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2293         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2294         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2295         SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2296         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2297         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2298         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2299         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2300         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2301         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2302         SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2303         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2304         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2305         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2306         SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2307         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2308         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2309         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2310         SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2311         {}
2312 };
2313
2314 static int __devinit check_position_fix(struct azx *chip, int fix)
2315 {
2316         const struct snd_pci_quirk *q;
2317
2318         switch (fix) {
2319         case POS_FIX_LPIB:
2320         case POS_FIX_POSBUF:
2321                 return fix;
2322         }
2323
2324         /* Check VIA/ATI HD Audio Controller exist */
2325         switch (chip->driver_type) {
2326         case AZX_DRIVER_VIA:
2327         case AZX_DRIVER_ATI:
2328                 chip->via_dmapos_patch = 1;
2329                 /* Use link position directly, avoid any transfer problem. */
2330                 return POS_FIX_LPIB;
2331         }
2332         chip->via_dmapos_patch = 0;
2333
2334         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2335         if (q) {
2336                 printk(KERN_INFO
2337                        "hda_intel: position_fix set to %d "
2338                        "for device %04x:%04x\n",
2339                        q->value, q->subvendor, q->subdevice);
2340                 return q->value;
2341         }
2342         return POS_FIX_AUTO;
2343 }
2344
2345 /*
2346  * black-lists for probe_mask
2347  */
2348 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2349         /* Thinkpad often breaks the controller communication when accessing
2350          * to the non-working (or non-existing) modem codec slot.
2351          */
2352         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2353         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2354         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2355         /* broken BIOS */
2356         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2357         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2358         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2359         /* forced codec slots */
2360         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2361         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2362         {}
2363 };
2364
2365 #define AZX_FORCE_CODEC_MASK    0x100
2366
2367 static void __devinit check_probe_mask(struct azx *chip, int dev)
2368 {
2369         const struct snd_pci_quirk *q;
2370
2371         chip->codec_probe_mask = probe_mask[dev];
2372         if (chip->codec_probe_mask == -1) {
2373                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2374                 if (q) {
2375                         printk(KERN_INFO
2376                                "hda_intel: probe_mask set to 0x%x "
2377                                "for device %04x:%04x\n",
2378                                q->value, q->subvendor, q->subdevice);
2379                         chip->codec_probe_mask = q->value;
2380                 }
2381         }
2382
2383         /* check forced option */
2384         if (chip->codec_probe_mask != -1 &&
2385             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2386                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2387                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2388                        chip->codec_mask);
2389         }
2390 }
2391
2392 /*
2393  * white/black-list for enable_msi
2394  */
2395 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2396         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2397         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2398         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2399         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2400         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2401         {}
2402 };
2403
2404 static void __devinit check_msi(struct azx *chip)
2405 {
2406         const struct snd_pci_quirk *q;
2407
2408         if (enable_msi >= 0) {
2409                 chip->msi = !!enable_msi;
2410                 return;
2411         }
2412         chip->msi = 1;  /* enable MSI as default */
2413         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2414         if (q) {
2415                 printk(KERN_INFO
2416                        "hda_intel: msi for device %04x:%04x set to %d\n",
2417                        q->subvendor, q->subdevice, q->value);
2418                 chip->msi = q->value;
2419                 return;
2420         }
2421
2422         /* NVidia chipsets seem to cause troubles with MSI */
2423         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2424                 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2425                 chip->msi = 0;
2426         }
2427 }
2428
2429
2430 /*
2431  * constructor
2432  */
2433 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2434                                 int dev, int driver_type,
2435                                 struct azx **rchip)
2436 {
2437         struct azx *chip;
2438         int i, err;
2439         unsigned short gcap;
2440         static struct snd_device_ops ops = {
2441                 .dev_free = azx_dev_free,
2442         };
2443
2444         *rchip = NULL;
2445
2446         err = pci_enable_device(pci);
2447         if (err < 0)
2448                 return err;
2449
2450         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2451         if (!chip) {
2452                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2453                 pci_disable_device(pci);
2454                 return -ENOMEM;
2455         }
2456
2457         spin_lock_init(&chip->reg_lock);
2458         mutex_init(&chip->open_mutex);
2459         chip->card = card;
2460         chip->pci = pci;
2461         chip->irq = -1;
2462         chip->driver_type = driver_type;
2463         check_msi(chip);
2464         chip->dev_index = dev;
2465         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2466
2467         chip->position_fix[0] = chip->position_fix[1] =
2468                 check_position_fix(chip, position_fix[dev]);
2469         check_probe_mask(chip, dev);
2470
2471         chip->single_cmd = single_cmd;
2472
2473         if (bdl_pos_adj[dev] < 0) {
2474                 switch (chip->driver_type) {
2475                 case AZX_DRIVER_ICH:
2476                 case AZX_DRIVER_PCH:
2477                         bdl_pos_adj[dev] = 1;
2478                         break;
2479                 default:
2480                         bdl_pos_adj[dev] = 32;
2481                         break;
2482                 }
2483         }
2484
2485 #if BITS_PER_LONG != 64
2486         /* Fix up base address on ULI M5461 */
2487         if (chip->driver_type == AZX_DRIVER_ULI) {
2488                 u16 tmp3;
2489                 pci_read_config_word(pci, 0x40, &tmp3);
2490                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2491                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2492         }
2493 #endif
2494
2495         err = pci_request_regions(pci, "ICH HD audio");
2496         if (err < 0) {
2497                 kfree(chip);
2498                 pci_disable_device(pci);
2499                 return err;
2500         }
2501
2502         chip->addr = pci_resource_start(pci, 0);
2503         chip->remap_addr = pci_ioremap_bar(pci, 0);
2504         if (chip->remap_addr == NULL) {
2505                 snd_printk(KERN_ERR SFX "ioremap error\n");
2506                 err = -ENXIO;
2507                 goto errout;
2508         }
2509
2510         if (chip->msi)
2511                 if (pci_enable_msi(pci) < 0)
2512                         chip->msi = 0;
2513
2514         if (azx_acquire_irq(chip, 0) < 0) {
2515                 err = -EBUSY;
2516                 goto errout;
2517         }
2518
2519         pci_set_master(pci);
2520         synchronize_irq(chip->irq);
2521
2522         gcap = azx_readw(chip, GCAP);
2523         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2524
2525         /* disable SB600 64bit support for safety */
2526         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2527             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2528                 struct pci_dev *p_smbus;
2529                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2530                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2531                                          NULL);
2532                 if (p_smbus) {
2533                         if (p_smbus->revision < 0x30)
2534                                 gcap &= ~ICH6_GCAP_64OK;
2535                         pci_dev_put(p_smbus);
2536                 }
2537         }
2538
2539         /* disable 64bit DMA address for Teradici */
2540         /* it does not work with device 6549:1200 subsys e4a2:040b */
2541         if (chip->driver_type == AZX_DRIVER_TERA)
2542                 gcap &= ~ICH6_GCAP_64OK;
2543
2544         /* allow 64bit DMA address if supported by H/W */
2545         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2546                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2547         else {
2548                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2549                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2550         }
2551
2552         /* read number of streams from GCAP register instead of using
2553          * hardcoded value
2554          */
2555         chip->capture_streams = (gcap >> 8) & 0x0f;
2556         chip->playback_streams = (gcap >> 12) & 0x0f;
2557         if (!chip->playback_streams && !chip->capture_streams) {
2558                 /* gcap didn't give any info, switching to old method */
2559
2560                 switch (chip->driver_type) {
2561                 case AZX_DRIVER_ULI:
2562                         chip->playback_streams = ULI_NUM_PLAYBACK;
2563                         chip->capture_streams = ULI_NUM_CAPTURE;
2564                         break;
2565                 case AZX_DRIVER_ATIHDMI:
2566                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2567                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2568                         break;
2569                 case AZX_DRIVER_GENERIC:
2570                 default:
2571                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2572                         chip->capture_streams = ICH6_NUM_CAPTURE;
2573                         break;
2574                 }
2575         }
2576         chip->capture_index_offset = 0;
2577         chip->playback_index_offset = chip->capture_streams;
2578         chip->num_streams = chip->playback_streams + chip->capture_streams;
2579         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2580                                 GFP_KERNEL);
2581         if (!chip->azx_dev) {
2582                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2583                 goto errout;
2584         }
2585
2586         for (i = 0; i < chip->num_streams; i++) {
2587                 /* allocate memory for the BDL for each stream */
2588                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2589                                           snd_dma_pci_data(chip->pci),
2590                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2591                 if (err < 0) {
2592                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2593                         goto errout;
2594                 }
2595         }
2596         /* allocate memory for the position buffer */
2597         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2598                                   snd_dma_pci_data(chip->pci),
2599                                   chip->num_streams * 8, &chip->posbuf);
2600         if (err < 0) {
2601                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2602                 goto errout;
2603         }
2604         /* allocate CORB/RIRB */
2605         err = azx_alloc_cmd_io(chip);
2606         if (err < 0)
2607                 goto errout;
2608
2609         /* initialize streams */
2610         azx_init_stream(chip);
2611
2612         /* initialize chip */
2613         azx_init_pci(chip);
2614         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2615
2616         /* codec detection */
2617         if (!chip->codec_mask) {
2618                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2619                 err = -ENODEV;
2620                 goto errout;
2621         }
2622
2623         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2624         if (err <0) {
2625                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2626                 goto errout;
2627         }
2628
2629         strcpy(card->driver, "HDA-Intel");
2630         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2631                 sizeof(card->shortname));
2632         snprintf(card->longname, sizeof(card->longname),
2633                  "%s at 0x%lx irq %i",
2634                  card->shortname, chip->addr, chip->irq);
2635
2636         *rchip = chip;
2637         return 0;
2638
2639  errout:
2640         azx_free(chip);
2641         return err;
2642 }
2643
2644 static void power_down_all_codecs(struct azx *chip)
2645 {
2646 #ifdef CONFIG_SND_HDA_POWER_SAVE
2647         /* The codecs were powered up in snd_hda_codec_new().
2648          * Now all initialization done, so turn them down if possible
2649          */
2650         struct hda_codec *codec;
2651         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2652                 snd_hda_power_down(codec);
2653         }
2654 #endif
2655 }
2656
2657 static int __devinit azx_probe(struct pci_dev *pci,
2658                                const struct pci_device_id *pci_id)
2659 {
2660         static int dev;
2661         struct snd_card *card;
2662         struct azx *chip;
2663         int err;
2664
2665         if (dev >= SNDRV_CARDS)
2666                 return -ENODEV;
2667         if (!enable[dev]) {
2668                 dev++;
2669                 return -ENOENT;
2670         }
2671
2672         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2673         if (err < 0) {
2674                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2675                 return err;
2676         }
2677
2678         /* set this here since it's referred in snd_hda_load_patch() */
2679         snd_card_set_dev(card, &pci->dev);
2680
2681         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2682         if (err < 0)
2683                 goto out_free;
2684         card->private_data = chip;
2685
2686 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2687         chip->beep_mode = beep_mode[dev];
2688 #endif
2689
2690         /* create codec instances */
2691         err = azx_codec_create(chip, model[dev]);
2692         if (err < 0)
2693                 goto out_free;
2694 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2695         if (patch[dev]) {
2696                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2697                            patch[dev]);
2698                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2699                 if (err < 0)
2700                         goto out_free;
2701         }
2702 #endif
2703         if ((probe_only[dev] & 1) == 0) {
2704                 err = azx_codec_configure(chip);
2705                 if (err < 0)
2706                         goto out_free;
2707         }
2708
2709         /* create PCM streams */
2710         err = snd_hda_build_pcms(chip->bus);
2711         if (err < 0)
2712                 goto out_free;
2713
2714         /* create mixer controls */
2715         err = azx_mixer_create(chip);
2716         if (err < 0)
2717                 goto out_free;
2718
2719         err = snd_card_register(card);
2720         if (err < 0)
2721                 goto out_free;
2722
2723         pci_set_drvdata(pci, card);
2724         chip->running = 1;
2725         power_down_all_codecs(chip);
2726         azx_notifier_register(chip);
2727
2728         dev++;
2729         return err;
2730 out_free:
2731         snd_card_free(card);
2732         return err;
2733 }
2734
2735 static void __devexit azx_remove(struct pci_dev *pci)
2736 {
2737         snd_card_free(pci_get_drvdata(pci));
2738         pci_set_drvdata(pci, NULL);
2739 }
2740
2741 /* PCI IDs */
2742 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2743         /* ICH 6..10 */
2744         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2745         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2746         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2747         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2748         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2749         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2750         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2751         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2752         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2753         /* PCH */
2754         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2755         { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
2756         /* CPT */
2757         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2758         /* PBG */
2759         { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
2760         /* SCH */
2761         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2762         /* ATI SB 450/600 */
2763         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2764         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2765         /* ATI HDMI */
2766         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2767         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2768         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2769         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2770         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2771         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2772         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2773         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2774         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2775         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2776         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2777         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2778         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2779         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2780         /* VIA VT8251/VT8237A */
2781         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2782         /* SIS966 */
2783         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2784         /* ULI M5461 */
2785         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2786         /* NVIDIA MCP */
2787         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2788           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2789           .class_mask = 0xffffff,
2790           .driver_data = AZX_DRIVER_NVIDIA },
2791         /* Teradici */
2792         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2793         /* Creative X-Fi (CA0110-IBG) */
2794 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2795         /* the following entry conflicts with snd-ctxfi driver,
2796          * as ctxfi driver mutates from HD-audio to native mode with
2797          * a special command sequence.
2798          */
2799         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2800           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2801           .class_mask = 0xffffff,
2802           .driver_data = AZX_DRIVER_GENERIC },
2803 #else
2804         /* this entry seems still valid -- i.e. without emu20kx chip */
2805         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2806 #endif
2807         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2808         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2809           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2810           .class_mask = 0xffffff,
2811           .driver_data = AZX_DRIVER_GENERIC },
2812         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2813           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2814           .class_mask = 0xffffff,
2815           .driver_data = AZX_DRIVER_GENERIC },
2816         { 0, }
2817 };
2818 MODULE_DEVICE_TABLE(pci, azx_ids);
2819
2820 /* pci_driver definition */
2821 static struct pci_driver driver = {
2822         .name = "HDA Intel",
2823         .id_table = azx_ids,
2824         .probe = azx_probe,
2825         .remove = __devexit_p(azx_remove),
2826 #ifdef CONFIG_PM
2827         .suspend = azx_suspend,
2828         .resume = azx_resume,
2829 #endif
2830 };
2831
2832 static int __init alsa_card_azx_init(void)
2833 {
2834         return pci_register_driver(&driver);
2835 }
2836
2837 static void __exit alsa_card_azx_exit(void)
2838 {
2839         pci_unregister_driver(&driver);
2840 }
2841
2842 module_init(alsa_card_azx_init)
2843 module_exit(alsa_card_azx_exit)