drivers/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2009 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14
  15 /* Notes:
  16  * 1. there should be 2 types of register access method, one for
  17  *    UART ports, the other for the general purpose registers
  18  *
  19  * 2. It used to have a Irda port, but was defeatured recently
  20  *
  21  * 3. Based on the info from HSU MAS, 0/1 channel are assigned to
  22  *    port0, 2/3 chan to port 1, 4/5 chan to port 3. Even number
  23  *    chan will be read, odd chan for write
  24  *
  25  * 4. HUS supports both the 64B and 16B FIFO version, but this driver
  26  *    will only use 64B version
  27  *
  28  * 5. In A0 stepping, UART will not support TX half empty flag, thus
  29  *    need add a #ifdef judgement
  30  *
  31  * 6. One more bug for A0, the loopback mode won't support AFC
  32  *    auto-flow control
  33  *
  34  * 7. HSU has some special FCR control bits, we add it to serial_reg.h
  35  *
  36  * 8. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always asserted,
  37  *    only when the HW is reset the DDCD and DDSR will be triggered
  38  */
  39
  40 #include <linux/module.h>
  41 #include <linux/init.h>
  42 #include <linux/console.h>
  43 #include <linux/sysrq.h>
  44 #include <linux/serial_reg.h>
  45 #include <linux/circ_buf.h>
  46 #include <linux/delay.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/tty.h>
  49 #include <linux/tty_flip.h>
  50 #include <linux/serial_core.h>
  51 #include <linux/serial_mfd.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/pci.h>
  54 #include <linux/io.h>
  55 #include <linux/debugfs.h>
  56
  57 #define  MFD_HSU_A0_STEPPING    1
  58
  59 #define HSU_DMA_BUF_SIZE        2048
  60
  61 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  62 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  63
  64 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  65 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  66
  67 #define HSU_DMA_TIMEOUT_CHECK_FREQ      (HZ/10)
  68
  69 struct hsu_dma_buffer {
  70         u8              *buf;
  71         dma_addr_t      dma_addr;
  72         u32             dma_size;
  73         u32             ofs;
  74 };
  75
  76 struct hsu_dma_chan {
  77         u32     id;
  78         u32     dirt;   /* to or from device */
  79         struct uart_hsu_port    *uport;
  80         void __iomem            *reg;
  81         struct timer_list       rx_timer; /* only needed by RX channel */
  82 };
  83
  84 struct uart_hsu_port {
  85         struct uart_port        port;
  86         unsigned char           ier;
  87         unsigned char           lcr;
  88         unsigned char           mcr;
  89         unsigned int            lsr_break_flag;
  90         char                    name[12];
  91         int                     index;
  92         struct device           *dev;
  93
  94         struct hsu_dma_chan     *txc;
  95         struct hsu_dma_chan     *rxc;
  96         struct hsu_dma_buffer   txbuf;
  97         struct hsu_dma_buffer   rxbuf;
  98         int                     use_dma;        /* flag for DMA/PIO */
  99         int                     running;
 100         int                     dma_tx_on;
 101 };
 102
 103 /* Top level data structure of HSU */
 104 struct hsu_port {
 105         struct pci_device       *pdev;
 106
 107         void __iomem    *reg;
 108         unsigned long   paddr;
 109         unsigned long   iolen;
 110         u32             irq;
 111
 112         struct uart_hsu_port    port[3];
 113         struct hsu_dma_chan     chans[10];
 114
 115 #ifdef CONFIG_DEBUG_FS
 116         struct dentry *debugfs;
 117 #endif
 118 };
 119
 120 static inline void hexdump(char *str, u8 *addr, int cnt)
 121 {
 122         int i;
 123
 124         for (i = 0; i < cnt; i += 8) {
 125                 printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
 126                         addr[i], addr[i+1], addr[i+2], addr[i+3],
 127                         addr[i+4], addr[i+5], addr[i+6], addr[i+7]);
 128                 printk("\n");
 129         }
 130 }
 131
 132 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 133 {
 134         unsigned int val;
 135
 136         if (offset > UART_MSR) {
 137                 offset <<= 2;
 138                 val = readl(up->port.membase + offset);
 139         } else
 140                 val = (unsigned int)readb(up->port.membase + offset);
 141
 142         return val;
 143 }
 144
 145 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 146 {
 147         if (offset > UART_MSR) {
 148                 offset <<= 2;
 149                 writel(value, up->port.membase + offset);
 150         } else {
 151                 unsigned char val = value & 0xff;
 152                 writeb(val, up->port.membase + offset);
 153         }
 154 }
 155
 156 #ifdef CONFIG_DEBUG_FS
 157
 158 #define HSU_REGS_BUFSIZE        1024
 159
 160 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 161 {
 162         file->private_data = inode->i_private;
 163         return 0;
 164 }
 165
 166 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 167                                 size_t count, loff_t *ppos)
 168 {
 169         struct uart_hsu_port *up = file->private_data;
 170         char *buf;
 171         u32 len = 0;
 172         ssize_t ret;
 173
 174         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 175         if (!buf)
 176                 return 0;
 177
 178         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 179                         "MFD HSU port[%d] regs:\n", up->index);
 180
 181         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 182                         "=================================\n");
 183         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 184                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 185         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 186                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 187         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 188                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 189         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 190                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 191         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 192                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 193         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 194                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 195         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 196                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 197         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 198                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 199         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 200                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 201         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 202                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 203
 204         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 205         kfree(buf);
 206         return ret;
 207 }
 208
 209 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 210                                 size_t count, loff_t *ppos)
 211 {
 212         struct hsu_dma_chan *chan = file->private_data;
 213         char *buf;
 214         u32 len = 0;
 215         ssize_t ret;
 216
 217         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 218         if (!buf)
 219                 return 0;
 220
 221         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 222                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 223
 224         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 225                         "=================================\n");
 226         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 227                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 228         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 229                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 230         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 231                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 232         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 233                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 234         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 235                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 236         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 237                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 238         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 239                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 240         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 241                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 242         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 243                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 244         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 245                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 246         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 247                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 248         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 249                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 250
 251         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 252         kfree(buf);
 253         return ret;
 254 }
 255
 256 static const struct file_operations port_regs_ops = {
 257         .owner          = THIS_MODULE,
 258         .open           = hsu_show_regs_open,
 259         .read           = port_show_regs,
 260 };
 261
 262 static const struct file_operations dma_regs_ops = {
 263         .owner          = THIS_MODULE,
 264         .open           = hsu_show_regs_open,
 265         .read           = dma_show_regs,
 266 };
 267
 268 static int hsu_debugfs_init(struct hsu_port *hsu)
 269 {
 270         int i;
 271         char name[32];
 272
 273         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 274         if (!hsu->debugfs)
 275                 return -ENOMEM;
 276
 277         for (i = 0; i < 3; i++) {
 278                 snprintf(name, sizeof(name), "port_%d_regs", i);
 279                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 280                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 281         }
 282
 283         for (i = 0; i < 6; i++) {
 284                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 285                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 286                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 287         }
 288
 289         return 0;
 290 }
 291
 292 static void hsu_debugfs_remove(struct hsu_port *hsu)
 293 {
 294         if (hsu->debugfs)
 295                 debugfs_remove_recursive(hsu->debugfs);
 296 }
 297
 298 #else
 299 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 300 {
 301         return 0;
 302 }
 303
 304 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 305 {
 306 }
 307 #endif /* CONFIG_DEBUG_FS */
 308
 309 static void serial_hsu_enable_ms(struct uart_port *port)
 310 {
 311         struct uart_hsu_port *up =
 312                 container_of(port, struct uart_hsu_port, port);
 313
 314         up->ier |= UART_IER_MSI;
 315         serial_out(up, UART_IER, up->ier);
 316 }
 317
 318 void hsu_dma_tx(struct uart_hsu_port *up)
 319 {
 320         struct circ_buf *xmit = &up->port.state->xmit;
 321         struct hsu_dma_buffer *dbuf = &up->txbuf;
 322         int count;
 323
 324         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 325         if (up->dma_tx_on)
 326                 return;
 327
 328         /* Update the circ buf info */
 329         xmit->tail += dbuf->ofs;
 330         xmit->tail &= UART_XMIT_SIZE - 1;
 331
 332         up->port.icount.tx += dbuf->ofs;
 333         dbuf->ofs = 0;
 334
 335         /* Disable the channel */
 336         chan_writel(up->txc, HSU_CH_CR, 0x0);
 337
 338         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 339                 dma_sync_single_for_device(up->port.dev,
 340                                            dbuf->dma_addr,
 341                                            dbuf->dma_size,
 342                                            DMA_TO_DEVICE);
 343
 344                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 345                 dbuf->ofs = count;
 346
 347                 /* Reprogram the channel */
 348                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 349                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 350
 351                 /* Reenable the channel */
 352                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 353                                                  | (0x1 << 8)
 354                                                  | (0x1 << 16)
 355                                                  | (0x1 << 24));
 356
 357                 WARN(chan_readl(up->txc, HSU_CH_CR) & 0x1,
 358                         "TX channel has already be started!!\n");
 359                 up->dma_tx_on = 1;
 360                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 361         }
 362
 363         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 364                 uart_write_wakeup(&up->port);
 365 }
 366
 367 /* The buffer is already cache coherent */
 368 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 369 {
 370         /* Need start RX dma channel here */
 371         dbuf->ofs = 0;
 372
 373         chan_writel(rxc, HSU_CH_BSR, 32);
 374         chan_writel(rxc, HSU_CH_MOTSR, 4);
 375
 376         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 377         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 378         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 379                                          | (0x1 << 16)
 380                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 381                                          );
 382         chan_writel(rxc, HSU_CH_CR, 0x3);
 383
 384         mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
 385 }
 386
 387 /* Protected by spin_lock_irqsave(port->lock) */
 388 static void serial_hsu_start_tx(struct uart_port *port)
 389 {
 390         struct uart_hsu_port *up =
 391                 container_of(port, struct uart_hsu_port, port);
 392
 393         if (up->use_dma) {
 394                 hsu_dma_tx(up);
 395         } else if (!(up->ier & UART_IER_THRI)) {
 396                 up->ier |= UART_IER_THRI;
 397                 serial_out(up, UART_IER, up->ier);
 398         }
 399 }
 400
 401 static void serial_hsu_stop_tx(struct uart_port *port)
 402 {
 403         struct uart_hsu_port *up =
 404                 container_of(port, struct uart_hsu_port, port);
 405         struct hsu_dma_chan *txc = up->txc;
 406
 407         if (up->use_dma)
 408                 chan_writel(txc, HSU_CH_CR, 0x0);
 409         else if (up->ier & UART_IER_THRI) {
 410                 up->ier &= ~UART_IER_THRI;
 411                 serial_out(up, UART_IER, up->ier);
 412         }
 413 }
 414
 415 /* This is always called in spinlock protected mode, so
 416  * modify timeout timer is safe here */
 417 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 418 {
 419         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 420         struct hsu_dma_chan *chan = up->rxc;
 421         struct uart_port *port = &up->port;
 422         struct tty_struct *tty = port->state->port.tty;
 423         int count;
 424
 425         if (!tty)
 426                 return;
 427
 428         /*
 429          * first need to know how many is already transferred,
 430          * then check if its a timeout DMA irq, and return
 431          * the trail bytes out, push them up and reenable the
 432          * channel, better to use 2 descriptors at the same time
 433          */
 434
 435         /* timeout IRQ, need wait some time, see Errata 2 */
 436         if (int_sts & 0xf00)
 437                 udelay(2);
 438
 439         /* Stop the channel */
 440         chan_writel(chan, HSU_CH_CR, 0x0);
 441
 442         /* We can use 2 ways to calc the actual transfer len */
 443         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 444
 445         if (!count) {
 446                 /* restart the channel before we leave */
 447                 chan_writel(chan, HSU_CH_CR, 0x3);
 448                 return;
 449         }
 450
 451         del_timer(&chan->rx_timer);
 452
 453         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 454                         dbuf->dma_size, DMA_FROM_DEVICE);
 455
 456         /*
 457          * head will only wrap around when we recycle
 458          * the DMA buffer, and when that happens, we
 459          * explicitly set tail to 0. So head will
 460          * always be greater than tail.
 461          */
 462         tty_insert_flip_string(tty, dbuf->buf, count);
 463         port->icount.rx += count;
 464
 465         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 466                         dbuf->dma_size, DMA_FROM_DEVICE);
 467
 468         /* Reprogram the channel */
 469         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 470         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 471         chan_writel(chan, HSU_CH_DCR, 0x1
 472                                          | (0x1 << 8)
 473                                          | (0x1 << 16)
 474                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 475                                          );
 476         tty_flip_buffer_push(tty);
 477
 478         chan_writel(chan, HSU_CH_CR, 0x3);
 479         chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
 480         add_timer(&chan->rx_timer);
 481
 482 }
 483
 484 static void serial_hsu_stop_rx(struct uart_port *port)
 485 {
 486         struct uart_hsu_port *up =
 487                 container_of(port, struct uart_hsu_port, port);
 488         struct hsu_dma_chan *chan = up->rxc;
 489
 490         if (up->use_dma)
 491                 chan_writel(chan, HSU_CH_CR, 0x2);
 492         else {
 493                 up->ier &= ~UART_IER_RLSI;
 494                 up->port.read_status_mask &= ~UART_LSR_DR;
 495                 serial_out(up, UART_IER, up->ier);
 496         }
 497 }
 498
 499 /*
 500  * if there is error flag, should we just reset the FIFO or keeps
 501  * working on it
 502  */
 503 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 504 {
 505         struct tty_struct *tty = up->port.state->port.tty;
 506         unsigned int ch, flag;
 507         unsigned int max_count = 256;
 508
 509         if (!tty)
 510                 return;
 511
 512         do {
 513                 ch = serial_in(up, UART_RX);
 514                 flag = TTY_NORMAL;
 515                 up->port.icount.rx++;
 516
 517                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 518                                        UART_LSR_FE | UART_LSR_OE))) {
 519
 520                         dev_warn(up->dev, "We really rush into ERR/BI case"
 521                                 "status = 0x%02x", *status);
 522                         /* For statistics only */
 523                         if (*status & UART_LSR_BI) {
 524                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 525                                 up->port.icount.brk++;
 526                                 /*
 527                                  * We do the SysRQ and SAK checking
 528                                  * here because otherwise the break
 529                                  * may get masked by ignore_status_mask
 530                                  * or read_status_mask.
 531                                  */
 532                                 if (uart_handle_break(&up->port))
 533                                         goto ignore_char;
 534                         } else if (*status & UART_LSR_PE)
 535                                 up->port.icount.parity++;
 536                         else if (*status & UART_LSR_FE)
 537                                 up->port.icount.frame++;
 538                         if (*status & UART_LSR_OE)
 539                                 up->port.icount.overrun++;
 540
 541                         /* Mask off conditions which should be ignored. */
 542                         *status &= up->port.read_status_mask;
 543
 544 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 545                         if (up->port.cons &&
 546                                 up->port.cons->index == up->port.line) {
 547                                 /* Recover the break flag from console xmit */
 548                                 *status |= up->lsr_break_flag;
 549                                 up->lsr_break_flag = 0;
 550                         }
 551 #endif
 552                         if (*status & UART_LSR_BI) {
 553                                 flag = TTY_BREAK;
 554                         } else if (*status & UART_LSR_PE)
 555                                 flag = TTY_PARITY;
 556                         else if (*status & UART_LSR_FE)
 557                                 flag = TTY_FRAME;
 558                 }
 559
 560                 if (uart_handle_sysrq_char(&up->port, ch))
 561                         goto ignore_char;
 562
 563                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 564         ignore_char:
 565                 *status = serial_in(up, UART_LSR);
 566         } while ((*status & UART_LSR_DR) && max_count--);
 567         tty_flip_buffer_push(tty);
 568 }
 569
 570 static void transmit_chars(struct uart_hsu_port *up)
 571 {
 572         struct circ_buf *xmit = &up->port.state->xmit;
 573         int count;
 574         int i = 0; /* for debug use */
 575
 576         if (up->port.x_char) {
 577                 serial_out(up, UART_TX, up->port.x_char);
 578                 up->port.icount.tx++;
 579                 up->port.x_char = 0;
 580                 return;
 581         }
 582         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 583                 serial_hsu_stop_tx(&up->port);
 584                 return;
 585         }
 586
 587 #ifndef MFD_HSU_A0_STEPPING
 588         count = up->port.fifosize / 2;
 589 #else
 590         /*
 591          * A0 only supports fully empty IRQ, and the first char written
 592          * into it won't clear the EMPT bit, so we may need be cautious
 593          * by useing a shorter buffer
 594          */
 595         /* count = up->port.fifosize; */
 596         count = up->port.fifosize - 4;
 597 #endif
 598         do {
 599                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 600                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 601                 i++;
 602
 603                 up->port.icount.tx++;
 604                 if (uart_circ_empty(xmit))
 605                         break;
 606         } while (--count > 0);
 607
 608         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 609                 uart_write_wakeup(&up->port);
 610
 611         if (uart_circ_empty(xmit))
 612                 serial_hsu_stop_tx(&up->port);
 613 }
 614
 615 static inline void check_modem_status(struct uart_hsu_port *up)
 616 {
 617         int status;
 618
 619         status = serial_in(up, UART_MSR);
 620
 621         if ((status & UART_MSR_ANY_DELTA) == 0)
 622                 return;
 623
 624         if (status & UART_MSR_TERI)
 625                 up->port.icount.rng++;
 626         if (status & UART_MSR_DDSR)
 627                 up->port.icount.dsr++;
 628         /* We may only get DDCD when HW init and reset */
 629         if (status & UART_MSR_DDCD)
 630                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 631         /* will start/stop_tx accordingly */
 632         if (status & UART_MSR_DCTS)
 633                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 634
 635         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 636 }
 637
 638 /*
 639  * This handles the interrupt from one port.
 640  */
 641 static irqreturn_t port_irq(int irq, void *dev_id)
 642 {
 643         struct uart_hsu_port *up = dev_id;
 644         unsigned int iir, lsr;
 645         unsigned long flags;
 646
 647         if (unlikely(!up->running))
 648                 return IRQ_NONE;
 649
 650         if (up->use_dma) {
 651                 lsr = serial_in(up, UART_LSR);
 652                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 653                                        UART_LSR_FE | UART_LSR_OE)))
 654                         dev_warn(up->dev,
 655                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 656                                 lsr);
 657                 check_modem_status(up);
 658                 return IRQ_HANDLED;
 659         }
 660
 661         spin_lock_irqsave(&up->port.lock, flags);
 662         iir = serial_in(up, UART_IIR);
 663         if (iir & UART_IIR_NO_INT) {
 664                 spin_unlock_irqrestore(&up->port.lock, flags);
 665                 return IRQ_NONE;
 666         }
 667
 668         lsr = serial_in(up, UART_LSR);
 669
 670         if (lsr & UART_LSR_DR)
 671                 receive_chars(up, &lsr);
 672
 673         /* lsr will be renewed during the receive_chars */
 674         if (lsr & UART_LSR_THRE)
 675                 transmit_chars(up);
 676
 677         spin_unlock_irqrestore(&up->port.lock, flags);
 678         return IRQ_HANDLED;
 679 }
 680
 681 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 682 {
 683         struct uart_hsu_port *up = chan->uport;
 684         unsigned long flags;
 685         u32 int_sts;
 686
 687         spin_lock_irqsave(&up->port.lock, flags);
 688
 689         if (!up->use_dma || !up->running)
 690                 goto exit;
 691
 692         /*
 693          * No matter what situation, need read clear the IRQ status
 694          * There is a bug, see Errata 5, HSD 2900918
 695          */
 696         int_sts = chan_readl(chan, HSU_CH_SR);
 697
 698         /* Rx channel */
 699         if (chan->dirt == DMA_FROM_DEVICE)
 700                 hsu_dma_rx(up, int_sts);
 701
 702         /* Tx channel */
 703         if (chan->dirt == DMA_TO_DEVICE) {
 704                 /* dma for irq should be done */
 705                 chan_writel(chan, HSU_CH_CR, 0x0);
 706                 up->dma_tx_on = 0;
 707                 hsu_dma_tx(up);
 708         }
 709
 710 exit:
 711         spin_unlock_irqrestore(&up->port.lock, flags);
 712         return;
 713 }
 714
 715 static irqreturn_t dma_irq(int irq, void *dev_id)
 716 {
 717         struct hsu_port *hsu = dev_id;
 718         u32 int_sts, i;
 719
 720         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 721
 722         /* Currently we only have 6 channels may be used */
 723         for (i = 0; i < 6; i++) {
 724                 if (int_sts & 0x1)
 725                         dma_chan_irq(&hsu->chans[i]);
 726                 int_sts >>= 1;
 727         }
 728
 729         return IRQ_HANDLED;
 730 }
 731
 732 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 733 {
 734         struct uart_hsu_port *up =
 735                 container_of(port, struct uart_hsu_port, port);
 736         unsigned long flags;
 737         unsigned int ret;
 738
 739         spin_lock_irqsave(&up->port.lock, flags);
 740         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 741         spin_unlock_irqrestore(&up->port.lock, flags);
 742
 743         return ret;
 744 }
 745
 746 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 747 {
 748         struct uart_hsu_port *up =
 749                 container_of(port, struct uart_hsu_port, port);
 750         unsigned char status;
 751         unsigned int ret;
 752
 753         status = serial_in(up, UART_MSR);
 754
 755         ret = 0;
 756         if (status & UART_MSR_DCD)
 757                 ret |= TIOCM_CAR;
 758         if (status & UART_MSR_RI)
 759                 ret |= TIOCM_RNG;
 760         if (status & UART_MSR_DSR)
 761                 ret |= TIOCM_DSR;
 762         if (status & UART_MSR_CTS)
 763                 ret |= TIOCM_CTS;
 764         return ret;
 765 }
 766
 767 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 768 {
 769         struct uart_hsu_port *up =
 770                 container_of(port, struct uart_hsu_port, port);
 771         unsigned char mcr = 0;
 772
 773         if (mctrl & TIOCM_RTS)
 774                 mcr |= UART_MCR_RTS;
 775         if (mctrl & TIOCM_DTR)
 776                 mcr |= UART_MCR_DTR;
 777         if (mctrl & TIOCM_OUT1)
 778                 mcr |= UART_MCR_OUT1;
 779         if (mctrl & TIOCM_OUT2)
 780                 mcr |= UART_MCR_OUT2;
 781         if (mctrl & TIOCM_LOOP)
 782                 mcr |= UART_MCR_LOOP;
 783
 784         mcr |= up->mcr;
 785
 786         serial_out(up, UART_MCR, mcr);
 787 }
 788
 789 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 790 {
 791         struct uart_hsu_port *up =
 792                 container_of(port, struct uart_hsu_port, port);
 793         unsigned long flags;
 794
 795         spin_lock_irqsave(&up->port.lock, flags);
 796         if (break_state == -1)
 797                 up->lcr |= UART_LCR_SBC;
 798         else
 799                 up->lcr &= ~UART_LCR_SBC;
 800         serial_out(up, UART_LCR, up->lcr);
 801         spin_unlock_irqrestore(&up->port.lock, flags);
 802 }
 803
 804 /*
 805  * What special to do:
 806  * 1. chose the 64B fifo mode
 807  * 2. make sure not to select half empty mode for A0 stepping
 808  * 3. start dma or pio depends on configuration
 809  * 4. we only allocate dma memory when needed
 810  */
 811 static int serial_hsu_startup(struct uart_port *port)
 812 {
 813         struct uart_hsu_port *up =
 814                 container_of(port, struct uart_hsu_port, port);
 815         unsigned long flags;
 816
 817         /*
 818          * Clear the FIFO buffers and disable them.
 819          * (they will be reenabled in set_termios())
 820          */
 821         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 822         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 823                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 824         serial_out(up, UART_FCR, 0);
 825
 826         /* Clear the interrupt registers. */
 827         (void) serial_in(up, UART_LSR);
 828         (void) serial_in(up, UART_RX);
 829         (void) serial_in(up, UART_IIR);
 830         (void) serial_in(up, UART_MSR);
 831
 832         /* Now, initialize the UART, default is 8n1 */
 833         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 834
 835         spin_lock_irqsave(&up->port.lock, flags);
 836
 837         up->port.mctrl |= TIOCM_OUT2;
 838         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 839
 840         /*
 841          * Finally, enable interrupts.  Note: Modem status interrupts
 842          * are set via set_termios(), which will be occurring imminently
 843          * anyway, so we don't enable them here.
 844          */
 845         if (!up->use_dma)
 846                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 847         else
 848                 up->ier = 0;
 849         serial_out(up, UART_IER, up->ier);
 850
 851         spin_unlock_irqrestore(&up->port.lock, flags);
 852
 853         /* DMA init */
 854         /* When use DMA, TX/RX's FIFO and IRQ should be disabled */
 855         if (up->use_dma) {
 856                 struct hsu_dma_buffer *dbuf;
 857                 struct circ_buf *xmit = &port->state->xmit;
 858
 859                 up->dma_tx_on = 0;
 860
 861                 /* First allocate the RX buffer */
 862                 dbuf = &up->rxbuf;
 863                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 864                 if (!dbuf->buf) {
 865                         up->use_dma = 0;
 866                         goto exit;
 867                 }
 868                 dbuf->dma_addr = dma_map_single(port->dev,
 869                                                 dbuf->buf,
 870                                                 HSU_DMA_BUF_SIZE,
 871                                                 DMA_FROM_DEVICE);
 872                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 873
 874                 /* Start the RX channel right now */
 875                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 876
 877                 /* Next init the TX DMA */
 878                 dbuf = &up->txbuf;
 879                 dbuf->buf = xmit->buf;
 880                 dbuf->dma_addr = dma_map_single(port->dev,
 881                                                dbuf->buf,
 882                                                UART_XMIT_SIZE,
 883                                                DMA_TO_DEVICE);
 884                 dbuf->dma_size = UART_XMIT_SIZE;
 885
 886                 /* This should not be changed all around */
 887                 chan_writel(up->txc, HSU_CH_BSR, 32);
 888                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 889                 dbuf->ofs = 0;
 890         }
 891
 892 exit:
 893          /* And clear the interrupt registers again for luck. */
 894         (void) serial_in(up, UART_LSR);
 895         (void) serial_in(up, UART_RX);
 896         (void) serial_in(up, UART_IIR);
 897         (void) serial_in(up, UART_MSR);
 898
 899         up->running = 1;
 900         return 0;
 901 }
 902
 903 static void serial_hsu_shutdown(struct uart_port *port)
 904 {
 905         struct uart_hsu_port *up =
 906                 container_of(port, struct uart_hsu_port, port);
 907         unsigned long flags;
 908
 909         del_timer_sync(&up->rxc->rx_timer);
 910
 911         /* Disable interrupts from this port */
 912         up->ier = 0;
 913         serial_out(up, UART_IER, 0);
 914         up->running = 0;
 915
 916         spin_lock_irqsave(&up->port.lock, flags);
 917         up->port.mctrl &= ~TIOCM_OUT2;
 918         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 919         spin_unlock_irqrestore(&up->port.lock, flags);
 920
 921         /* Disable break condition and FIFOs */
 922         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 923         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 924                                   UART_FCR_CLEAR_RCVR |
 925                                   UART_FCR_CLEAR_XMIT);
 926         serial_out(up, UART_FCR, 0);
 927 }
 928
 929 static void
 930 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 931                        struct ktermios *old)
 932 {
 933         struct uart_hsu_port *up =
 934                         container_of(port, struct uart_hsu_port, port);
 935         struct tty_struct *tty = port->state->port.tty;
 936         unsigned char cval, fcr = 0;
 937         unsigned long flags;
 938         unsigned int baud, quot;
 939         u32 mul = 0x3600;
 940         u32 ps = 0x10;
 941
 942         switch (termios->c_cflag & CSIZE) {
 943         case CS5:
 944                 cval = UART_LCR_WLEN5;
 945                 break;
 946         case CS6:
 947                 cval = UART_LCR_WLEN6;
 948                 break;
 949         case CS7:
 950                 cval = UART_LCR_WLEN7;
 951                 break;
 952         default:
 953         case CS8:
 954                 cval = UART_LCR_WLEN8;
 955                 break;
 956         }
 957
 958         /* CMSPAR isn't supported by this driver */
 959         if (tty)
 960                 tty->termios->c_cflag &= ~CMSPAR;
 961
 962         if (termios->c_cflag & CSTOPB)
 963                 cval |= UART_LCR_STOP;
 964         if (termios->c_cflag & PARENB)
 965                 cval |= UART_LCR_PARITY;
 966         if (!(termios->c_cflag & PARODD))
 967                 cval |= UART_LCR_EPAR;
 968
 969         /*
 970          * For those basic low baud rate we can get the direct
 971          * scalar from 2746800, like 115200 = 2746800/24, for those
 972          * higher baud rate, we have to handle them case by case,
 973          * but DIV reg is never touched as its default value 0x3d09
 974          */
 975         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 976         quot = uart_get_divisor(port, baud);
 977
 978         switch (baud) {
 979         case 3500000:
 980                 mul = 0x3345;
 981                 ps = 0xC;
 982                 quot = 1;
 983                 break;
 984         case 2500000:
 985                 mul = 0x2710;
 986                 ps = 0x10;
 987                 quot = 1;
 988                 break;
 989         case 18432000:
 990                 mul = 0x2400;
 991                 ps = 0x10;
 992                 quot = 1;
 993                 break;
 994         case 1500000:
 995                 mul = 0x1D4C;
 996                 ps = 0xc;
 997                 quot = 1;
 998                 break;
 999         default:
1000                 ;
1001         }
1002
1003         if ((up->port.uartclk / quot) < (2400 * 16))
1004                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
1005         else if ((up->port.uartclk / quot) < (230400 * 16))
1006                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
1007         else
1008                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
1009
1010         fcr |= UART_FCR_HSU_64B_FIFO;
1011 #ifdef MFD_HSU_A0_STEPPING
1012         /* A0 doesn't support half empty IRQ */
1013         fcr |= UART_FCR_FULL_EMPT_TXI;
1014 #endif
1015
1016         /*
1017          * Ok, we're now changing the port state.  Do it with
1018          * interrupts disabled.
1019          */
1020         spin_lock_irqsave(&up->port.lock, flags);
1021
1022         /* Update the per-port timeout */
1023         uart_update_timeout(port, termios->c_cflag, baud);
1024
1025         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1026         if (termios->c_iflag & INPCK)
1027                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1028         if (termios->c_iflag & (BRKINT | PARMRK))
1029                 up->port.read_status_mask |= UART_LSR_BI;
1030
1031         /* Characters to ignore */
1032         up->port.ignore_status_mask = 0;
1033         if (termios->c_iflag & IGNPAR)
1034                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1035         if (termios->c_iflag & IGNBRK) {
1036                 up->port.ignore_status_mask |= UART_LSR_BI;
1037                 /*
1038                  * If we're ignoring parity and break indicators,
1039                  * ignore overruns too (for real raw support).
1040                  */
1041                 if (termios->c_iflag & IGNPAR)
1042                         up->port.ignore_status_mask |= UART_LSR_OE;
1043         }
1044
1045         /* Ignore all characters if CREAD is not set */
1046         if ((termios->c_cflag & CREAD) == 0)
1047                 up->port.ignore_status_mask |= UART_LSR_DR;
1048
1049         /*
1050          * CTS flow control flag and modem status interrupts, disable
1051          * MSI by default
1052          */
1053         up->ier &= ~UART_IER_MSI;
1054         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1055                 up->ier |= UART_IER_MSI;
1056
1057         serial_out(up, UART_IER, up->ier);
1058
1059         if (termios->c_cflag & CRTSCTS)
1060                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1061         else
1062                 up->mcr &= ~UART_MCR_AFE;
1063
1064         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1065         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1066         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1067         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1068         serial_out(up, UART_MUL, mul);                  /* set MUL */
1069         serial_out(up, UART_PS, ps);                    /* set PS */
1070         up->lcr = cval;                                 /* Save LCR */
1071         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1072         serial_out(up, UART_FCR, fcr);
1073         spin_unlock_irqrestore(&up->port.lock, flags);
1074 }
1075
1076 static void
1077 serial_hsu_pm(struct uart_port *port, unsigned int state,
1078               unsigned int oldstate)
1079 {
1080 }
1081
1082 static void serial_hsu_release_port(struct uart_port *port)
1083 {
1084 }
1085
1086 static int serial_hsu_request_port(struct uart_port *port)
1087 {
1088         return 0;
1089 }
1090
1091 static void serial_hsu_config_port(struct uart_port *port, int flags)
1092 {
1093 #if 0
1094         struct uart_hsu_port *up =
1095                 container_of(port, struct uart_hsu_port, port);
1096         up->port.type = PORT_MFD;
1097 #endif
1098 }
1099
1100 static int
1101 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1102 {
1103         /* We don't want the core code to modify any port params */
1104         return -EINVAL;
1105 }
1106
1107 static const char *
1108 serial_hsu_type(struct uart_port *port)
1109 {
1110         struct uart_hsu_port *up =
1111                 container_of(port, struct uart_hsu_port, port);
1112         return up->name;
1113 }
1114
1115 /* Mainly for uart console use */
1116 static struct uart_hsu_port *serial_hsu_ports[3];
1117 static struct uart_driver serial_hsu_reg;
1118
1119 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1120
1121 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1122
1123 /* Wait for transmitter & holding register to empty */
1124 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1125 {
1126         unsigned int status, tmout = 1000;
1127
1128         /* Wait up to 1ms for the character to be sent. */
1129         do {
1130                 status = serial_in(up, UART_LSR);
1131
1132                 if (status & UART_LSR_BI)
1133                         up->lsr_break_flag = UART_LSR_BI;
1134
1135                 if (--tmout == 0)
1136                         break;
1137                 udelay(1);
1138         } while (!(status & BOTH_EMPTY));
1139
1140         /* Wait up to 1s for flow control if necessary */
1141         if (up->port.flags & UPF_CONS_FLOW) {
1142                 tmout = 1000000;
1143                 while (--tmout &&
1144                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1145                         udelay(1);
1146         }
1147 }
1148
1149 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1150 {
1151         struct uart_hsu_port *up =
1152                 container_of(port, struct uart_hsu_port, port);
1153
1154         wait_for_xmitr(up);
1155         serial_out(up, UART_TX, ch);
1156 }
1157
1158 /*
1159  * Print a string to the serial port trying not to disturb
1160  * any possible real use of the port...
1161  *
1162  *      The console_lock must be held when we get here.
1163  */
1164 static void
1165 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1166 {
1167         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1168         unsigned long flags;
1169         unsigned int ier;
1170         int locked = 1;
1171
1172         local_irq_save(flags);
1173         if (up->port.sysrq)
1174                 locked = 0;
1175         else if (oops_in_progress) {
1176                 locked = spin_trylock(&up->port.lock);
1177         } else
1178                 spin_lock(&up->port.lock);
1179
1180         /* First save the IER then disable the interrupts */
1181         ier = serial_in(up, UART_IER);
1182         serial_out(up, UART_IER, 0);
1183
1184         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1185
1186         /*
1187          * Finally, wait for transmitter to become empty
1188          * and restore the IER
1189          */
1190         wait_for_xmitr(up);
1191         serial_out(up, UART_IER, ier);
1192
1193         if (locked)
1194                 spin_unlock(&up->port.lock);
1195         local_irq_restore(flags);
1196 }
1197
1198 static struct console serial_hsu_console;
1199
1200 static int __init
1201 serial_hsu_console_setup(struct console *co, char *options)
1202 {
1203         struct uart_hsu_port *up;
1204         int baud = 115200;
1205         int bits = 8;
1206         int parity = 'n';
1207         int flow = 'n';
1208         int ret;
1209
1210         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1211                 co->index = 0;
1212         up = serial_hsu_ports[co->index];
1213         if (!up)
1214                 return -ENODEV;
1215
1216         if (options)
1217                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1218
1219         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1220
1221         return ret;
1222 }
1223
1224 static struct console serial_hsu_console = {
1225         .name           = "ttyMFD",
1226         .write          = serial_hsu_console_write,
1227         .device         = uart_console_device,
1228         .setup          = serial_hsu_console_setup,
1229         .flags          = CON_PRINTBUFFER,
1230         .index          = 2,
1231         .data           = &serial_hsu_reg,
1232 };
1233 #endif
1234
1235 struct uart_ops serial_hsu_pops = {
1236         .tx_empty       = serial_hsu_tx_empty,
1237         .set_mctrl      = serial_hsu_set_mctrl,
1238         .get_mctrl      = serial_hsu_get_mctrl,
1239         .stop_tx        = serial_hsu_stop_tx,
1240         .start_tx       = serial_hsu_start_tx,
1241         .stop_rx        = serial_hsu_stop_rx,
1242         .enable_ms      = serial_hsu_enable_ms,
1243         .break_ctl      = serial_hsu_break_ctl,
1244         .startup        = serial_hsu_startup,
1245         .shutdown       = serial_hsu_shutdown,
1246         .set_termios    = serial_hsu_set_termios,
1247         .pm             = serial_hsu_pm,
1248         .type           = serial_hsu_type,
1249         .release_port   = serial_hsu_release_port,
1250         .request_port   = serial_hsu_request_port,
1251         .config_port    = serial_hsu_config_port,
1252         .verify_port    = serial_hsu_verify_port,
1253 };
1254
1255 static struct uart_driver serial_hsu_reg = {
1256         .owner          = THIS_MODULE,
1257         .driver_name    = "MFD serial",
1258         .dev_name       = "ttyMFD",
1259         .major          = TTY_MAJOR,
1260         .minor          = 128,
1261         .nr             = 3,
1262 };
1263
1264 #ifdef CONFIG_PM
1265 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1266 {
1267         struct uart_hsu_port *up;
1268
1269         up = pci_get_drvdata(pdev);
1270         if (!up)
1271                 return 0;
1272
1273         uart_suspend_port(&serial_hsu_reg, &up->port);
1274
1275         return 0;
1276 }
1277
1278 static int serial_hsu_resume(struct pci_dev *pdev)
1279 {
1280         struct uart_hsu_port *up;
1281
1282         up = pci_get_drvdata(pdev);
1283         if (!up)
1284                 return 0;
1285         uart_resume_port(&serial_hsu_reg, &up->port);
1286         return 0;
1287 }
1288 #else
1289 #define serial_hsu_suspend      NULL
1290 #define serial_hsu_resume       NULL
1291 #endif
1292
1293 /* temp global pointer before we settle down on using one or four PCI dev */
1294 static struct hsu_port *phsu;
1295
1296 static int serial_hsu_probe(struct pci_dev *pdev,
1297                                 const struct pci_device_id *ent)
1298 {
1299         struct uart_hsu_port *uport;
1300         int index, ret;
1301
1302         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1303                 pdev->vendor, pdev->device);
1304
1305         switch (pdev->device) {
1306         case 0x081B:
1307                 index = 0;
1308                 break;
1309         case 0x081C:
1310                 index = 1;
1311                 break;
1312         case 0x081D:
1313                 index = 2;
1314                 break;
1315         case 0x081E:
1316                 /* internal DMA controller */
1317                 index = 3;
1318                 break;
1319         default:
1320                 dev_err(&pdev->dev, "HSU: out of index!");
1321                 return -ENODEV;
1322         }
1323
1324         ret = pci_enable_device(pdev);
1325         if (ret)
1326                 return ret;
1327
1328         if (index == 3) {
1329                 /* DMA controller */
1330                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1331                 if (ret) {
1332                         dev_err(&pdev->dev, "can not get IRQ\n");
1333                         goto err_disable;
1334                 }
1335                 pci_set_drvdata(pdev, phsu);
1336         } else {
1337                 /* UART port 0~2 */
1338                 uport = &phsu->port[index];
1339                 uport->port.irq = pdev->irq;
1340                 uport->port.dev = &pdev->dev;
1341                 uport->dev = &pdev->dev;
1342
1343                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1344                 if (ret) {
1345                         dev_err(&pdev->dev, "can not get IRQ\n");
1346                         goto err_disable;
1347                 }
1348                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1349
1350 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1351                 if (index == 2) {
1352                         register_console(&serial_hsu_console);
1353                         uport->port.cons = &serial_hsu_console;
1354                 }
1355 #endif
1356                 pci_set_drvdata(pdev, uport);
1357         }
1358
1359         return 0;
1360
1361 err_disable:
1362         pci_disable_device(pdev);
1363         return ret;
1364 }
1365
1366 static void hsu_dma_rx_timeout(unsigned long data)
1367 {
1368         struct hsu_dma_chan *chan = (void *)data;
1369         struct uart_hsu_port *up = chan->uport;
1370         struct hsu_dma_buffer *dbuf = &up->rxbuf;
1371         int count = 0;
1372         unsigned long flags;
1373
1374         spin_lock_irqsave(&up->port.lock, flags);
1375
1376         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1377
1378         if (!count) {
1379                 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1380                 goto exit;
1381         }
1382
1383         hsu_dma_rx(up, 0);
1384 exit:
1385         spin_unlock_irqrestore(&up->port.lock, flags);
1386 }
1387
1388 static void hsu_global_init(void)
1389 {
1390         struct hsu_port *hsu;
1391         struct uart_hsu_port *uport;
1392         struct hsu_dma_chan *dchan;
1393         int i, ret;
1394
1395         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1396         if (!hsu)
1397                 return;
1398
1399         /* Get basic io resource and map it */
1400         hsu->paddr = 0xffa28000;
1401         hsu->iolen = 0x1000;
1402
1403         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1404                 pr_warning("HSU: error in request mem region\n");
1405
1406         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1407         if (!hsu->reg) {
1408                 pr_err("HSU: error in ioremap\n");
1409                 ret = -ENOMEM;
1410                 goto err_free_region;
1411         }
1412
1413         /* Initialise the 3 UART ports */
1414         uport = hsu->port;
1415         for (i = 0; i < 3; i++) {
1416                 uport->port.type = PORT_MFD;
1417                 uport->port.iotype = UPIO_MEM;
1418                 uport->port.mapbase = (resource_size_t)hsu->paddr
1419                                         + HSU_PORT_REG_OFFSET
1420                                         + i * HSU_PORT_REG_LENGTH;
1421                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1422                                         + i * HSU_PORT_REG_LENGTH;
1423
1424                 sprintf(uport->name, "hsu_port%d", i);
1425                 uport->port.fifosize = 64;
1426                 uport->port.ops = &serial_hsu_pops;
1427                 uport->port.line = i;
1428                 uport->port.flags = UPF_IOREMAP;
1429                 /* make the maxim support rate to 2746800 bps */
1430                 uport->port.uartclk = 115200 * 24 * 16;
1431
1432                 uport->running = 0;
1433                 uport->txc = &hsu->chans[i * 2];
1434                 uport->rxc = &hsu->chans[i * 2 + 1];
1435
1436                 serial_hsu_ports[i] = uport;
1437                 uport->index = i;
1438                 uport++;
1439         }
1440
1441         /* Initialise 6 dma channels */
1442         dchan = hsu->chans;
1443         for (i = 0; i < 6; i++) {
1444                 dchan->id = i;
1445                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1446                 dchan->uport = &hsu->port[i/2];
1447                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1448                                 i * HSU_DMA_CHANS_REG_LENGTH;
1449
1450                 /* Work around for RX */
1451                 if (dchan->dirt == DMA_FROM_DEVICE) {
1452                         init_timer(&dchan->rx_timer);
1453                         dchan->rx_timer.function = hsu_dma_rx_timeout;
1454                         dchan->rx_timer.data = (unsigned long)dchan;
1455                 }
1456                 dchan++;
1457         }
1458
1459         phsu = hsu;
1460
1461         hsu_debugfs_init(hsu);
1462         return;
1463
1464 err_free_region:
1465         release_mem_region(hsu->paddr, hsu->iolen);
1466         kfree(hsu);
1467         return;
1468 }
1469
1470 static void serial_hsu_remove(struct pci_dev *pdev)
1471 {
1472         struct hsu_port *hsu;
1473         int i;
1474
1475         hsu = pci_get_drvdata(pdev);
1476         if (!hsu)
1477                 return;
1478
1479         for (i = 0; i < 3; i++)
1480                 uart_remove_one_port(&serial_hsu_reg, &hsu->port[i].port);
1481
1482         pci_set_drvdata(pdev, NULL);
1483         free_irq(hsu->irq, hsu);
1484         pci_disable_device(pdev);
1485 }
1486
1487 /* First 3 are UART ports, and the 4th is the DMA */
1488 static const struct pci_device_id pci_ids[] __devinitdata = {
1489         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1490         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1491         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1492         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1493         {},
1494 };
1495
1496 static struct pci_driver hsu_pci_driver = {
1497         .name =         "HSU serial",
1498         .id_table =     pci_ids,
1499         .probe =        serial_hsu_probe,
1500         .remove =       __devexit_p(serial_hsu_remove),
1501         .suspend =      serial_hsu_suspend,
1502         .resume =       serial_hsu_resume,
1503 };
1504
1505 static int __init hsu_pci_init(void)
1506 {
1507         int ret;
1508
1509         hsu_global_init();
1510
1511         ret = uart_register_driver(&serial_hsu_reg);
1512         if (ret)
1513                 return ret;
1514
1515         return pci_register_driver(&hsu_pci_driver);
1516 }
1517
1518 static void __exit hsu_pci_exit(void)
1519 {
1520         pci_unregister_driver(&hsu_pci_driver);
1521         uart_unregister_driver(&serial_hsu_reg);
1522
1523         hsu_debugfs_remove(phsu);
1524
1525         kfree(phsu);
1526 }
1527
1528 module_init(hsu_pci_init);
1529 module_exit(hsu_pci_exit);
1530
1531 MODULE_LICENSE("GPL v2");
1532 MODULE_ALIAS("platform:medfield-hsu");