sunxi: Cleanup the reset code and add meaningful registers defines

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index fb8fbcecb17f3038a989dc4dae3154d10bc5b233..23afb732cb404be4952c87b1ce1ebefeee62ea65 100644 (file)
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -27,7 +27,10 @@
 #include "sunxi.h"
 
 #define WATCHDOG_CTRL_REG      0x00
+#define WATCHDOG_CTRL_RESTART          (1 << 0)
 #define WATCHDOG_MODE_REG      0x04
+#define WATCHDOG_MODE_ENABLE           (1 << 0)
+#define WATCHDOG_MODE_RESET_ENABLE     (1 << 1)
 
 static void __iomem *wdt_base;
 
@@ -48,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd)
                return;
 
        /* Enable timer and set reset bit in the watchdog */
-       writel(3, wdt_base + WATCHDOG_MODE_REG);
-       writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
-       while(1) {
+       writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
+               wdt_base + WATCHDOG_MODE_REG);
+
+       /*
+        * Restart the watchdog. The default (and lowest) interval
+        * value for the watchdog is 0.5s.
+        */
+       writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
+
+       while (1) {
                mdelay(5);
-               writel(3, wdt_base + WATCHDOG_MODE_REG);
+               writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
+                       wdt_base + WATCHDOG_MODE_REG);
        }
 }