read_nic_*() functions are defined in r8192U_core.c.
They call internally usb_control_msg() to read the
nic registers and return the value read.
Following a remark made by Dan Carpenter, if usb_control_msg()
fails, the value returned will be invalid.
To accommodate for this, this patch changes the functions
to take a pointer as argument to set the value read and
return 0 on success and the error status on failure, so
that callers of read_nic_*() can check the return status.
Some other fixes introduced in read_nic_*() functions are:
The expressions (1<<EPROM_*_SHIFT) used to address and set
the individual bits of the eeprom register were replaced
with EPROM_*_BIT bitmasks to make the code more intuitive.
EPROM_*_BIT bitmasks were defined in r8192U_hw.h and
EPROM_*_SHIFT were removed.
In netdev_err(), which is called in case of failure,
the hardcoded function name in the error log message was
replaced with __func__ to reduce line size.
Also, from the error log message, it was omitted the word
"Timeout" and it is just reported the error code since the
failure can not only be due to timeout expiration but also
due to a memory allocation failure. In case of timeout
expiration, usb_start_wait_urb() prints an appropriate log
message when debug is enabled.
Finally, some minor fixes to the coding style were applied in
lines affected by the above changes, including the removal
of ifdef DEBUG_RX (the debugging of reads and writes of the
nic registers shall be done with explicit check on their
return status which will be added in a follow on patch).
Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
void eprom_cs(struct net_device *dev, short bit)
{
+ u8 cmdreg;
+
+ read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
- write_nic_byte_E(dev, EPROM_CMD,
- (1<<EPROM_CS_SHIFT) | \
- read_nic_byte_E(dev, EPROM_CMD)); //enable EPROM
+ /* enable EPROM */
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CS_BIT);
else
- write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev, EPROM_CMD)\
- & ~(1<<EPROM_CS_SHIFT)); //disable EPROM
+ /* disable EPROM */
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CS_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
void eprom_ck_cycle(struct net_device *dev)
{
- write_nic_byte_E(dev, EPROM_CMD,
- (1<<EPROM_CK_SHIFT) | read_nic_byte_E(dev,EPROM_CMD));
+ u8 cmdreg;
+
+ read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
- write_nic_byte_E(dev, EPROM_CMD,
- read_nic_byte_E(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
+
+ read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
void eprom_w(struct net_device *dev,short bit)
{
+ u8 cmdreg;
+
+ read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
- write_nic_byte_E(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | \
- read_nic_byte_E(dev,EPROM_CMD));
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_W_BIT);
else
- write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev,EPROM_CMD)\
- & ~(1<<EPROM_W_SHIFT));
+ write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_W_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
short eprom_r(struct net_device *dev)
{
- short bit;
+ u8 bit;
- bit=(read_nic_byte_E(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT) );
+ read_nic_byte_E(dev, EPROM_CMD, &bit);
udelay(EPROM_DELAY);
- if (bit) return 1;
+ if (bit & EPROM_R_BIT)
+ return 1;
+
return 0;
}
u32 read_cam(struct net_device *dev, u8 addr);
void write_cam(struct net_device *dev, u8 addr, u32 data);
-u8 read_nic_byte(struct net_device *dev, int x);
-u8 read_nic_byte_E(struct net_device *dev, int x);
-u32 read_nic_dword(struct net_device *dev, int x);
-u16 read_nic_word(struct net_device *dev, int x) ;
+int read_nic_byte(struct net_device *dev, int x, u8 *data);
+int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
+int read_nic_dword(struct net_device *dev, int x, u32 *data);
+int read_nic_word(struct net_device *dev, int x, u16 *data);
void write_nic_byte(struct net_device *dev, int x,u8 y);
void write_nic_byte_E(struct net_device *dev, int x,u8 y);
void write_nic_word(struct net_device *dev, int x,u16 y);
u32 read_cam(struct net_device *dev, u8 addr)
{
+ u32 data;
+
write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff));
- return read_nic_dword(dev, 0xa8);
+ read_nic_dword(dev, 0xa8, &data);
+ return data;
}
void write_nic_byte_E(struct net_device *dev, int indx, u8 data)
netdev_err(dev, "write_nic_byte_E TimeOut! status: %d\n", status);
}
-u8 read_nic_byte_E(struct net_device *dev, int indx)
+int read_nic_byte_E(struct net_device *dev, int indx, u8 *data)
{
int status;
- u8 data;
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
- indx|0xfe00, 0, &data, 1, HZ / 2);
+ indx|0xfe00, 0, data, 1, HZ / 2);
- if (status < 0)
- netdev_err(dev, "read_nic_byte_E TimeOut! status: %d\n", status);
+ if (status < 0) {
+ netdev_err(dev, "%s failure status: %d\n", __func__, status);
+ return status;
+ }
- return data;
+ return 0;
}
//as 92U has extend page from 4 to 16, so modify functions below.
void write_nic_byte(struct net_device *dev, int indx, u8 data)
-u8 read_nic_byte(struct net_device *dev, int indx)
+int read_nic_byte(struct net_device *dev, int indx, u8 *data)
{
- u8 data;
int status;
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
- (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
+ (indx&0xff)|0xff00, (indx>>8)&0x0f, data, 1, HZ / 2);
- if (status < 0)
- netdev_err(dev, "read_nic_byte TimeOut! status: %d\n", status);
+ if (status < 0) {
+ netdev_err(dev, "%s failure status: %d\n", __func__, status);
+ return status;
+ }
- return data;
+ return 0;
}
-u16 read_nic_word(struct net_device *dev, int indx)
+int read_nic_word(struct net_device *dev, int indx, u16 *data)
{
- u16 data;
int status;
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
(indx&0xff)|0xff00, (indx>>8)&0x0f,
- &data, 2, HZ / 2);
+ data, 2, HZ / 2);
- if (status < 0)
- netdev_err(dev, "read_nic_word TimeOut! status: %d\n", status);
+ if (status < 0) {
+ netdev_err(dev, "%s failure status: %d\n", __func__, status);
+ return status;
+ }
- return data;
+ return 0;
}
-u16 read_nic_word_E(struct net_device *dev, int indx)
+int read_nic_word_E(struct net_device *dev, int indx, u16 *data)
{
- u16 data;
int status;
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
- indx|0xfe00, 0, &data, 2, HZ / 2);
+ indx|0xfe00, 0, data, 2, HZ / 2);
- if (status < 0)
- netdev_err(dev, "read_nic_word TimeOut! status: %d\n", status);
+ if (status < 0) {
+ netdev_err(dev, "%s failure status: %d\n", __func__, status);
+ return status;
+ }
- return data;
+ return 0;
}
-u32 read_nic_dword(struct net_device *dev, int indx)
+int read_nic_dword(struct net_device *dev, int indx, u32 *data)
{
- u32 data;
int status;
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
(indx&0xff)|0xff00, (indx>>8)&0x0f,
- &data, 4, HZ / 2);
+ data, 4, HZ / 2);
- if (status < 0)
- netdev_err(dev, "read_nic_dword TimeOut! status:%d\n", status);
+ if (status < 0) {
+ netdev_err(dev, "%s failure status: %d\n", __func__, status);
+ return status;
+ }
- return data;
+ return 0;
}
/* u8 read_phy_cck(struct net_device *dev, u8 adr); */
{
struct net_device *dev = m->private;
int i, n, max = 0xff;
+ u8 byte_rd;
seq_puts(m, "\n####################page 0##################\n ");
for (n = 0; n <= max;) {
seq_printf(m, "\nD: %2x > ", n);
- for (i = 0; i < 16 && n <= max; i++, n++)
- seq_printf(m, "%2x ", read_nic_byte(dev, 0x000|n));
+ for (i = 0; i < 16 && n <= max; i++, n++) {
+ read_nic_byte(dev, 0x000|n, &byte_rd);
+ seq_printf(m, "%2x ", byte_rd);
+ }
}
seq_puts(m, "\n####################page 1##################\n ");
for (n = 0; n <= max;) {
seq_printf(m, "\nD: %2x > ", n);
- for (i = 0; i < 16 && n <= max; i++, n++)
- seq_printf(m, "%2x ", read_nic_byte(dev, 0x100|n));
+ for (i = 0; i < 16 && n <= max; i++, n++) {
+ read_nic_byte(dev, 0x100|n, &byte_rd);
+ seq_printf(m, "%2x ", byte_rd);
+ }
}
seq_puts(m, "\n####################page 3##################\n ");
for (n = 0; n <= max;) {
seq_printf(m, "\nD: %2x > ", n);
- for (i = 0; i < 16 && n <= max; i++, n++)
- seq_printf(m, "%2x ", read_nic_byte(dev, 0x300|n));
+ for (i = 0; i < 16 && n <= max; i++, n++) {
+ read_nic_byte(dev, 0x300|n, &byte_rd);
+ seq_printf(m, "%2x ", byte_rd);
+ }
}
seq_putc(m, '\n');
void rtl8192_set_mode(struct net_device *dev, int mode)
{
u8 ecmd;
- ecmd = read_nic_byte(dev, EPROM_CMD);
+ read_nic_byte(dev, EPROM_CMD, &ecmd);
ecmd = ecmd & ~EPROM_CMD_OPERATING_MODE_MASK;
ecmd = ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
- ecmd = ecmd & ~(1<<EPROM_CS_SHIFT);
- ecmd = ecmd & ~(1<<EPROM_CK_SHIFT);
+ ecmd = ecmd & ~EPROM_CS_BIT;
+ ecmd = ecmd & ~EPROM_CK_BIT;
write_nic_byte(dev, EPROM_CMD, ecmd);
}
struct r8192_priv *priv = ieee80211_priv(dev);
u8 msr;
- msr = read_nic_byte(dev, MSR);
+ read_nic_byte(dev, MSR, &msr);
msr &= ~MSR_LINK_MASK;
/* do not change in link_state != WLAN_LINK_ASSOCIATED.
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
u32 rxconf;
- rxconf = read_nic_dword(dev, RCR);
+ read_nic_dword(dev, RCR, &rxconf);
rxconf = rxconf & ~MAC_FILTER_MASK;
rxconf = rxconf | RCR_AMF;
rxconf = rxconf | RCR_ADF;
rxconf = rxconf | RCR_ONLYERLPKT;
write_nic_dword(dev, RCR, rxconf);
-
-#ifdef DEBUG_RX
- DMESG("rxconf: %x %x", rxconf, read_nic_dword(dev, RCR));
-#endif
}
//wait to be removed
void rtl8192_rx_enable(struct net_device *dev)
struct sk_buff *skb;
struct rtl8192_rx_info *info;
- cmd = read_nic_byte(dev, CMDR);
+ read_nic_byte(dev, CMDR, &cmd);
write_nic_byte(dev, CMDR, cmd & ~(CR_TE|CR_RE));
force_pci_posting(dev);
mdelay(10);
u8 msr, msrm, msr2;
struct r8192_priv *priv = ieee80211_priv(dev);
- msr = read_nic_byte(dev, MSR);
+ read_nic_byte(dev, MSR, &msr);
msrm = msr & MSR_LINK_MASK;
msr2 = msr & ~MSR_LINK_MASK;
/*update timing params*/
if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
u32 reg = 0;
- reg = read_nic_dword(dev, RCR);
+ read_nic_dword(dev, RCR, ®);
if (priv->ieee80211->state == IEEE80211_LINKED)
priv->ReceiveConfig = reg |= RCR_CBSSID;
else
u16 curCR = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
RT_TRACE(COMP_EPROM, "===========>%s()\n", __func__);
- curCR = read_nic_word_E(dev, EPROM_CMD);
+ read_nic_word_E(dev, EPROM_CMD, &curCR);
RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);
//whether need I consider BIT5?
priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;
ratr_value &= ~(RATE_ALL_OFDM_2SS);
write_nic_dword(dev, RATR0, ratr_value);
write_nic_byte(dev, UFWP, 1);
- regTmp = read_nic_byte(dev, 0x313);
+ read_nic_byte(dev, 0x313, ®Tmp);
regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
write_nic_dword(dev, RRSR, regRRSR);
u32 dwRegRead = 0;
bool init_status = true;
u8 SECR_value = 0x0;
+ u8 tmp;
RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
priv->Rf_Mode = RF_OP_By_SW_3wire;
//for ASIC power on sequence
priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
//config CPUReset Register
//Firmware Reset or not?
- dwRegRead = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &dwRegRead);
if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
dwRegRead |= CPU_GEN_SYSTEM_RESET; //do nothing here?
else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
//Loopback mode or not
priv->LoopbackMode = RTL819xU_NO_LOOPBACK;
- dwRegRead = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &dwRegRead);
if (priv->LoopbackMode == RTL819xU_NO_LOOPBACK)
dwRegRead = ((dwRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
else if (priv->LoopbackMode == RTL819xU_MAC_LOOPBACK)
udelay(500);
//xiong add for new bitfile:usb suspend reset pin set to 1. //do we need?
- write_nic_byte_E(dev, 0x5f, (read_nic_byte_E(dev, 0x5f)|0x20));
+ read_nic_byte_E(dev, 0x5f, &tmp);
+ write_nic_byte_E(dev, 0x5f, tmp|0x20);
//Set Hardware
rtl8192_hwconfig(dev);
if (priv->ResetProgress == RESET_TYPE_NORESET) {
//if D or C cut
- u8 tmpvalue = read_nic_byte(dev, 0x301);
+ u8 tmpvalue;
+ read_nic_byte(dev, 0x301, &tmpvalue);
if (tmpvalue == 0x03) {
priv->bDcut = TRUE;
RT_TRACE(COMP_POWER_TRACKING, "D-cut\n");
bool HalTxCheckStuck819xUsb(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- u16 RegTxCounter = read_nic_word(dev, 0x128);
+ u16 RegTxCounter;
bool bStuck = FALSE;
+ read_nic_word(dev, 0x128, &RegTxCounter);
RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n", __func__, RegTxCounter, priv->TxCounter);
if (priv->TxCounter == RegTxCounter)
bStuck = TRUE;
bool HalRxCheckStuck819xUsb(struct net_device *dev)
{
- u16 RegRxCounter = read_nic_word(dev, 0x130);
+ u16 RegRxCounter;
struct r8192_priv *priv = ieee80211_priv(dev);
bool bStuck = FALSE;
static u8 rx_chk_cnt;
+ read_nic_word(dev, 0x130, &RegRxCounter);
RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d,RxCounter is %d\n", __func__, RegRxCounter, priv->RxCounter);
// If rssi is small, we should check rx for long time because of bad rx.
// or maybe it will continuous silent reset every 2 seconds.
//Check polling bit is clear
while ((i--) >= 0) {
- ulStatus = read_nic_dword(dev, RWCAM);
+ read_nic_dword(dev, RWCAM, &ulStatus);
if (ulStatus & BIT31)
continue;
else
}
write_nic_dword(dev, RWCAM, target_command);
RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A0: %x \n", target_command);
- target_content = read_nic_dword(dev, RCAMO);
+ read_nic_dword(dev, RCAMO, &target_content);
RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n", target_content);
}
printk("\n");
//
// Check whether updating of RATR0 is required
//
- currentRATR = read_nic_dword(dev, RATR0);
+ read_nic_dword(dev, RATR0, ¤tRATR);
if(targetRATR != currentRATR)
{
u32 ratr_value;
//DbgPrint("hi, vivi, strange\n");
for(i = 0;i <= 30; i++)
{
- Pwr_Flag = read_nic_byte(dev, 0x1ba);
+ read_nic_byte(dev, 0x1ba, &Pwr_Flag);
if (Pwr_Flag == 0)
{
continue;
}
#ifdef RTL8190P
- Avg_TSSI_Meas = read_nic_word(dev, 0x1bc);
+ read_nic_word(dev, 0x1bc, &Avg_TSSI_Meas);
#else
- Avg_TSSI_Meas = read_nic_word(dev, 0x13c);
+ read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
#endif
if(Avg_TSSI_Meas == 0)
{
for(k = 0;k < 5; k++)
{
#ifdef RTL8190P
- tmp_report[k] = read_nic_byte(dev, 0x1d8+k);
+ read_nic_byte(dev, 0x1d8+k, &tmp_report[k]);
#else
if(k !=4)
- tmp_report[k] = read_nic_byte(dev, 0x134+k);
+ read_nic_byte(dev, 0x134+k, &tmp_report[k]);
else
- tmp_report[k] = read_nic_byte(dev, 0x13e);
+ read_nic_byte(dev, 0x13e, &tmp_report[k]);
#endif
RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
}
u8 initial_gain=0;
static u8 initialized, force_write;
static u32 reset_cnt;
+ u8 tmp;
if(dm_digtable.dig_algorithm_switch)
{
reset_cnt = priv->reset_count;
}
- if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
+ read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
+ if (dm_digtable.pre_ig_value != tmp)
force_write = 1;
{
// TODO: Modified this part and try to set acm control in only 1 IO processing!!
PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
- u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
+ u8 AcmCtrl;
+ read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
if(pAciAifsn->f.ACM)
{ // ACM bit is 1.
AcmCtrl |= AcmHw_BeqEn;
u8 tmp1byte;
- tmp1byte = read_nic_byte(dev,GPI);
+ read_nic_byte(dev, GPI, &tmp1byte);
if(tmp1byte == 0xff)
return;
{
// 0x108 GPIO input register is read only
//set 0x108 B1= 1: RF-ON; 0: RF-OFF.
- tmp1byte = read_nic_byte(dev,GPI);
+ read_nic_byte(dev, GPI, &tmp1byte);
eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
always be the same. We only read 0xc04 now. */
- rfpath = read_nic_byte(dev, 0xc04);
+ read_nic_byte(dev, 0xc04, &rfpath);
// Check Bit 0-3, it means if RF A-D is enabled.
for (i = 0; i < RF90_PATH_MAX; i++)
if(!cck_Rx_Path_initialized)
{
- DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
+ read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_Rx_path);
+ DM_RxPathSelTable.cck_Rx_path &= 0xf;
cck_Rx_Path_initialized = 1;
}
- DM_RxPathSelTable.disabledRF = 0xf;
- DM_RxPathSelTable.disabledRF &= ~(read_nic_byte(dev, 0xc04));
+ read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabledRF);
+ DM_RxPathSelTable.disabledRF = ~DM_RxPathSelTable.disabledRF & 0xf;
if(priv->ieee80211->mode == WIRELESS_MODE_B)
{
for (page = 0; page < 5; page++)
for (offset = 0; offset < 256; offset++)
{
- dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
+ read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
//DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
}
for (page = 8; page < 11; page++)
for (offset = 0; offset < 256; offset++)
- dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
+ read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
for (page = 12; page < 15; page++)
for (offset = 0; offset < 256; offset++)
- dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
+ read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
} /* dm_shadow_init */
struct ieee80211_device *ieee = priv->ieee80211;
//for 11n tx rate
// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
- ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
+ read_nic_byte(dev, Current_Tx_Rate_Reg, &ieee->softmac_stats.CurrentShowTxate);
//printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
//for initial tx rate
// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
- ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
+ read_nic_byte(dev, Initial_Tx_Rate_Reg, &ieee->softmac_stats.last_packet_rate);
//for tx tx retry count
// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
- ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
+ read_nic_dword(dev, Tx_Retry_Count_Reg, &ieee->softmac_stats.txretrycount);
}
static void dm_send_rssi_tofw(struct net_device *dev)
#define EPROM_CMD_NORMAL 0
#define EPROM_CMD_LOAD 1
#define EPROM_CMD_PROGRAM 2
-#define EPROM_CS_SHIFT 3
-#define EPROM_CK_SHIFT 2
-#define EPROM_W_SHIFT 1
-#define EPROM_R_SHIFT 0
+#define EPROM_CS_BIT BIT(3)
+#define EPROM_CK_BIT BIT(2)
+#define EPROM_W_BIT BIT(1)
+#define EPROM_R_BIT BIT(0)
+
MAC0 = 0x000,
MAC1 = 0x001,
MAC2 = 0x002,
down(&priv->wx_sem);
get_user(addr,(u32 *)wrqu->data.pointer);
- data1 = read_nic_byte(dev, addr);
+ read_nic_byte(dev, addr, &data1);
wrqu->data.length = data1;
up(&priv->wx_sem);
/* Check whether put code OK */
do {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_PUT_CODE_OK)
break;
}
/* Turn On CPU */
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &CPU_status);
write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
mdelay(1000);
/* Check whether CPU boot OK */
do {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_BOOT_RDY)
break;
/* Check Firmware Ready */
do {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &CPU_status);
if (CPU_status&CPU_GEN_FIRM_RDY)
break;
if(dwBitMask!= bMaskDWord)
{//if not "double word" write
- OriginalValue = read_nic_dword(dev, dwRegAddr);
+ read_nic_dword(dev, dwRegAddr, &OriginalValue);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
write_nic_dword(dev, dwRegAddr, NewValue);
{
u32 Ret = 0, OriginalValue, BitShift;
- OriginalValue = read_nic_dword(dev, dwRegAddr);
+ read_nic_dword(dev, dwRegAddr, &OriginalValue);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
Ret =(OriginalValue & dwBitMask) >> BitShift;
u32 retValue = 0;
u32 Data = 0;
u8 time = 0;
+ u32 tmp;
//DbgPrint("FW RF CTRL\n\r");
/* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
not execute the scheme in the initial step. Otherwise, RF-R/W will waste
// 5. Trigger Fw to operate the command. bit 31
Data |= 0x80000000;
// 6. We can not execute read operation if bit 31 is 1.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ read_nic_dword(dev, QPNR, &tmp);
+ while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-R Time=%d\n\r", time);
udelay(10);
+ read_nic_dword(dev, QPNR, &tmp);
}
else
break;
// 7. Execute read operation.
write_nic_dword(dev, QPNR, Data);
// 8. Check if firmawre send back RF content.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ read_nic_dword(dev, QPNR, &tmp);
+ while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-W Time=%d\n\r", time);
udelay(10);
+ read_nic_dword(dev, QPNR, &tmp);
}
else
return (0);
}
- retValue = read_nic_dword(dev, RF_DATA);
+ read_nic_dword(dev, RF_DATA, &retValue);
return (retValue);
u32 Data )
{
u8 time = 0;
+ u32 tmp;
//DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
/* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
Data |= 0x80000000;
// 6. Write operation. We can not write if bit 31 is 1.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ read_nic_dword(dev, QPNR, &tmp);
+ while (tmp & 0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
{
//DbgPrint("FW not finish RF-W Time=%d\n\r", time);
udelay(10);
+ read_nic_dword(dev, QPNR, &tmp);
}
else
break;
case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1:
write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
- dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
+ read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
break;
case HW90_BLOCK_RF:
**************************************/
/*--set BB Global Reset--*/
- bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
+ read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
mdelay(50);
/*---set BB reset Active---*/
- dwRegValue = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &dwRegValue);
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
/*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
/*----Set BB reset de-Active----*/
- dwRegValue = read_nic_dword(dev, CPU_GEN);
+ read_nic_dword(dev, CPU_GEN, &dwRegValue);
write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
/*----BB AGC table Initialization----*/
void rtl8192_phy_getTxPower(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- priv->MCSTxPowerLevelOriginalOffset[0] =
- read_nic_dword(dev, rTxAGC_Rate18_06);
- priv->MCSTxPowerLevelOriginalOffset[1] =
- read_nic_dword(dev, rTxAGC_Rate54_24);
- priv->MCSTxPowerLevelOriginalOffset[2] =
- read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
- priv->MCSTxPowerLevelOriginalOffset[3] =
- read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
- priv->MCSTxPowerLevelOriginalOffset[4] =
- read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
- priv->MCSTxPowerLevelOriginalOffset[5] =
- read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
+ u8 tmp;
+ read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
+ read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
+ read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
+ read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
+ read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
+ read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
// read rx initial gain
- priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
- priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
- priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
- priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
+ read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
+ read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
+ read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
+ read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
// read framesync
- priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
- priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2);
+ read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
+ read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
+ priv->framesyncC34 = tmp;
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
rOFDM0_RxDetector3, priv->framesync);
// read SIFS (save the value read fome MACPHY_REG.txt)
- priv->SifsTime = read_nic_word(dev, SIFS);
+ read_nic_word(dev, SIFS, &priv->SifsTime);
return;
}
}
//<1>Set MAC register
- regBwOpMode = read_nic_byte(dev, BW_OPMODE);
+ read_nic_byte(dev, BW_OPMODE, ®BwOpMode);
switch (priv->CurrentChannelBW)
{
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