drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

... instead of PIPECONF_INTERLACE_MASK.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: applied the change by hand due to patch reorder.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7bab7adf73455b92ec348f1a9abbfbf5791bbd4b..787e62a44542e64f067f7ab66ea9aa64d393c282 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1732,7 +1732,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
        val = TRANS_ENABLE;
        pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
-       if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+       if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+           PIPECONF_INTERLACED_ILK)
                val |= TRANS_INTERLACED;
        else
                val |= TRANS_PROGRESSIVE;