ARM: sunxi: dt: Reorganize the dtsi

In the early days, the A10 and A13 shared quite some code. Nowadays it
shares less and less code, the A31 diverging even more, so it doesn't
make much sense to continue to maintain this structure, just use one
DTSI for every SoC, and that's it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 99558f624554cb211e64551b13f7810be0d65e81..b70fe0db6bb7583cd541d25b7573a057caec130d 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,7 +26,7 @@
                bootargs = "earlyprintk console=ttyS0,115200";
        };
 
-       soc {
+       soc@01c20000 {
                pinctrl@01c20800 {
                        led_pins_cubieboard: led_pins@0 {
                                allwinner,pins = "PH20", "PH21";

diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 20460007a89f6bdc479c6128ae5ecefcfa61ebb9..b9efac100c85b2aac70c41a5bb4c9b8d83a11a11 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,7 +22,7 @@
                bootargs = "earlyprintk console=ttyS0,115200";
        };
 
-       soc {
+       soc@01c20000 {
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index f6405204e7e219d095170c3e9e2b6d05e9e330b4..81accf4814a594843d3a4169ff1efb601401ad54 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -10,14 +10,172 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+       interrupt-parent = <&intc>;
+
+       cpus {
+               cpu@0 {
+                       compatible = "arm,cortex-a8";
+               };
+       };
+
        memory {
                reg = <0x40000000 0x80000000>;
        };
 
-       soc {
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               /*
+                * This is a dummy clock, to be used as placeholder on
+                * other mux clocks when a specific parent clock is not
+                * yet implemented. It should be dropped when the driver
+                * is complete.
+                */
+               dummy: dummy {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <0>;
+               };
+
+               osc24M_fixed: osc24M_fixed {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+
+               osc24M: osc24M@01c20050 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-osc-clk";
+                       reg = <0x01c20050 0x4>;
+                       clocks = <&osc24M_fixed>;
+               };
+
+               osc32k: osc32k {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <32768>;
+               };
+
+               pll1: pll1@01c20000 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20000 0x4>;
+                       clocks = <&osc24M>;
+               };
+
+               /* dummy is 200M */
+               cpu: cpu@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-cpu-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+               };
+
+               axi: axi@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-axi-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&cpu>;
+               };
+
+               axi_gates: axi_gates@01c2005c {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       reg = <0x01c2005c 0x4>;
+                       clocks = <&axi>;
+                       clock-output-names = "axi_dram";
+               };
+
+               ahb: ahb@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-ahb-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&axi>;
+               };
+
+               ahb_gates: ahb_gates@01c20060 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-ahb-gates-clk";
+                       reg = <0x01c20060 0x8>;
+                       clocks = <&ahb>;
+                       clock-output-names = "ahb_usb0", "ahb_ehci0",
+                               "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                               "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                               "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                               "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                               "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                               "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                               "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                               "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                               "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                               "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+               };
+
+               apb0: apb0@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb0-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&ahb>;
+               };
+
+               apb0_gates: apb0_gates@01c20068 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-apb0-gates-clk";
+                       reg = <0x01c20068 0x4>;
+                       clocks = <&apb0>;
+                       clock-output-names = "apb0_codec", "apb0_spdif",
+                               "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                               "apb0_ir1", "apb0_keypad";
+               };
+
+               /* dummy is pll62 */
+               apb1_mux: apb1_mux@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
+               };
+
+               apb1_gates: apb1_gates@01c2006c {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-apb1-gates-clk";
+                       reg = <0x01c2006c 0x4>;
+                       clocks = <&apb1>;
+                       clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                               "apb1_i2c2", "apb1_can", "apb1_scr",
+                               "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                               "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                               "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                               "apb1_uart7";
+               };
+       };
+
+       soc@01c20000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x01c20000 0x300000>;
+               ranges;
+
+               intc: interrupt-controller@01c20400 {
+                       compatible = "allwinner,sunxi-ic";
+                       reg = <0x01c20400 0x400>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
                pio: pinctrl@01c20800 {
                        compatible = "allwinner,sun4i-a10-pinctrl";
                        reg = <0x01c20800 0x400>;
@@ -49,6 +207,18 @@
                        };
                };
 
+               timer@01c20c00 {
+                       compatible = "allwinner,sunxi-timer";
+                       reg = <0x01c20c00 0x90>;
+                       interrupts = <22>;
+                       clocks = <&osc24M>;
+               };
+
+               wdt: watchdog@01c20c90 {
+                       compatible = "allwinner,sunxi-wdt";
+                       reg = <0x01c20c90 0x10>;
+               };
+
                uart0: serial@01c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;
@@ -59,6 +229,16 @@
                        status = "disabled";
                };
 
+               uart1: serial@01c28400 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28400 0x400>;
+                       interrupts = <2>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&apb1_gates 17>;
+                       status = "disabled";
+               };
+
                uart2: serial@01c28800 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28800 0x400>;
@@ -69,6 +249,16 @@
                        status = "disabled";
                };
 
+               uart3: serial@01c28c00 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28c00 0x400>;
+                       interrupts = <4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&apb1_gates 19>;
+                       status = "disabled";
+               };
+
                uart4: serial@01c29000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c29000 0x400>;

diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index f1579a831f905434928e23375f89444d3de7c250..3ca55067f86848eee329392d65d078fdd5b72faf 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,7 +22,7 @@
                bootargs = "earlyprintk console=ttyS0,115200";
        };
 
-       soc {
+       soc@01c20000 {
                pinctrl@01c20800 {
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PG9";

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 10ee8eedd36bb462923f3051fe7290ce27fcd670..990fef70ba85f9df00b97cd64fa89def12d5cc71 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -11,14 +11,172 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+       interrupt-parent = <&intc>;
+
+       cpus {
+               cpu@0 {
+                       compatible = "arm,cortex-a8";
+               };
+       };
+
        memory {
                reg = <0x40000000 0x20000000>;
        };
 
-       soc {
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               /*
+                * This is a dummy clock, to be used as placeholder on
+                * other mux clocks when a specific parent clock is not
+                * yet implemented. It should be dropped when the driver
+                * is complete.
+                */
+               dummy: dummy {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <0>;
+               };
+
+               osc24M_fixed: osc24M_fixed {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+
+               osc24M: osc24M@01c20050 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-osc-clk";
+                       reg = <0x01c20050 0x4>;
+                       clocks = <&osc24M_fixed>;
+               };
+
+               osc32k: osc32k {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <32768>;
+               };
+
+               pll1: pll1@01c20000 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20000 0x4>;
+                       clocks = <&osc24M>;
+               };
+
+               /* dummy is 200M */
+               cpu: cpu@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-cpu-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+               };
+
+               axi: axi@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-axi-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&cpu>;
+               };
+
+               axi_gates: axi_gates@01c2005c {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       reg = <0x01c2005c 0x4>;
+                       clocks = <&axi>;
+                       clock-output-names = "axi_dram";
+               };
+
+               ahb: ahb@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-ahb-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&axi>;
+               };
+
+               ahb_gates: ahb_gates@01c20060 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-ahb-gates-clk";
+                       reg = <0x01c20060 0x8>;
+                       clocks = <&ahb>;
+                       clock-output-names = "ahb_usb0", "ahb_ehci0",
+                               "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                               "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                               "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                               "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                               "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                               "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                               "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                               "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                               "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                               "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+               };
+
+               apb0: apb0@01c20054 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb0-clk";
+                       reg = <0x01c20054 0x4>;
+                       clocks = <&ahb>;
+               };
+
+               apb0_gates: apb0_gates@01c20068 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-apb0-gates-clk";
+                       reg = <0x01c20068 0x4>;
+                       clocks = <&apb0>;
+                       clock-output-names = "apb0_codec", "apb0_spdif",
+                               "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                               "apb0_ir1", "apb0_keypad";
+               };
+
+               /* dummy is pll62 */
+               apb1_mux: apb1_mux@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
+               };
+
+               apb1_gates: apb1_gates@01c2006c {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-apb1-gates-clk";
+                       reg = <0x01c2006c 0x4>;
+                       clocks = <&apb1>;
+                       clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                               "apb1_i2c2", "apb1_can", "apb1_scr",
+                               "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                               "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                               "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                               "apb1_uart7";
+               };
+       };
+
+       soc@01c20000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x01c20000 0x300000>;
+               ranges;
+
+               intc: interrupt-controller@01c20400 {
+                       compatible = "allwinner,sunxi-ic";
+                       reg = <0x01c20400 0x400>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
                pio: pinctrl@01c20800 {
                        compatible = "allwinner,sun5i-a13-pinctrl";
                        reg = <0x01c20800 0x400>;
@@ -42,5 +200,37 @@
                                allwinner,pull = <0>;
                        };
                };
+
+               timer@01c20c00 {
+                       compatible = "allwinner,sunxi-timer";
+                       reg = <0x01c20c00 0x90>;
+                       interrupts = <22>;
+                       clocks = <&osc24M>;
+               };
+
+               wdt: watchdog@01c20c90 {
+                       compatible = "allwinner,sunxi-wdt";
+                       reg = <0x01c20c90 0x10>;
+               };
+
+               uart1: serial@01c28400 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28400 0x400>;
+                       interrupts = <2>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&apb1_gates 17>;
+                       status = "disabled";
+               };
+
+               uart3: serial@01c28c00 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28c00 0x400>;
+                       interrupts = <4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&apb1_gates 19>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644 (file)
index a8d47e2..0000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-       interrupt-parent = <&intc>;
-
-       cpus {
-               cpu@0 {
-                       compatible = "arm,cortex-a8";
-               };
-       };
-
-       clocks {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               ranges;
-
-               /*
-                * This is a dummy clock, to be used as placeholder on
-                * other mux clocks when a specific parent clock is not
-                * yet implemented. It should be dropped when the driver
-                * is complete.
-                */
-               dummy: dummy {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <0>;
-               };
-
-               osc24M_fixed: osc24M_fixed {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <24000000>;
-               };
-
-               osc24M: osc24M@01c20050 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
-                       reg = <0x01c20050 0x4>;
-                       clocks = <&osc24M_fixed>;
-               };
-
-               osc32k: osc32k {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <32768>;
-               };
-
-               pll1: pll1@01c20000 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
-                       reg = <0x01c20000 0x4>;
-                       clocks = <&osc24M>;
-               };
-
-               /* dummy is 200M */
-               cpu: cpu@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-               };
-
-               axi: axi@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&cpu>;
-               };
-
-               axi_gates: axi_gates@01c2005c {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
-                       reg = <0x01c2005c 0x4>;
-                       clocks = <&axi>;
-                       clock-output-names = "axi_dram";
-               };
-
-               ahb: ahb@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&axi>;
-               };
-
-               ahb_gates: ahb_gates@01c20060 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-ahb-gates-clk";
-                       reg = <0x01c20060 0x8>;
-                       clocks = <&ahb>;
-                       clock-output-names = "ahb_usb0", "ahb_ehci0",
-                               "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-                               "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-                               "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-                               "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
-                               "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-                               "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                               "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                               "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                               "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                               "ahb_de_fe1", "ahb_mp", "ahb_mali400";
-               };
-
-               apb0: apb0@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&ahb>;
-               };
-
-               apb0_gates: apb0_gates@01c20068 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-apb0-gates-clk";
-                       reg = <0x01c20068 0x4>;
-                       clocks = <&apb0>;
-                       clock-output-names = "apb0_codec", "apb0_spdif",
-                               "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                               "apb0_ir1", "apb0_keypad";
-               };
-
-               /* dummy is pll62 */
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
-               };
-
-               apb1: apb1@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&apb1_mux>;
-               };
-
-               apb1_gates: apb1_gates@01c2006c {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-apb1-gates-clk";
-                       reg = <0x01c2006c 0x4>;
-                       clocks = <&apb1>;
-                       clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                               "apb1_i2c2", "apb1_can", "apb1_scr",
-                               "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                               "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                               "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                               "apb1_uart7";
-               };
-       };
-
-       soc {
-               compatible = "simple-bus";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               reg = <0x01c20000 0x300000>;
-               ranges;
-
-               timer@01c20c00 {
-                       compatible = "allwinner,sunxi-timer";
-                       reg = <0x01c20c00 0x90>;
-                       interrupts = <22>;
-                       clocks = <&osc24M>;
-               };
-
-               wdt: watchdog@01c20c90 {
-                       compatible = "allwinner,sunxi-wdt";
-                       reg = <0x01c20c90 0x10>;
-               };
-
-               intc: interrupt-controller@01c20400 {
-                       compatible = "allwinner,sunxi-ic";
-                       reg = <0x01c20400 0x400>;
-                       interrupt-controller;
-                       #interrupt-cells = <1>;
-               };
-
-               uart1: serial@01c28400 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x01c28400 0x400>;
-                       interrupts = <2>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clocks = <&apb1_gates 17>;
-                       status = "disabled";
-               };
-
-               uart3: serial@01c28c00 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x01c28c00 0x400>;
-                       interrupts = <4>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clocks = <&apb1_gates 19>;
-                       status = "disabled";
-               };
-       };
-};