]> rtime.felk.cvut.cz Git - linux-imx.git/commitdiff
drm/radeon/dpm: add helper to calculate vblank time
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Jul 2013 15:26:42 +0000 (11:26 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Jul 2013 21:40:09 +0000 (17:40 -0400)
Required for checking vblank time for mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/r600_dpm.c
drivers/gpu/drm/radeon/r600_dpm.h
drivers/gpu/drm/radeon/radeon_mode.h

index c7ad4b9308507588619246cf2629190310e145e3..b9d3b43f19c0ed097f43ab3afef3f4b79d17152a 100644 (file)
@@ -1841,6 +1841,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
        atombios_crtc_set_base(crtc, x, y, old_fb);
        atombios_overscan_setup(crtc, mode, adjusted_mode);
        atombios_scaler_setup(crtc);
+       /* update the hw version fpr dpm */
+       radeon_crtc->hw_mode = *adjusted_mode;
+
        return 0;
 }
 
index 76368c04f8092a82e5d44aa9ec3288a8828e3521..b88f54b134abaa838b44dc0a5e614df2c06f3be5 100644 (file)
@@ -150,6 +150,30 @@ void r600_dpm_print_ps_status(struct radeon_device *rdev,
        printk("\n");
 }
 
+u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
+{
+       struct drm_device *dev = rdev->ddev;
+       struct drm_crtc *crtc;
+       struct radeon_crtc *radeon_crtc;
+       u32 line_time_us, vblank_lines;
+       u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
+
+       list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+               radeon_crtc = to_radeon_crtc(crtc);
+               if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
+                       line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
+                               radeon_crtc->hw_mode.clock;
+                       vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
+                               radeon_crtc->hw_mode.crtc_vdisplay +
+                               (radeon_crtc->v_border * 2);
+                       vblank_time_us = vblank_lines * line_time_us;
+                       break;
+               }
+       }
+
+       return vblank_time_us;
+}
+
 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
                            u32 *p, u32 *u)
 {
index a95ab214289b8a9034997f02a82e0fbbedf655b3..7c822d9ae53d62777bbea9bc8d3a6975b70286c5 100644 (file)
@@ -129,6 +129,7 @@ void r600_dpm_print_class_info(u32 class, u32 class2);
 void r600_dpm_print_cap_info(u32 caps);
 void r600_dpm_print_ps_status(struct radeon_device *rdev,
                              struct radeon_ps *rps);
+u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);
 bool r600_is_uvd_state(u32 class, u32 class2);
 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
                            u32 *p, u32 *u);
index b568cb19a7fa316faaa94ffa349b52f8564380ec..8296632a42358d9055446ea3e547f7a80e9c0788 100644 (file)
@@ -335,6 +335,7 @@ struct radeon_crtc {
        u32 line_time;
        u32 wm_low;
        u32 wm_high;
+       struct drm_display_mode hw_mode;
 };
 
 struct radeon_encoder_primary_dac {