drm/i915: fix DSPADDR Gen check

The first version of commit "drm/i915: there's no DSPADDR register on
Haswell" added 2 "!IS_HASWELL" checks. When reviewing the patch, Ben
suggested to make these checks more future-proof, so when Daniel
applied the patch he fixed the first check but not the second. This
commit makes the second check also "future-proof".

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3380d02dff7fba167d2278c31b5c317f3c3c4e39..f1dbdd4cb09f857f76c7f75f3a5fe9358c520c04 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9420,7 +9420,7 @@ intel_display_print_error_state(struct seq_file *m,
                if (INTEL_INFO(dev)->gen <= 3)
                        seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
                seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
-               if (!IS_HASWELL(dev))
+               if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
                        seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
                if (INTEL_INFO(dev)->gen >= 4) {
                        seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);