drm/i915: Scale ring, rather than ia, frequency on Haswell

Haswell introduces a separate frequency domain for the ring (uncore). So
where we used to increase the CPU (IA) clock with GPU busyness, we now
need to scale the ring frequency directly instead. As the ring limits
our memory bandwidth, it is vital for performance that when the GPU is
busy, we increase the frequency of the ring to increase the available
memory bandwidth.

v2: Fix the algorithm to actually use the scaled gpu frequency for the ring.
v3: s/max_ring_freq/min_ring_freq/ as that is what it is

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Add space checkpatch complained about.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 23187fc99ca6d9435ccca9a61267edaa40974022..e913d325d5b808d184a82f760e90f7505cec251e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1357,7 +1357,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
        if (ret)
                return ret;
 
-       seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
+       seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
 
        for (gpu_freq = dev_priv->rps.min_delay;
             gpu_freq <= dev_priv->rps.max_delay;
@@ -1366,7 +1366,10 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
                sandybridge_pcode_read(dev_priv,
                                       GEN6_PCODE_READ_MIN_FREQ_TABLE,
                                       &ia_freq);
-               seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
+               seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
+                          gpu_freq * GT_FREQUENCY_MULTIPLIER,
+                          ((ia_freq >> 0) & 0xff) * 100,
+                          ((ia_freq >> 8) & 0xff) * 100);
        }
 
        mutex_unlock(&dev_priv->rps.hw_lock);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0fc0706e0344bafddd87207862d319b0e793d55..077d40f37b97d838f5b55b0595c2a12e95540d39 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1210,6 +1210,9 @@
 
 #define MCHBAR_MIRROR_BASE_SNB 0x140000
 
+/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
+#define DCLK 0x5e04
+
 /** 915-945 and GM965 MCH register controlling DRAM channel access */
 #define DCC                    0x10200
 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL             (0 << 0)
@@ -4390,6 +4393,7 @@
 #define   GEN6_DECODE_RC6_VID(vids)            (((vids) * 5) + 245)
 #define GEN6_PCODE_DATA                                0x138128
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
+#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT     16
 
 #define VLV_IOSF_DOORBELL_REQ                  0x182100
 #define   IOSF_DEVFN_SHIFT                     24

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dc06a1bd43d77d446101c1e5f670646b32692c0..5e1cdd54ba134a1d4050dd930639bf817254b116 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2684,8 +2684,8 @@ static void gen6_update_ring_freq(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        int min_freq = 15;
-       int gpu_freq;
-       unsigned int ia_freq, max_ia_freq;
+       unsigned int gpu_freq;
+       unsigned int max_ia_freq, min_ring_freq;
        int scaling_factor = 180;
 
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -2701,6 +2701,10 @@ static void gen6_update_ring_freq(struct drm_device *dev)
        /* Convert from kHz to MHz */
        max_ia_freq /= 1000;
 
+       min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
+       /* convert DDR frequency from units of 133.3MHz to bandwidth */
+       min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+
        /*
         * For each potential GPU frequency, load a ring frequency we'd like
         * to use for memory access.  We do this by specifying the IA frequency
@@ -2709,21 +2713,32 @@ static void gen6_update_ring_freq(struct drm_device *dev)
        for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
             gpu_freq--) {
                int diff = dev_priv->rps.max_delay - gpu_freq;
-
-               /*
-                * For GPU frequencies less than 750MHz, just use the lowest
-                * ring freq.
-                */
-               if (gpu_freq < min_freq)
-                       ia_freq = 800;
-               else
-                       ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
-               ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
-               ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
+               unsigned int ia_freq = 0, ring_freq = 0;
+
+               if (IS_HASWELL(dev)) {
+                       ring_freq = (gpu_freq * 5 + 3) / 4;
+                       ring_freq = max(min_ring_freq, ring_freq);
+                       /* leave ia_freq as the default, chosen by cpufreq */
+               } else {
+                       /* On older processors, there is no separate ring
+                        * clock domain, so in order to boost the bandwidth
+                        * of the ring, we need to upclock the CPU (ia_freq).
+                        *
+                        * For GPU frequencies less than 750MHz,
+                        * just use the lowest ring freq.
+                        */
+                       if (gpu_freq < min_freq)
+                               ia_freq = 800;
+                       else
+                               ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
+                       ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
+               }
 
                sandybridge_pcode_write(dev_priv,
                                        GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
-                                       ia_freq | gpu_freq);
+                                       ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
+                                       ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
+                                       gpu_freq);
        }
 }