drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e398963797a60b77fb65e636bceddd63648ef0a0..48283167c19521dd31bee08cb2e101efaad1b8c7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -268,6 +268,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
                   IVB_DPFC_CTL_FENCE_EN |
                   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 
+       /* WaFbcAsynchFlipDisableFbcQueue */
+       I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
        I915_WRITE(SNB_DPFC_CTL_SA,
                   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
        I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);