staging: xgifb: drop XG41 code

XG_41 is not listed in xgifb_pci_table, so the code can be safely dropped.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/xgifb/XGI_main.h b/drivers/staging/xgifb/XGI_main.h
index e828fd403c357ad7119308d929baae43e299d7c2..7621bbf3756b1fc19c6a01694866b77ee53b4f16 100644 (file)
--- a/drivers/staging/xgifb/XGI_main.h
+++ b/drivers/staging/xgifb/XGI_main.h
@@ -12,9 +12,6 @@
 
 #define XGIFAIL(x) do { printk(x "\n"); return -EINVAL; } while (0)
 
-#ifndef PCI_DEVICE_ID_XGI_41
-#define PCI_DEVICE_ID_XGI_41      0x041
-#endif
 #ifndef PCI_DEVICE_ID_XGI_42
 #define PCI_DEVICE_ID_XGI_42      0x042
 #endif

diff --git a/drivers/staging/xgifb/XGI_main_26.c b/drivers/staging/xgifb/XGI_main_26.c
index 055acb36e1eb9ab8e9d32b7fb286fb868798abeb..8d1095211065cec439f18800474b8d0e5906e7cd 100644 (file)
--- a/drivers/staging/xgifb/XGI_main_26.c
+++ b/drivers/staging/xgifb/XGI_main_26.c
@@ -1924,9 +1924,6 @@ static int __devinit xgifb_probe(struct pci_dev *pdev,
        case PCI_DEVICE_ID_XGI_40:
                xgifb_info->chip = XG40;
                break;
-       case PCI_DEVICE_ID_XGI_41:
-               xgifb_info->chip = XG41;
-               break;
        case PCI_DEVICE_ID_XGI_42:
                xgifb_info->chip = XG42;
                break;

diff --git a/drivers/staging/xgifb/XGIfb.h b/drivers/staging/xgifb/XGIfb.h
index bea222d06fe6807eab4ca8d72754aac2802c81f7..223ba66284bf9ed62bca068d1a3acbf6622b7a4a 100644 (file)
--- a/drivers/staging/xgifb/XGIfb.h
+++ b/drivers/staging/xgifb/XGIfb.h
@@ -23,7 +23,6 @@ enum xgifb_display_type {
 
 enum XGI_CHIP_TYPE {
        XG40 = 32,
-       XG41,
        XG42,
        XG45,
        XG20 = 48,

diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index a951ca4d8287a7138cc3a3407ff8ef27fd14024e..0c2c0176fb1d480794b120a7913c4a2f41a6b72f 100644 (file)
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -353,7 +353,6 @@ static void XGINew_DDR1x_DefaultRegister(
                XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 
                switch (HwDeviceExtension->jChipType) {
-               case XG41:
                case XG42:
                        /* CR82 */
                        xgifb_reg_set(P3d4,
@@ -556,8 +555,7 @@ static void XGINew_SetDRAMDefaultRegister340(
                xgifb_reg_set(P3d4, (0x8A + j),
                                pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 
-       if ((HwDeviceExtension->jChipType == XG41) ||
-           (HwDeviceExtension->jChipType == XG42))
+       if (HwDeviceExtension->jChipType == XG42)
                xgifb_reg_set(P3d4, 0x8C, 0x87);
 
        xgifb_reg_set(P3d4,
@@ -854,78 +852,6 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
                pVBInfo->ram_channel = 1; /* Single channel */
                xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
                break;
-       case XG41:
-               if (XGINew_CheckFrequence(pVBInfo) == 1) {
-                       pVBInfo->ram_bus = 32; /* 32 bits */
-                       pVBInfo->ram_channel = 3; /* Quad Channel */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
-
-                       if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
-                               return;
-
-                       pVBInfo->ram_channel = 2; /* Dual channels */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       pVBInfo->ram_channel = 3;
-                       xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
-
-                       if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
-                               return;
-                       else
-                               xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
-               } else { /* DDR */
-                       pVBInfo->ram_bus = 64; /* 64 bits */
-                       pVBInfo->ram_channel = 2; /* Dual channels */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
-
-                       if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
-                               return;
-
-                       pVBInfo->ram_channel = 1; /* Single channels */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       pVBInfo->ram_channel = 2; /* Dual channels */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
-
-                       if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
-                               return;
-
-                       pVBInfo->ram_channel = 1; /* Single channels */
-                       xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
-
-                       if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
-                               return;
-                       else
-                               xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
-               }
-
-               break;
-
        case XG42:
                /*
                 XG42 SR14 D[3] Reserve