drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. "
 125                 "Enable Haswell and ValleyView Support. "
 126                 "(default: false)");
 127
 128 static struct drm_driver driver;
 129 extern int intel_agp_enabled;
 130
 131 #define INTEL_VGA_DEVICE(id, info) {            \
 132         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 133         .class_mask = 0xff0000,                 \
 134         .vendor = 0x8086,                       \
 135         .device = id,                           \
 136         .subvendor = PCI_ANY_ID,                \
 137         .subdevice = PCI_ANY_ID,                \
 138         .driver_data = (unsigned long) info }
 139
 140 static const struct intel_device_info intel_i830_info = {
 141         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_845g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i85x_info = {
 151         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 152         .cursor_needs_physical = 1,
 153         .has_overlay = 1, .overlay_needs_physical = 1,
 154 };
 155
 156 static const struct intel_device_info intel_i865g_info = {
 157         .gen = 2,
 158         .has_overlay = 1, .overlay_needs_physical = 1,
 159 };
 160
 161 static const struct intel_device_info intel_i915g_info = {
 162         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 163         .has_overlay = 1, .overlay_needs_physical = 1,
 164 };
 165 static const struct intel_device_info intel_i915gm_info = {
 166         .gen = 3, .is_mobile = 1,
 167         .cursor_needs_physical = 1,
 168         .has_overlay = 1, .overlay_needs_physical = 1,
 169         .supports_tv = 1,
 170 };
 171 static const struct intel_device_info intel_i945g_info = {
 172         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 173         .has_overlay = 1, .overlay_needs_physical = 1,
 174 };
 175 static const struct intel_device_info intel_i945gm_info = {
 176         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 177         .has_hotplug = 1, .cursor_needs_physical = 1,
 178         .has_overlay = 1, .overlay_needs_physical = 1,
 179         .supports_tv = 1,
 180 };
 181
 182 static const struct intel_device_info intel_i965g_info = {
 183         .gen = 4, .is_broadwater = 1,
 184         .has_hotplug = 1,
 185         .has_overlay = 1,
 186 };
 187
 188 static const struct intel_device_info intel_i965gm_info = {
 189         .gen = 4, .is_crestline = 1,
 190         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_g33_info = {
 196         .gen = 3, .is_g33 = 1,
 197         .need_gfx_hws = 1, .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_g45_info = {
 202         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .has_bsd_ring = 1,
 205 };
 206
 207 static const struct intel_device_info intel_gm45_info = {
 208         .gen = 4, .is_g4x = 1,
 209         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 210         .has_pipe_cxsr = 1, .has_hotplug = 1,
 211         .supports_tv = 1,
 212         .has_bsd_ring = 1,
 213 };
 214
 215 static const struct intel_device_info intel_pineview_info = {
 216         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_overlay = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_d_info = {
 222         .gen = 5,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_bsd_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_ironlake_m_info = {
 228         .gen = 5, .is_mobile = 1,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_fbc = 1,
 231         .has_bsd_ring = 1,
 232 };
 233
 234 static const struct intel_device_info intel_sandybridge_d_info = {
 235         .gen = 6,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238         .has_blt_ring = 1,
 239         .has_llc = 1,
 240         .has_force_wake = 1,
 241 };
 242
 243 static const struct intel_device_info intel_sandybridge_m_info = {
 244         .gen = 6, .is_mobile = 1,
 245         .need_gfx_hws = 1, .has_hotplug = 1,
 246         .has_fbc = 1,
 247         .has_bsd_ring = 1,
 248         .has_blt_ring = 1,
 249         .has_llc = 1,
 250         .has_force_wake = 1,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_d_info = {
 254         .is_ivybridge = 1, .gen = 7,
 255         .need_gfx_hws = 1, .has_hotplug = 1,
 256         .has_bsd_ring = 1,
 257         .has_blt_ring = 1,
 258         .has_llc = 1,
 259         .has_force_wake = 1,
 260 };
 261
 262 static const struct intel_device_info intel_ivybridge_m_info = {
 263         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 264         .need_gfx_hws = 1, .has_hotplug = 1,
 265         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 266         .has_bsd_ring = 1,
 267         .has_blt_ring = 1,
 268         .has_llc = 1,
 269         .has_force_wake = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_m_info = {
 273         .gen = 7, .is_mobile = 1,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279         .display_mmio_offset = VLV_DISPLAY_BASE,
 280 };
 281
 282 static const struct intel_device_info intel_valleyview_d_info = {
 283         .gen = 7,
 284         .need_gfx_hws = 1, .has_hotplug = 1,
 285         .has_fbc = 0,
 286         .has_bsd_ring = 1,
 287         .has_blt_ring = 1,
 288         .is_valleyview = 1,
 289         .display_mmio_offset = VLV_DISPLAY_BASE,
 290 };
 291
 292 static const struct intel_device_info intel_haswell_d_info = {
 293         .is_haswell = 1, .gen = 7,
 294         .need_gfx_hws = 1, .has_hotplug = 1,
 295         .has_bsd_ring = 1,
 296         .has_blt_ring = 1,
 297         .has_llc = 1,
 298         .has_force_wake = 1,
 299 };
 300
 301 static const struct intel_device_info intel_haswell_m_info = {
 302         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 303         .need_gfx_hws = 1, .has_hotplug = 1,
 304         .has_bsd_ring = 1,
 305         .has_blt_ring = 1,
 306         .has_llc = 1,
 307         .has_force_wake = 1,
 308 };
 309
 310 static const struct pci_device_id pciidlist[] = {               /* aka */
 311         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 312         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 313         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 314         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 315         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 316         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 317         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 318         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 319         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 320         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 321         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 322         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 323         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 324         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 325         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 326         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 327         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 328         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 329         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 330         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 331         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 332         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 333         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 334         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 335         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 336         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 337         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 338         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 339         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 340         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 341         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 342         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 343         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 344         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 345         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 346         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 347         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 348         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 349         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 350         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 351         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 352         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 353         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 354         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 355         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 356         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 357         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 358         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 359         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 360         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 361         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 362         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 363         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 364         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 365         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 366         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 367         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 368         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 369         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 370         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 371         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 372         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 373         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 374         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 375         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 376         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 377         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 378         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 379         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 380         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 381         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 382         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
 383         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 384         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
 385         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
 386         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 387         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
 388         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
 389         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 390         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 391         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 392         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 393         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 394         {0, 0, 0}
 395 };
 396
 397 #if defined(CONFIG_DRM_I915_KMS)
 398 MODULE_DEVICE_TABLE(pci, pciidlist);
 399 #endif
 400
 401 void intel_detect_pch(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct pci_dev *pch;
 405
 406         /*
 407          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 408          * make graphics device passthrough work easy for VMM, that only
 409          * need to expose ISA bridge to let driver know the real hardware
 410          * underneath. This is a requirement from virtualization team.
 411          */
 412         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 413         if (pch) {
 414                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 415                         unsigned short id;
 416                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 417                         dev_priv->pch_id = id;
 418
 419                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 420                                 dev_priv->pch_type = PCH_IBX;
 421                                 dev_priv->num_pch_pll = 2;
 422                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 423                                 WARN_ON(!IS_GEN5(dev));
 424                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 425                                 dev_priv->pch_type = PCH_CPT;
 426                                 dev_priv->num_pch_pll = 2;
 427                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 428                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 429                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 430                                 /* PantherPoint is CPT compatible */
 431                                 dev_priv->pch_type = PCH_CPT;
 432                                 dev_priv->num_pch_pll = 2;
 433                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 434                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 435                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_LPT;
 437                                 dev_priv->num_pch_pll = 0;
 438                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 439                                 WARN_ON(!IS_HASWELL(dev));
 440                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 441                                 dev_priv->pch_type = PCH_LPT;
 442                                 dev_priv->num_pch_pll = 0;
 443                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 444                                 WARN_ON(!IS_HASWELL(dev));
 445                         }
 446                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 447                 }
 448                 pci_dev_put(pch);
 449         }
 450 }
 451
 452 bool i915_semaphore_is_enabled(struct drm_device *dev)
 453 {
 454         if (INTEL_INFO(dev)->gen < 6)
 455                 return 0;
 456
 457         if (i915_semaphores >= 0)
 458                 return i915_semaphores;
 459
 460 #ifdef CONFIG_INTEL_IOMMU
 461         /* Enable semaphores on SNB when IO remapping is off */
 462         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 463                 return false;
 464 #endif
 465
 466         return 1;
 467 }
 468
 469 static int i915_drm_freeze(struct drm_device *dev)
 470 {
 471         struct drm_i915_private *dev_priv = dev->dev_private;
 472
 473         drm_kms_helper_poll_disable(dev);
 474
 475         pci_save_state(dev->pdev);
 476
 477         /* If KMS is active, we do the leavevt stuff here */
 478         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 479                 int error = i915_gem_idle(dev);
 480                 if (error) {
 481                         dev_err(&dev->pdev->dev,
 482                                 "GEM idle failed, resume might fail\n");
 483                         return error;
 484                 }
 485
 486                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 487
 488                 intel_modeset_disable(dev);
 489
 490                 drm_irq_uninstall(dev);
 491         }
 492
 493         i915_save_state(dev);
 494
 495         intel_opregion_fini(dev);
 496
 497         /* Modeset on resume, not lid events */
 498         dev_priv->modeset_on_lid = 0;
 499
 500         console_lock();
 501         intel_fbdev_set_suspend(dev, 1);
 502         console_unlock();
 503
 504         return 0;
 505 }
 506
 507 int i915_suspend(struct drm_device *dev, pm_message_t state)
 508 {
 509         int error;
 510
 511         if (!dev || !dev->dev_private) {
 512                 DRM_ERROR("dev: %p\n", dev);
 513                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 514                 return -ENODEV;
 515         }
 516
 517         if (state.event == PM_EVENT_PRETHAW)
 518                 return 0;
 519
 520
 521         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 522                 return 0;
 523
 524         error = i915_drm_freeze(dev);
 525         if (error)
 526                 return error;
 527
 528         if (state.event == PM_EVENT_SUSPEND) {
 529                 /* Shut down the device */
 530                 pci_disable_device(dev->pdev);
 531                 pci_set_power_state(dev->pdev, PCI_D3hot);
 532         }
 533
 534         return 0;
 535 }
 536
 537 void intel_console_resume(struct work_struct *work)
 538 {
 539         struct drm_i915_private *dev_priv =
 540                 container_of(work, struct drm_i915_private,
 541                              console_resume_work);
 542         struct drm_device *dev = dev_priv->dev;
 543
 544         console_lock();
 545         intel_fbdev_set_suspend(dev, 0);
 546         console_unlock();
 547 }
 548
 549 static int __i915_drm_thaw(struct drm_device *dev)
 550 {
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552         int error = 0;
 553
 554         i915_restore_state(dev);
 555         intel_opregion_setup(dev);
 556
 557         /* KMS EnterVT equivalent */
 558         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 559                 intel_init_pch_refclk(dev);
 560
 561                 mutex_lock(&dev->struct_mutex);
 562                 dev_priv->mm.suspended = 0;
 563
 564                 error = i915_gem_init_hw(dev);
 565                 mutex_unlock(&dev->struct_mutex);
 566
 567                 intel_modeset_init_hw(dev);
 568                 intel_modeset_setup_hw_state(dev, false);
 569                 drm_irq_install(dev);
 570                 intel_hpd_init(dev);
 571         }
 572
 573         intel_opregion_init(dev);
 574
 575         dev_priv->modeset_on_lid = 0;
 576
 577         /*
 578          * The console lock can be pretty contented on resume due
 579          * to all the printk activity.  Try to keep it out of the hot
 580          * path of resume if possible.
 581          */
 582         if (console_trylock()) {
 583                 intel_fbdev_set_suspend(dev, 0);
 584                 console_unlock();
 585         } else {
 586                 schedule_work(&dev_priv->console_resume_work);
 587         }
 588
 589         return error;
 590 }
 591
 592 static int i915_drm_thaw(struct drm_device *dev)
 593 {
 594         int error = 0;
 595
 596         intel_gt_reset(dev);
 597
 598         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 599                 mutex_lock(&dev->struct_mutex);
 600                 i915_gem_restore_gtt_mappings(dev);
 601                 mutex_unlock(&dev->struct_mutex);
 602         }
 603
 604         __i915_drm_thaw(dev);
 605
 606         return error;
 607 }
 608
 609 int i915_resume(struct drm_device *dev)
 610 {
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         int ret;
 613
 614         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 615                 return 0;
 616
 617         if (pci_enable_device(dev->pdev))
 618                 return -EIO;
 619
 620         pci_set_master(dev->pdev);
 621
 622         intel_gt_reset(dev);
 623
 624         /*
 625          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 626          * earlier) need this since the BIOS might clear all our scratch PTEs.
 627          */
 628         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 629             !dev_priv->opregion.header) {
 630                 mutex_lock(&dev->struct_mutex);
 631                 i915_gem_restore_gtt_mappings(dev);
 632                 mutex_unlock(&dev->struct_mutex);
 633         }
 634
 635         ret = __i915_drm_thaw(dev);
 636         if (ret)
 637                 return ret;
 638
 639         drm_kms_helper_poll_enable(dev);
 640         return 0;
 641 }
 642
 643 static int i8xx_do_reset(struct drm_device *dev)
 644 {
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646
 647         if (IS_I85X(dev))
 648                 return -ENODEV;
 649
 650         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 651         POSTING_READ(D_STATE);
 652
 653         if (IS_I830(dev) || IS_845G(dev)) {
 654                 I915_WRITE(DEBUG_RESET_I830,
 655                            DEBUG_RESET_DISPLAY |
 656                            DEBUG_RESET_RENDER |
 657                            DEBUG_RESET_FULL);
 658                 POSTING_READ(DEBUG_RESET_I830);
 659                 msleep(1);
 660
 661                 I915_WRITE(DEBUG_RESET_I830, 0);
 662                 POSTING_READ(DEBUG_RESET_I830);
 663         }
 664
 665         msleep(1);
 666
 667         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 668         POSTING_READ(D_STATE);
 669
 670         return 0;
 671 }
 672
 673 static int i965_reset_complete(struct drm_device *dev)
 674 {
 675         u8 gdrst;
 676         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 677         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 678 }
 679
 680 static int i965_do_reset(struct drm_device *dev)
 681 {
 682         int ret;
 683         u8 gdrst;
 684
 685         /*
 686          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 687          * well as the reset bit (GR/bit 0).  Setting the GR bit
 688          * triggers the reset; when done, the hardware will clear it.
 689          */
 690         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 691         pci_write_config_byte(dev->pdev, I965_GDRST,
 692                               gdrst | GRDOM_RENDER |
 693                               GRDOM_RESET_ENABLE);
 694         ret =  wait_for(i965_reset_complete(dev), 500);
 695         if (ret)
 696                 return ret;
 697
 698         /* We can't reset render&media without also resetting display ... */
 699         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 700         pci_write_config_byte(dev->pdev, I965_GDRST,
 701                               gdrst | GRDOM_MEDIA |
 702                               GRDOM_RESET_ENABLE);
 703
 704         return wait_for(i965_reset_complete(dev), 500);
 705 }
 706
 707 static int ironlake_do_reset(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         u32 gdrst;
 711         int ret;
 712
 713         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 714         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 715                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 716         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 717         if (ret)
 718                 return ret;
 719
 720         /* We can't reset render&media without also resetting display ... */
 721         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 722         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 723                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 724         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 725 }
 726
 727 static int gen6_do_reset(struct drm_device *dev)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         int     ret;
 731         unsigned long irqflags;
 732
 733         /* Hold gt_lock across reset to prevent any register access
 734          * with forcewake not set correctly
 735          */
 736         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 737
 738         /* Reset the chip */
 739
 740         /* GEN6_GDRST is not in the gt power well, no need to check
 741          * for fifo space for the write or forcewake the chip for
 742          * the read
 743          */
 744         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 745
 746         /* Spin waiting for the device to ack the reset request */
 747         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 748
 749         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 750         if (dev_priv->forcewake_count)
 751                 dev_priv->gt.force_wake_get(dev_priv);
 752         else
 753                 dev_priv->gt.force_wake_put(dev_priv);
 754
 755         /* Restore fifo count */
 756         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 757
 758         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 759         return ret;
 760 }
 761
 762 int intel_gpu_reset(struct drm_device *dev)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         int ret = -ENODEV;
 766
 767         switch (INTEL_INFO(dev)->gen) {
 768         case 7:
 769         case 6:
 770                 ret = gen6_do_reset(dev);
 771                 break;
 772         case 5:
 773                 ret = ironlake_do_reset(dev);
 774                 break;
 775         case 4:
 776                 ret = i965_do_reset(dev);
 777                 break;
 778         case 2:
 779                 ret = i8xx_do_reset(dev);
 780                 break;
 781         }
 782
 783         /* Also reset the gpu hangman. */
 784         if (dev_priv->gpu_error.stop_rings) {
 785                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 786                 dev_priv->gpu_error.stop_rings = 0;
 787                 if (ret == -ENODEV) {
 788                         DRM_ERROR("Reset not implemented, but ignoring "
 789                                   "error for simulated gpu hangs\n");
 790                         ret = 0;
 791                 }
 792         }
 793
 794         return ret;
 795 }
 796
 797 /**
 798  * i915_reset - reset chip after a hang
 799  * @dev: drm device to reset
 800  *
 801  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 802  * reset or otherwise an error code.
 803  *
 804  * Procedure is fairly simple:
 805  *   - reset the chip using the reset reg
 806  *   - re-init context state
 807  *   - re-init hardware status page
 808  *   - re-init ring buffer
 809  *   - re-init interrupt state
 810  *   - re-init display
 811  */
 812 int i915_reset(struct drm_device *dev)
 813 {
 814         drm_i915_private_t *dev_priv = dev->dev_private;
 815         int ret;
 816
 817         if (!i915_try_reset)
 818                 return 0;
 819
 820         mutex_lock(&dev->struct_mutex);
 821
 822         i915_gem_reset(dev);
 823
 824         ret = -ENODEV;
 825         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 826                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 827         else
 828                 ret = intel_gpu_reset(dev);
 829
 830         dev_priv->gpu_error.last_reset = get_seconds();
 831         if (ret) {
 832                 DRM_ERROR("Failed to reset chip.\n");
 833                 mutex_unlock(&dev->struct_mutex);
 834                 return ret;
 835         }
 836
 837         /* Ok, now get things going again... */
 838
 839         /*
 840          * Everything depends on having the GTT running, so we need to start
 841          * there.  Fortunately we don't need to do this unless we reset the
 842          * chip at a PCI level.
 843          *
 844          * Next we need to restore the context, but we don't use those
 845          * yet either...
 846          *
 847          * Ring buffer needs to be re-initialized in the KMS case, or if X
 848          * was running at the time of the reset (i.e. we weren't VT
 849          * switched away).
 850          */
 851         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 852                         !dev_priv->mm.suspended) {
 853                 struct intel_ring_buffer *ring;
 854                 int i;
 855
 856                 dev_priv->mm.suspended = 0;
 857
 858                 i915_gem_init_swizzling(dev);
 859
 860                 for_each_ring(ring, dev_priv, i)
 861                         ring->init(ring);
 862
 863                 i915_gem_context_init(dev);
 864                 i915_gem_init_ppgtt(dev);
 865
 866                 /*
 867                  * It would make sense to re-init all the other hw state, at
 868                  * least the rps/rc6/emon init done within modeset_init_hw. For
 869                  * some unknown reason, this blows up my ilk, so don't.
 870                  */
 871
 872                 mutex_unlock(&dev->struct_mutex);
 873
 874                 drm_irq_uninstall(dev);
 875                 drm_irq_install(dev);
 876                 intel_hpd_init(dev);
 877         } else {
 878                 mutex_unlock(&dev->struct_mutex);
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 885 {
 886         struct intel_device_info *intel_info =
 887                 (struct intel_device_info *) ent->driver_data;
 888
 889         if (intel_info->is_valleyview)
 890                 if(!i915_preliminary_hw_support) {
 891                         DRM_ERROR("Preliminary hardware support disabled\n");
 892                         return -ENODEV;
 893                 }
 894
 895         /* Only bind to function 0 of the device. Early generations
 896          * used function 1 as a placeholder for multi-head. This causes
 897          * us confusion instead, especially on the systems where both
 898          * functions have the same PCI-ID!
 899          */
 900         if (PCI_FUNC(pdev->devfn))
 901                 return -ENODEV;
 902
 903         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 904          * implementation for gen3 (and only gen3) that used legacy drm maps
 905          * (gasp!) to share buffers between X and the client. Hence we need to
 906          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 907         if (intel_info->gen != 3) {
 908                 driver.driver_features &=
 909                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 910         } else if (!intel_agp_enabled) {
 911                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 912                 return -ENODEV;
 913         }
 914
 915         return drm_get_pci_dev(pdev, ent, &driver);
 916 }
 917
 918 static void
 919 i915_pci_remove(struct pci_dev *pdev)
 920 {
 921         struct drm_device *dev = pci_get_drvdata(pdev);
 922
 923         drm_put_dev(dev);
 924 }
 925
 926 static int i915_pm_suspend(struct device *dev)
 927 {
 928         struct pci_dev *pdev = to_pci_dev(dev);
 929         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 930         int error;
 931
 932         if (!drm_dev || !drm_dev->dev_private) {
 933                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 934                 return -ENODEV;
 935         }
 936
 937         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 938                 return 0;
 939
 940         error = i915_drm_freeze(drm_dev);
 941         if (error)
 942                 return error;
 943
 944         pci_disable_device(pdev);
 945         pci_set_power_state(pdev, PCI_D3hot);
 946
 947         return 0;
 948 }
 949
 950 static int i915_pm_resume(struct device *dev)
 951 {
 952         struct pci_dev *pdev = to_pci_dev(dev);
 953         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 954
 955         return i915_resume(drm_dev);
 956 }
 957
 958 static int i915_pm_freeze(struct device *dev)
 959 {
 960         struct pci_dev *pdev = to_pci_dev(dev);
 961         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 962
 963         if (!drm_dev || !drm_dev->dev_private) {
 964                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 965                 return -ENODEV;
 966         }
 967
 968         return i915_drm_freeze(drm_dev);
 969 }
 970
 971 static int i915_pm_thaw(struct device *dev)
 972 {
 973         struct pci_dev *pdev = to_pci_dev(dev);
 974         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 975
 976         return i915_drm_thaw(drm_dev);
 977 }
 978
 979 static int i915_pm_poweroff(struct device *dev)
 980 {
 981         struct pci_dev *pdev = to_pci_dev(dev);
 982         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 983
 984         return i915_drm_freeze(drm_dev);
 985 }
 986
 987 static const struct dev_pm_ops i915_pm_ops = {
 988         .suspend = i915_pm_suspend,
 989         .resume = i915_pm_resume,
 990         .freeze = i915_pm_freeze,
 991         .thaw = i915_pm_thaw,
 992         .poweroff = i915_pm_poweroff,
 993         .restore = i915_pm_resume,
 994 };
 995
 996 static const struct vm_operations_struct i915_gem_vm_ops = {
 997         .fault = i915_gem_fault,
 998         .open = drm_gem_vm_open,
 999         .close = drm_gem_vm_close,
1000 };
1001
1002 static const struct file_operations i915_driver_fops = {
1003         .owner = THIS_MODULE,
1004         .open = drm_open,
1005         .release = drm_release,
1006         .unlocked_ioctl = drm_ioctl,
1007         .mmap = drm_gem_mmap,
1008         .poll = drm_poll,
1009         .fasync = drm_fasync,
1010         .read = drm_read,
1011 #ifdef CONFIG_COMPAT
1012         .compat_ioctl = i915_compat_ioctl,
1013 #endif
1014         .llseek = noop_llseek,
1015 };
1016
1017 static struct drm_driver driver = {
1018         /* Don't use MTRRs here; the Xserver or userspace app should
1019          * deal with them for Intel hardware.
1020          */
1021         .driver_features =
1022             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1023             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1024         .load = i915_driver_load,
1025         .unload = i915_driver_unload,
1026         .open = i915_driver_open,
1027         .lastclose = i915_driver_lastclose,
1028         .preclose = i915_driver_preclose,
1029         .postclose = i915_driver_postclose,
1030
1031         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1032         .suspend = i915_suspend,
1033         .resume = i915_resume,
1034
1035         .device_is_agp = i915_driver_device_is_agp,
1036         .master_create = i915_master_create,
1037         .master_destroy = i915_master_destroy,
1038 #if defined(CONFIG_DEBUG_FS)
1039         .debugfs_init = i915_debugfs_init,
1040         .debugfs_cleanup = i915_debugfs_cleanup,
1041 #endif
1042         .gem_init_object = i915_gem_init_object,
1043         .gem_free_object = i915_gem_free_object,
1044         .gem_vm_ops = &i915_gem_vm_ops,
1045
1046         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1047         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1048         .gem_prime_export = i915_gem_prime_export,
1049         .gem_prime_import = i915_gem_prime_import,
1050
1051         .dumb_create = i915_gem_dumb_create,
1052         .dumb_map_offset = i915_gem_mmap_gtt,
1053         .dumb_destroy = i915_gem_dumb_destroy,
1054         .ioctls = i915_ioctls,
1055         .fops = &i915_driver_fops,
1056         .name = DRIVER_NAME,
1057         .desc = DRIVER_DESC,
1058         .date = DRIVER_DATE,
1059         .major = DRIVER_MAJOR,
1060         .minor = DRIVER_MINOR,
1061         .patchlevel = DRIVER_PATCHLEVEL,
1062 };
1063
1064 static struct pci_driver i915_pci_driver = {
1065         .name = DRIVER_NAME,
1066         .id_table = pciidlist,
1067         .probe = i915_pci_probe,
1068         .remove = i915_pci_remove,
1069         .driver.pm = &i915_pm_ops,
1070 };
1071
1072 static int __init i915_init(void)
1073 {
1074         driver.num_ioctls = i915_max_ioctl;
1075
1076         /*
1077          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1078          * explicitly disabled with the module pararmeter.
1079          *
1080          * Otherwise, just follow the parameter (defaulting to off).
1081          *
1082          * Allow optional vga_text_mode_force boot option to override
1083          * the default behavior.
1084          */
1085 #if defined(CONFIG_DRM_I915_KMS)
1086         if (i915_modeset != 0)
1087                 driver.driver_features |= DRIVER_MODESET;
1088 #endif
1089         if (i915_modeset == 1)
1090                 driver.driver_features |= DRIVER_MODESET;
1091
1092 #ifdef CONFIG_VGA_CONSOLE
1093         if (vgacon_text_force() && i915_modeset == -1)
1094                 driver.driver_features &= ~DRIVER_MODESET;
1095 #endif
1096
1097         if (!(driver.driver_features & DRIVER_MODESET))
1098                 driver.get_vblank_timestamp = NULL;
1099
1100         return drm_pci_init(&driver, &i915_pci_driver);
1101 }
1102
1103 static void __exit i915_exit(void)
1104 {
1105         drm_pci_exit(&driver, &i915_pci_driver);
1106 }
1107
1108 module_init(i915_init);
1109 module_exit(i915_exit);
1110
1111 MODULE_AUTHOR(DRIVER_AUTHOR);
1112 MODULE_DESCRIPTION(DRIVER_DESC);
1113 MODULE_LICENSE("GPL and additional rights");
1114
1115 /* We give fast paths for the really cool registers */
1116 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1117         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1118          ((reg) < 0x40000) &&            \
1119          ((reg) != FORCEWAKE))
1120
1121 static bool IS_DISPLAYREG(u32 reg)
1122 {
1123         /*
1124          * This should make it easier to transition modules over to the
1125          * new register block scheme, since we can do it incrementally.
1126          */
1127         if (reg >= VLV_DISPLAY_BASE)
1128                 return false;
1129
1130         if (reg >= RENDER_RING_BASE &&
1131             reg < RENDER_RING_BASE + 0xff)
1132                 return false;
1133         if (reg >= GEN6_BSD_RING_BASE &&
1134             reg < GEN6_BSD_RING_BASE + 0xff)
1135                 return false;
1136         if (reg >= BLT_RING_BASE &&
1137             reg < BLT_RING_BASE + 0xff)
1138                 return false;
1139
1140         if (reg == PGTBL_ER)
1141                 return false;
1142
1143         if (reg >= IPEIR_I965 &&
1144             reg < HWSTAM)
1145                 return false;
1146
1147         if (reg == MI_MODE)
1148                 return false;
1149
1150         if (reg == GFX_MODE_GEN7)
1151                 return false;
1152
1153         if (reg == RENDER_HWS_PGA_GEN7 ||
1154             reg == BSD_HWS_PGA_GEN7 ||
1155             reg == BLT_HWS_PGA_GEN7)
1156                 return false;
1157
1158         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1159             reg == GEN6_BSD_RNCID)
1160                 return false;
1161
1162         if (reg == GEN6_BLITTER_ECOSKPD)
1163                 return false;
1164
1165         if (reg >= 0x4000c &&
1166             reg <= 0x4002c)
1167                 return false;
1168
1169         if (reg >= 0x4f000 &&
1170             reg <= 0x4f08f)
1171                 return false;
1172
1173         if (reg >= 0x4f100 &&
1174             reg <= 0x4f11f)
1175                 return false;
1176
1177         if (reg >= VLV_MASTER_IER &&
1178             reg <= GEN6_PMIER)
1179                 return false;
1180
1181         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1182             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1183                 return false;
1184
1185         if (reg >= VLV_IIR_RW &&
1186             reg <= VLV_ISR)
1187                 return false;
1188
1189         if (reg == FORCEWAKE_VLV ||
1190             reg == FORCEWAKE_ACK_VLV)
1191                 return false;
1192
1193         if (reg == GEN6_GDRST)
1194                 return false;
1195
1196         switch (reg) {
1197         case _3D_CHICKEN3:
1198         case IVB_CHICKEN3:
1199         case GEN7_COMMON_SLICE_CHICKEN1:
1200         case GEN7_L3CNTLREG1:
1201         case GEN7_L3_CHICKEN_MODE_REGISTER:
1202         case GEN7_ROW_CHICKEN2:
1203         case GEN7_L3SQCREG4:
1204         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
1205         case GEN7_HALF_SLICE_CHICKEN1:
1206         case GEN6_MBCTL:
1207         case GEN6_UCGCTL2:
1208                 return false;
1209         default:
1210                 break;
1211         }
1212
1213         return true;
1214 }
1215
1216 static void
1217 ilk_dummy_write(struct drm_i915_private *dev_priv)
1218 {
1219         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1220          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1221          * harmless to write 0 into. */
1222         I915_WRITE_NOTRACE(MI_MODE, 0);
1223 }
1224
1225 #define __i915_read(x, y) \
1226 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1227         u##x val = 0; \
1228         if (IS_GEN5(dev_priv->dev)) \
1229                 ilk_dummy_write(dev_priv); \
1230         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1231                 unsigned long irqflags; \
1232                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1233                 if (dev_priv->forcewake_count == 0) \
1234                         dev_priv->gt.force_wake_get(dev_priv); \
1235                 val = read##y(dev_priv->regs + reg); \
1236                 if (dev_priv->forcewake_count == 0) \
1237                         dev_priv->gt.force_wake_put(dev_priv); \
1238                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1239         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1240                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1241         } else { \
1242                 val = read##y(dev_priv->regs + reg); \
1243         } \
1244         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1245         return val; \
1246 }
1247
1248 __i915_read(8, b)
1249 __i915_read(16, w)
1250 __i915_read(32, l)
1251 __i915_read(64, q)
1252 #undef __i915_read
1253
1254 #define __i915_write(x, y) \
1255 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1256         u32 __fifo_ret = 0; \
1257         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1258         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1259                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1260         } \
1261         if (IS_GEN5(dev_priv->dev)) \
1262                 ilk_dummy_write(dev_priv); \
1263         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1264                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1265                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1266         } \
1267         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1268                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1269         } else {                                                        \
1270                 write##y(val, dev_priv->regs + reg);                    \
1271         }                                                               \
1272         if (unlikely(__fifo_ret)) { \
1273                 gen6_gt_check_fifodbg(dev_priv); \
1274         } \
1275         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1276                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1277                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
1278         } \
1279 }
1280 __i915_write(8, b)
1281 __i915_write(16, w)
1282 __i915_write(32, l)
1283 __i915_write(64, q)
1284 #undef __i915_write
1285
1286 static const struct register_whitelist {
1287         uint64_t offset;
1288         uint32_t size;
1289         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1290 } whitelist[] = {
1291         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1292 };
1293
1294 int i915_reg_read_ioctl(struct drm_device *dev,
1295                         void *data, struct drm_file *file)
1296 {
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct drm_i915_reg_read *reg = data;
1299         struct register_whitelist const *entry = whitelist;
1300         int i;
1301
1302         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1303                 if (entry->offset == reg->offset &&
1304                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1305                         break;
1306         }
1307
1308         if (i == ARRAY_SIZE(whitelist))
1309                 return -EINVAL;
1310
1311         switch (entry->size) {
1312         case 8:
1313                 reg->val = I915_READ64(reg->offset);
1314                 break;
1315         case 4:
1316                 reg->val = I915_READ(reg->offset);
1317                 break;
1318         case 2:
1319                 reg->val = I915_READ16(reg->offset);
1320                 break;
1321         case 1:
1322                 reg->val = I915_READ8(reg->offset);
1323                 break;
1324         default:
1325                 WARN_ON(1);
1326                 return -EINVAL;
1327         }
1328
1329         return 0;
1330 }