2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "cypress_dpm.h"
31 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
32 #define SUMO_MINIMUM_ENGINE_CLOCK 800
33 #define BOOST_DPM_LEVEL 7
35 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
54 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
73 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
75 struct sumo_ps *ps = rps->ps_priv;
80 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
82 struct sumo_power_info *pi = rdev->pm.dpm.priv;
87 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
90 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
92 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
93 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
95 RREG32(GB_ADDR_CONFIG);
99 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
100 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
102 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
107 local0 = RREG32(CG_CGTT_LOCAL_0);
108 local1 = RREG32(CG_CGTT_LOCAL_1);
111 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
112 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
114 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
115 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
119 static void sumo_program_git(struct radeon_device *rdev)
122 u32 xclk = radeon_get_xclk(rdev);
124 r600_calculate_u_and_p(SUMO_GICST_DFLT,
127 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
130 static void sumo_program_grsd(struct radeon_device *rdev)
133 u32 xclk = radeon_get_xclk(rdev);
134 u32 grs = 256 * 25 / 100;
136 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
138 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
141 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
143 sumo_program_git(rdev);
144 sumo_program_grsd(rdev);
147 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
149 u32 rcu_pwr_gating_cntl;
153 u32 xclk = radeon_get_xclk(rdev);
155 if (rdev->family == CHIP_PALM) {
160 p_p = 50 + 1000/200 + 6 * 32;
169 WREG32(CG_SCRATCH2, 0x01B60A17);
171 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
174 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
175 ~(PGP_MASK | PGU_MASK));
177 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
180 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
181 ~(PGP_MASK | PGU_MASK));
183 if (rdev->family == CHIP_PALM) {
184 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
185 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
187 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
188 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
191 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
192 rcu_pwr_gating_cntl &=
193 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
194 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
195 if (rdev->family == CHIP_PALM) {
196 rcu_pwr_gating_cntl &= ~PCP_MASK;
197 rcu_pwr_gating_cntl |= PCP(0x77);
199 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
201 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
202 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
203 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
204 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
206 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
207 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
208 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
209 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
211 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
212 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
213 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
214 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
216 if (rdev->family == CHIP_PALM)
217 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
219 sumo_smu_pg_init(rdev);
221 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
222 rcu_pwr_gating_cntl &=
223 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
224 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
225 if (rdev->family == CHIP_PALM) {
226 rcu_pwr_gating_cntl &= ~PCP_MASK;
227 rcu_pwr_gating_cntl |= PCP(0x77);
229 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
231 if (rdev->family == CHIP_PALM) {
232 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
233 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
234 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
235 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
237 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
238 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
239 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
240 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
243 sumo_smu_pg_init(rdev);
245 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
246 rcu_pwr_gating_cntl &=
247 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
248 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
250 if (rdev->family == CHIP_PALM) {
251 rcu_pwr_gating_cntl |= PCV(4);
252 rcu_pwr_gating_cntl &= ~PCP_MASK;
253 rcu_pwr_gating_cntl |= PCP(0x77);
255 rcu_pwr_gating_cntl |= PCV(11);
256 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
258 if (rdev->family == CHIP_PALM) {
259 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
260 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
261 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
262 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
264 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
265 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
266 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
267 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
270 sumo_smu_pg_init(rdev);
273 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
276 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
278 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
279 RREG32(GB_ADDR_CONFIG);
283 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
285 struct sumo_power_info *pi = sumo_get_pi(rdev);
287 if (pi->enable_gfx_clock_gating)
288 sumo_gfx_clockgating_initialize(rdev);
289 if (pi->enable_gfx_power_gating)
290 sumo_gfx_powergating_initialize(rdev);
291 if (pi->enable_mg_clock_gating)
292 sumo_mg_clockgating_enable(rdev, true);
293 if (pi->enable_gfx_clock_gating)
294 sumo_gfx_clockgating_enable(rdev, true);
295 if (pi->enable_gfx_power_gating)
296 sumo_gfx_powergating_enable(rdev, true);
301 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
303 struct sumo_power_info *pi = sumo_get_pi(rdev);
305 if (pi->enable_gfx_clock_gating)
306 sumo_gfx_clockgating_enable(rdev, false);
307 if (pi->enable_gfx_power_gating)
308 sumo_gfx_powergating_enable(rdev, false);
309 if (pi->enable_mg_clock_gating)
310 sumo_mg_clockgating_enable(rdev, false);
313 static void sumo_calculate_bsp(struct radeon_device *rdev,
316 struct sumo_power_info *pi = sumo_get_pi(rdev);
317 u32 xclk = radeon_get_xclk(rdev);
319 pi->pasi = 65535 * 100 / high_clk;
320 pi->asi = 65535 * 100 / high_clk;
322 r600_calculate_u_and_p(pi->asi,
323 xclk, 16, &pi->bsp, &pi->bsu);
325 r600_calculate_u_and_p(pi->pasi,
326 xclk, 16, &pi->pbsp, &pi->pbsu);
328 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
329 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
332 static void sumo_init_bsp(struct radeon_device *rdev)
334 struct sumo_power_info *pi = sumo_get_pi(rdev);
336 WREG32(CG_BSP_0, pi->psp);
340 static void sumo_program_bsp(struct radeon_device *rdev,
341 struct radeon_ps *rps)
343 struct sumo_power_info *pi = sumo_get_pi(rdev);
344 struct sumo_ps *ps = sumo_get_ps(rps);
346 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
348 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
349 highest_engine_clock = pi->boost_pl.sclk;
351 sumo_calculate_bsp(rdev, highest_engine_clock);
353 for (i = 0; i < ps->num_levels - 1; i++)
354 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
356 WREG32(CG_BSP_0 + (i * 4), pi->psp);
358 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
359 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
362 static void sumo_write_at(struct radeon_device *rdev,
363 u32 index, u32 value)
366 WREG32(CG_AT_0, value);
368 WREG32(CG_AT_1, value);
370 WREG32(CG_AT_2, value);
372 WREG32(CG_AT_3, value);
374 WREG32(CG_AT_4, value);
376 WREG32(CG_AT_5, value);
378 WREG32(CG_AT_6, value);
380 WREG32(CG_AT_7, value);
383 static void sumo_program_at(struct radeon_device *rdev,
384 struct radeon_ps *rps)
386 struct sumo_power_info *pi = sumo_get_pi(rdev);
387 struct sumo_ps *ps = sumo_get_ps(rps);
392 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
393 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
407 for (i = 0; i < ps->num_levels; i++) {
408 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
410 m_a = asi * ps->levels[i].sclk / 100;
412 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
414 sumo_write_at(rdev, i, a_t);
417 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
420 m_a = asi * pi->boost_pl.sclk / 100;
422 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
423 CG_L(m_a * l[ps->num_levels - 1] / 100);
425 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
429 static void sumo_program_tp(struct radeon_device *rdev)
432 enum r600_td td = R600_TD_DFLT;
434 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
435 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
436 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
439 if (td == R600_TD_AUTO)
440 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
442 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
444 if (td == R600_TD_UP)
445 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
447 if (td == R600_TD_DOWN)
448 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
451 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
456 void sumo_clear_vc(struct radeon_device *rdev)
461 void sumo_program_sstp(struct radeon_device *rdev)
464 u32 xclk = radeon_get_xclk(rdev);
466 r600_calculate_u_and_p(SUMO_SST_DFLT,
469 WREG32(CG_SSP, SSTU(u) | SST(p));
472 static void sumo_set_divider_value(struct radeon_device *rdev,
473 u32 index, u32 divider)
475 u32 reg_index = index / 4;
476 u32 field_index = index % 4;
478 if (field_index == 0)
479 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
480 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
481 else if (field_index == 1)
482 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
483 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
484 else if (field_index == 2)
485 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
486 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
487 else if (field_index == 3)
488 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
489 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
492 static void sumo_set_ds_dividers(struct radeon_device *rdev,
493 u32 index, u32 divider)
495 struct sumo_power_info *pi = sumo_get_pi(rdev);
497 if (pi->enable_sclk_ds) {
498 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
500 dpm_ctrl &= ~(0x7 << (index * 3));
501 dpm_ctrl |= (divider << (index * 3));
502 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
506 static void sumo_set_ss_dividers(struct radeon_device *rdev,
507 u32 index, u32 divider)
509 struct sumo_power_info *pi = sumo_get_pi(rdev);
511 if (pi->enable_sclk_ds) {
512 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
514 dpm_ctrl &= ~(0x7 << (index * 3));
515 dpm_ctrl |= (divider << (index * 3));
516 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
520 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
522 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
524 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
525 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
526 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
529 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
531 struct sumo_power_info *pi = sumo_get_pi(rdev);
533 u32 cg_sclk_dpm_ctrl_3;
535 if (pi->driver_nbps_policy_disable)
538 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
539 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
540 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
542 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
545 static void sumo_program_power_level(struct radeon_device *rdev,
546 struct sumo_pl *pl, u32 index)
548 struct sumo_power_info *pi = sumo_get_pi(rdev);
550 struct atom_clock_dividers dividers;
551 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
553 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
554 pl->sclk, false, ÷rs);
558 sumo_set_divider_value(rdev, index, dividers.post_div);
560 sumo_set_vid(rdev, index, pl->vddc_index);
562 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
564 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
566 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
567 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
570 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
573 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
575 if (pi->enable_boost)
576 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
579 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
581 u32 reg_index = index / 4;
582 u32 field_index = index % 4;
584 if (field_index == 0)
585 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
586 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
587 else if (field_index == 1)
588 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
589 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
590 else if (field_index == 2)
591 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
592 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
593 else if (field_index == 3)
594 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
595 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
598 static bool sumo_dpm_enabled(struct radeon_device *rdev)
600 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
606 static void sumo_start_dpm(struct radeon_device *rdev)
608 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
611 static void sumo_stop_dpm(struct radeon_device *rdev)
613 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
616 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
619 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
621 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
624 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
628 sumo_set_forced_mode(rdev, true);
629 for (i = 0; i < rdev->usec_timeout; i++) {
630 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
636 static void sumo_wait_for_level_0(struct radeon_device *rdev)
640 for (i = 0; i < rdev->usec_timeout; i++) {
641 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
645 for (i = 0; i < rdev->usec_timeout; i++) {
646 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
652 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
654 sumo_set_forced_mode(rdev, false);
657 static void sumo_enable_power_level_0(struct radeon_device *rdev)
659 sumo_power_level_enable(rdev, 0, true);
662 static void sumo_patch_boost_state(struct radeon_device *rdev,
663 struct radeon_ps *rps)
665 struct sumo_power_info *pi = sumo_get_pi(rdev);
666 struct sumo_ps *new_ps = sumo_get_ps(rps);
668 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
669 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
670 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
671 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
672 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
676 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
677 struct radeon_ps *new_rps,
678 struct radeon_ps *old_rps)
680 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
681 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
686 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
688 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
690 if (nbps1_old == 1 && nbps1_new == 0)
691 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
694 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
695 struct radeon_ps *new_rps,
696 struct radeon_ps *old_rps)
698 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
699 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
704 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
706 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
708 if (nbps1_old == 0 && nbps1_new == 1)
709 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
712 static void sumo_enable_boost(struct radeon_device *rdev,
713 struct radeon_ps *rps,
716 struct sumo_ps *new_ps = sumo_get_ps(rps);
719 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
720 sumo_boost_state_enable(rdev, true);
722 sumo_boost_state_enable(rdev, false);
725 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
727 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
730 static void sumo_set_forced_level_0(struct radeon_device *rdev)
732 sumo_set_forced_level(rdev, 0);
735 static void sumo_program_wl(struct radeon_device *rdev,
736 struct radeon_ps *rps)
738 struct sumo_ps *new_ps = sumo_get_ps(rps);
739 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
741 dpm_ctrl4 &= 0xFFFFFF00;
742 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
744 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
745 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
747 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
750 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
751 struct radeon_ps *new_rps,
752 struct radeon_ps *old_rps)
754 struct sumo_power_info *pi = sumo_get_pi(rdev);
755 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
756 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
758 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
760 for (i = 0; i < new_ps->num_levels; i++) {
761 sumo_program_power_level(rdev, &new_ps->levels[i], i);
762 sumo_power_level_enable(rdev, i, true);
765 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
766 sumo_power_level_enable(rdev, i, false);
768 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
769 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
772 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
774 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
777 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
779 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
782 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
784 struct sumo_power_info *pi = sumo_get_pi(rdev);
785 struct atom_clock_dividers dividers;
788 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
794 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
795 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
798 static void sumo_program_bootup_state(struct radeon_device *rdev)
800 struct sumo_power_info *pi = sumo_get_pi(rdev);
801 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
804 sumo_program_power_level(rdev, &pi->boot_pl, 0);
806 dpm_ctrl4 &= 0xFFFFFF00;
807 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
809 for (i = 1; i < 8; i++)
810 sumo_power_level_enable(rdev, i, false);
813 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
814 struct radeon_ps *new_rps,
815 struct radeon_ps *old_rps)
817 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
818 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
820 if ((new_rps->vclk == old_rps->vclk) &&
821 (new_rps->dclk == old_rps->dclk))
824 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
825 current_ps->levels[current_ps->num_levels - 1].sclk)
828 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
831 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
832 struct radeon_ps *new_rps,
833 struct radeon_ps *old_rps)
835 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
836 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
838 if ((new_rps->vclk == old_rps->vclk) &&
839 (new_rps->dclk == old_rps->dclk))
842 if (new_ps->levels[new_ps->num_levels - 1].sclk <
843 current_ps->levels[current_ps->num_levels - 1].sclk)
846 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
849 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
851 /* This bit selects who handles display phy powergating.
852 * Clear the bit to let atom handle it.
853 * Set it to let the driver handle it.
854 * For now we just let atom handle it.
857 u32 v = RREG32(DOUT_SCRATCH3);
864 WREG32(DOUT_SCRATCH3, v);
868 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
871 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
872 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
875 deep_sleep_cntl &= ~R_DIS;
876 deep_sleep_cntl &= ~HS_MASK;
877 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
879 deep_sleep_cntl2 |= LB_UFP_EN;
880 deep_sleep_cntl2 &= INOUT_C_MASK;
881 deep_sleep_cntl2 |= INOUT_C(0xf);
883 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
884 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
886 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
889 static void sumo_program_bootup_at(struct radeon_device *rdev)
891 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
892 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
895 static void sumo_reset_am(struct radeon_device *rdev)
897 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
900 static void sumo_start_am(struct radeon_device *rdev)
902 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
905 static void sumo_program_ttp(struct radeon_device *rdev)
907 u32 xclk = radeon_get_xclk(rdev);
909 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
911 r600_calculate_u_and_p(1000,
914 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
915 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
917 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
920 static void sumo_program_ttt(struct radeon_device *rdev)
922 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
923 struct sumo_power_info *pi = sumo_get_pi(rdev);
925 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
926 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
928 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
932 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
935 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
936 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
938 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
939 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
943 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
945 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
946 ~CNB_THERMTHRO_MASK_SCLK);
949 static void sumo_program_dc_hto(struct radeon_device *rdev)
951 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
953 u32 xclk = radeon_get_xclk(rdev);
955 r600_calculate_u_and_p(100000,
958 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
959 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
961 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
964 static void sumo_force_nbp_state(struct radeon_device *rdev,
965 struct radeon_ps *rps)
967 struct sumo_power_info *pi = sumo_get_pi(rdev);
968 struct sumo_ps *new_ps = sumo_get_ps(rps);
970 if (!pi->driver_nbps_policy_disable) {
971 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
972 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
974 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
978 u32 sumo_get_sleep_divider_from_id(u32 id)
983 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
987 struct sumo_power_info *pi = sumo_get_pi(rdev);
990 u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
991 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
996 if (!pi->enable_sclk_ds)
999 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1000 temp = sclk / sumo_get_sleep_divider_from_id(i);
1002 if (temp >= min || i == 0)
1008 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1011 struct sumo_power_info *pi = sumo_get_pi(rdev);
1014 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1015 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1016 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1019 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1022 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1024 struct sumo_ps *current_ps)
1026 struct sumo_power_info *pi = sumo_get_pi(rdev);
1027 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1030 u32 current_index = 0;
1033 current_vddc = current_ps->levels[current_index].vddc_index;
1034 current_sclk = current_ps->levels[current_index].sclk;
1036 current_vddc = pi->boot_pl.vddc_index;
1037 current_sclk = pi->boot_pl.sclk;
1040 ps->levels[0].vddc_index = current_vddc;
1042 if (ps->levels[0].sclk > current_sclk)
1043 ps->levels[0].sclk = current_sclk;
1045 ps->levels[0].ss_divider_index =
1046 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1048 ps->levels[0].ds_divider_index =
1049 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1051 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1052 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1054 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1055 if (ps->levels[0].ss_divider_index > 1)
1056 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1059 if (ps->levels[0].ss_divider_index == 0)
1060 ps->levels[0].ds_divider_index = 0;
1062 if (ps->levels[0].ds_divider_index == 0)
1063 ps->levels[0].ss_divider_index = 0;
1066 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1067 struct radeon_ps *new_rps,
1068 struct radeon_ps *old_rps)
1070 struct sumo_ps *ps = sumo_get_ps(new_rps);
1071 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1072 struct sumo_power_info *pi = sumo_get_pi(rdev);
1073 u32 min_voltage = 0; /* ??? */
1074 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1075 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1078 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1079 return sumo_patch_thermal_state(rdev, ps, current_ps);
1081 if (pi->enable_boost) {
1082 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1083 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1086 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1087 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1088 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1089 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1091 for (i = 0; i < ps->num_levels; i++) {
1092 if (ps->levels[i].vddc_index < min_voltage)
1093 ps->levels[i].vddc_index = min_voltage;
1095 if (ps->levels[i].sclk < min_sclk)
1096 ps->levels[i].sclk =
1097 sumo_get_valid_engine_clock(rdev, min_sclk);
1099 ps->levels[i].ss_divider_index =
1100 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1102 ps->levels[i].ds_divider_index =
1103 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1105 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1106 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1108 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1109 if (ps->levels[i].ss_divider_index > 1)
1110 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1113 if (ps->levels[i].ss_divider_index == 0)
1114 ps->levels[i].ds_divider_index = 0;
1116 if (ps->levels[i].ds_divider_index == 0)
1117 ps->levels[i].ss_divider_index = 0;
1119 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1120 ps->levels[i].allow_gnb_slow = 1;
1121 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1122 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1123 ps->levels[i].allow_gnb_slow = 0;
1124 else if (i == ps->num_levels - 1)
1125 ps->levels[i].allow_gnb_slow = 0;
1127 ps->levels[i].allow_gnb_slow = 1;
1131 static void sumo_cleanup_asic(struct radeon_device *rdev)
1133 sumo_take_smu_control(rdev, false);
1136 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1137 int min_temp, int max_temp)
1139 int low_temp = 0 * 1000;
1140 int high_temp = 255 * 1000;
1142 if (low_temp < min_temp)
1143 low_temp = min_temp;
1144 if (high_temp > max_temp)
1145 high_temp = max_temp;
1146 if (high_temp < low_temp) {
1147 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1151 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1152 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1154 rdev->pm.dpm.thermal.min_temp = low_temp;
1155 rdev->pm.dpm.thermal.max_temp = high_temp;
1160 static void sumo_update_current_ps(struct radeon_device *rdev,
1161 struct radeon_ps *rps)
1163 struct sumo_ps *new_ps = sumo_get_ps(rps);
1164 struct sumo_power_info *pi = sumo_get_pi(rdev);
1166 pi->current_rps = *rps;
1167 pi->current_ps = *new_ps;
1168 pi->current_rps.ps_priv = &pi->current_ps;
1171 static void sumo_update_requested_ps(struct radeon_device *rdev,
1172 struct radeon_ps *rps)
1174 struct sumo_ps *new_ps = sumo_get_ps(rps);
1175 struct sumo_power_info *pi = sumo_get_pi(rdev);
1177 pi->requested_rps = *rps;
1178 pi->requested_ps = *new_ps;
1179 pi->requested_rps.ps_priv = &pi->requested_ps;
1182 int sumo_dpm_enable(struct radeon_device *rdev)
1184 struct sumo_power_info *pi = sumo_get_pi(rdev);
1187 if (sumo_dpm_enabled(rdev))
1190 ret = sumo_enable_clock_power_gating(rdev);
1193 sumo_program_bootup_state(rdev);
1194 sumo_init_bsp(rdev);
1195 sumo_reset_am(rdev);
1196 sumo_program_tp(rdev);
1197 sumo_program_bootup_at(rdev);
1198 sumo_start_am(rdev);
1199 if (pi->enable_auto_thermal_throttling) {
1200 sumo_program_ttp(rdev);
1201 sumo_program_ttt(rdev);
1203 sumo_program_dc_hto(rdev);
1204 sumo_program_power_level_enter_state(rdev);
1205 sumo_enable_voltage_scaling(rdev, true);
1206 sumo_program_sstp(rdev);
1207 sumo_program_vc(rdev, SUMO_VRC_DFLT);
1208 sumo_override_cnb_thermal_events(rdev);
1209 sumo_start_dpm(rdev);
1210 sumo_wait_for_level_0(rdev);
1211 if (pi->enable_sclk_ds)
1212 sumo_enable_sclk_ds(rdev, true);
1213 if (pi->enable_boost)
1214 sumo_enable_boost_timer(rdev);
1216 if (rdev->irq.installed &&
1217 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1218 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1221 rdev->irq.dpm_thermal = true;
1222 radeon_irq_set(rdev);
1225 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1230 void sumo_dpm_disable(struct radeon_device *rdev)
1232 struct sumo_power_info *pi = sumo_get_pi(rdev);
1234 if (!sumo_dpm_enabled(rdev))
1236 sumo_disable_clock_power_gating(rdev);
1237 if (pi->enable_sclk_ds)
1238 sumo_enable_sclk_ds(rdev, false);
1239 sumo_clear_vc(rdev);
1240 sumo_wait_for_level_0(rdev);
1241 sumo_stop_dpm(rdev);
1242 sumo_enable_voltage_scaling(rdev, false);
1244 if (rdev->irq.installed &&
1245 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1246 rdev->irq.dpm_thermal = false;
1247 radeon_irq_set(rdev);
1250 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1253 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1255 struct sumo_power_info *pi = sumo_get_pi(rdev);
1256 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1257 struct radeon_ps *new_ps = &requested_ps;
1259 sumo_update_requested_ps(rdev, new_ps);
1261 if (pi->enable_dynamic_patch_ps)
1262 sumo_apply_state_adjust_rules(rdev,
1269 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1271 struct sumo_power_info *pi = sumo_get_pi(rdev);
1272 struct radeon_ps *new_ps = &pi->requested_rps;
1273 struct radeon_ps *old_ps = &pi->current_rps;
1276 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1277 if (pi->enable_boost) {
1278 sumo_enable_boost(rdev, new_ps, false);
1279 sumo_patch_boost_state(rdev, new_ps);
1281 if (pi->enable_dpm) {
1282 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1283 sumo_enable_power_level_0(rdev);
1284 sumo_set_forced_level_0(rdev);
1285 sumo_set_forced_mode_enabled(rdev);
1286 sumo_wait_for_level_0(rdev);
1287 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1288 sumo_program_wl(rdev, new_ps);
1289 sumo_program_bsp(rdev, new_ps);
1290 sumo_program_at(rdev, new_ps);
1291 sumo_force_nbp_state(rdev, new_ps);
1292 sumo_set_forced_mode_disabled(rdev);
1293 sumo_set_forced_mode_enabled(rdev);
1294 sumo_set_forced_mode_disabled(rdev);
1295 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1297 if (pi->enable_boost)
1298 sumo_enable_boost(rdev, new_ps, true);
1300 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1305 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1307 struct sumo_power_info *pi = sumo_get_pi(rdev);
1308 struct radeon_ps *new_ps = &pi->requested_rps;
1310 sumo_update_current_ps(rdev, new_ps);
1313 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1315 sumo_program_bootup_state(rdev);
1316 sumo_enable_power_level_0(rdev);
1317 sumo_set_forced_level_0(rdev);
1318 sumo_set_forced_mode_enabled(rdev);
1319 sumo_wait_for_level_0(rdev);
1320 sumo_set_forced_mode_disabled(rdev);
1321 sumo_set_forced_mode_enabled(rdev);
1322 sumo_set_forced_mode_disabled(rdev);
1325 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1327 struct sumo_power_info *pi = sumo_get_pi(rdev);
1329 sumo_initialize_m3_arb(rdev);
1330 pi->fw_version = sumo_get_running_fw_version(rdev);
1331 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1332 sumo_program_acpi_power_level(rdev);
1333 sumo_enable_acpi_pm(rdev);
1334 sumo_take_smu_control(rdev, true);
1337 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1343 struct _ATOM_POWERPLAY_INFO info;
1344 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1345 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1346 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1347 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1348 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1351 union pplib_clock_info {
1352 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1353 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1354 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1355 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1358 union pplib_power_state {
1359 struct _ATOM_PPLIB_STATE v1;
1360 struct _ATOM_PPLIB_STATE_V2 v2;
1363 static void sumo_patch_boot_state(struct radeon_device *rdev,
1366 struct sumo_power_info *pi = sumo_get_pi(rdev);
1370 ps->levels[0] = pi->boot_pl;
1373 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1374 struct radeon_ps *rps,
1375 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1378 struct sumo_ps *ps = sumo_get_ps(rps);
1380 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1381 rps->class = le16_to_cpu(non_clock_info->usClassification);
1382 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1384 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1385 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1386 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1392 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1393 rdev->pm.dpm.boot_ps = rps;
1394 sumo_patch_boot_state(rdev, ps);
1396 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1397 rdev->pm.dpm.uvd_ps = rps;
1400 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1401 struct radeon_ps *rps, int index,
1402 union pplib_clock_info *clock_info)
1404 struct sumo_power_info *pi = sumo_get_pi(rdev);
1405 struct sumo_ps *ps = sumo_get_ps(rps);
1406 struct sumo_pl *pl = &ps->levels[index];
1409 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1410 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1412 pl->vddc_index = clock_info->sumo.vddcIndex;
1413 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1415 ps->num_levels = index + 1;
1417 if (pi->enable_sclk_ds) {
1418 pl->ds_divider_index = 5;
1419 pl->ss_divider_index = 4;
1423 static int sumo_parse_power_table(struct radeon_device *rdev)
1425 struct radeon_mode_info *mode_info = &rdev->mode_info;
1426 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1427 union pplib_power_state *power_state;
1428 int i, j, k, non_clock_array_index, clock_array_index;
1429 union pplib_clock_info *clock_info;
1430 struct _StateArray *state_array;
1431 struct _ClockInfoArray *clock_info_array;
1432 struct _NonClockInfoArray *non_clock_info_array;
1433 union power_info *power_info;
1434 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1437 u8 *power_state_offset;
1440 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1441 &frev, &crev, &data_offset))
1443 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1445 state_array = (struct _StateArray *)
1446 (mode_info->atom_context->bios + data_offset +
1447 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1448 clock_info_array = (struct _ClockInfoArray *)
1449 (mode_info->atom_context->bios + data_offset +
1450 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1451 non_clock_info_array = (struct _NonClockInfoArray *)
1452 (mode_info->atom_context->bios + data_offset +
1453 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1455 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1456 state_array->ucNumEntries, GFP_KERNEL);
1457 if (!rdev->pm.dpm.ps)
1459 power_state_offset = (u8 *)state_array->states;
1460 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1461 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1462 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1463 for (i = 0; i < state_array->ucNumEntries; i++) {
1464 power_state = (union pplib_power_state *)power_state_offset;
1465 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1466 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1467 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1468 if (!rdev->pm.power_state[i].clock_info)
1470 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1472 kfree(rdev->pm.dpm.ps);
1475 rdev->pm.dpm.ps[i].ps_priv = ps;
1477 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1478 clock_array_index = power_state->v2.clockInfoIndex[j];
1479 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1481 clock_info = (union pplib_clock_info *)
1482 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1483 sumo_parse_pplib_clock_info(rdev,
1484 &rdev->pm.dpm.ps[i], k,
1488 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1490 non_clock_info_array->ucEntrySize);
1491 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1493 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1497 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1498 struct sumo_vid_mapping_table *vid_mapping_table,
1503 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1504 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1505 return vid_mapping_table->entries[i].vid_7bit;
1508 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1511 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1514 struct sumo_power_info *pi = sumo_get_pi(rdev);
1515 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1517 if (vid_7bit > 0x7C)
1520 return (15500 - vid_7bit * 125 + 5) / 10;
1523 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1524 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1525 ATOM_CLK_VOLT_CAPABILITY *table)
1529 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1530 if (table[i].ulMaximumSupportedCLK == 0)
1533 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1534 table[i].ulMaximumSupportedCLK;
1537 disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1539 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1540 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1541 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1545 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1546 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1547 ATOM_AVAILABLE_SCLK_LIST *table)
1553 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1554 if (table[i].ulSupportedSCLK > prev_sclk) {
1555 sclk_voltage_mapping_table->entries[n].sclk_frequency =
1556 table[i].ulSupportedSCLK;
1557 sclk_voltage_mapping_table->entries[n].vid_2bit =
1558 table[i].usVoltageIndex;
1559 prev_sclk = table[i].ulSupportedSCLK;
1564 sclk_voltage_mapping_table->num_max_dpm_entries = n;
1567 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1568 struct sumo_vid_mapping_table *vid_mapping_table,
1569 ATOM_AVAILABLE_SCLK_LIST *table)
1573 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1574 if (table[i].ulSupportedSCLK != 0) {
1575 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1576 table[i].usVoltageID;
1577 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1578 table[i].usVoltageIndex;
1582 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1583 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1584 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1585 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1586 vid_mapping_table->entries[i] =
1587 vid_mapping_table->entries[j];
1588 vid_mapping_table->entries[j].vid_7bit = 0;
1593 if (j == SUMO_MAX_NUMBER_VOLTAGES)
1598 vid_mapping_table->num_entries = i;
1602 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1603 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1604 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1605 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1608 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1610 struct sumo_power_info *pi = sumo_get_pi(rdev);
1611 struct radeon_mode_info *mode_info = &rdev->mode_info;
1612 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1613 union igp_info *igp_info;
1618 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1619 &frev, &crev, &data_offset)) {
1620 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1624 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1627 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1628 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1629 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1630 pi->sys_info.bootup_nb_voltage_index =
1631 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1632 if (igp_info->info_6.ucHtcTmpLmt == 0)
1633 pi->sys_info.htc_tmp_lmt = 203;
1635 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1636 if (igp_info->info_6.ucHtcHystLmt == 0)
1637 pi->sys_info.htc_hyst_lmt = 5;
1639 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1640 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1641 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1643 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1644 pi->sys_info.csr_m3_arb_cntl_default[i] =
1645 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1646 pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1647 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1648 pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1649 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1651 pi->sys_info.sclk_dpm_boost_margin =
1652 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1653 pi->sys_info.sclk_dpm_throttle_margin =
1654 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1655 pi->sys_info.sclk_dpm_tdp_limit_pg =
1656 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1657 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1658 pi->sys_info.sclk_dpm_tdp_limit_boost =
1659 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1660 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1661 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1662 if (igp_info->info_6.EnableBoost)
1663 pi->sys_info.enable_boost = true;
1665 pi->sys_info.enable_boost = false;
1666 sumo_construct_display_voltage_mapping_table(rdev,
1667 &pi->sys_info.disp_clk_voltage_mapping_table,
1668 igp_info->info_6.sDISPCLK_Voltage);
1669 sumo_construct_sclk_voltage_mapping_table(rdev,
1670 &pi->sys_info.sclk_voltage_mapping_table,
1671 igp_info->info_6.sAvail_SCLK);
1672 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1673 igp_info->info_6.sAvail_SCLK);
1679 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1681 struct sumo_power_info *pi = sumo_get_pi(rdev);
1683 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1684 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1685 pi->boot_pl.ds_divider_index = 0;
1686 pi->boot_pl.ss_divider_index = 0;
1687 pi->boot_pl.allow_gnb_slow = 1;
1688 pi->acpi_pl = pi->boot_pl;
1689 pi->current_ps.num_levels = 1;
1690 pi->current_ps.levels[0] = pi->boot_pl;
1693 int sumo_dpm_init(struct radeon_device *rdev)
1695 struct sumo_power_info *pi;
1696 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1699 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1702 rdev->pm.dpm.priv = pi;
1704 pi->driver_nbps_policy_disable = false;
1705 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1706 pi->disable_gfx_power_gating_in_uvd = true;
1708 pi->disable_gfx_power_gating_in_uvd = false;
1709 pi->enable_alt_vddnb = true;
1710 pi->enable_sclk_ds = true;
1711 pi->enable_dynamic_m3_arbiter = false;
1712 pi->enable_dynamic_patch_ps = true;
1713 pi->enable_gfx_power_gating = true;
1714 pi->enable_gfx_clock_gating = true;
1715 pi->enable_mg_clock_gating = true;
1716 pi->enable_auto_thermal_throttling = true;
1718 ret = sumo_parse_sys_info_table(rdev);
1722 sumo_construct_boot_and_acpi_state(rdev);
1724 ret = sumo_parse_power_table(rdev);
1728 pi->pasi = CYPRESS_HASI_DFLT;
1729 pi->asi = RV770_ASI_DFLT;
1730 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1731 pi->enable_boost = pi->sys_info.enable_boost;
1732 pi->enable_dpm = true;
1737 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1738 struct radeon_ps *rps)
1741 struct sumo_ps *ps = sumo_get_ps(rps);
1743 r600_dpm_print_class_info(rps->class, rps->class2);
1744 r600_dpm_print_cap_info(rps->caps);
1745 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1746 for (i = 0; i < ps->num_levels; i++) {
1747 struct sumo_pl *pl = &ps->levels[i];
1748 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1750 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1752 r600_dpm_print_ps_status(rdev, rps);
1755 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1758 struct sumo_power_info *pi = sumo_get_pi(rdev);
1759 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1760 struct sumo_ps *ps = sumo_get_ps(rps);
1763 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1766 if (current_index == BOOST_DPM_LEVEL) {
1768 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1769 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1770 current_index, pl->sclk,
1771 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1772 } else if (current_index >= ps->num_levels) {
1773 seq_printf(m, "invalid dpm profile %d\n", current_index);
1775 pl = &ps->levels[current_index];
1776 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1777 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1778 current_index, pl->sclk,
1779 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1783 void sumo_dpm_fini(struct radeon_device *rdev)
1787 sumo_cleanup_asic(rdev); /* ??? */
1789 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1790 kfree(rdev->pm.dpm.ps[i].ps_priv);
1792 kfree(rdev->pm.dpm.ps);
1793 kfree(rdev->pm.dpm.priv);
1796 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1798 struct sumo_power_info *pi = sumo_get_pi(rdev);
1799 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1802 return requested_state->levels[0].sclk;
1804 return requested_state->levels[requested_state->num_levels - 1].sclk;
1807 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1809 struct sumo_power_info *pi = sumo_get_pi(rdev);
1811 return pi->sys_info.bootup_uma_clk;