drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175 static struct radeon_asic r100_asic = {
 176         .init = &r100_init,
 177         .fini = &r100_fini,
 178         .suspend = &r100_suspend,
 179         .resume = &r100_resume,
 180         .vga_set_state = &r100_vga_set_state,
 181         .asic_reset = &r100_asic_reset,
 182         .ioctl_wait_idle = NULL,
 183         .gui_idle = &r100_gui_idle,
 184         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 185         .gart = {
 186                 .tlb_flush = &r100_pci_gart_tlb_flush,
 187                 .set_page = &r100_pci_gart_set_page,
 188         },
 189         .ring = {
 190                 [RADEON_RING_TYPE_GFX_INDEX] = {
 191                         .ib_execute = &r100_ring_ib_execute,
 192                         .emit_fence = &r100_fence_ring_emit,
 193                         .emit_semaphore = &r100_semaphore_ring_emit,
 194                         .cs_parse = &r100_cs_parse,
 195                         .ring_start = &r100_ring_start,
 196                         .ring_test = &r100_ring_test,
 197                         .ib_test = &r100_ib_test,
 198                         .is_lockup = &r100_gpu_is_lockup,
 199                         .get_rptr = &radeon_ring_generic_get_rptr,
 200                         .get_wptr = &radeon_ring_generic_get_wptr,
 201                         .set_wptr = &radeon_ring_generic_set_wptr,
 202                 }
 203         },
 204         .irq = {
 205                 .set = &r100_irq_set,
 206                 .process = &r100_irq_process,
 207         },
 208         .display = {
 209                 .bandwidth_update = &r100_bandwidth_update,
 210                 .get_vblank_counter = &r100_get_vblank_counter,
 211                 .wait_for_vblank = &r100_wait_for_vblank,
 212                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 213                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 214         },
 215         .copy = {
 216                 .blit = &r100_copy_blit,
 217                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 218                 .dma = NULL,
 219                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 220                 .copy = &r100_copy_blit,
 221                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222         },
 223         .surface = {
 224                 .set_reg = r100_set_surface_reg,
 225                 .clear_reg = r100_clear_surface_reg,
 226         },
 227         .hpd = {
 228                 .init = &r100_hpd_init,
 229                 .fini = &r100_hpd_fini,
 230                 .sense = &r100_hpd_sense,
 231                 .set_polarity = &r100_hpd_set_polarity,
 232         },
 233         .pm = {
 234                 .misc = &r100_pm_misc,
 235                 .prepare = &r100_pm_prepare,
 236                 .finish = &r100_pm_finish,
 237                 .init_profile = &r100_pm_init_profile,
 238                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 239                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 240                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 241                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 242                 .set_memory_clock = NULL,
 243                 .get_pcie_lanes = NULL,
 244                 .set_pcie_lanes = NULL,
 245                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 246         },
 247         .pflip = {
 248                 .pre_page_flip = &r100_pre_page_flip,
 249                 .page_flip = &r100_page_flip,
 250                 .post_page_flip = &r100_post_page_flip,
 251         },
 252 };
 253
 254 static struct radeon_asic r200_asic = {
 255         .init = &r100_init,
 256         .fini = &r100_fini,
 257         .suspend = &r100_suspend,
 258         .resume = &r100_resume,
 259         .vga_set_state = &r100_vga_set_state,
 260         .asic_reset = &r100_asic_reset,
 261         .ioctl_wait_idle = NULL,
 262         .gui_idle = &r100_gui_idle,
 263         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 264         .gart = {
 265                 .tlb_flush = &r100_pci_gart_tlb_flush,
 266                 .set_page = &r100_pci_gart_set_page,
 267         },
 268         .ring = {
 269                 [RADEON_RING_TYPE_GFX_INDEX] = {
 270                         .ib_execute = &r100_ring_ib_execute,
 271                         .emit_fence = &r100_fence_ring_emit,
 272                         .emit_semaphore = &r100_semaphore_ring_emit,
 273                         .cs_parse = &r100_cs_parse,
 274                         .ring_start = &r100_ring_start,
 275                         .ring_test = &r100_ring_test,
 276                         .ib_test = &r100_ib_test,
 277                         .is_lockup = &r100_gpu_is_lockup,
 278                         .get_rptr = &radeon_ring_generic_get_rptr,
 279                         .get_wptr = &radeon_ring_generic_get_wptr,
 280                         .set_wptr = &radeon_ring_generic_set_wptr,
 281                 }
 282         },
 283         .irq = {
 284                 .set = &r100_irq_set,
 285                 .process = &r100_irq_process,
 286         },
 287         .display = {
 288                 .bandwidth_update = &r100_bandwidth_update,
 289                 .get_vblank_counter = &r100_get_vblank_counter,
 290                 .wait_for_vblank = &r100_wait_for_vblank,
 291                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 292                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 293         },
 294         .copy = {
 295                 .blit = &r100_copy_blit,
 296                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 297                 .dma = &r200_copy_dma,
 298                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 299                 .copy = &r100_copy_blit,
 300                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 301         },
 302         .surface = {
 303                 .set_reg = r100_set_surface_reg,
 304                 .clear_reg = r100_clear_surface_reg,
 305         },
 306         .hpd = {
 307                 .init = &r100_hpd_init,
 308                 .fini = &r100_hpd_fini,
 309                 .sense = &r100_hpd_sense,
 310                 .set_polarity = &r100_hpd_set_polarity,
 311         },
 312         .pm = {
 313                 .misc = &r100_pm_misc,
 314                 .prepare = &r100_pm_prepare,
 315                 .finish = &r100_pm_finish,
 316                 .init_profile = &r100_pm_init_profile,
 317                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 318                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 319                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 320                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 321                 .set_memory_clock = NULL,
 322                 .get_pcie_lanes = NULL,
 323                 .set_pcie_lanes = NULL,
 324                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 325         },
 326         .pflip = {
 327                 .pre_page_flip = &r100_pre_page_flip,
 328                 .page_flip = &r100_page_flip,
 329                 .post_page_flip = &r100_post_page_flip,
 330         },
 331 };
 332
 333 static struct radeon_asic r300_asic = {
 334         .init = &r300_init,
 335         .fini = &r300_fini,
 336         .suspend = &r300_suspend,
 337         .resume = &r300_resume,
 338         .vga_set_state = &r100_vga_set_state,
 339         .asic_reset = &r300_asic_reset,
 340         .ioctl_wait_idle = NULL,
 341         .gui_idle = &r100_gui_idle,
 342         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 343         .gart = {
 344                 .tlb_flush = &r100_pci_gart_tlb_flush,
 345                 .set_page = &r100_pci_gart_set_page,
 346         },
 347         .ring = {
 348                 [RADEON_RING_TYPE_GFX_INDEX] = {
 349                         .ib_execute = &r100_ring_ib_execute,
 350                         .emit_fence = &r300_fence_ring_emit,
 351                         .emit_semaphore = &r100_semaphore_ring_emit,
 352                         .cs_parse = &r300_cs_parse,
 353                         .ring_start = &r300_ring_start,
 354                         .ring_test = &r100_ring_test,
 355                         .ib_test = &r100_ib_test,
 356                         .is_lockup = &r100_gpu_is_lockup,
 357                         .get_rptr = &radeon_ring_generic_get_rptr,
 358                         .get_wptr = &radeon_ring_generic_get_wptr,
 359                         .set_wptr = &radeon_ring_generic_set_wptr,
 360                 }
 361         },
 362         .irq = {
 363                 .set = &r100_irq_set,
 364                 .process = &r100_irq_process,
 365         },
 366         .display = {
 367                 .bandwidth_update = &r100_bandwidth_update,
 368                 .get_vblank_counter = &r100_get_vblank_counter,
 369                 .wait_for_vblank = &r100_wait_for_vblank,
 370                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 371                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 372         },
 373         .copy = {
 374                 .blit = &r100_copy_blit,
 375                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 376                 .dma = &r200_copy_dma,
 377                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 378                 .copy = &r100_copy_blit,
 379                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 380         },
 381         .surface = {
 382                 .set_reg = r100_set_surface_reg,
 383                 .clear_reg = r100_clear_surface_reg,
 384         },
 385         .hpd = {
 386                 .init = &r100_hpd_init,
 387                 .fini = &r100_hpd_fini,
 388                 .sense = &r100_hpd_sense,
 389                 .set_polarity = &r100_hpd_set_polarity,
 390         },
 391         .pm = {
 392                 .misc = &r100_pm_misc,
 393                 .prepare = &r100_pm_prepare,
 394                 .finish = &r100_pm_finish,
 395                 .init_profile = &r100_pm_init_profile,
 396                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 397                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 398                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 399                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 400                 .set_memory_clock = NULL,
 401                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 402                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 403                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 404         },
 405         .pflip = {
 406                 .pre_page_flip = &r100_pre_page_flip,
 407                 .page_flip = &r100_page_flip,
 408                 .post_page_flip = &r100_post_page_flip,
 409         },
 410 };
 411
 412 static struct radeon_asic r300_asic_pcie = {
 413         .init = &r300_init,
 414         .fini = &r300_fini,
 415         .suspend = &r300_suspend,
 416         .resume = &r300_resume,
 417         .vga_set_state = &r100_vga_set_state,
 418         .asic_reset = &r300_asic_reset,
 419         .ioctl_wait_idle = NULL,
 420         .gui_idle = &r100_gui_idle,
 421         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 422         .gart = {
 423                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 424                 .set_page = &rv370_pcie_gart_set_page,
 425         },
 426         .ring = {
 427                 [RADEON_RING_TYPE_GFX_INDEX] = {
 428                         .ib_execute = &r100_ring_ib_execute,
 429                         .emit_fence = &r300_fence_ring_emit,
 430                         .emit_semaphore = &r100_semaphore_ring_emit,
 431                         .cs_parse = &r300_cs_parse,
 432                         .ring_start = &r300_ring_start,
 433                         .ring_test = &r100_ring_test,
 434                         .ib_test = &r100_ib_test,
 435                         .is_lockup = &r100_gpu_is_lockup,
 436                         .get_rptr = &radeon_ring_generic_get_rptr,
 437                         .get_wptr = &radeon_ring_generic_get_wptr,
 438                         .set_wptr = &radeon_ring_generic_set_wptr,
 439                 }
 440         },
 441         .irq = {
 442                 .set = &r100_irq_set,
 443                 .process = &r100_irq_process,
 444         },
 445         .display = {
 446                 .bandwidth_update = &r100_bandwidth_update,
 447                 .get_vblank_counter = &r100_get_vblank_counter,
 448                 .wait_for_vblank = &r100_wait_for_vblank,
 449                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 450                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 451         },
 452         .copy = {
 453                 .blit = &r100_copy_blit,
 454                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 455                 .dma = &r200_copy_dma,
 456                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 457                 .copy = &r100_copy_blit,
 458                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 459         },
 460         .surface = {
 461                 .set_reg = r100_set_surface_reg,
 462                 .clear_reg = r100_clear_surface_reg,
 463         },
 464         .hpd = {
 465                 .init = &r100_hpd_init,
 466                 .fini = &r100_hpd_fini,
 467                 .sense = &r100_hpd_sense,
 468                 .set_polarity = &r100_hpd_set_polarity,
 469         },
 470         .pm = {
 471                 .misc = &r100_pm_misc,
 472                 .prepare = &r100_pm_prepare,
 473                 .finish = &r100_pm_finish,
 474                 .init_profile = &r100_pm_init_profile,
 475                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 476                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 477                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 478                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 479                 .set_memory_clock = NULL,
 480                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 481                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 482                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 483         },
 484         .pflip = {
 485                 .pre_page_flip = &r100_pre_page_flip,
 486                 .page_flip = &r100_page_flip,
 487                 .post_page_flip = &r100_post_page_flip,
 488         },
 489 };
 490
 491 static struct radeon_asic r420_asic = {
 492         .init = &r420_init,
 493         .fini = &r420_fini,
 494         .suspend = &r420_suspend,
 495         .resume = &r420_resume,
 496         .vga_set_state = &r100_vga_set_state,
 497         .asic_reset = &r300_asic_reset,
 498         .ioctl_wait_idle = NULL,
 499         .gui_idle = &r100_gui_idle,
 500         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 501         .gart = {
 502                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 503                 .set_page = &rv370_pcie_gart_set_page,
 504         },
 505         .ring = {
 506                 [RADEON_RING_TYPE_GFX_INDEX] = {
 507                         .ib_execute = &r100_ring_ib_execute,
 508                         .emit_fence = &r300_fence_ring_emit,
 509                         .emit_semaphore = &r100_semaphore_ring_emit,
 510                         .cs_parse = &r300_cs_parse,
 511                         .ring_start = &r300_ring_start,
 512                         .ring_test = &r100_ring_test,
 513                         .ib_test = &r100_ib_test,
 514                         .is_lockup = &r100_gpu_is_lockup,
 515                         .get_rptr = &radeon_ring_generic_get_rptr,
 516                         .get_wptr = &radeon_ring_generic_get_wptr,
 517                         .set_wptr = &radeon_ring_generic_set_wptr,
 518                 }
 519         },
 520         .irq = {
 521                 .set = &r100_irq_set,
 522                 .process = &r100_irq_process,
 523         },
 524         .display = {
 525                 .bandwidth_update = &r100_bandwidth_update,
 526                 .get_vblank_counter = &r100_get_vblank_counter,
 527                 .wait_for_vblank = &r100_wait_for_vblank,
 528                 .set_backlight_level = &atombios_set_backlight_level,
 529                 .get_backlight_level = &atombios_get_backlight_level,
 530         },
 531         .copy = {
 532                 .blit = &r100_copy_blit,
 533                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 534                 .dma = &r200_copy_dma,
 535                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 536                 .copy = &r100_copy_blit,
 537                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 538         },
 539         .surface = {
 540                 .set_reg = r100_set_surface_reg,
 541                 .clear_reg = r100_clear_surface_reg,
 542         },
 543         .hpd = {
 544                 .init = &r100_hpd_init,
 545                 .fini = &r100_hpd_fini,
 546                 .sense = &r100_hpd_sense,
 547                 .set_polarity = &r100_hpd_set_polarity,
 548         },
 549         .pm = {
 550                 .misc = &r100_pm_misc,
 551                 .prepare = &r100_pm_prepare,
 552                 .finish = &r100_pm_finish,
 553                 .init_profile = &r420_pm_init_profile,
 554                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 555                 .get_engine_clock = &radeon_atom_get_engine_clock,
 556                 .set_engine_clock = &radeon_atom_set_engine_clock,
 557                 .get_memory_clock = &radeon_atom_get_memory_clock,
 558                 .set_memory_clock = &radeon_atom_set_memory_clock,
 559                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 560                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 561                 .set_clock_gating = &radeon_atom_set_clock_gating,
 562         },
 563         .pflip = {
 564                 .pre_page_flip = &r100_pre_page_flip,
 565                 .page_flip = &r100_page_flip,
 566                 .post_page_flip = &r100_post_page_flip,
 567         },
 568 };
 569
 570 static struct radeon_asic rs400_asic = {
 571         .init = &rs400_init,
 572         .fini = &rs400_fini,
 573         .suspend = &rs400_suspend,
 574         .resume = &rs400_resume,
 575         .vga_set_state = &r100_vga_set_state,
 576         .asic_reset = &r300_asic_reset,
 577         .ioctl_wait_idle = NULL,
 578         .gui_idle = &r100_gui_idle,
 579         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 580         .gart = {
 581                 .tlb_flush = &rs400_gart_tlb_flush,
 582                 .set_page = &rs400_gart_set_page,
 583         },
 584         .ring = {
 585                 [RADEON_RING_TYPE_GFX_INDEX] = {
 586                         .ib_execute = &r100_ring_ib_execute,
 587                         .emit_fence = &r300_fence_ring_emit,
 588                         .emit_semaphore = &r100_semaphore_ring_emit,
 589                         .cs_parse = &r300_cs_parse,
 590                         .ring_start = &r300_ring_start,
 591                         .ring_test = &r100_ring_test,
 592                         .ib_test = &r100_ib_test,
 593                         .is_lockup = &r100_gpu_is_lockup,
 594                         .get_rptr = &radeon_ring_generic_get_rptr,
 595                         .get_wptr = &radeon_ring_generic_get_wptr,
 596                         .set_wptr = &radeon_ring_generic_set_wptr,
 597                 }
 598         },
 599         .irq = {
 600                 .set = &r100_irq_set,
 601                 .process = &r100_irq_process,
 602         },
 603         .display = {
 604                 .bandwidth_update = &r100_bandwidth_update,
 605                 .get_vblank_counter = &r100_get_vblank_counter,
 606                 .wait_for_vblank = &r100_wait_for_vblank,
 607                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 608                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 609         },
 610         .copy = {
 611                 .blit = &r100_copy_blit,
 612                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 613                 .dma = &r200_copy_dma,
 614                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 615                 .copy = &r100_copy_blit,
 616                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 617         },
 618         .surface = {
 619                 .set_reg = r100_set_surface_reg,
 620                 .clear_reg = r100_clear_surface_reg,
 621         },
 622         .hpd = {
 623                 .init = &r100_hpd_init,
 624                 .fini = &r100_hpd_fini,
 625                 .sense = &r100_hpd_sense,
 626                 .set_polarity = &r100_hpd_set_polarity,
 627         },
 628         .pm = {
 629                 .misc = &r100_pm_misc,
 630                 .prepare = &r100_pm_prepare,
 631                 .finish = &r100_pm_finish,
 632                 .init_profile = &r100_pm_init_profile,
 633                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 634                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 635                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 636                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 637                 .set_memory_clock = NULL,
 638                 .get_pcie_lanes = NULL,
 639                 .set_pcie_lanes = NULL,
 640                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 641         },
 642         .pflip = {
 643                 .pre_page_flip = &r100_pre_page_flip,
 644                 .page_flip = &r100_page_flip,
 645                 .post_page_flip = &r100_post_page_flip,
 646         },
 647 };
 648
 649 static struct radeon_asic rs600_asic = {
 650         .init = &rs600_init,
 651         .fini = &rs600_fini,
 652         .suspend = &rs600_suspend,
 653         .resume = &rs600_resume,
 654         .vga_set_state = &r100_vga_set_state,
 655         .asic_reset = &rs600_asic_reset,
 656         .ioctl_wait_idle = NULL,
 657         .gui_idle = &r100_gui_idle,
 658         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 659         .gart = {
 660                 .tlb_flush = &rs600_gart_tlb_flush,
 661                 .set_page = &rs600_gart_set_page,
 662         },
 663         .ring = {
 664                 [RADEON_RING_TYPE_GFX_INDEX] = {
 665                         .ib_execute = &r100_ring_ib_execute,
 666                         .emit_fence = &r300_fence_ring_emit,
 667                         .emit_semaphore = &r100_semaphore_ring_emit,
 668                         .cs_parse = &r300_cs_parse,
 669                         .ring_start = &r300_ring_start,
 670                         .ring_test = &r100_ring_test,
 671                         .ib_test = &r100_ib_test,
 672                         .is_lockup = &r100_gpu_is_lockup,
 673                         .get_rptr = &radeon_ring_generic_get_rptr,
 674                         .get_wptr = &radeon_ring_generic_get_wptr,
 675                         .set_wptr = &radeon_ring_generic_set_wptr,
 676                 }
 677         },
 678         .irq = {
 679                 .set = &rs600_irq_set,
 680                 .process = &rs600_irq_process,
 681         },
 682         .display = {
 683                 .bandwidth_update = &rs600_bandwidth_update,
 684                 .get_vblank_counter = &rs600_get_vblank_counter,
 685                 .wait_for_vblank = &avivo_wait_for_vblank,
 686                 .set_backlight_level = &atombios_set_backlight_level,
 687                 .get_backlight_level = &atombios_get_backlight_level,
 688                 .hdmi_enable = &r600_hdmi_enable,
 689                 .hdmi_setmode = &r600_hdmi_setmode,
 690         },
 691         .copy = {
 692                 .blit = &r100_copy_blit,
 693                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 694                 .dma = &r200_copy_dma,
 695                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 696                 .copy = &r100_copy_blit,
 697                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 698         },
 699         .surface = {
 700                 .set_reg = r100_set_surface_reg,
 701                 .clear_reg = r100_clear_surface_reg,
 702         },
 703         .hpd = {
 704                 .init = &rs600_hpd_init,
 705                 .fini = &rs600_hpd_fini,
 706                 .sense = &rs600_hpd_sense,
 707                 .set_polarity = &rs600_hpd_set_polarity,
 708         },
 709         .pm = {
 710                 .misc = &rs600_pm_misc,
 711                 .prepare = &rs600_pm_prepare,
 712                 .finish = &rs600_pm_finish,
 713                 .init_profile = &r420_pm_init_profile,
 714                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 715                 .get_engine_clock = &radeon_atom_get_engine_clock,
 716                 .set_engine_clock = &radeon_atom_set_engine_clock,
 717                 .get_memory_clock = &radeon_atom_get_memory_clock,
 718                 .set_memory_clock = &radeon_atom_set_memory_clock,
 719                 .get_pcie_lanes = NULL,
 720                 .set_pcie_lanes = NULL,
 721                 .set_clock_gating = &radeon_atom_set_clock_gating,
 722         },
 723         .pflip = {
 724                 .pre_page_flip = &rs600_pre_page_flip,
 725                 .page_flip = &rs600_page_flip,
 726                 .post_page_flip = &rs600_post_page_flip,
 727         },
 728 };
 729
 730 static struct radeon_asic rs690_asic = {
 731         .init = &rs690_init,
 732         .fini = &rs690_fini,
 733         .suspend = &rs690_suspend,
 734         .resume = &rs690_resume,
 735         .vga_set_state = &r100_vga_set_state,
 736         .asic_reset = &rs600_asic_reset,
 737         .ioctl_wait_idle = NULL,
 738         .gui_idle = &r100_gui_idle,
 739         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 740         .gart = {
 741                 .tlb_flush = &rs400_gart_tlb_flush,
 742                 .set_page = &rs400_gart_set_page,
 743         },
 744         .ring = {
 745                 [RADEON_RING_TYPE_GFX_INDEX] = {
 746                         .ib_execute = &r100_ring_ib_execute,
 747                         .emit_fence = &r300_fence_ring_emit,
 748                         .emit_semaphore = &r100_semaphore_ring_emit,
 749                         .cs_parse = &r300_cs_parse,
 750                         .ring_start = &r300_ring_start,
 751                         .ring_test = &r100_ring_test,
 752                         .ib_test = &r100_ib_test,
 753                         .is_lockup = &r100_gpu_is_lockup,
 754                         .get_rptr = &radeon_ring_generic_get_rptr,
 755                         .get_wptr = &radeon_ring_generic_get_wptr,
 756                         .set_wptr = &radeon_ring_generic_set_wptr,
 757                 }
 758         },
 759         .irq = {
 760                 .set = &rs600_irq_set,
 761                 .process = &rs600_irq_process,
 762         },
 763         .display = {
 764                 .get_vblank_counter = &rs600_get_vblank_counter,
 765                 .bandwidth_update = &rs690_bandwidth_update,
 766                 .wait_for_vblank = &avivo_wait_for_vblank,
 767                 .set_backlight_level = &atombios_set_backlight_level,
 768                 .get_backlight_level = &atombios_get_backlight_level,
 769                 .hdmi_enable = &r600_hdmi_enable,
 770                 .hdmi_setmode = &r600_hdmi_setmode,
 771         },
 772         .copy = {
 773                 .blit = &r100_copy_blit,
 774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 775                 .dma = &r200_copy_dma,
 776                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 777                 .copy = &r200_copy_dma,
 778                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 779         },
 780         .surface = {
 781                 .set_reg = r100_set_surface_reg,
 782                 .clear_reg = r100_clear_surface_reg,
 783         },
 784         .hpd = {
 785                 .init = &rs600_hpd_init,
 786                 .fini = &rs600_hpd_fini,
 787                 .sense = &rs600_hpd_sense,
 788                 .set_polarity = &rs600_hpd_set_polarity,
 789         },
 790         .pm = {
 791                 .misc = &rs600_pm_misc,
 792                 .prepare = &rs600_pm_prepare,
 793                 .finish = &rs600_pm_finish,
 794                 .init_profile = &r420_pm_init_profile,
 795                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 796                 .get_engine_clock = &radeon_atom_get_engine_clock,
 797                 .set_engine_clock = &radeon_atom_set_engine_clock,
 798                 .get_memory_clock = &radeon_atom_get_memory_clock,
 799                 .set_memory_clock = &radeon_atom_set_memory_clock,
 800                 .get_pcie_lanes = NULL,
 801                 .set_pcie_lanes = NULL,
 802                 .set_clock_gating = &radeon_atom_set_clock_gating,
 803         },
 804         .pflip = {
 805                 .pre_page_flip = &rs600_pre_page_flip,
 806                 .page_flip = &rs600_page_flip,
 807                 .post_page_flip = &rs600_post_page_flip,
 808         },
 809 };
 810
 811 static struct radeon_asic rv515_asic = {
 812         .init = &rv515_init,
 813         .fini = &rv515_fini,
 814         .suspend = &rv515_suspend,
 815         .resume = &rv515_resume,
 816         .vga_set_state = &r100_vga_set_state,
 817         .asic_reset = &rs600_asic_reset,
 818         .ioctl_wait_idle = NULL,
 819         .gui_idle = &r100_gui_idle,
 820         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 821         .gart = {
 822                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 823                 .set_page = &rv370_pcie_gart_set_page,
 824         },
 825         .ring = {
 826                 [RADEON_RING_TYPE_GFX_INDEX] = {
 827                         .ib_execute = &r100_ring_ib_execute,
 828                         .emit_fence = &r300_fence_ring_emit,
 829                         .emit_semaphore = &r100_semaphore_ring_emit,
 830                         .cs_parse = &r300_cs_parse,
 831                         .ring_start = &rv515_ring_start,
 832                         .ring_test = &r100_ring_test,
 833                         .ib_test = &r100_ib_test,
 834                         .is_lockup = &r100_gpu_is_lockup,
 835                         .get_rptr = &radeon_ring_generic_get_rptr,
 836                         .get_wptr = &radeon_ring_generic_get_wptr,
 837                         .set_wptr = &radeon_ring_generic_set_wptr,
 838                 }
 839         },
 840         .irq = {
 841                 .set = &rs600_irq_set,
 842                 .process = &rs600_irq_process,
 843         },
 844         .display = {
 845                 .get_vblank_counter = &rs600_get_vblank_counter,
 846                 .bandwidth_update = &rv515_bandwidth_update,
 847                 .wait_for_vblank = &avivo_wait_for_vblank,
 848                 .set_backlight_level = &atombios_set_backlight_level,
 849                 .get_backlight_level = &atombios_get_backlight_level,
 850         },
 851         .copy = {
 852                 .blit = &r100_copy_blit,
 853                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 854                 .dma = &r200_copy_dma,
 855                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 856                 .copy = &r100_copy_blit,
 857                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 858         },
 859         .surface = {
 860                 .set_reg = r100_set_surface_reg,
 861                 .clear_reg = r100_clear_surface_reg,
 862         },
 863         .hpd = {
 864                 .init = &rs600_hpd_init,
 865                 .fini = &rs600_hpd_fini,
 866                 .sense = &rs600_hpd_sense,
 867                 .set_polarity = &rs600_hpd_set_polarity,
 868         },
 869         .pm = {
 870                 .misc = &rs600_pm_misc,
 871                 .prepare = &rs600_pm_prepare,
 872                 .finish = &rs600_pm_finish,
 873                 .init_profile = &r420_pm_init_profile,
 874                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 875                 .get_engine_clock = &radeon_atom_get_engine_clock,
 876                 .set_engine_clock = &radeon_atom_set_engine_clock,
 877                 .get_memory_clock = &radeon_atom_get_memory_clock,
 878                 .set_memory_clock = &radeon_atom_set_memory_clock,
 879                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 880                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 881                 .set_clock_gating = &radeon_atom_set_clock_gating,
 882         },
 883         .pflip = {
 884                 .pre_page_flip = &rs600_pre_page_flip,
 885                 .page_flip = &rs600_page_flip,
 886                 .post_page_flip = &rs600_post_page_flip,
 887         },
 888 };
 889
 890 static struct radeon_asic r520_asic = {
 891         .init = &r520_init,
 892         .fini = &rv515_fini,
 893         .suspend = &rv515_suspend,
 894         .resume = &r520_resume,
 895         .vga_set_state = &r100_vga_set_state,
 896         .asic_reset = &rs600_asic_reset,
 897         .ioctl_wait_idle = NULL,
 898         .gui_idle = &r100_gui_idle,
 899         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 900         .gart = {
 901                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 902                 .set_page = &rv370_pcie_gart_set_page,
 903         },
 904         .ring = {
 905                 [RADEON_RING_TYPE_GFX_INDEX] = {
 906                         .ib_execute = &r100_ring_ib_execute,
 907                         .emit_fence = &r300_fence_ring_emit,
 908                         .emit_semaphore = &r100_semaphore_ring_emit,
 909                         .cs_parse = &r300_cs_parse,
 910                         .ring_start = &rv515_ring_start,
 911                         .ring_test = &r100_ring_test,
 912                         .ib_test = &r100_ib_test,
 913                         .is_lockup = &r100_gpu_is_lockup,
 914                         .get_rptr = &radeon_ring_generic_get_rptr,
 915                         .get_wptr = &radeon_ring_generic_get_wptr,
 916                         .set_wptr = &radeon_ring_generic_set_wptr,
 917                 }
 918         },
 919         .irq = {
 920                 .set = &rs600_irq_set,
 921                 .process = &rs600_irq_process,
 922         },
 923         .display = {
 924                 .bandwidth_update = &rv515_bandwidth_update,
 925                 .get_vblank_counter = &rs600_get_vblank_counter,
 926                 .wait_for_vblank = &avivo_wait_for_vblank,
 927                 .set_backlight_level = &atombios_set_backlight_level,
 928                 .get_backlight_level = &atombios_get_backlight_level,
 929         },
 930         .copy = {
 931                 .blit = &r100_copy_blit,
 932                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 933                 .dma = &r200_copy_dma,
 934                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 935                 .copy = &r100_copy_blit,
 936                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 937         },
 938         .surface = {
 939                 .set_reg = r100_set_surface_reg,
 940                 .clear_reg = r100_clear_surface_reg,
 941         },
 942         .hpd = {
 943                 .init = &rs600_hpd_init,
 944                 .fini = &rs600_hpd_fini,
 945                 .sense = &rs600_hpd_sense,
 946                 .set_polarity = &rs600_hpd_set_polarity,
 947         },
 948         .pm = {
 949                 .misc = &rs600_pm_misc,
 950                 .prepare = &rs600_pm_prepare,
 951                 .finish = &rs600_pm_finish,
 952                 .init_profile = &r420_pm_init_profile,
 953                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 954                 .get_engine_clock = &radeon_atom_get_engine_clock,
 955                 .set_engine_clock = &radeon_atom_set_engine_clock,
 956                 .get_memory_clock = &radeon_atom_get_memory_clock,
 957                 .set_memory_clock = &radeon_atom_set_memory_clock,
 958                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 959                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 960                 .set_clock_gating = &radeon_atom_set_clock_gating,
 961         },
 962         .pflip = {
 963                 .pre_page_flip = &rs600_pre_page_flip,
 964                 .page_flip = &rs600_page_flip,
 965                 .post_page_flip = &rs600_post_page_flip,
 966         },
 967 };
 968
 969 static struct radeon_asic r600_asic = {
 970         .init = &r600_init,
 971         .fini = &r600_fini,
 972         .suspend = &r600_suspend,
 973         .resume = &r600_resume,
 974         .vga_set_state = &r600_vga_set_state,
 975         .asic_reset = &r600_asic_reset,
 976         .ioctl_wait_idle = r600_ioctl_wait_idle,
 977         .gui_idle = &r600_gui_idle,
 978         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 979         .get_xclk = &r600_get_xclk,
 980         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 981         .gart = {
 982                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 983                 .set_page = &rs600_gart_set_page,
 984         },
 985         .ring = {
 986                 [RADEON_RING_TYPE_GFX_INDEX] = {
 987                         .ib_execute = &r600_ring_ib_execute,
 988                         .emit_fence = &r600_fence_ring_emit,
 989                         .emit_semaphore = &r600_semaphore_ring_emit,
 990                         .cs_parse = &r600_cs_parse,
 991                         .ring_test = &r600_ring_test,
 992                         .ib_test = &r600_ib_test,
 993                         .is_lockup = &r600_gfx_is_lockup,
 994                         .get_rptr = &radeon_ring_generic_get_rptr,
 995                         .get_wptr = &radeon_ring_generic_get_wptr,
 996                         .set_wptr = &radeon_ring_generic_set_wptr,
 997                 },
 998                 [R600_RING_TYPE_DMA_INDEX] = {
 999                         .ib_execute = &r600_dma_ring_ib_execute,
1000                         .emit_fence = &r600_dma_fence_ring_emit,
1001                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002                         .cs_parse = &r600_dma_cs_parse,
1003                         .ring_test = &r600_dma_ring_test,
1004                         .ib_test = &r600_dma_ib_test,
1005                         .is_lockup = &r600_dma_is_lockup,
1006                         .get_rptr = &radeon_ring_generic_get_rptr,
1007                         .get_wptr = &radeon_ring_generic_get_wptr,
1008                         .set_wptr = &radeon_ring_generic_set_wptr,
1009                 }
1010         },
1011         .irq = {
1012                 .set = &r600_irq_set,
1013                 .process = &r600_irq_process,
1014         },
1015         .display = {
1016                 .bandwidth_update = &rv515_bandwidth_update,
1017                 .get_vblank_counter = &rs600_get_vblank_counter,
1018                 .wait_for_vblank = &avivo_wait_for_vblank,
1019                 .set_backlight_level = &atombios_set_backlight_level,
1020                 .get_backlight_level = &atombios_get_backlight_level,
1021                 .hdmi_enable = &r600_hdmi_enable,
1022                 .hdmi_setmode = &r600_hdmi_setmode,
1023         },
1024         .copy = {
1025                 .blit = &r600_copy_blit,
1026                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027                 .dma = &r600_copy_dma,
1028                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029                 .copy = &r600_copy_dma,
1030                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031         },
1032         .surface = {
1033                 .set_reg = r600_set_surface_reg,
1034                 .clear_reg = r600_clear_surface_reg,
1035         },
1036         .hpd = {
1037                 .init = &r600_hpd_init,
1038                 .fini = &r600_hpd_fini,
1039                 .sense = &r600_hpd_sense,
1040                 .set_polarity = &r600_hpd_set_polarity,
1041         },
1042         .pm = {
1043                 .misc = &r600_pm_misc,
1044                 .prepare = &rs600_pm_prepare,
1045                 .finish = &rs600_pm_finish,
1046                 .init_profile = &r600_pm_init_profile,
1047                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048                 .get_engine_clock = &radeon_atom_get_engine_clock,
1049                 .set_engine_clock = &radeon_atom_set_engine_clock,
1050                 .get_memory_clock = &radeon_atom_get_memory_clock,
1051                 .set_memory_clock = &radeon_atom_set_memory_clock,
1052                 .get_pcie_lanes = &r600_get_pcie_lanes,
1053                 .set_pcie_lanes = &r600_set_pcie_lanes,
1054                 .set_clock_gating = NULL,
1055         },
1056         .pflip = {
1057                 .pre_page_flip = &rs600_pre_page_flip,
1058                 .page_flip = &rs600_page_flip,
1059                 .post_page_flip = &rs600_post_page_flip,
1060         },
1061 };
1062
1063 static struct radeon_asic rs780_asic = {
1064         .init = &r600_init,
1065         .fini = &r600_fini,
1066         .suspend = &r600_suspend,
1067         .resume = &r600_resume,
1068         .vga_set_state = &r600_vga_set_state,
1069         .asic_reset = &r600_asic_reset,
1070         .ioctl_wait_idle = r600_ioctl_wait_idle,
1071         .gui_idle = &r600_gui_idle,
1072         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1073         .get_xclk = &r600_get_xclk,
1074         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1075         .gart = {
1076                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1077                 .set_page = &rs600_gart_set_page,
1078         },
1079         .ring = {
1080                 [RADEON_RING_TYPE_GFX_INDEX] = {
1081                         .ib_execute = &r600_ring_ib_execute,
1082                         .emit_fence = &r600_fence_ring_emit,
1083                         .emit_semaphore = &r600_semaphore_ring_emit,
1084                         .cs_parse = &r600_cs_parse,
1085                         .ring_test = &r600_ring_test,
1086                         .ib_test = &r600_ib_test,
1087                         .is_lockup = &r600_gfx_is_lockup,
1088                         .get_rptr = &radeon_ring_generic_get_rptr,
1089                         .get_wptr = &radeon_ring_generic_get_wptr,
1090                         .set_wptr = &radeon_ring_generic_set_wptr,
1091                 },
1092                 [R600_RING_TYPE_DMA_INDEX] = {
1093                         .ib_execute = &r600_dma_ring_ib_execute,
1094                         .emit_fence = &r600_dma_fence_ring_emit,
1095                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1096                         .cs_parse = &r600_dma_cs_parse,
1097                         .ring_test = &r600_dma_ring_test,
1098                         .ib_test = &r600_dma_ib_test,
1099                         .is_lockup = &r600_dma_is_lockup,
1100                         .get_rptr = &radeon_ring_generic_get_rptr,
1101                         .get_wptr = &radeon_ring_generic_get_wptr,
1102                         .set_wptr = &radeon_ring_generic_set_wptr,
1103                 }
1104         },
1105         .irq = {
1106                 .set = &r600_irq_set,
1107                 .process = &r600_irq_process,
1108         },
1109         .display = {
1110                 .bandwidth_update = &rs690_bandwidth_update,
1111                 .get_vblank_counter = &rs600_get_vblank_counter,
1112                 .wait_for_vblank = &avivo_wait_for_vblank,
1113                 .set_backlight_level = &atombios_set_backlight_level,
1114                 .get_backlight_level = &atombios_get_backlight_level,
1115                 .hdmi_enable = &r600_hdmi_enable,
1116                 .hdmi_setmode = &r600_hdmi_setmode,
1117         },
1118         .copy = {
1119                 .blit = &r600_copy_blit,
1120                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1121                 .dma = &r600_copy_dma,
1122                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1123                 .copy = &r600_copy_dma,
1124                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1125         },
1126         .surface = {
1127                 .set_reg = r600_set_surface_reg,
1128                 .clear_reg = r600_clear_surface_reg,
1129         },
1130         .hpd = {
1131                 .init = &r600_hpd_init,
1132                 .fini = &r600_hpd_fini,
1133                 .sense = &r600_hpd_sense,
1134                 .set_polarity = &r600_hpd_set_polarity,
1135         },
1136         .pm = {
1137                 .misc = &r600_pm_misc,
1138                 .prepare = &rs600_pm_prepare,
1139                 .finish = &rs600_pm_finish,
1140                 .init_profile = &rs780_pm_init_profile,
1141                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1142                 .get_engine_clock = &radeon_atom_get_engine_clock,
1143                 .set_engine_clock = &radeon_atom_set_engine_clock,
1144                 .get_memory_clock = NULL,
1145                 .set_memory_clock = NULL,
1146                 .get_pcie_lanes = NULL,
1147                 .set_pcie_lanes = NULL,
1148                 .set_clock_gating = NULL,
1149         },
1150         .pflip = {
1151                 .pre_page_flip = &rs600_pre_page_flip,
1152                 .page_flip = &rs600_page_flip,
1153                 .post_page_flip = &rs600_post_page_flip,
1154         },
1155 };
1156
1157 static struct radeon_asic rv770_asic = {
1158         .init = &rv770_init,
1159         .fini = &rv770_fini,
1160         .suspend = &rv770_suspend,
1161         .resume = &rv770_resume,
1162         .asic_reset = &r600_asic_reset,
1163         .vga_set_state = &r600_vga_set_state,
1164         .ioctl_wait_idle = r600_ioctl_wait_idle,
1165         .gui_idle = &r600_gui_idle,
1166         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1167         .get_xclk = &rv770_get_xclk,
1168         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1169         .gart = {
1170                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1171                 .set_page = &rs600_gart_set_page,
1172         },
1173         .ring = {
1174                 [RADEON_RING_TYPE_GFX_INDEX] = {
1175                         .ib_execute = &r600_ring_ib_execute,
1176                         .emit_fence = &r600_fence_ring_emit,
1177                         .emit_semaphore = &r600_semaphore_ring_emit,
1178                         .cs_parse = &r600_cs_parse,
1179                         .ring_test = &r600_ring_test,
1180                         .ib_test = &r600_ib_test,
1181                         .is_lockup = &r600_gfx_is_lockup,
1182                         .get_rptr = &radeon_ring_generic_get_rptr,
1183                         .get_wptr = &radeon_ring_generic_get_wptr,
1184                         .set_wptr = &radeon_ring_generic_set_wptr,
1185                 },
1186                 [R600_RING_TYPE_DMA_INDEX] = {
1187                         .ib_execute = &r600_dma_ring_ib_execute,
1188                         .emit_fence = &r600_dma_fence_ring_emit,
1189                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1190                         .cs_parse = &r600_dma_cs_parse,
1191                         .ring_test = &r600_dma_ring_test,
1192                         .ib_test = &r600_dma_ib_test,
1193                         .is_lockup = &r600_dma_is_lockup,
1194                         .get_rptr = &radeon_ring_generic_get_rptr,
1195                         .get_wptr = &radeon_ring_generic_get_wptr,
1196                         .set_wptr = &radeon_ring_generic_set_wptr,
1197                 },
1198                 [R600_RING_TYPE_UVD_INDEX] = {
1199                         .ib_execute = &r600_uvd_ib_execute,
1200                         .emit_fence = &r600_uvd_fence_emit,
1201                         .emit_semaphore = &r600_uvd_semaphore_emit,
1202                         .cs_parse = &radeon_uvd_cs_parse,
1203                         .ring_test = &r600_uvd_ring_test,
1204                         .ib_test = &r600_uvd_ib_test,
1205                         .is_lockup = &radeon_ring_test_lockup,
1206                         .get_rptr = &radeon_ring_generic_get_rptr,
1207                         .get_wptr = &radeon_ring_generic_get_wptr,
1208                         .set_wptr = &radeon_ring_generic_set_wptr,
1209                 }
1210         },
1211         .irq = {
1212                 .set = &r600_irq_set,
1213                 .process = &r600_irq_process,
1214         },
1215         .display = {
1216                 .bandwidth_update = &rv515_bandwidth_update,
1217                 .get_vblank_counter = &rs600_get_vblank_counter,
1218                 .wait_for_vblank = &avivo_wait_for_vblank,
1219                 .set_backlight_level = &atombios_set_backlight_level,
1220                 .get_backlight_level = &atombios_get_backlight_level,
1221                 .hdmi_enable = &r600_hdmi_enable,
1222                 .hdmi_setmode = &r600_hdmi_setmode,
1223         },
1224         .copy = {
1225                 .blit = &r600_copy_blit,
1226                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1227                 .dma = &rv770_copy_dma,
1228                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1229                 .copy = &rv770_copy_dma,
1230                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1231         },
1232         .surface = {
1233                 .set_reg = r600_set_surface_reg,
1234                 .clear_reg = r600_clear_surface_reg,
1235         },
1236         .hpd = {
1237                 .init = &r600_hpd_init,
1238                 .fini = &r600_hpd_fini,
1239                 .sense = &r600_hpd_sense,
1240                 .set_polarity = &r600_hpd_set_polarity,
1241         },
1242         .pm = {
1243                 .misc = &rv770_pm_misc,
1244                 .prepare = &rs600_pm_prepare,
1245                 .finish = &rs600_pm_finish,
1246                 .init_profile = &r600_pm_init_profile,
1247                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1248                 .get_engine_clock = &radeon_atom_get_engine_clock,
1249                 .set_engine_clock = &radeon_atom_set_engine_clock,
1250                 .get_memory_clock = &radeon_atom_get_memory_clock,
1251                 .set_memory_clock = &radeon_atom_set_memory_clock,
1252                 .get_pcie_lanes = &r600_get_pcie_lanes,
1253                 .set_pcie_lanes = &r600_set_pcie_lanes,
1254                 .set_clock_gating = &radeon_atom_set_clock_gating,
1255                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1256         },
1257         .pflip = {
1258                 .pre_page_flip = &rs600_pre_page_flip,
1259                 .page_flip = &rv770_page_flip,
1260                 .post_page_flip = &rs600_post_page_flip,
1261         },
1262 };
1263
1264 static struct radeon_asic evergreen_asic = {
1265         .init = &evergreen_init,
1266         .fini = &evergreen_fini,
1267         .suspend = &evergreen_suspend,
1268         .resume = &evergreen_resume,
1269         .asic_reset = &evergreen_asic_reset,
1270         .vga_set_state = &r600_vga_set_state,
1271         .ioctl_wait_idle = r600_ioctl_wait_idle,
1272         .gui_idle = &r600_gui_idle,
1273         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1274         .get_xclk = &rv770_get_xclk,
1275         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1276         .gart = {
1277                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1278                 .set_page = &rs600_gart_set_page,
1279         },
1280         .ring = {
1281                 [RADEON_RING_TYPE_GFX_INDEX] = {
1282                         .ib_execute = &evergreen_ring_ib_execute,
1283                         .emit_fence = &r600_fence_ring_emit,
1284                         .emit_semaphore = &r600_semaphore_ring_emit,
1285                         .cs_parse = &evergreen_cs_parse,
1286                         .ring_test = &r600_ring_test,
1287                         .ib_test = &r600_ib_test,
1288                         .is_lockup = &evergreen_gfx_is_lockup,
1289                         .get_rptr = &radeon_ring_generic_get_rptr,
1290                         .get_wptr = &radeon_ring_generic_get_wptr,
1291                         .set_wptr = &radeon_ring_generic_set_wptr,
1292                 },
1293                 [R600_RING_TYPE_DMA_INDEX] = {
1294                         .ib_execute = &evergreen_dma_ring_ib_execute,
1295                         .emit_fence = &evergreen_dma_fence_ring_emit,
1296                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1297                         .cs_parse = &evergreen_dma_cs_parse,
1298                         .ring_test = &r600_dma_ring_test,
1299                         .ib_test = &r600_dma_ib_test,
1300                         .is_lockup = &evergreen_dma_is_lockup,
1301                         .get_rptr = &radeon_ring_generic_get_rptr,
1302                         .get_wptr = &radeon_ring_generic_get_wptr,
1303                         .set_wptr = &radeon_ring_generic_set_wptr,
1304                 },
1305                 [R600_RING_TYPE_UVD_INDEX] = {
1306                         .ib_execute = &r600_uvd_ib_execute,
1307                         .emit_fence = &r600_uvd_fence_emit,
1308                         .emit_semaphore = &r600_uvd_semaphore_emit,
1309                         .cs_parse = &radeon_uvd_cs_parse,
1310                         .ring_test = &r600_uvd_ring_test,
1311                         .ib_test = &r600_uvd_ib_test,
1312                         .is_lockup = &radeon_ring_test_lockup,
1313                         .get_rptr = &radeon_ring_generic_get_rptr,
1314                         .get_wptr = &radeon_ring_generic_get_wptr,
1315                         .set_wptr = &radeon_ring_generic_set_wptr,
1316                 }
1317         },
1318         .irq = {
1319                 .set = &evergreen_irq_set,
1320                 .process = &evergreen_irq_process,
1321         },
1322         .display = {
1323                 .bandwidth_update = &evergreen_bandwidth_update,
1324                 .get_vblank_counter = &evergreen_get_vblank_counter,
1325                 .wait_for_vblank = &dce4_wait_for_vblank,
1326                 .set_backlight_level = &atombios_set_backlight_level,
1327                 .get_backlight_level = &atombios_get_backlight_level,
1328                 .hdmi_enable = &evergreen_hdmi_enable,
1329                 .hdmi_setmode = &evergreen_hdmi_setmode,
1330         },
1331         .copy = {
1332                 .blit = &r600_copy_blit,
1333                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1334                 .dma = &evergreen_copy_dma,
1335                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1336                 .copy = &evergreen_copy_dma,
1337                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1338         },
1339         .surface = {
1340                 .set_reg = r600_set_surface_reg,
1341                 .clear_reg = r600_clear_surface_reg,
1342         },
1343         .hpd = {
1344                 .init = &evergreen_hpd_init,
1345                 .fini = &evergreen_hpd_fini,
1346                 .sense = &evergreen_hpd_sense,
1347                 .set_polarity = &evergreen_hpd_set_polarity,
1348         },
1349         .pm = {
1350                 .misc = &evergreen_pm_misc,
1351                 .prepare = &evergreen_pm_prepare,
1352                 .finish = &evergreen_pm_finish,
1353                 .init_profile = &r600_pm_init_profile,
1354                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1355                 .get_engine_clock = &radeon_atom_get_engine_clock,
1356                 .set_engine_clock = &radeon_atom_set_engine_clock,
1357                 .get_memory_clock = &radeon_atom_get_memory_clock,
1358                 .set_memory_clock = &radeon_atom_set_memory_clock,
1359                 .get_pcie_lanes = &r600_get_pcie_lanes,
1360                 .set_pcie_lanes = &r600_set_pcie_lanes,
1361                 .set_clock_gating = NULL,
1362                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1363         },
1364         .pflip = {
1365                 .pre_page_flip = &evergreen_pre_page_flip,
1366                 .page_flip = &evergreen_page_flip,
1367                 .post_page_flip = &evergreen_post_page_flip,
1368         },
1369 };
1370
1371 static struct radeon_asic sumo_asic = {
1372         .init = &evergreen_init,
1373         .fini = &evergreen_fini,
1374         .suspend = &evergreen_suspend,
1375         .resume = &evergreen_resume,
1376         .asic_reset = &evergreen_asic_reset,
1377         .vga_set_state = &r600_vga_set_state,
1378         .ioctl_wait_idle = r600_ioctl_wait_idle,
1379         .gui_idle = &r600_gui_idle,
1380         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1381         .get_xclk = &r600_get_xclk,
1382         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1383         .gart = {
1384                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1385                 .set_page = &rs600_gart_set_page,
1386         },
1387         .ring = {
1388                 [RADEON_RING_TYPE_GFX_INDEX] = {
1389                         .ib_execute = &evergreen_ring_ib_execute,
1390                         .emit_fence = &r600_fence_ring_emit,
1391                         .emit_semaphore = &r600_semaphore_ring_emit,
1392                         .cs_parse = &evergreen_cs_parse,
1393                         .ring_test = &r600_ring_test,
1394                         .ib_test = &r600_ib_test,
1395                         .is_lockup = &evergreen_gfx_is_lockup,
1396                         .get_rptr = &radeon_ring_generic_get_rptr,
1397                         .get_wptr = &radeon_ring_generic_get_wptr,
1398                         .set_wptr = &radeon_ring_generic_set_wptr,
1399                 },
1400                 [R600_RING_TYPE_DMA_INDEX] = {
1401                         .ib_execute = &evergreen_dma_ring_ib_execute,
1402                         .emit_fence = &evergreen_dma_fence_ring_emit,
1403                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1404                         .cs_parse = &evergreen_dma_cs_parse,
1405                         .ring_test = &r600_dma_ring_test,
1406                         .ib_test = &r600_dma_ib_test,
1407                         .is_lockup = &evergreen_dma_is_lockup,
1408                         .get_rptr = &radeon_ring_generic_get_rptr,
1409                         .get_wptr = &radeon_ring_generic_get_wptr,
1410                         .set_wptr = &radeon_ring_generic_set_wptr,
1411                 },
1412                 [R600_RING_TYPE_UVD_INDEX] = {
1413                         .ib_execute = &r600_uvd_ib_execute,
1414                         .emit_fence = &r600_uvd_fence_emit,
1415                         .emit_semaphore = &r600_uvd_semaphore_emit,
1416                         .cs_parse = &radeon_uvd_cs_parse,
1417                         .ring_test = &r600_uvd_ring_test,
1418                         .ib_test = &r600_uvd_ib_test,
1419                         .is_lockup = &radeon_ring_test_lockup,
1420                         .get_rptr = &radeon_ring_generic_get_rptr,
1421                         .get_wptr = &radeon_ring_generic_get_wptr,
1422                         .set_wptr = &radeon_ring_generic_set_wptr,
1423                 }
1424         },
1425         .irq = {
1426                 .set = &evergreen_irq_set,
1427                 .process = &evergreen_irq_process,
1428         },
1429         .display = {
1430                 .bandwidth_update = &evergreen_bandwidth_update,
1431                 .get_vblank_counter = &evergreen_get_vblank_counter,
1432                 .wait_for_vblank = &dce4_wait_for_vblank,
1433                 .set_backlight_level = &atombios_set_backlight_level,
1434                 .get_backlight_level = &atombios_get_backlight_level,
1435                 .hdmi_enable = &evergreen_hdmi_enable,
1436                 .hdmi_setmode = &evergreen_hdmi_setmode,
1437         },
1438         .copy = {
1439                 .blit = &r600_copy_blit,
1440                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1441                 .dma = &evergreen_copy_dma,
1442                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1443                 .copy = &evergreen_copy_dma,
1444                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1445         },
1446         .surface = {
1447                 .set_reg = r600_set_surface_reg,
1448                 .clear_reg = r600_clear_surface_reg,
1449         },
1450         .hpd = {
1451                 .init = &evergreen_hpd_init,
1452                 .fini = &evergreen_hpd_fini,
1453                 .sense = &evergreen_hpd_sense,
1454                 .set_polarity = &evergreen_hpd_set_polarity,
1455         },
1456         .pm = {
1457                 .misc = &evergreen_pm_misc,
1458                 .prepare = &evergreen_pm_prepare,
1459                 .finish = &evergreen_pm_finish,
1460                 .init_profile = &sumo_pm_init_profile,
1461                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1462                 .get_engine_clock = &radeon_atom_get_engine_clock,
1463                 .set_engine_clock = &radeon_atom_set_engine_clock,
1464                 .get_memory_clock = NULL,
1465                 .set_memory_clock = NULL,
1466                 .get_pcie_lanes = NULL,
1467                 .set_pcie_lanes = NULL,
1468                 .set_clock_gating = NULL,
1469                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1470         },
1471         .pflip = {
1472                 .pre_page_flip = &evergreen_pre_page_flip,
1473                 .page_flip = &evergreen_page_flip,
1474                 .post_page_flip = &evergreen_post_page_flip,
1475         },
1476 };
1477
1478 static struct radeon_asic btc_asic = {
1479         .init = &evergreen_init,
1480         .fini = &evergreen_fini,
1481         .suspend = &evergreen_suspend,
1482         .resume = &evergreen_resume,
1483         .asic_reset = &evergreen_asic_reset,
1484         .vga_set_state = &r600_vga_set_state,
1485         .ioctl_wait_idle = r600_ioctl_wait_idle,
1486         .gui_idle = &r600_gui_idle,
1487         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1488         .get_xclk = &rv770_get_xclk,
1489         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1490         .gart = {
1491                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1492                 .set_page = &rs600_gart_set_page,
1493         },
1494         .ring = {
1495                 [RADEON_RING_TYPE_GFX_INDEX] = {
1496                         .ib_execute = &evergreen_ring_ib_execute,
1497                         .emit_fence = &r600_fence_ring_emit,
1498                         .emit_semaphore = &r600_semaphore_ring_emit,
1499                         .cs_parse = &evergreen_cs_parse,
1500                         .ring_test = &r600_ring_test,
1501                         .ib_test = &r600_ib_test,
1502                         .is_lockup = &evergreen_gfx_is_lockup,
1503                         .get_rptr = &radeon_ring_generic_get_rptr,
1504                         .get_wptr = &radeon_ring_generic_get_wptr,
1505                         .set_wptr = &radeon_ring_generic_set_wptr,
1506                 },
1507                 [R600_RING_TYPE_DMA_INDEX] = {
1508                         .ib_execute = &evergreen_dma_ring_ib_execute,
1509                         .emit_fence = &evergreen_dma_fence_ring_emit,
1510                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1511                         .cs_parse = &evergreen_dma_cs_parse,
1512                         .ring_test = &r600_dma_ring_test,
1513                         .ib_test = &r600_dma_ib_test,
1514                         .is_lockup = &evergreen_dma_is_lockup,
1515                         .get_rptr = &radeon_ring_generic_get_rptr,
1516                         .get_wptr = &radeon_ring_generic_get_wptr,
1517                         .set_wptr = &radeon_ring_generic_set_wptr,
1518                 },
1519                 [R600_RING_TYPE_UVD_INDEX] = {
1520                         .ib_execute = &r600_uvd_ib_execute,
1521                         .emit_fence = &r600_uvd_fence_emit,
1522                         .emit_semaphore = &r600_uvd_semaphore_emit,
1523                         .cs_parse = &radeon_uvd_cs_parse,
1524                         .ring_test = &r600_uvd_ring_test,
1525                         .ib_test = &r600_uvd_ib_test,
1526                         .is_lockup = &radeon_ring_test_lockup,
1527                         .get_rptr = &radeon_ring_generic_get_rptr,
1528                         .get_wptr = &radeon_ring_generic_get_wptr,
1529                         .set_wptr = &radeon_ring_generic_set_wptr,
1530                 }
1531         },
1532         .irq = {
1533                 .set = &evergreen_irq_set,
1534                 .process = &evergreen_irq_process,
1535         },
1536         .display = {
1537                 .bandwidth_update = &evergreen_bandwidth_update,
1538                 .get_vblank_counter = &evergreen_get_vblank_counter,
1539                 .wait_for_vblank = &dce4_wait_for_vblank,
1540                 .set_backlight_level = &atombios_set_backlight_level,
1541                 .get_backlight_level = &atombios_get_backlight_level,
1542                 .hdmi_enable = &evergreen_hdmi_enable,
1543                 .hdmi_setmode = &evergreen_hdmi_setmode,
1544         },
1545         .copy = {
1546                 .blit = &r600_copy_blit,
1547                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1548                 .dma = &evergreen_copy_dma,
1549                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1550                 .copy = &evergreen_copy_dma,
1551                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1552         },
1553         .surface = {
1554                 .set_reg = r600_set_surface_reg,
1555                 .clear_reg = r600_clear_surface_reg,
1556         },
1557         .hpd = {
1558                 .init = &evergreen_hpd_init,
1559                 .fini = &evergreen_hpd_fini,
1560                 .sense = &evergreen_hpd_sense,
1561                 .set_polarity = &evergreen_hpd_set_polarity,
1562         },
1563         .pm = {
1564                 .misc = &evergreen_pm_misc,
1565                 .prepare = &evergreen_pm_prepare,
1566                 .finish = &evergreen_pm_finish,
1567                 .init_profile = &btc_pm_init_profile,
1568                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1569                 .get_engine_clock = &radeon_atom_get_engine_clock,
1570                 .set_engine_clock = &radeon_atom_set_engine_clock,
1571                 .get_memory_clock = &radeon_atom_get_memory_clock,
1572                 .set_memory_clock = &radeon_atom_set_memory_clock,
1573                 .get_pcie_lanes = &r600_get_pcie_lanes,
1574                 .set_pcie_lanes = &r600_set_pcie_lanes,
1575                 .set_clock_gating = NULL,
1576                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1577         },
1578         .pflip = {
1579                 .pre_page_flip = &evergreen_pre_page_flip,
1580                 .page_flip = &evergreen_page_flip,
1581                 .post_page_flip = &evergreen_post_page_flip,
1582         },
1583 };
1584
1585 static struct radeon_asic cayman_asic = {
1586         .init = &cayman_init,
1587         .fini = &cayman_fini,
1588         .suspend = &cayman_suspend,
1589         .resume = &cayman_resume,
1590         .asic_reset = &cayman_asic_reset,
1591         .vga_set_state = &r600_vga_set_state,
1592         .ioctl_wait_idle = r600_ioctl_wait_idle,
1593         .gui_idle = &r600_gui_idle,
1594         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1595         .get_xclk = &rv770_get_xclk,
1596         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1597         .gart = {
1598                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1599                 .set_page = &rs600_gart_set_page,
1600         },
1601         .vm = {
1602                 .init = &cayman_vm_init,
1603                 .fini = &cayman_vm_fini,
1604                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1605                 .set_page = &cayman_vm_set_page,
1606         },
1607         .ring = {
1608                 [RADEON_RING_TYPE_GFX_INDEX] = {
1609                         .ib_execute = &cayman_ring_ib_execute,
1610                         .ib_parse = &evergreen_ib_parse,
1611                         .emit_fence = &cayman_fence_ring_emit,
1612                         .emit_semaphore = &r600_semaphore_ring_emit,
1613                         .cs_parse = &evergreen_cs_parse,
1614                         .ring_test = &r600_ring_test,
1615                         .ib_test = &r600_ib_test,
1616                         .is_lockup = &cayman_gfx_is_lockup,
1617                         .vm_flush = &cayman_vm_flush,
1618                         .get_rptr = &radeon_ring_generic_get_rptr,
1619                         .get_wptr = &radeon_ring_generic_get_wptr,
1620                         .set_wptr = &radeon_ring_generic_set_wptr,
1621                 },
1622                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1623                         .ib_execute = &cayman_ring_ib_execute,
1624                         .ib_parse = &evergreen_ib_parse,
1625                         .emit_fence = &cayman_fence_ring_emit,
1626                         .emit_semaphore = &r600_semaphore_ring_emit,
1627                         .cs_parse = &evergreen_cs_parse,
1628                         .ring_test = &r600_ring_test,
1629                         .ib_test = &r600_ib_test,
1630                         .is_lockup = &cayman_gfx_is_lockup,
1631                         .vm_flush = &cayman_vm_flush,
1632                         .get_rptr = &radeon_ring_generic_get_rptr,
1633                         .get_wptr = &radeon_ring_generic_get_wptr,
1634                         .set_wptr = &radeon_ring_generic_set_wptr,
1635                 },
1636                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1637                         .ib_execute = &cayman_ring_ib_execute,
1638                         .ib_parse = &evergreen_ib_parse,
1639                         .emit_fence = &cayman_fence_ring_emit,
1640                         .emit_semaphore = &r600_semaphore_ring_emit,
1641                         .cs_parse = &evergreen_cs_parse,
1642                         .ring_test = &r600_ring_test,
1643                         .ib_test = &r600_ib_test,
1644                         .is_lockup = &cayman_gfx_is_lockup,
1645                         .vm_flush = &cayman_vm_flush,
1646                         .get_rptr = &radeon_ring_generic_get_rptr,
1647                         .get_wptr = &radeon_ring_generic_get_wptr,
1648                         .set_wptr = &radeon_ring_generic_set_wptr,
1649                 },
1650                 [R600_RING_TYPE_DMA_INDEX] = {
1651                         .ib_execute = &cayman_dma_ring_ib_execute,
1652                         .ib_parse = &evergreen_dma_ib_parse,
1653                         .emit_fence = &evergreen_dma_fence_ring_emit,
1654                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1655                         .cs_parse = &evergreen_dma_cs_parse,
1656                         .ring_test = &r600_dma_ring_test,
1657                         .ib_test = &r600_dma_ib_test,
1658                         .is_lockup = &cayman_dma_is_lockup,
1659                         .vm_flush = &cayman_dma_vm_flush,
1660                         .get_rptr = &radeon_ring_generic_get_rptr,
1661                         .get_wptr = &radeon_ring_generic_get_wptr,
1662                         .set_wptr = &radeon_ring_generic_set_wptr,
1663                 },
1664                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1665                         .ib_execute = &cayman_dma_ring_ib_execute,
1666                         .ib_parse = &evergreen_dma_ib_parse,
1667                         .emit_fence = &evergreen_dma_fence_ring_emit,
1668                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1669                         .cs_parse = &evergreen_dma_cs_parse,
1670                         .ring_test = &r600_dma_ring_test,
1671                         .ib_test = &r600_dma_ib_test,
1672                         .is_lockup = &cayman_dma_is_lockup,
1673                         .vm_flush = &cayman_dma_vm_flush,
1674                         .get_rptr = &radeon_ring_generic_get_rptr,
1675                         .get_wptr = &radeon_ring_generic_get_wptr,
1676                         .set_wptr = &radeon_ring_generic_set_wptr,
1677                 },
1678                 [R600_RING_TYPE_UVD_INDEX] = {
1679                         .ib_execute = &r600_uvd_ib_execute,
1680                         .emit_fence = &r600_uvd_fence_emit,
1681                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1682                         .cs_parse = &radeon_uvd_cs_parse,
1683                         .ring_test = &r600_uvd_ring_test,
1684                         .ib_test = &r600_uvd_ib_test,
1685                         .is_lockup = &radeon_ring_test_lockup,
1686                         .get_rptr = &radeon_ring_generic_get_rptr,
1687                         .get_wptr = &radeon_ring_generic_get_wptr,
1688                         .set_wptr = &radeon_ring_generic_set_wptr,
1689                 }
1690         },
1691         .irq = {
1692                 .set = &evergreen_irq_set,
1693                 .process = &evergreen_irq_process,
1694         },
1695         .display = {
1696                 .bandwidth_update = &evergreen_bandwidth_update,
1697                 .get_vblank_counter = &evergreen_get_vblank_counter,
1698                 .wait_for_vblank = &dce4_wait_for_vblank,
1699                 .set_backlight_level = &atombios_set_backlight_level,
1700                 .get_backlight_level = &atombios_get_backlight_level,
1701                 .hdmi_enable = &evergreen_hdmi_enable,
1702                 .hdmi_setmode = &evergreen_hdmi_setmode,
1703         },
1704         .copy = {
1705                 .blit = &r600_copy_blit,
1706                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1707                 .dma = &evergreen_copy_dma,
1708                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1709                 .copy = &evergreen_copy_dma,
1710                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1711         },
1712         .surface = {
1713                 .set_reg = r600_set_surface_reg,
1714                 .clear_reg = r600_clear_surface_reg,
1715         },
1716         .hpd = {
1717                 .init = &evergreen_hpd_init,
1718                 .fini = &evergreen_hpd_fini,
1719                 .sense = &evergreen_hpd_sense,
1720                 .set_polarity = &evergreen_hpd_set_polarity,
1721         },
1722         .pm = {
1723                 .misc = &evergreen_pm_misc,
1724                 .prepare = &evergreen_pm_prepare,
1725                 .finish = &evergreen_pm_finish,
1726                 .init_profile = &btc_pm_init_profile,
1727                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1728                 .get_engine_clock = &radeon_atom_get_engine_clock,
1729                 .set_engine_clock = &radeon_atom_set_engine_clock,
1730                 .get_memory_clock = &radeon_atom_get_memory_clock,
1731                 .set_memory_clock = &radeon_atom_set_memory_clock,
1732                 .get_pcie_lanes = &r600_get_pcie_lanes,
1733                 .set_pcie_lanes = &r600_set_pcie_lanes,
1734                 .set_clock_gating = NULL,
1735                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1736         },
1737         .pflip = {
1738                 .pre_page_flip = &evergreen_pre_page_flip,
1739                 .page_flip = &evergreen_page_flip,
1740                 .post_page_flip = &evergreen_post_page_flip,
1741         },
1742 };
1743
1744 static struct radeon_asic trinity_asic = {
1745         .init = &cayman_init,
1746         .fini = &cayman_fini,
1747         .suspend = &cayman_suspend,
1748         .resume = &cayman_resume,
1749         .asic_reset = &cayman_asic_reset,
1750         .vga_set_state = &r600_vga_set_state,
1751         .ioctl_wait_idle = r600_ioctl_wait_idle,
1752         .gui_idle = &r600_gui_idle,
1753         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1754         .get_xclk = &r600_get_xclk,
1755         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1756         .gart = {
1757                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1758                 .set_page = &rs600_gart_set_page,
1759         },
1760         .vm = {
1761                 .init = &cayman_vm_init,
1762                 .fini = &cayman_vm_fini,
1763                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1764                 .set_page = &cayman_vm_set_page,
1765         },
1766         .ring = {
1767                 [RADEON_RING_TYPE_GFX_INDEX] = {
1768                         .ib_execute = &cayman_ring_ib_execute,
1769                         .ib_parse = &evergreen_ib_parse,
1770                         .emit_fence = &cayman_fence_ring_emit,
1771                         .emit_semaphore = &r600_semaphore_ring_emit,
1772                         .cs_parse = &evergreen_cs_parse,
1773                         .ring_test = &r600_ring_test,
1774                         .ib_test = &r600_ib_test,
1775                         .is_lockup = &cayman_gfx_is_lockup,
1776                         .vm_flush = &cayman_vm_flush,
1777                         .get_rptr = &radeon_ring_generic_get_rptr,
1778                         .get_wptr = &radeon_ring_generic_get_wptr,
1779                         .set_wptr = &radeon_ring_generic_set_wptr,
1780                 },
1781                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1782                         .ib_execute = &cayman_ring_ib_execute,
1783                         .ib_parse = &evergreen_ib_parse,
1784                         .emit_fence = &cayman_fence_ring_emit,
1785                         .emit_semaphore = &r600_semaphore_ring_emit,
1786                         .cs_parse = &evergreen_cs_parse,
1787                         .ring_test = &r600_ring_test,
1788                         .ib_test = &r600_ib_test,
1789                         .is_lockup = &cayman_gfx_is_lockup,
1790                         .vm_flush = &cayman_vm_flush,
1791                         .get_rptr = &radeon_ring_generic_get_rptr,
1792                         .get_wptr = &radeon_ring_generic_get_wptr,
1793                         .set_wptr = &radeon_ring_generic_set_wptr,
1794                 },
1795                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1796                         .ib_execute = &cayman_ring_ib_execute,
1797                         .ib_parse = &evergreen_ib_parse,
1798                         .emit_fence = &cayman_fence_ring_emit,
1799                         .emit_semaphore = &r600_semaphore_ring_emit,
1800                         .cs_parse = &evergreen_cs_parse,
1801                         .ring_test = &r600_ring_test,
1802                         .ib_test = &r600_ib_test,
1803                         .is_lockup = &cayman_gfx_is_lockup,
1804                         .vm_flush = &cayman_vm_flush,
1805                         .get_rptr = &radeon_ring_generic_get_rptr,
1806                         .get_wptr = &radeon_ring_generic_get_wptr,
1807                         .set_wptr = &radeon_ring_generic_set_wptr,
1808                 },
1809                 [R600_RING_TYPE_DMA_INDEX] = {
1810                         .ib_execute = &cayman_dma_ring_ib_execute,
1811                         .ib_parse = &evergreen_dma_ib_parse,
1812                         .emit_fence = &evergreen_dma_fence_ring_emit,
1813                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1814                         .cs_parse = &evergreen_dma_cs_parse,
1815                         .ring_test = &r600_dma_ring_test,
1816                         .ib_test = &r600_dma_ib_test,
1817                         .is_lockup = &cayman_dma_is_lockup,
1818                         .vm_flush = &cayman_dma_vm_flush,
1819                         .get_rptr = &radeon_ring_generic_get_rptr,
1820                         .get_wptr = &radeon_ring_generic_get_wptr,
1821                         .set_wptr = &radeon_ring_generic_set_wptr,
1822                 },
1823                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1824                         .ib_execute = &cayman_dma_ring_ib_execute,
1825                         .ib_parse = &evergreen_dma_ib_parse,
1826                         .emit_fence = &evergreen_dma_fence_ring_emit,
1827                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1828                         .cs_parse = &evergreen_dma_cs_parse,
1829                         .ring_test = &r600_dma_ring_test,
1830                         .ib_test = &r600_dma_ib_test,
1831                         .is_lockup = &cayman_dma_is_lockup,
1832                         .vm_flush = &cayman_dma_vm_flush,
1833                         .get_rptr = &radeon_ring_generic_get_rptr,
1834                         .get_wptr = &radeon_ring_generic_get_wptr,
1835                         .set_wptr = &radeon_ring_generic_set_wptr,
1836                 },
1837                 [R600_RING_TYPE_UVD_INDEX] = {
1838                         .ib_execute = &r600_uvd_ib_execute,
1839                         .emit_fence = &r600_uvd_fence_emit,
1840                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1841                         .cs_parse = &radeon_uvd_cs_parse,
1842                         .ring_test = &r600_uvd_ring_test,
1843                         .ib_test = &r600_uvd_ib_test,
1844                         .is_lockup = &radeon_ring_test_lockup,
1845                         .get_rptr = &radeon_ring_generic_get_rptr,
1846                         .get_wptr = &radeon_ring_generic_get_wptr,
1847                         .set_wptr = &radeon_ring_generic_set_wptr,
1848                 }
1849         },
1850         .irq = {
1851                 .set = &evergreen_irq_set,
1852                 .process = &evergreen_irq_process,
1853         },
1854         .display = {
1855                 .bandwidth_update = &dce6_bandwidth_update,
1856                 .get_vblank_counter = &evergreen_get_vblank_counter,
1857                 .wait_for_vblank = &dce4_wait_for_vblank,
1858                 .set_backlight_level = &atombios_set_backlight_level,
1859                 .get_backlight_level = &atombios_get_backlight_level,
1860         },
1861         .copy = {
1862                 .blit = &r600_copy_blit,
1863                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1864                 .dma = &evergreen_copy_dma,
1865                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1866                 .copy = &evergreen_copy_dma,
1867                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1868         },
1869         .surface = {
1870                 .set_reg = r600_set_surface_reg,
1871                 .clear_reg = r600_clear_surface_reg,
1872         },
1873         .hpd = {
1874                 .init = &evergreen_hpd_init,
1875                 .fini = &evergreen_hpd_fini,
1876                 .sense = &evergreen_hpd_sense,
1877                 .set_polarity = &evergreen_hpd_set_polarity,
1878         },
1879         .pm = {
1880                 .misc = &evergreen_pm_misc,
1881                 .prepare = &evergreen_pm_prepare,
1882                 .finish = &evergreen_pm_finish,
1883                 .init_profile = &sumo_pm_init_profile,
1884                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1885                 .get_engine_clock = &radeon_atom_get_engine_clock,
1886                 .set_engine_clock = &radeon_atom_set_engine_clock,
1887                 .get_memory_clock = NULL,
1888                 .set_memory_clock = NULL,
1889                 .get_pcie_lanes = NULL,
1890                 .set_pcie_lanes = NULL,
1891                 .set_clock_gating = NULL,
1892                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1893         },
1894         .pflip = {
1895                 .pre_page_flip = &evergreen_pre_page_flip,
1896                 .page_flip = &evergreen_page_flip,
1897                 .post_page_flip = &evergreen_post_page_flip,
1898         },
1899 };
1900
1901 static struct radeon_asic si_asic = {
1902         .init = &si_init,
1903         .fini = &si_fini,
1904         .suspend = &si_suspend,
1905         .resume = &si_resume,
1906         .asic_reset = &si_asic_reset,
1907         .vga_set_state = &r600_vga_set_state,
1908         .ioctl_wait_idle = r600_ioctl_wait_idle,
1909         .gui_idle = &r600_gui_idle,
1910         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1911         .get_xclk = &si_get_xclk,
1912         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1913         .gart = {
1914                 .tlb_flush = &si_pcie_gart_tlb_flush,
1915                 .set_page = &rs600_gart_set_page,
1916         },
1917         .vm = {
1918                 .init = &si_vm_init,
1919                 .fini = &si_vm_fini,
1920                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1921                 .set_page = &si_vm_set_page,
1922         },
1923         .ring = {
1924                 [RADEON_RING_TYPE_GFX_INDEX] = {
1925                         .ib_execute = &si_ring_ib_execute,
1926                         .ib_parse = &si_ib_parse,
1927                         .emit_fence = &si_fence_ring_emit,
1928                         .emit_semaphore = &r600_semaphore_ring_emit,
1929                         .cs_parse = NULL,
1930                         .ring_test = &r600_ring_test,
1931                         .ib_test = &r600_ib_test,
1932                         .is_lockup = &si_gfx_is_lockup,
1933                         .vm_flush = &si_vm_flush,
1934                         .get_rptr = &radeon_ring_generic_get_rptr,
1935                         .get_wptr = &radeon_ring_generic_get_wptr,
1936                         .set_wptr = &radeon_ring_generic_set_wptr,
1937                 },
1938                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1939                         .ib_execute = &si_ring_ib_execute,
1940                         .ib_parse = &si_ib_parse,
1941                         .emit_fence = &si_fence_ring_emit,
1942                         .emit_semaphore = &r600_semaphore_ring_emit,
1943                         .cs_parse = NULL,
1944                         .ring_test = &r600_ring_test,
1945                         .ib_test = &r600_ib_test,
1946                         .is_lockup = &si_gfx_is_lockup,
1947                         .vm_flush = &si_vm_flush,
1948                         .get_rptr = &radeon_ring_generic_get_rptr,
1949                         .get_wptr = &radeon_ring_generic_get_wptr,
1950                         .set_wptr = &radeon_ring_generic_set_wptr,
1951                 },
1952                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1953                         .ib_execute = &si_ring_ib_execute,
1954                         .ib_parse = &si_ib_parse,
1955                         .emit_fence = &si_fence_ring_emit,
1956                         .emit_semaphore = &r600_semaphore_ring_emit,
1957                         .cs_parse = NULL,
1958                         .ring_test = &r600_ring_test,
1959                         .ib_test = &r600_ib_test,
1960                         .is_lockup = &si_gfx_is_lockup,
1961                         .vm_flush = &si_vm_flush,
1962                         .get_rptr = &radeon_ring_generic_get_rptr,
1963                         .get_wptr = &radeon_ring_generic_get_wptr,
1964                         .set_wptr = &radeon_ring_generic_set_wptr,
1965                 },
1966                 [R600_RING_TYPE_DMA_INDEX] = {
1967                         .ib_execute = &cayman_dma_ring_ib_execute,
1968                         .ib_parse = &evergreen_dma_ib_parse,
1969                         .emit_fence = &evergreen_dma_fence_ring_emit,
1970                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1971                         .cs_parse = NULL,
1972                         .ring_test = &r600_dma_ring_test,
1973                         .ib_test = &r600_dma_ib_test,
1974                         .is_lockup = &si_dma_is_lockup,
1975                         .vm_flush = &si_dma_vm_flush,
1976                         .get_rptr = &radeon_ring_generic_get_rptr,
1977                         .get_wptr = &radeon_ring_generic_get_wptr,
1978                         .set_wptr = &radeon_ring_generic_set_wptr,
1979                 },
1980                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1981                         .ib_execute = &cayman_dma_ring_ib_execute,
1982                         .ib_parse = &evergreen_dma_ib_parse,
1983                         .emit_fence = &evergreen_dma_fence_ring_emit,
1984                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1985                         .cs_parse = NULL,
1986                         .ring_test = &r600_dma_ring_test,
1987                         .ib_test = &r600_dma_ib_test,
1988                         .is_lockup = &si_dma_is_lockup,
1989                         .vm_flush = &si_dma_vm_flush,
1990                         .get_rptr = &radeon_ring_generic_get_rptr,
1991                         .get_wptr = &radeon_ring_generic_get_wptr,
1992                         .set_wptr = &radeon_ring_generic_set_wptr,
1993                 },
1994                 [R600_RING_TYPE_UVD_INDEX] = {
1995                         .ib_execute = &r600_uvd_ib_execute,
1996                         .emit_fence = &r600_uvd_fence_emit,
1997                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1998                         .cs_parse = &radeon_uvd_cs_parse,
1999                         .ring_test = &r600_uvd_ring_test,
2000                         .ib_test = &r600_uvd_ib_test,
2001                         .is_lockup = &radeon_ring_test_lockup,
2002                         .get_rptr = &radeon_ring_generic_get_rptr,
2003                         .get_wptr = &radeon_ring_generic_get_wptr,
2004                         .set_wptr = &radeon_ring_generic_set_wptr,
2005                 }
2006         },
2007         .irq = {
2008                 .set = &si_irq_set,
2009                 .process = &si_irq_process,
2010         },
2011         .display = {
2012                 .bandwidth_update = &dce6_bandwidth_update,
2013                 .get_vblank_counter = &evergreen_get_vblank_counter,
2014                 .wait_for_vblank = &dce4_wait_for_vblank,
2015                 .set_backlight_level = &atombios_set_backlight_level,
2016                 .get_backlight_level = &atombios_get_backlight_level,
2017         },
2018         .copy = {
2019                 .blit = NULL,
2020                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2021                 .dma = &si_copy_dma,
2022                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2023                 .copy = &si_copy_dma,
2024                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2025         },
2026         .surface = {
2027                 .set_reg = r600_set_surface_reg,
2028                 .clear_reg = r600_clear_surface_reg,
2029         },
2030         .hpd = {
2031                 .init = &evergreen_hpd_init,
2032                 .fini = &evergreen_hpd_fini,
2033                 .sense = &evergreen_hpd_sense,
2034                 .set_polarity = &evergreen_hpd_set_polarity,
2035         },
2036         .pm = {
2037                 .misc = &evergreen_pm_misc,
2038                 .prepare = &evergreen_pm_prepare,
2039                 .finish = &evergreen_pm_finish,
2040                 .init_profile = &sumo_pm_init_profile,
2041                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2042                 .get_engine_clock = &radeon_atom_get_engine_clock,
2043                 .set_engine_clock = &radeon_atom_set_engine_clock,
2044                 .get_memory_clock = &radeon_atom_get_memory_clock,
2045                 .set_memory_clock = &radeon_atom_set_memory_clock,
2046                 .get_pcie_lanes = &r600_get_pcie_lanes,
2047                 .set_pcie_lanes = &r600_set_pcie_lanes,
2048                 .set_clock_gating = NULL,
2049                 .set_uvd_clocks = &si_set_uvd_clocks,
2050         },
2051         .pflip = {
2052                 .pre_page_flip = &evergreen_pre_page_flip,
2053                 .page_flip = &evergreen_page_flip,
2054                 .post_page_flip = &evergreen_post_page_flip,
2055         },
2056 };
2057
2058 /**
2059  * radeon_asic_init - register asic specific callbacks
2060  *
2061  * @rdev: radeon device pointer
2062  *
2063  * Registers the appropriate asic specific callbacks for each
2064  * chip family.  Also sets other asics specific info like the number
2065  * of crtcs and the register aperture accessors (all asics).
2066  * Returns 0 for success.
2067  */
2068 int radeon_asic_init(struct radeon_device *rdev)
2069 {
2070         radeon_register_accessor_init(rdev);
2071
2072         /* set the number of crtcs */
2073         if (rdev->flags & RADEON_SINGLE_CRTC)
2074                 rdev->num_crtc = 1;
2075         else
2076                 rdev->num_crtc = 2;
2077
2078         rdev->has_uvd = false;
2079
2080         switch (rdev->family) {
2081         case CHIP_R100:
2082         case CHIP_RV100:
2083         case CHIP_RS100:
2084         case CHIP_RV200:
2085         case CHIP_RS200:
2086                 rdev->asic = &r100_asic;
2087                 break;
2088         case CHIP_R200:
2089         case CHIP_RV250:
2090         case CHIP_RS300:
2091         case CHIP_RV280:
2092                 rdev->asic = &r200_asic;
2093                 break;
2094         case CHIP_R300:
2095         case CHIP_R350:
2096         case CHIP_RV350:
2097         case CHIP_RV380:
2098                 if (rdev->flags & RADEON_IS_PCIE)
2099                         rdev->asic = &r300_asic_pcie;
2100                 else
2101                         rdev->asic = &r300_asic;
2102                 break;
2103         case CHIP_R420:
2104         case CHIP_R423:
2105         case CHIP_RV410:
2106                 rdev->asic = &r420_asic;
2107                 /* handle macs */
2108                 if (rdev->bios == NULL) {
2109                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2110                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2111                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2112                         rdev->asic->pm.set_memory_clock = NULL;
2113                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2114                 }
2115                 break;
2116         case CHIP_RS400:
2117         case CHIP_RS480:
2118                 rdev->asic = &rs400_asic;
2119                 break;
2120         case CHIP_RS600:
2121                 rdev->asic = &rs600_asic;
2122                 break;
2123         case CHIP_RS690:
2124         case CHIP_RS740:
2125                 rdev->asic = &rs690_asic;
2126                 break;
2127         case CHIP_RV515:
2128                 rdev->asic = &rv515_asic;
2129                 break;
2130         case CHIP_R520:
2131         case CHIP_RV530:
2132         case CHIP_RV560:
2133         case CHIP_RV570:
2134         case CHIP_R580:
2135                 rdev->asic = &r520_asic;
2136                 break;
2137         case CHIP_R600:
2138         case CHIP_RV610:
2139         case CHIP_RV630:
2140         case CHIP_RV620:
2141         case CHIP_RV635:
2142         case CHIP_RV670:
2143                 rdev->asic = &r600_asic;
2144                 if (rdev->family == CHIP_R600)
2145                         rdev->has_uvd = false;
2146                 else
2147                         rdev->has_uvd = true;
2148                 break;
2149         case CHIP_RS780:
2150         case CHIP_RS880:
2151                 rdev->asic = &rs780_asic;
2152                 rdev->has_uvd = true;
2153                 break;
2154         case CHIP_RV770:
2155         case CHIP_RV730:
2156         case CHIP_RV710:
2157         case CHIP_RV740:
2158                 rdev->asic = &rv770_asic;
2159                 rdev->has_uvd = true;
2160                 break;
2161         case CHIP_CEDAR:
2162         case CHIP_REDWOOD:
2163         case CHIP_JUNIPER:
2164         case CHIP_CYPRESS:
2165         case CHIP_HEMLOCK:
2166                 /* set num crtcs */
2167                 if (rdev->family == CHIP_CEDAR)
2168                         rdev->num_crtc = 4;
2169                 else
2170                         rdev->num_crtc = 6;
2171                 rdev->asic = &evergreen_asic;
2172                 rdev->has_uvd = true;
2173                 break;
2174         case CHIP_PALM:
2175         case CHIP_SUMO:
2176         case CHIP_SUMO2:
2177                 rdev->asic = &sumo_asic;
2178                 rdev->has_uvd = true;
2179                 break;
2180         case CHIP_BARTS:
2181         case CHIP_TURKS:
2182         case CHIP_CAICOS:
2183                 /* set num crtcs */
2184                 if (rdev->family == CHIP_CAICOS)
2185                         rdev->num_crtc = 4;
2186                 else
2187                         rdev->num_crtc = 6;
2188                 rdev->asic = &btc_asic;
2189                 rdev->has_uvd = true;
2190                 break;
2191         case CHIP_CAYMAN:
2192                 rdev->asic = &cayman_asic;
2193                 /* set num crtcs */
2194                 rdev->num_crtc = 6;
2195                 rdev->has_uvd = true;
2196                 break;
2197         case CHIP_ARUBA:
2198                 rdev->asic = &trinity_asic;
2199                 /* set num crtcs */
2200                 rdev->num_crtc = 4;
2201                 rdev->has_uvd = true;
2202                 break;
2203         case CHIP_TAHITI:
2204         case CHIP_PITCAIRN:
2205         case CHIP_VERDE:
2206         case CHIP_OLAND:
2207         case CHIP_HAINAN:
2208                 rdev->asic = &si_asic;
2209                 /* set num crtcs */
2210                 if (rdev->family == CHIP_HAINAN)
2211                         rdev->num_crtc = 0;
2212                 else if (rdev->family == CHIP_OLAND)
2213                         rdev->num_crtc = 2;
2214                 else
2215                         rdev->num_crtc = 6;
2216                 if (rdev->family == CHIP_HAINAN)
2217                         rdev->has_uvd = false;
2218                 else
2219                         rdev->has_uvd = true;
2220                 break;
2221         default:
2222                 /* FIXME: not supported yet */
2223                 return -EINVAL;
2224         }
2225
2226         if (rdev->flags & RADEON_IS_IGP) {
2227                 rdev->asic->pm.get_memory_clock = NULL;
2228                 rdev->asic->pm.set_memory_clock = NULL;
2229         }
2230
2231         return 0;
2232 }
2233