2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
33 #define SI_MAX_SH_GPRS 256
34 #define SI_MAX_TEMP_GPRS 16
35 #define SI_MAX_SH_THREADS 256
36 #define SI_MAX_SH_STACK_ENTRIES 4096
37 #define SI_MAX_FRC_EOV_CNT 16384
38 #define SI_MAX_BACKENDS 8
39 #define SI_MAX_BACKENDS_MASK 0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
41 #define SI_MAX_SIMDS 12
42 #define SI_MAX_SIMDS_MASK 0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
44 #define SI_MAX_PIPES 8
45 #define SI_MAX_PIPES_MASK 0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47 #define SI_MAX_LDS_NUM 0xFFFF
49 #define SI_MAX_TCC_MASK 0xFFFF
51 /* SMC IND accessor regs */
52 #define SMC_IND_INDEX_0 0x200
53 #define SMC_IND_DATA_0 0x204
55 #define SMC_IND_ACCESS_CNTL 0x228
56 # define AUTO_INCREMENT_IND_0 (1 << 0)
57 #define SMC_MESSAGE_0 0x22c
58 #define SMC_RESP_0 0x230
60 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
61 #define SMC_CG_IND_START 0xc0030000
62 #define SMC_CG_IND_END 0xc0040000
64 #define CG_CGTT_LOCAL_0 0x400
65 #define CG_CGTT_LOCAL_1 0x401
67 /* SMC IND registers */
68 #define SMC_SYSCON_RESET_CNTL 0x80000000
69 # define RST_REG (1 << 0)
70 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
71 # define CK_DISABLE (1 << 0)
72 # define CKEN (1 << 24)
74 #define VGA_HDP_CONTROL 0x328
75 #define VGA_MEMORY_DISABLE (1 << 4)
77 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc
78 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
79 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
80 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
81 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
82 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
83 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4
85 #define CG_SPLL_FUNC_CNTL 0x600
86 #define SPLL_RESET (1 << 0)
87 #define SPLL_SLEEP (1 << 1)
88 #define SPLL_BYPASS_EN (1 << 3)
89 #define SPLL_REF_DIV(x) ((x) << 4)
90 #define SPLL_REF_DIV_MASK (0x3f << 4)
91 #define SPLL_PDIV_A(x) ((x) << 20)
92 #define SPLL_PDIV_A_MASK (0x7f << 20)
93 #define SPLL_PDIV_A_SHIFT 20
94 #define CG_SPLL_FUNC_CNTL_2 0x604
95 #define SCLK_MUX_SEL(x) ((x) << 0)
96 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
97 #define CG_SPLL_FUNC_CNTL_3 0x608
98 #define SPLL_FB_DIV(x) ((x) << 0)
99 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
100 #define SPLL_FB_DIV_SHIFT 0
101 #define SPLL_DITHEN (1 << 28)
102 #define CG_SPLL_FUNC_CNTL_4 0x60c
104 #define SPLL_CNTL_MODE 0x618
105 # define SPLL_REFCLK_SEL(x) ((x) << 8)
106 # define SPLL_REFCLK_SEL_MASK 0xFF00
108 #define CG_SPLL_SPREAD_SPECTRUM 0x620
109 #define SSEN (1 << 0)
110 #define CLK_S(x) ((x) << 4)
111 #define CLK_S_MASK (0xfff << 4)
112 #define CLK_S_SHIFT 4
113 #define CG_SPLL_SPREAD_SPECTRUM_2 0x624
114 #define CLK_V(x) ((x) << 0)
115 #define CLK_V_MASK (0x3ffffff << 0)
116 #define CLK_V_SHIFT 0
118 #define CG_SPLL_AUTOSCALE_CNTL 0x62c
119 # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
121 /* discrete uvd clocks */
122 #define CG_UPLL_FUNC_CNTL 0x634
123 # define UPLL_RESET_MASK 0x00000001
124 # define UPLL_SLEEP_MASK 0x00000002
125 # define UPLL_BYPASS_EN_MASK 0x00000004
126 # define UPLL_CTLREQ_MASK 0x00000008
127 # define UPLL_VCO_MODE_MASK 0x00000600
128 # define UPLL_REF_DIV_MASK 0x003F0000
129 # define UPLL_CTLACK_MASK 0x40000000
130 # define UPLL_CTLACK2_MASK 0x80000000
131 #define CG_UPLL_FUNC_CNTL_2 0x638
132 # define UPLL_PDIV_A(x) ((x) << 0)
133 # define UPLL_PDIV_A_MASK 0x0000007F
134 # define UPLL_PDIV_B(x) ((x) << 8)
135 # define UPLL_PDIV_B_MASK 0x00007F00
136 # define VCLK_SRC_SEL(x) ((x) << 20)
137 # define VCLK_SRC_SEL_MASK 0x01F00000
138 # define DCLK_SRC_SEL(x) ((x) << 25)
139 # define DCLK_SRC_SEL_MASK 0x3E000000
140 #define CG_UPLL_FUNC_CNTL_3 0x63C
141 # define UPLL_FB_DIV(x) ((x) << 0)
142 # define UPLL_FB_DIV_MASK 0x01FFFFFF
143 #define CG_UPLL_FUNC_CNTL_4 0x644
144 # define UPLL_SPARE_ISPARE9 0x00020000
145 #define CG_UPLL_FUNC_CNTL_5 0x648
146 # define RESET_ANTI_MUX_MASK 0x00000200
147 #define CG_UPLL_SPREAD_SPECTRUM 0x650
148 # define SSEN_MASK 0x00000001
150 #define MPLL_BYPASSCLK_SEL 0x65c
151 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
152 # define MPLL_CLKOUT_SEL_MASK 0xFF00
154 #define CG_CLKPIN_CNTL 0x660
155 # define XTALIN_DIVIDE (1 << 1)
156 # define BCLK_AS_XCLK (1 << 2)
157 #define CG_CLKPIN_CNTL_2 0x664
158 # define FORCE_BIF_REFCLK_EN (1 << 3)
159 # define MUX_TCLK_TO_XCLK (1 << 8)
161 #define THM_CLK_CNTL 0x66c
162 # define CMON_CLK_SEL(x) ((x) << 0)
163 # define CMON_CLK_SEL_MASK 0xFF
164 # define TMON_CLK_SEL(x) ((x) << 8)
165 # define TMON_CLK_SEL_MASK 0xFF00
166 #define MISC_CLK_CNTL 0x670
167 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
168 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
169 # define ZCLK_SEL(x) ((x) << 8)
170 # define ZCLK_SEL_MASK 0xFF00
172 #define CG_THERMAL_CTRL 0x700
173 #define DPM_EVENT_SRC(x) ((x) << 0)
174 #define DPM_EVENT_SRC_MASK (7 << 0)
175 #define DIG_THERM_DPM(x) ((x) << 14)
176 #define DIG_THERM_DPM_MASK 0x003FC000
177 #define DIG_THERM_DPM_SHIFT 14
179 #define CG_THERMAL_INT 0x708
180 #define DIG_THERM_INTH(x) ((x) << 8)
181 #define DIG_THERM_INTH_MASK 0x0000FF00
182 #define DIG_THERM_INTH_SHIFT 8
183 #define DIG_THERM_INTL(x) ((x) << 16)
184 #define DIG_THERM_INTL_MASK 0x00FF0000
185 #define DIG_THERM_INTL_SHIFT 16
186 #define THERM_INT_MASK_HIGH (1 << 24)
187 #define THERM_INT_MASK_LOW (1 << 25)
189 #define CG_MULT_THERMAL_STATUS 0x714
190 #define ASIC_MAX_TEMP(x) ((x) << 0)
191 #define ASIC_MAX_TEMP_MASK 0x000001ff
192 #define ASIC_MAX_TEMP_SHIFT 0
193 #define CTF_TEMP(x) ((x) << 9)
194 #define CTF_TEMP_MASK 0x0003fe00
195 #define CTF_TEMP_SHIFT 9
197 #define GENERAL_PWRMGT 0x780
198 # define GLOBAL_PWRMGT_EN (1 << 0)
199 # define STATIC_PM_EN (1 << 1)
200 # define THERMAL_PROTECTION_DIS (1 << 2)
201 # define THERMAL_PROTECTION_TYPE (1 << 3)
202 # define SW_SMIO_INDEX(x) ((x) << 6)
203 # define SW_SMIO_INDEX_MASK (1 << 6)
204 # define SW_SMIO_INDEX_SHIFT 6
205 # define VOLT_PWRMGT_EN (1 << 10)
206 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
208 #define SCLK_PWRMGT_CNTL 0x788
209 # define SCLK_PWRMGT_OFF (1 << 0)
210 # define SCLK_LOW_D1 (1 << 1)
211 # define FIR_RESET (1 << 4)
212 # define FIR_FORCE_TREND_SEL (1 << 5)
213 # define FIR_TREND_MODE (1 << 6)
214 # define DYN_GFX_CLK_OFF_EN (1 << 7)
215 # define GFX_CLK_FORCE_ON (1 << 8)
216 # define GFX_CLK_REQUEST_OFF (1 << 9)
217 # define GFX_CLK_FORCE_OFF (1 << 10)
218 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
219 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
220 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
221 # define DYN_LIGHT_SLEEP_EN (1 << 14)
225 #define CG_FFCT_0 0x7c0
226 # define UTC_0(x) ((x) << 0)
227 # define UTC_0_MASK (0x3ff << 0)
228 # define DTC_0(x) ((x) << 10)
229 # define DTC_0_MASK (0x3ff << 10)
232 # define BSP(x) ((x) << 0)
233 # define BSP_MASK (0xffff << 0)
234 # define BSU(x) ((x) << 16)
235 # define BSU_MASK (0xf << 16)
237 # define CG_R(x) ((x) << 0)
238 # define CG_R_MASK (0xffff << 0)
239 # define CG_L(x) ((x) << 16)
240 # define CG_L_MASK (0xffff << 16)
243 # define CG_GICST(x) ((x) << 0)
244 # define CG_GICST_MASK (0xffff << 0)
245 # define CG_GIPOT(x) ((x) << 16)
246 # define CG_GIPOT_MASK (0xffff << 16)
249 # define SST(x) ((x) << 0)
250 # define SST_MASK (0xffff << 0)
251 # define SSTU(x) ((x) << 16)
252 # define SSTU_MASK (0xf << 16)
254 #define CG_DISPLAY_GAP_CNTL 0x828
255 # define DISP1_GAP(x) ((x) << 0)
256 # define DISP1_GAP_MASK (3 << 0)
257 # define DISP2_GAP(x) ((x) << 2)
258 # define DISP2_GAP_MASK (3 << 2)
259 # define VBI_TIMER_COUNT(x) ((x) << 4)
260 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
261 # define VBI_TIMER_UNIT(x) ((x) << 20)
262 # define VBI_TIMER_UNIT_MASK (7 << 20)
263 # define DISP1_GAP_MCHG(x) ((x) << 24)
264 # define DISP1_GAP_MCHG_MASK (3 << 24)
265 # define DISP2_GAP_MCHG(x) ((x) << 26)
266 # define DISP2_GAP_MCHG_MASK (3 << 26)
268 #define CG_ULV_CONTROL 0x878
269 #define CG_ULV_PARAMETER 0x87c
271 #define SMC_SCRATCH0 0x884
273 #define CG_CAC_CTRL 0x8b8
274 # define CAC_WINDOW(x) ((x) << 0)
275 # define CAC_WINDOW_MASK 0x00ffffff
277 #define DMIF_ADDR_CONFIG 0xBD4
279 #define DMIF_ADDR_CALC 0xC00
281 #define SRBM_STATUS 0xE50
282 #define GRBM_RQ_PENDING (1 << 5)
283 #define VMC_BUSY (1 << 8)
284 #define MCB_BUSY (1 << 9)
285 #define MCB_NON_DISPLAY_BUSY (1 << 10)
286 #define MCC_BUSY (1 << 11)
287 #define MCD_BUSY (1 << 12)
288 #define SEM_BUSY (1 << 14)
289 #define IH_BUSY (1 << 17)
291 #define SRBM_SOFT_RESET 0x0E60
292 #define SOFT_RESET_BIF (1 << 1)
293 #define SOFT_RESET_DC (1 << 5)
294 #define SOFT_RESET_DMA1 (1 << 6)
295 #define SOFT_RESET_GRBM (1 << 8)
296 #define SOFT_RESET_HDP (1 << 9)
297 #define SOFT_RESET_IH (1 << 10)
298 #define SOFT_RESET_MC (1 << 11)
299 #define SOFT_RESET_ROM (1 << 14)
300 #define SOFT_RESET_SEM (1 << 15)
301 #define SOFT_RESET_VMC (1 << 17)
302 #define SOFT_RESET_DMA (1 << 20)
303 #define SOFT_RESET_TST (1 << 21)
304 #define SOFT_RESET_REGBB (1 << 22)
305 #define SOFT_RESET_ORB (1 << 23)
307 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
308 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
310 #define SRBM_STATUS2 0x0EC4
311 #define DMA_BUSY (1 << 5)
312 #define DMA1_BUSY (1 << 6)
314 #define VM_L2_CNTL 0x1400
315 #define ENABLE_L2_CACHE (1 << 0)
316 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
317 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
318 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
319 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
320 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
321 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
322 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
323 #define VM_L2_CNTL2 0x1404
324 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
325 #define INVALIDATE_L2_CACHE (1 << 1)
326 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
327 #define INVALIDATE_PTE_AND_PDE_CACHES 0
328 #define INVALIDATE_ONLY_PTE_CACHES 1
329 #define INVALIDATE_ONLY_PDE_CACHES 2
330 #define VM_L2_CNTL3 0x1408
331 #define BANK_SELECT(x) ((x) << 0)
332 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
333 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
334 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
335 #define VM_L2_STATUS 0x140C
336 #define L2_BUSY (1 << 0)
337 #define VM_CONTEXT0_CNTL 0x1410
338 #define ENABLE_CONTEXT (1 << 0)
339 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
340 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
341 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
342 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
343 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
344 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
345 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
346 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
347 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
348 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
349 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
350 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
351 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
352 #define VM_CONTEXT1_CNTL 0x1414
353 #define VM_CONTEXT0_CNTL2 0x1430
354 #define VM_CONTEXT1_CNTL2 0x1434
355 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
356 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
357 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
358 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
359 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
360 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
361 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
362 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
364 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
365 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
367 #define VM_INVALIDATE_REQUEST 0x1478
368 #define VM_INVALIDATE_RESPONSE 0x147c
370 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
371 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
373 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
374 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
375 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
376 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
377 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
378 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
379 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
380 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
381 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
382 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
384 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
385 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
387 #define VM_L2_CG 0x15c0
388 #define MC_CG_ENABLE (1 << 18)
389 #define MC_LS_ENABLE (1 << 19)
391 #define MC_SHARED_CHMAP 0x2004
392 #define NOOFCHAN_SHIFT 12
393 #define NOOFCHAN_MASK 0x0000f000
394 #define MC_SHARED_CHREMAP 0x2008
396 #define MC_VM_FB_LOCATION 0x2024
397 #define MC_VM_AGP_TOP 0x2028
398 #define MC_VM_AGP_BOT 0x202C
399 #define MC_VM_AGP_BASE 0x2030
400 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
401 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
402 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
404 #define MC_VM_MX_L1_TLB_CNTL 0x2064
405 #define ENABLE_L1_TLB (1 << 0)
406 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
407 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
408 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
409 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
410 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
411 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
412 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
414 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
416 #define MC_HUB_MISC_HUB_CG 0x20b8
417 #define MC_HUB_MISC_VM_CG 0x20bc
419 #define MC_HUB_MISC_SIP_CG 0x20c0
421 #define MC_XPB_CLK_GAT 0x2478
423 #define MC_CITF_MISC_RD_CG 0x2648
424 #define MC_CITF_MISC_WR_CG 0x264c
425 #define MC_CITF_MISC_VM_CG 0x2650
427 #define MC_ARB_RAMCFG 0x2760
428 #define NOOFBANK_SHIFT 0
429 #define NOOFBANK_MASK 0x00000003
430 #define NOOFRANK_SHIFT 2
431 #define NOOFRANK_MASK 0x00000004
432 #define NOOFROWS_SHIFT 3
433 #define NOOFROWS_MASK 0x00000038
434 #define NOOFCOLS_SHIFT 6
435 #define NOOFCOLS_MASK 0x000000C0
436 #define CHANSIZE_SHIFT 8
437 #define CHANSIZE_MASK 0x00000100
438 #define CHANSIZE_OVERRIDE (1 << 11)
439 #define NOOFGROUPS_SHIFT 12
440 #define NOOFGROUPS_MASK 0x00001000
442 #define MC_ARB_DRAM_TIMING 0x2774
443 #define MC_ARB_DRAM_TIMING2 0x2778
445 #define MC_ARB_BURST_TIME 0x2808
446 #define STATE0(x) ((x) << 0)
447 #define STATE0_MASK (0x1f << 0)
448 #define STATE0_SHIFT 0
449 #define STATE1(x) ((x) << 5)
450 #define STATE1_MASK (0x1f << 5)
451 #define STATE1_SHIFT 5
452 #define STATE2(x) ((x) << 10)
453 #define STATE2_MASK (0x1f << 10)
454 #define STATE2_SHIFT 10
455 #define STATE3(x) ((x) << 15)
456 #define STATE3_MASK (0x1f << 15)
457 #define STATE3_SHIFT 15
459 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
460 #define TRAIN_DONE_D0 (1 << 30)
461 #define TRAIN_DONE_D1 (1 << 31)
463 #define MC_SEQ_SUP_CNTL 0x28c8
464 #define RUN_MASK (1 << 0)
465 #define MC_SEQ_SUP_PGM 0x28cc
466 #define MC_PMG_AUTO_CMD 0x28d0
468 #define MC_IO_PAD_CNTL_D0 0x29d0
469 #define MEM_FALL_OUT_CMD (1 << 8)
471 #define MC_SEQ_RAS_TIMING 0x28a0
472 #define MC_SEQ_CAS_TIMING 0x28a4
473 #define MC_SEQ_MISC_TIMING 0x28a8
474 #define MC_SEQ_MISC_TIMING2 0x28ac
475 #define MC_SEQ_PMG_TIMING 0x28b0
476 #define MC_SEQ_RD_CTL_D0 0x28b4
477 #define MC_SEQ_RD_CTL_D1 0x28b8
478 #define MC_SEQ_WR_CTL_D0 0x28bc
479 #define MC_SEQ_WR_CTL_D1 0x28c0
481 #define MC_SEQ_MISC0 0x2a00
482 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
483 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
484 #define MC_SEQ_MISC0_VEN_ID_VALUE 3
485 #define MC_SEQ_MISC0_REV_ID_SHIFT 12
486 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
487 #define MC_SEQ_MISC0_REV_ID_VALUE 1
488 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
489 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
490 #define MC_SEQ_MISC0_GDDR5_VALUE 5
491 #define MC_SEQ_MISC1 0x2a04
492 #define MC_SEQ_RESERVE_M 0x2a08
493 #define MC_PMG_CMD_EMRS 0x2a0c
495 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
496 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
498 #define MC_SEQ_MISC5 0x2a54
499 #define MC_SEQ_MISC6 0x2a58
501 #define MC_SEQ_MISC7 0x2a64
503 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
504 #define MC_SEQ_CAS_TIMING_LP 0x2a70
505 #define MC_SEQ_MISC_TIMING_LP 0x2a74
506 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
507 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
508 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
509 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
510 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
512 #define MC_PMG_CMD_MRS 0x2aac
514 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
515 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
517 #define MC_PMG_CMD_MRS1 0x2b44
518 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
519 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
521 #define MC_SEQ_WR_CTL_2 0x2b54
522 #define MC_SEQ_WR_CTL_2_LP 0x2b58
523 #define MC_PMG_CMD_MRS2 0x2b5c
524 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
526 #define MCLK_PWRMGT_CNTL 0x2ba0
527 # define DLL_SPEED(x) ((x) << 0)
528 # define DLL_SPEED_MASK (0x1f << 0)
529 # define DLL_READY (1 << 6)
530 # define MC_INT_CNTL (1 << 7)
531 # define MRDCK0_PDNB (1 << 8)
532 # define MRDCK1_PDNB (1 << 9)
533 # define MRDCK0_RESET (1 << 16)
534 # define MRDCK1_RESET (1 << 17)
535 # define DLL_READY_READ (1 << 24)
536 #define DLL_CNTL 0x2ba4
537 # define MRDCK0_BYPASS (1 << 24)
538 # define MRDCK1_BYPASS (1 << 25)
540 #define MPLL_FUNC_CNTL 0x2bb4
541 #define BWCTRL(x) ((x) << 20)
542 #define BWCTRL_MASK (0xff << 20)
543 #define MPLL_FUNC_CNTL_1 0x2bb8
544 #define VCO_MODE(x) ((x) << 0)
545 #define VCO_MODE_MASK (3 << 0)
546 #define CLKFRAC(x) ((x) << 4)
547 #define CLKFRAC_MASK (0xfff << 4)
548 #define CLKF(x) ((x) << 16)
549 #define CLKF_MASK (0xfff << 16)
550 #define MPLL_FUNC_CNTL_2 0x2bbc
551 #define MPLL_AD_FUNC_CNTL 0x2bc0
552 #define YCLK_POST_DIV(x) ((x) << 0)
553 #define YCLK_POST_DIV_MASK (7 << 0)
554 #define MPLL_DQ_FUNC_CNTL 0x2bc4
555 #define YCLK_SEL(x) ((x) << 4)
556 #define YCLK_SEL_MASK (1 << 4)
558 #define MPLL_SS1 0x2bcc
559 #define CLKV(x) ((x) << 0)
560 #define CLKV_MASK (0x3ffffff << 0)
561 #define MPLL_SS2 0x2bd0
562 #define CLKS(x) ((x) << 0)
563 #define CLKS_MASK (0xfff << 0)
565 #define HDP_HOST_PATH_CNTL 0x2C00
566 #define HDP_NONSURFACE_BASE 0x2C04
567 #define HDP_NONSURFACE_INFO 0x2C08
568 #define HDP_NONSURFACE_SIZE 0x2C0C
570 #define HDP_ADDR_CONFIG 0x2F48
571 #define HDP_MISC_CNTL 0x2F4C
572 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
574 #define ATC_MISC_CG 0x3350
576 #define IH_RB_CNTL 0x3e00
577 # define IH_RB_ENABLE (1 << 0)
578 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
579 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
580 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
581 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
582 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
583 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
584 #define IH_RB_BASE 0x3e04
585 #define IH_RB_RPTR 0x3e08
586 #define IH_RB_WPTR 0x3e0c
587 # define RB_OVERFLOW (1 << 0)
588 # define WPTR_OFFSET_MASK 0x3fffc
589 #define IH_RB_WPTR_ADDR_HI 0x3e10
590 #define IH_RB_WPTR_ADDR_LO 0x3e14
591 #define IH_CNTL 0x3e18
592 # define ENABLE_INTR (1 << 0)
593 # define IH_MC_SWAP(x) ((x) << 1)
594 # define IH_MC_SWAP_NONE 0
595 # define IH_MC_SWAP_16BIT 1
596 # define IH_MC_SWAP_32BIT 2
597 # define IH_MC_SWAP_64BIT 3
598 # define RPTR_REARM (1 << 4)
599 # define MC_WRREQ_CREDIT(x) ((x) << 15)
600 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
601 # define MC_VMID(x) ((x) << 25)
603 #define CONFIG_MEMSIZE 0x5428
605 #define INTERRUPT_CNTL 0x5468
606 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
607 # define IH_DUMMY_RD_EN (1 << 1)
608 # define IH_REQ_NONSNOOP_EN (1 << 3)
609 # define GEN_IH_INT_EN (1 << 8)
610 #define INTERRUPT_CNTL2 0x546c
612 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
614 #define BIF_FB_EN 0x5490
615 #define FB_READ_EN (1 << 0)
616 #define FB_WRITE_EN (1 << 1)
618 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
620 #define DC_LB_MEMORY_SPLIT 0x6b0c
621 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
623 #define PRIORITY_A_CNT 0x6b18
624 #define PRIORITY_MARK_MASK 0x7fff
625 #define PRIORITY_OFF (1 << 16)
626 #define PRIORITY_ALWAYS_ON (1 << 20)
627 #define PRIORITY_B_CNT 0x6b1c
629 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
630 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
631 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
632 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
633 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
635 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
636 #define VLINE_STATUS 0x6bb8
637 # define VLINE_OCCURRED (1 << 0)
638 # define VLINE_ACK (1 << 4)
639 # define VLINE_STAT (1 << 12)
640 # define VLINE_INTERRUPT (1 << 16)
641 # define VLINE_INTERRUPT_TYPE (1 << 17)
642 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
643 #define VBLANK_STATUS 0x6bbc
644 # define VBLANK_OCCURRED (1 << 0)
645 # define VBLANK_ACK (1 << 4)
646 # define VBLANK_STAT (1 << 12)
647 # define VBLANK_INTERRUPT (1 << 16)
648 # define VBLANK_INTERRUPT_TYPE (1 << 17)
650 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
651 #define INT_MASK 0x6b40
652 # define VBLANK_INT_MASK (1 << 0)
653 # define VLINE_INT_MASK (1 << 4)
655 #define DISP_INTERRUPT_STATUS 0x60f4
656 # define LB_D1_VLINE_INTERRUPT (1 << 2)
657 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
658 # define DC_HPD1_INTERRUPT (1 << 17)
659 # define DC_HPD1_RX_INTERRUPT (1 << 18)
660 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
661 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
662 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
663 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
664 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
665 # define LB_D2_VLINE_INTERRUPT (1 << 2)
666 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
667 # define DC_HPD2_INTERRUPT (1 << 17)
668 # define DC_HPD2_RX_INTERRUPT (1 << 18)
669 # define DISP_TIMER_INTERRUPT (1 << 24)
670 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
671 # define LB_D3_VLINE_INTERRUPT (1 << 2)
672 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
673 # define DC_HPD3_INTERRUPT (1 << 17)
674 # define DC_HPD3_RX_INTERRUPT (1 << 18)
675 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
676 # define LB_D4_VLINE_INTERRUPT (1 << 2)
677 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
678 # define DC_HPD4_INTERRUPT (1 << 17)
679 # define DC_HPD4_RX_INTERRUPT (1 << 18)
680 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
681 # define LB_D5_VLINE_INTERRUPT (1 << 2)
682 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
683 # define DC_HPD5_INTERRUPT (1 << 17)
684 # define DC_HPD5_RX_INTERRUPT (1 << 18)
685 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
686 # define LB_D6_VLINE_INTERRUPT (1 << 2)
687 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
688 # define DC_HPD6_INTERRUPT (1 << 17)
689 # define DC_HPD6_RX_INTERRUPT (1 << 18)
691 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
692 #define GRPH_INT_STATUS 0x6858
693 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
694 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
695 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
696 #define GRPH_INT_CONTROL 0x685c
697 # define GRPH_PFLIP_INT_MASK (1 << 0)
698 # define GRPH_PFLIP_INT_TYPE (1 << 8)
700 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
702 #define DC_HPD1_INT_STATUS 0x601c
703 #define DC_HPD2_INT_STATUS 0x6028
704 #define DC_HPD3_INT_STATUS 0x6034
705 #define DC_HPD4_INT_STATUS 0x6040
706 #define DC_HPD5_INT_STATUS 0x604c
707 #define DC_HPD6_INT_STATUS 0x6058
708 # define DC_HPDx_INT_STATUS (1 << 0)
709 # define DC_HPDx_SENSE (1 << 1)
710 # define DC_HPDx_RX_INT_STATUS (1 << 8)
712 #define DC_HPD1_INT_CONTROL 0x6020
713 #define DC_HPD2_INT_CONTROL 0x602c
714 #define DC_HPD3_INT_CONTROL 0x6038
715 #define DC_HPD4_INT_CONTROL 0x6044
716 #define DC_HPD5_INT_CONTROL 0x6050
717 #define DC_HPD6_INT_CONTROL 0x605c
718 # define DC_HPDx_INT_ACK (1 << 0)
719 # define DC_HPDx_INT_POLARITY (1 << 8)
720 # define DC_HPDx_INT_EN (1 << 16)
721 # define DC_HPDx_RX_INT_ACK (1 << 20)
722 # define DC_HPDx_RX_INT_EN (1 << 24)
724 #define DC_HPD1_CONTROL 0x6024
725 #define DC_HPD2_CONTROL 0x6030
726 #define DC_HPD3_CONTROL 0x603c
727 #define DC_HPD4_CONTROL 0x6048
728 #define DC_HPD5_CONTROL 0x6054
729 #define DC_HPD6_CONTROL 0x6060
730 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
731 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
732 # define DC_HPDx_EN (1 << 28)
734 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
735 # define STUTTER_ENABLE (1 << 0)
737 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
738 #define CRTC_STATUS_FRAME_COUNT 0x6e98
740 #define GRBM_CNTL 0x8000
741 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
743 #define GRBM_STATUS2 0x8008
744 #define RLC_RQ_PENDING (1 << 0)
745 #define RLC_BUSY (1 << 8)
746 #define TC_BUSY (1 << 9)
748 #define GRBM_STATUS 0x8010
749 #define CMDFIFO_AVAIL_MASK 0x0000000F
750 #define RING2_RQ_PENDING (1 << 4)
751 #define SRBM_RQ_PENDING (1 << 5)
752 #define RING1_RQ_PENDING (1 << 6)
753 #define CF_RQ_PENDING (1 << 7)
754 #define PF_RQ_PENDING (1 << 8)
755 #define GDS_DMA_RQ_PENDING (1 << 9)
756 #define GRBM_EE_BUSY (1 << 10)
757 #define DB_CLEAN (1 << 12)
758 #define CB_CLEAN (1 << 13)
759 #define TA_BUSY (1 << 14)
760 #define GDS_BUSY (1 << 15)
761 #define VGT_BUSY (1 << 17)
762 #define IA_BUSY_NO_DMA (1 << 18)
763 #define IA_BUSY (1 << 19)
764 #define SX_BUSY (1 << 20)
765 #define SPI_BUSY (1 << 22)
766 #define BCI_BUSY (1 << 23)
767 #define SC_BUSY (1 << 24)
768 #define PA_BUSY (1 << 25)
769 #define DB_BUSY (1 << 26)
770 #define CP_COHERENCY_BUSY (1 << 28)
771 #define CP_BUSY (1 << 29)
772 #define CB_BUSY (1 << 30)
773 #define GUI_ACTIVE (1 << 31)
774 #define GRBM_STATUS_SE0 0x8014
775 #define GRBM_STATUS_SE1 0x8018
776 #define SE_DB_CLEAN (1 << 1)
777 #define SE_CB_CLEAN (1 << 2)
778 #define SE_BCI_BUSY (1 << 22)
779 #define SE_VGT_BUSY (1 << 23)
780 #define SE_PA_BUSY (1 << 24)
781 #define SE_TA_BUSY (1 << 25)
782 #define SE_SX_BUSY (1 << 26)
783 #define SE_SPI_BUSY (1 << 27)
784 #define SE_SC_BUSY (1 << 29)
785 #define SE_DB_BUSY (1 << 30)
786 #define SE_CB_BUSY (1 << 31)
788 #define GRBM_SOFT_RESET 0x8020
789 #define SOFT_RESET_CP (1 << 0)
790 #define SOFT_RESET_CB (1 << 1)
791 #define SOFT_RESET_RLC (1 << 2)
792 #define SOFT_RESET_DB (1 << 3)
793 #define SOFT_RESET_GDS (1 << 4)
794 #define SOFT_RESET_PA (1 << 5)
795 #define SOFT_RESET_SC (1 << 6)
796 #define SOFT_RESET_BCI (1 << 7)
797 #define SOFT_RESET_SPI (1 << 8)
798 #define SOFT_RESET_SX (1 << 10)
799 #define SOFT_RESET_TC (1 << 11)
800 #define SOFT_RESET_TA (1 << 12)
801 #define SOFT_RESET_VGT (1 << 14)
802 #define SOFT_RESET_IA (1 << 15)
804 #define GRBM_GFX_INDEX 0x802C
805 #define INSTANCE_INDEX(x) ((x) << 0)
806 #define SH_INDEX(x) ((x) << 8)
807 #define SE_INDEX(x) ((x) << 16)
808 #define SH_BROADCAST_WRITES (1 << 29)
809 #define INSTANCE_BROADCAST_WRITES (1 << 30)
810 #define SE_BROADCAST_WRITES (1 << 31)
812 #define GRBM_INT_CNTL 0x8060
813 # define RDERR_INT_ENABLE (1 << 0)
814 # define GUI_IDLE_INT_ENABLE (1 << 19)
816 #define CP_STRMOUT_CNTL 0x84FC
817 #define SCRATCH_REG0 0x8500
818 #define SCRATCH_REG1 0x8504
819 #define SCRATCH_REG2 0x8508
820 #define SCRATCH_REG3 0x850C
821 #define SCRATCH_REG4 0x8510
822 #define SCRATCH_REG5 0x8514
823 #define SCRATCH_REG6 0x8518
824 #define SCRATCH_REG7 0x851C
826 #define SCRATCH_UMSK 0x8540
827 #define SCRATCH_ADDR 0x8544
829 #define CP_SEM_WAIT_TIMER 0x85BC
831 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
833 #define CP_ME_CNTL 0x86D8
834 #define CP_CE_HALT (1 << 24)
835 #define CP_PFP_HALT (1 << 26)
836 #define CP_ME_HALT (1 << 28)
838 #define CP_COHER_CNTL2 0x85E8
840 #define CP_RB2_RPTR 0x86f8
841 #define CP_RB1_RPTR 0x86fc
842 #define CP_RB0_RPTR 0x8700
843 #define CP_RB_WPTR_DELAY 0x8704
845 #define CP_QUEUE_THRESHOLDS 0x8760
846 #define ROQ_IB1_START(x) ((x) << 0)
847 #define ROQ_IB2_START(x) ((x) << 8)
848 #define CP_MEQ_THRESHOLDS 0x8764
849 #define MEQ1_START(x) ((x) << 0)
850 #define MEQ2_START(x) ((x) << 8)
852 #define CP_PERFMON_CNTL 0x87FC
854 #define VGT_VTX_VECT_EJECT_REG 0x88B0
856 #define VGT_CACHE_INVALIDATION 0x88C4
857 #define CACHE_INVALIDATION(x) ((x) << 0)
861 #define AUTO_INVLD_EN(x) ((x) << 6)
865 #define ES_AND_GS_AUTO 3
866 #define VGT_ESGS_RING_SIZE 0x88C8
867 #define VGT_GSVS_RING_SIZE 0x88CC
869 #define VGT_GS_VERTEX_REUSE 0x88D4
871 #define VGT_PRIMITIVE_TYPE 0x8958
872 #define VGT_INDEX_TYPE 0x895C
874 #define VGT_NUM_INDICES 0x8970
875 #define VGT_NUM_INSTANCES 0x8974
877 #define VGT_TF_RING_SIZE 0x8988
879 #define VGT_HS_OFFCHIP_PARAM 0x89B0
881 #define VGT_TF_MEMORY_BASE 0x89B8
883 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
884 #define INACTIVE_CUS_MASK 0xFFFF0000
885 #define INACTIVE_CUS_SHIFT 16
886 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
888 #define PA_CL_ENHANCE 0x8A14
889 #define CLIP_VTX_REORDER_ENA (1 << 0)
890 #define NUM_CLIP_SEQ(x) ((x) << 1)
892 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
894 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
896 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
897 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
898 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
900 #define PA_SC_FIFO_SIZE 0x8BCC
901 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
902 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
903 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
904 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
906 #define PA_SC_ENHANCE 0x8BF0
908 #define SQ_CONFIG 0x8C00
910 #define SQC_CACHES 0x8C08
912 #define SQ_POWER_THROTTLE 0x8e58
913 #define MIN_POWER(x) ((x) << 0)
914 #define MIN_POWER_MASK (0x3fff << 0)
915 #define MIN_POWER_SHIFT 0
916 #define MAX_POWER(x) ((x) << 16)
917 #define MAX_POWER_MASK (0x3fff << 16)
918 #define MAX_POWER_SHIFT 0
919 #define SQ_POWER_THROTTLE2 0x8e5c
920 #define MAX_POWER_DELTA(x) ((x) << 0)
921 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
922 #define MAX_POWER_DELTA_SHIFT 0
923 #define STI_SIZE(x) ((x) << 16)
924 #define STI_SIZE_MASK (0x3ff << 16)
925 #define STI_SIZE_SHIFT 16
926 #define LTI_RATIO(x) ((x) << 27)
927 #define LTI_RATIO_MASK (0xf << 27)
928 #define LTI_RATIO_SHIFT 27
930 #define SX_DEBUG_1 0x9060
932 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
933 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
934 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
935 #define SPI_PS_MAX_WAVE_ID 0x90EC
937 #define SPI_CONFIG_CNTL 0x9100
939 #define SPI_CONFIG_CNTL_1 0x913C
940 #define VTX_DONE_DELAY(x) ((x) << 0)
941 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
943 #define CGTS_TCC_DISABLE 0x9148
944 #define CGTS_USER_TCC_DISABLE 0x914C
945 #define TCC_DISABLE_MASK 0xFFFF0000
946 #define TCC_DISABLE_SHIFT 16
947 #define CGTS_SM_CTRL_REG 0x9150
948 #define OVERRIDE (1 << 21)
949 #define LS_OVERRIDE (1 << 22)
951 #define SPI_LB_CU_MASK 0x9354
953 #define TA_CNTL_AUX 0x9508
955 #define CC_RB_BACKEND_DISABLE 0x98F4
956 #define BACKEND_DISABLE(x) ((x) << 16)
957 #define GB_ADDR_CONFIG 0x98F8
958 #define NUM_PIPES(x) ((x) << 0)
959 #define NUM_PIPES_MASK 0x00000007
960 #define NUM_PIPES_SHIFT 0
961 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
962 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
963 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
964 #define NUM_SHADER_ENGINES(x) ((x) << 12)
965 #define NUM_SHADER_ENGINES_MASK 0x00003000
966 #define NUM_SHADER_ENGINES_SHIFT 12
967 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
968 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
969 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
970 #define NUM_GPUS(x) ((x) << 20)
971 #define NUM_GPUS_MASK 0x00700000
972 #define NUM_GPUS_SHIFT 20
973 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
974 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
975 #define MULTI_GPU_TILE_SIZE_SHIFT 24
976 #define ROW_SIZE(x) ((x) << 28)
977 #define ROW_SIZE_MASK 0x30000000
978 #define ROW_SIZE_SHIFT 28
980 #define GB_TILE_MODE0 0x9910
981 # define MICRO_TILE_MODE(x) ((x) << 0)
982 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
983 # define ADDR_SURF_THIN_MICRO_TILING 1
984 # define ADDR_SURF_DEPTH_MICRO_TILING 2
985 # define ARRAY_MODE(x) ((x) << 2)
986 # define ARRAY_LINEAR_GENERAL 0
987 # define ARRAY_LINEAR_ALIGNED 1
988 # define ARRAY_1D_TILED_THIN1 2
989 # define ARRAY_2D_TILED_THIN1 4
990 # define PIPE_CONFIG(x) ((x) << 6)
991 # define ADDR_SURF_P2 0
992 # define ADDR_SURF_P4_8x16 4
993 # define ADDR_SURF_P4_16x16 5
994 # define ADDR_SURF_P4_16x32 6
995 # define ADDR_SURF_P4_32x32 7
996 # define ADDR_SURF_P8_16x16_8x16 8
997 # define ADDR_SURF_P8_16x32_8x16 9
998 # define ADDR_SURF_P8_32x32_8x16 10
999 # define ADDR_SURF_P8_16x32_16x16 11
1000 # define ADDR_SURF_P8_32x32_16x16 12
1001 # define ADDR_SURF_P8_32x32_16x32 13
1002 # define ADDR_SURF_P8_32x64_32x32 14
1003 # define TILE_SPLIT(x) ((x) << 11)
1004 # define ADDR_SURF_TILE_SPLIT_64B 0
1005 # define ADDR_SURF_TILE_SPLIT_128B 1
1006 # define ADDR_SURF_TILE_SPLIT_256B 2
1007 # define ADDR_SURF_TILE_SPLIT_512B 3
1008 # define ADDR_SURF_TILE_SPLIT_1KB 4
1009 # define ADDR_SURF_TILE_SPLIT_2KB 5
1010 # define ADDR_SURF_TILE_SPLIT_4KB 6
1011 # define BANK_WIDTH(x) ((x) << 14)
1012 # define ADDR_SURF_BANK_WIDTH_1 0
1013 # define ADDR_SURF_BANK_WIDTH_2 1
1014 # define ADDR_SURF_BANK_WIDTH_4 2
1015 # define ADDR_SURF_BANK_WIDTH_8 3
1016 # define BANK_HEIGHT(x) ((x) << 16)
1017 # define ADDR_SURF_BANK_HEIGHT_1 0
1018 # define ADDR_SURF_BANK_HEIGHT_2 1
1019 # define ADDR_SURF_BANK_HEIGHT_4 2
1020 # define ADDR_SURF_BANK_HEIGHT_8 3
1021 # define MACRO_TILE_ASPECT(x) ((x) << 18)
1022 # define ADDR_SURF_MACRO_ASPECT_1 0
1023 # define ADDR_SURF_MACRO_ASPECT_2 1
1024 # define ADDR_SURF_MACRO_ASPECT_4 2
1025 # define ADDR_SURF_MACRO_ASPECT_8 3
1026 # define NUM_BANKS(x) ((x) << 20)
1027 # define ADDR_SURF_2_BANK 0
1028 # define ADDR_SURF_4_BANK 1
1029 # define ADDR_SURF_8_BANK 2
1030 # define ADDR_SURF_16_BANK 3
1032 #define CB_PERFCOUNTER0_SELECT0 0x9a20
1033 #define CB_PERFCOUNTER0_SELECT1 0x9a24
1034 #define CB_PERFCOUNTER1_SELECT0 0x9a28
1035 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
1036 #define CB_PERFCOUNTER2_SELECT0 0x9a30
1037 #define CB_PERFCOUNTER2_SELECT1 0x9a34
1038 #define CB_PERFCOUNTER3_SELECT0 0x9a38
1039 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
1041 #define CB_CGTT_SCLK_CTRL 0x9a60
1043 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1044 #define BACKEND_DISABLE_MASK 0x00FF0000
1045 #define BACKEND_DISABLE_SHIFT 16
1047 #define TCP_CHAN_STEER_LO 0xac0c
1048 #define TCP_CHAN_STEER_HI 0xac10
1050 #define CP_RB0_BASE 0xC100
1051 #define CP_RB0_CNTL 0xC104
1052 #define RB_BUFSZ(x) ((x) << 0)
1053 #define RB_BLKSZ(x) ((x) << 8)
1054 #define BUF_SWAP_32BIT (2 << 16)
1055 #define RB_NO_UPDATE (1 << 27)
1056 #define RB_RPTR_WR_ENA (1 << 31)
1058 #define CP_RB0_RPTR_ADDR 0xC10C
1059 #define CP_RB0_RPTR_ADDR_HI 0xC110
1060 #define CP_RB0_WPTR 0xC114
1062 #define CP_PFP_UCODE_ADDR 0xC150
1063 #define CP_PFP_UCODE_DATA 0xC154
1064 #define CP_ME_RAM_RADDR 0xC158
1065 #define CP_ME_RAM_WADDR 0xC15C
1066 #define CP_ME_RAM_DATA 0xC160
1068 #define CP_CE_UCODE_ADDR 0xC168
1069 #define CP_CE_UCODE_DATA 0xC16C
1071 #define CP_RB1_BASE 0xC180
1072 #define CP_RB1_CNTL 0xC184
1073 #define CP_RB1_RPTR_ADDR 0xC188
1074 #define CP_RB1_RPTR_ADDR_HI 0xC18C
1075 #define CP_RB1_WPTR 0xC190
1076 #define CP_RB2_BASE 0xC194
1077 #define CP_RB2_CNTL 0xC198
1078 #define CP_RB2_RPTR_ADDR 0xC19C
1079 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
1080 #define CP_RB2_WPTR 0xC1A4
1081 #define CP_INT_CNTL_RING0 0xC1A8
1082 #define CP_INT_CNTL_RING1 0xC1AC
1083 #define CP_INT_CNTL_RING2 0xC1B0
1084 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1085 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1086 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1087 # define TIME_STAMP_INT_ENABLE (1 << 26)
1088 # define CP_RINGID2_INT_ENABLE (1 << 29)
1089 # define CP_RINGID1_INT_ENABLE (1 << 30)
1090 # define CP_RINGID0_INT_ENABLE (1 << 31)
1091 #define CP_INT_STATUS_RING0 0xC1B4
1092 #define CP_INT_STATUS_RING1 0xC1B8
1093 #define CP_INT_STATUS_RING2 0xC1BC
1094 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
1095 # define TIME_STAMP_INT_STAT (1 << 26)
1096 # define CP_RINGID2_INT_STAT (1 << 29)
1097 # define CP_RINGID1_INT_STAT (1 << 30)
1098 # define CP_RINGID0_INT_STAT (1 << 31)
1100 #define CP_MEM_SLP_CNTL 0xC1E4
1101 # define CP_MEM_LS_EN (1 << 0)
1103 #define CP_DEBUG 0xC1FC
1105 #define RLC_CNTL 0xC300
1106 # define RLC_ENABLE (1 << 0)
1107 #define RLC_RL_BASE 0xC304
1108 #define RLC_RL_SIZE 0xC308
1109 #define RLC_LB_CNTL 0xC30C
1110 # define LOAD_BALANCE_ENABLE (1 << 0)
1111 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
1112 #define RLC_LB_CNTR_MAX 0xC314
1113 #define RLC_LB_CNTR_INIT 0xC318
1115 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
1117 #define RLC_UCODE_ADDR 0xC32C
1118 #define RLC_UCODE_DATA 0xC330
1120 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
1121 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
1122 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
1123 #define RLC_MC_CNTL 0xC344
1124 #define RLC_UCODE_CNTL 0xC348
1125 #define RLC_STAT 0xC34C
1126 # define RLC_BUSY_STATUS (1 << 0)
1127 # define GFX_POWER_STATUS (1 << 1)
1128 # define GFX_CLOCK_STATUS (1 << 2)
1129 # define GFX_LS_STATUS (1 << 3)
1131 #define RLC_PG_CNTL 0xC35C
1132 # define GFX_PG_ENABLE (1 << 0)
1133 # define GFX_PG_SRC (1 << 1)
1135 #define RLC_CGTT_MGCG_OVERRIDE 0xC400
1136 #define RLC_CGCG_CGLS_CTRL 0xC404
1137 # define CGCG_EN (1 << 0)
1138 # define CGLS_EN (1 << 1)
1140 #define RLC_TTOP_D 0xC414
1141 # define RLC_PUD(x) ((x) << 0)
1142 # define RLC_PUD_MASK (0xff << 0)
1143 # define RLC_PDD(x) ((x) << 8)
1144 # define RLC_PDD_MASK (0xff << 8)
1145 # define RLC_TTPD(x) ((x) << 16)
1146 # define RLC_TTPD_MASK (0xff << 16)
1147 # define RLC_MSD(x) ((x) << 24)
1148 # define RLC_MSD_MASK (0xff << 24)
1150 #define RLC_LB_INIT_CU_MASK 0xC41C
1152 #define RLC_PG_AO_CU_MASK 0xC42C
1153 #define RLC_MAX_PG_CU 0xC430
1154 # define MAX_PU_CU(x) ((x) << 0)
1155 # define MAX_PU_CU_MASK (0xff << 0)
1156 #define RLC_AUTO_PG_CTRL 0xC434
1157 # define AUTO_PG_EN (1 << 0)
1158 # define GRBM_REG_SGIT(x) ((x) << 3)
1159 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1160 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
1161 # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
1163 #define RLC_SERDES_WR_MASTER_MASK_0 0xC454
1164 #define RLC_SERDES_WR_MASTER_MASK_1 0xC458
1165 #define RLC_SERDES_WR_CTRL 0xC45C
1167 #define RLC_SERDES_MASTER_BUSY_0 0xC464
1168 #define RLC_SERDES_MASTER_BUSY_1 0xC468
1170 #define RLC_GCPM_GENERAL_3 0xC478
1172 #define DB_RENDER_CONTROL 0x28000
1174 #define DB_DEPTH_INFO 0x2803c
1176 #define PA_SC_RASTER_CONFIG 0x28350
1177 # define RASTER_CONFIG_RB_MAP_0 0
1178 # define RASTER_CONFIG_RB_MAP_1 1
1179 # define RASTER_CONFIG_RB_MAP_2 2
1180 # define RASTER_CONFIG_RB_MAP_3 3
1182 #define VGT_EVENT_INITIATOR 0x28a90
1183 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1184 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1185 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1186 # define CACHE_FLUSH_TS (4 << 0)
1187 # define CACHE_FLUSH (6 << 0)
1188 # define CS_PARTIAL_FLUSH (7 << 0)
1189 # define VGT_STREAMOUT_RESET (10 << 0)
1190 # define END_OF_PIPE_INCR_DE (11 << 0)
1191 # define END_OF_PIPE_IB_END (12 << 0)
1192 # define RST_PIX_CNT (13 << 0)
1193 # define VS_PARTIAL_FLUSH (15 << 0)
1194 # define PS_PARTIAL_FLUSH (16 << 0)
1195 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1196 # define ZPASS_DONE (21 << 0)
1197 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1198 # define PERFCOUNTER_START (23 << 0)
1199 # define PERFCOUNTER_STOP (24 << 0)
1200 # define PIPELINESTAT_START (25 << 0)
1201 # define PIPELINESTAT_STOP (26 << 0)
1202 # define PERFCOUNTER_SAMPLE (27 << 0)
1203 # define SAMPLE_PIPELINESTAT (30 << 0)
1204 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1205 # define RESET_VTX_CNT (33 << 0)
1206 # define VGT_FLUSH (36 << 0)
1207 # define BOTTOM_OF_PIPE_TS (40 << 0)
1208 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1209 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1210 # define FLUSH_AND_INV_DB_META (44 << 0)
1211 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1212 # define FLUSH_AND_INV_CB_META (46 << 0)
1213 # define CS_DONE (47 << 0)
1214 # define PS_DONE (48 << 0)
1215 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1216 # define THREAD_TRACE_START (51 << 0)
1217 # define THREAD_TRACE_STOP (52 << 0)
1218 # define THREAD_TRACE_FLUSH (54 << 0)
1219 # define THREAD_TRACE_FINISH (55 << 0)
1221 /* PIF PHY0 registers idx/data 0x8/0xc */
1222 #define PB0_PIF_CNTL 0x10
1223 # define LS2_EXIT_TIME(x) ((x) << 17)
1224 # define LS2_EXIT_TIME_MASK (0x7 << 17)
1225 # define LS2_EXIT_TIME_SHIFT 17
1226 #define PB0_PIF_PAIRING 0x11
1227 # define MULTI_PIF (1 << 25)
1228 #define PB0_PIF_PWRDOWN_0 0x12
1229 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1230 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1231 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1232 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1233 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1234 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1235 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1236 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1237 # define PLL_RAMP_UP_TIME_0_SHIFT 24
1238 #define PB0_PIF_PWRDOWN_1 0x13
1239 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1240 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1241 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1242 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1243 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1244 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1245 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1246 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1247 # define PLL_RAMP_UP_TIME_1_SHIFT 24
1249 #define PB0_PIF_PWRDOWN_2 0x17
1250 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
1251 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1252 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
1253 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
1254 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1255 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
1256 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
1257 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1258 # define PLL_RAMP_UP_TIME_2_SHIFT 24
1259 #define PB0_PIF_PWRDOWN_3 0x18
1260 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
1261 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1262 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
1263 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
1264 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1265 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
1266 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
1267 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1268 # define PLL_RAMP_UP_TIME_3_SHIFT 24
1269 /* PIF PHY1 registers idx/data 0x10/0x14 */
1270 #define PB1_PIF_CNTL 0x10
1271 #define PB1_PIF_PAIRING 0x11
1272 #define PB1_PIF_PWRDOWN_0 0x12
1273 #define PB1_PIF_PWRDOWN_1 0x13
1275 #define PB1_PIF_PWRDOWN_2 0x17
1276 #define PB1_PIF_PWRDOWN_3 0x18
1277 /* PCIE registers idx/data 0x30/0x34 */
1278 #define PCIE_CNTL2 0x1c /* PCIE */
1279 # define SLV_MEM_LS_EN (1 << 16)
1280 # define MST_MEM_LS_EN (1 << 18)
1281 # define REPLAY_MEM_LS_EN (1 << 19)
1282 #define PCIE_LC_STATUS1 0x28 /* PCIE */
1283 # define LC_REVERSE_RCVR (1 << 0)
1284 # define LC_REVERSE_XMIT (1 << 1)
1285 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1286 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
1287 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1288 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
1290 #define PCIE_P_CNTL 0x40 /* PCIE */
1291 # define P_IGNORE_EDB_ERR (1 << 6)
1293 /* PCIE PORT registers idx/data 0x38/0x3c */
1294 #define PCIE_LC_CNTL 0xa0
1295 # define LC_L0S_INACTIVITY(x) ((x) << 8)
1296 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
1297 # define LC_L0S_INACTIVITY_SHIFT 8
1298 # define LC_L1_INACTIVITY(x) ((x) << 12)
1299 # define LC_L1_INACTIVITY_MASK (0xf << 12)
1300 # define LC_L1_INACTIVITY_SHIFT 12
1301 # define LC_PMI_TO_L1_DIS (1 << 16)
1302 # define LC_ASPM_TO_L1_DIS (1 << 24)
1303 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1304 # define LC_LINK_WIDTH_SHIFT 0
1305 # define LC_LINK_WIDTH_MASK 0x7
1306 # define LC_LINK_WIDTH_X0 0
1307 # define LC_LINK_WIDTH_X1 1
1308 # define LC_LINK_WIDTH_X2 2
1309 # define LC_LINK_WIDTH_X4 3
1310 # define LC_LINK_WIDTH_X8 4
1311 # define LC_LINK_WIDTH_X16 6
1312 # define LC_LINK_WIDTH_RD_SHIFT 4
1313 # define LC_LINK_WIDTH_RD_MASK 0x70
1314 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1315 # define LC_RECONFIG_NOW (1 << 8)
1316 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1317 # define LC_RENEGOTIATE_EN (1 << 10)
1318 # define LC_SHORT_RECONFIG_EN (1 << 11)
1319 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1320 # define LC_UPCONFIGURE_DIS (1 << 13)
1321 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1322 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1323 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
1324 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1325 # define LC_XMIT_N_FTS(x) ((x) << 0)
1326 # define LC_XMIT_N_FTS_MASK (0xff << 0)
1327 # define LC_XMIT_N_FTS_SHIFT 0
1328 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1329 # define LC_N_FTS_MASK (0xff << 24)
1330 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1331 # define LC_GEN2_EN_STRAP (1 << 0)
1332 # define LC_GEN3_EN_STRAP (1 << 1)
1333 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1334 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1335 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
1336 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1337 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1338 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1339 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1340 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1341 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1342 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
1343 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1344 # define LC_CURRENT_DATA_RATE_SHIFT 13
1345 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1346 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1347 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1348 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1349 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1351 #define PCIE_LC_CNTL2 0xb1
1352 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1353 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1355 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1356 # define LC_GO_TO_RECOVERY (1 << 30)
1357 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1358 # define LC_REDO_EQ (1 << 5)
1359 # define LC_SET_QUIESCE (1 << 13)
1364 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1365 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1366 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1367 #define UVD_RBC_RB_RPTR 0xF690
1368 #define UVD_RBC_RB_WPTR 0xF694
1370 #define UVD_CGC_CTRL 0xF4B0
1371 # define DCM (1 << 0)
1372 # define CG_DT(x) ((x) << 2)
1373 # define CG_DT_MASK (0xf << 2)
1374 # define CLK_OD(x) ((x) << 6)
1375 # define CLK_OD_MASK (0x1f << 6)
1377 /* UVD CTX indirect */
1378 #define UVD_CGC_MEM_CTRL 0xC0
1379 #define UVD_CGC_CTRL2 0xC1
1380 # define DYN_OR_EN (1 << 0)
1381 # define DYN_RR_EN (1 << 1)
1382 # define G_DIV_ID(x) ((x) << 2)
1383 # define G_DIV_ID_MASK (0x7 << 2)
1388 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1389 (((reg) >> 2) & 0xFFFF) | \
1390 ((n) & 0x3FFF) << 16)
1391 #define CP_PACKET2 0x80000000
1392 #define PACKET2_PAD_SHIFT 0
1393 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1395 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1397 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1398 (((op) & 0xFF) << 8) | \
1399 ((n) & 0x3FFF) << 16)
1401 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1403 /* Packet 3 types */
1404 #define PACKET3_NOP 0x10
1405 #define PACKET3_SET_BASE 0x11
1406 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1407 #define GDS_PARTITION_BASE 2
1408 #define CE_PARTITION_BASE 3
1409 #define PACKET3_CLEAR_STATE 0x12
1410 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1411 #define PACKET3_DISPATCH_DIRECT 0x15
1412 #define PACKET3_DISPATCH_INDIRECT 0x16
1413 #define PACKET3_ALLOC_GDS 0x1B
1414 #define PACKET3_WRITE_GDS_RAM 0x1C
1415 #define PACKET3_ATOMIC_GDS 0x1D
1416 #define PACKET3_ATOMIC 0x1E
1417 #define PACKET3_OCCLUSION_QUERY 0x1F
1418 #define PACKET3_SET_PREDICATION 0x20
1419 #define PACKET3_REG_RMW 0x21
1420 #define PACKET3_COND_EXEC 0x22
1421 #define PACKET3_PRED_EXEC 0x23
1422 #define PACKET3_DRAW_INDIRECT 0x24
1423 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1424 #define PACKET3_INDEX_BASE 0x26
1425 #define PACKET3_DRAW_INDEX_2 0x27
1426 #define PACKET3_CONTEXT_CONTROL 0x28
1427 #define PACKET3_INDEX_TYPE 0x2A
1428 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1429 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1430 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1431 #define PACKET3_NUM_INSTANCES 0x2F
1432 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1433 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
1434 #define PACKET3_INDIRECT_BUFFER 0x32
1435 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1436 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1437 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1438 #define PACKET3_WRITE_DATA 0x37
1439 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1441 * 1 - memory (sync - via GRBM)
1445 * 5 - memory (async - direct)
1447 #define WR_ONE_ADDR (1 << 16)
1448 #define WR_CONFIRM (1 << 20)
1449 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1454 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1455 #define PACKET3_MEM_SEMAPHORE 0x39
1456 #define PACKET3_MPEG_INDEX 0x3A
1457 #define PACKET3_COPY_DW 0x3B
1458 #define PACKET3_WAIT_REG_MEM 0x3C
1459 #define PACKET3_MEM_WRITE 0x3D
1460 #define PACKET3_COPY_DATA 0x40
1461 #define PACKET3_CP_DMA 0x41
1463 * 2. SRC_ADDR_LO or DATA [31:0]
1464 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1466 * 4. DST_ADDR_LO [31:0]
1467 * 5. DST_ADDR_HI [7:0]
1468 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1470 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1474 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1478 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1483 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1485 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1486 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1492 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1498 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1502 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1506 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1507 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1508 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1509 #define PACKET3_PFP_SYNC_ME 0x42
1510 #define PACKET3_SURFACE_SYNC 0x43
1511 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1512 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1513 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1514 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1515 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1516 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1517 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1518 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1519 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1520 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1521 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1522 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1523 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1524 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1525 # define PACKET3_TC_ACTION_ENA (1 << 23)
1526 # define PACKET3_CB_ACTION_ENA (1 << 25)
1527 # define PACKET3_DB_ACTION_ENA (1 << 26)
1528 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1529 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1530 #define PACKET3_ME_INITIALIZE 0x44
1531 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1532 #define PACKET3_COND_WRITE 0x45
1533 #define PACKET3_EVENT_WRITE 0x46
1534 #define EVENT_TYPE(x) ((x) << 0)
1535 #define EVENT_INDEX(x) ((x) << 8)
1536 /* 0 - any non-TS event
1538 * 2 - SAMPLE_PIPELINESTAT
1539 * 3 - SAMPLE_STREAMOUTSTAT*
1540 * 4 - *S_PARTIAL_FLUSH
1543 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1545 #define INV_L2 (1 << 20)
1546 /* INV TC L2 cache when EVENT_INDEX = 7 */
1547 #define PACKET3_EVENT_WRITE_EOP 0x47
1548 #define DATA_SEL(x) ((x) << 29)
1550 * 1 - send low 32bit data
1551 * 2 - send 64bit data
1552 * 3 - send 64bit counter value
1554 #define INT_SEL(x) ((x) << 24)
1556 * 1 - interrupt only (DATA_SEL = 0)
1557 * 2 - interrupt when data write is confirmed
1559 #define PACKET3_EVENT_WRITE_EOS 0x48
1560 #define PACKET3_PREAMBLE_CNTL 0x4A
1561 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1562 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1563 #define PACKET3_ONE_REG_WRITE 0x57
1564 #define PACKET3_LOAD_CONFIG_REG 0x5F
1565 #define PACKET3_LOAD_CONTEXT_REG 0x60
1566 #define PACKET3_LOAD_SH_REG 0x61
1567 #define PACKET3_SET_CONFIG_REG 0x68
1568 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1569 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1570 #define PACKET3_SET_CONTEXT_REG 0x69
1571 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1572 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1573 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1574 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1575 #define PACKET3_SET_SH_REG 0x76
1576 #define PACKET3_SET_SH_REG_START 0x0000b000
1577 #define PACKET3_SET_SH_REG_END 0x0000c000
1578 #define PACKET3_SET_SH_REG_OFFSET 0x77
1579 #define PACKET3_ME_WRITE 0x7A
1580 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1581 #define PACKET3_SCRATCH_RAM_READ 0x7E
1582 #define PACKET3_CE_WRITE 0x7F
1583 #define PACKET3_LOAD_CONST_RAM 0x80
1584 #define PACKET3_WRITE_CONST_RAM 0x81
1585 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1586 #define PACKET3_DUMP_CONST_RAM 0x83
1587 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1588 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1589 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1590 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1591 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1592 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1593 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1594 #define PACKET3_SWITCH_BUFFER 0x8B
1596 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1597 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1598 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1600 #define DMA_RB_CNTL 0xd000
1601 # define DMA_RB_ENABLE (1 << 0)
1602 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1603 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1604 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1605 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1606 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1607 #define DMA_RB_BASE 0xd004
1608 #define DMA_RB_RPTR 0xd008
1609 #define DMA_RB_WPTR 0xd00c
1611 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1612 #define DMA_RB_RPTR_ADDR_LO 0xd020
1614 #define DMA_IB_CNTL 0xd024
1615 # define DMA_IB_ENABLE (1 << 0)
1616 # define DMA_IB_SWAP_ENABLE (1 << 4)
1617 #define DMA_IB_RPTR 0xd028
1618 #define DMA_CNTL 0xd02c
1619 # define TRAP_ENABLE (1 << 0)
1620 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1621 # define SEM_WAIT_INT_ENABLE (1 << 2)
1622 # define DATA_SWAP_ENABLE (1 << 3)
1623 # define FENCE_SWAP_ENABLE (1 << 4)
1624 # define CTXEMPTY_INT_ENABLE (1 << 28)
1625 #define DMA_STATUS_REG 0xd034
1626 # define DMA_IDLE (1 << 0)
1627 #define DMA_TILING_CONFIG 0xd0b8
1629 #define DMA_PG 0xd0d4
1630 # define PG_CNTL_ENABLE (1 << 0)
1631 #define DMA_PGFSM_CONFIG 0xd0d8
1632 #define DMA_PGFSM_WRITE 0xd0dc
1634 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1635 (((b) & 0x1) << 26) | \
1636 (((t) & 0x1) << 23) | \
1637 (((s) & 0x1) << 22) | \
1638 (((n) & 0xFFFFF) << 0))
1640 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1641 (((vmid) & 0xF) << 20) | \
1642 (((n) & 0xFFFFF) << 0))
1644 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1647 (((n) & 0xFFFFF) << 0))
1649 /* async DMA Packet types */
1650 #define DMA_PACKET_WRITE 0x2
1651 #define DMA_PACKET_COPY 0x3
1652 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1653 #define DMA_PACKET_SEMAPHORE 0x5
1654 #define DMA_PACKET_FENCE 0x6
1655 #define DMA_PACKET_TRAP 0x7
1656 #define DMA_PACKET_SRBM_WRITE 0x9
1657 #define DMA_PACKET_CONSTANT_FILL 0xd
1658 #define DMA_PACKET_NOP 0xf
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