drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_pch_pll *pll,
 915                            struct intel_crtc *crtc,
 916                            bool state)
 917 {
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_LPT(dev_priv->dev)) {
 922                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 923                 return;
 924         }
 925
 926         if (WARN (!pll,
 927                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 928                 return;
 929
 930         val = I915_READ(pll->pll_reg);
 931         cur_state = !!(val & DPLL_VCO_ENABLE);
 932         WARN(cur_state != state,
 933              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 934              pll->pll_reg, state_string(state), state_string(cur_state), val);
 935
 936         /* Make sure the selected PLL is correctly attached to the transcoder */
 937         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 938                 u32 pch_dpll;
 939
 940                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 941                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 942                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 943                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 944                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 945                         cur_state = !!(val >> (4*crtc->pipe + 3));
 946                         WARN(cur_state != state,
 947                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 948                              pll->pll_reg == _PCH_DPLL_B,
 949                              state_string(state),
 950                              pipe_name(crtc->pipe),
 951                              val);
 952                 }
 953         }
 954 }
 955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 957
 958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 959                           enum pipe pipe, bool state)
 960 {
 961         int reg;
 962         u32 val;
 963         bool cur_state;
 964         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 965                                                                       pipe);
 966
 967         if (HAS_DDI(dev_priv->dev)) {
 968                 /* DDI does not have a specific FDI_TX register */
 969                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 970                 val = I915_READ(reg);
 971                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 972         } else {
 973                 reg = FDI_TX_CTL(pipe);
 974                 val = I915_READ(reg);
 975                 cur_state = !!(val & FDI_TX_ENABLE);
 976         }
 977         WARN(cur_state != state,
 978              "FDI TX state assertion failure (expected %s, current %s)\n",
 979              state_string(state), state_string(cur_state));
 980 }
 981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 983
 984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990
 991         reg = FDI_RX_CTL(pipe);
 992         val = I915_READ(reg);
 993         cur_state = !!(val & FDI_RX_ENABLE);
 994         WARN(cur_state != state,
 995              "FDI RX state assertion failure (expected %s, current %s)\n",
 996              state_string(state), state_string(cur_state));
 997 }
 998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         /* ILK FDI PLL is always enabled */
1008         if (dev_priv->info->gen == 5)
1009                 return;
1010
1011         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012         if (HAS_DDI(dev_priv->dev))
1013                 return;
1014
1015         reg = FDI_TX_CTL(pipe);
1016         val = I915_READ(reg);
1017         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         reg = FDI_RX_CTL(pipe);
1027         val = I915_READ(reg);
1028         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032                                   enum pipe pipe)
1033 {
1034         int pp_reg, lvds_reg;
1035         u32 val;
1036         enum pipe panel_pipe = PIPE_A;
1037         bool locked = true;
1038
1039         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040                 pp_reg = PCH_PP_CONTROL;
1041                 lvds_reg = PCH_LVDS;
1042         } else {
1043                 pp_reg = PP_CONTROL;
1044                 lvds_reg = LVDS;
1045         }
1046
1047         val = I915_READ(pp_reg);
1048         if (!(val & PANEL_POWER_ON) ||
1049             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050                 locked = false;
1051
1052         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053                 panel_pipe = PIPE_B;
1054
1055         WARN(panel_pipe == pipe && locked,
1056              "panel assertion failure, pipe %c regs locked\n",
1057              pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061                  enum pipe pipe, bool state)
1062 {
1063         int reg;
1064         u32 val;
1065         bool cur_state;
1066         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067                                                                       pipe);
1068
1069         /* if we need the pipe A quirk it must be always on */
1070         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071                 state = true;
1072
1073         if (!intel_display_power_enabled(dev_priv->dev,
1074                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075                 cur_state = false;
1076         } else {
1077                 reg = PIPECONF(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & PIPECONF_ENABLE);
1080         }
1081
1082         WARN(cur_state != state,
1083              "pipe %c assertion failure (expected %s, current %s)\n",
1084              pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088                          enum plane plane, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = DSPCNTR(plane);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097         WARN(cur_state != state,
1098              "plane %c assertion failure (expected %s, current %s)\n",
1099              plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106                                    enum pipe pipe)
1107 {
1108         struct drm_device *dev = dev_priv->dev;
1109         int reg, i;
1110         u32 val;
1111         int cur_pipe;
1112
1113         /* Primary planes are fixed to pipes on gen4+ */
1114         if (INTEL_INFO(dev)->gen >= 4) {
1115                 reg = DSPCNTR(pipe);
1116                 val = I915_READ(reg);
1117                 WARN((val & DISPLAY_PLANE_ENABLE),
1118                      "plane %c assertion failure, should be disabled but not\n",
1119                      plane_name(pipe));
1120                 return;
1121         }
1122
1123         /* Need to check both planes against the pipe */
1124         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1125                 reg = DSPCNTR(i);
1126                 val = I915_READ(reg);
1127                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128                         DISPPLANE_SEL_PIPE_SHIFT;
1129                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1130                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131                      plane_name(i), pipe_name(pipe));
1132         }
1133 }
1134
1135 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136                                     enum pipe pipe)
1137 {
1138         struct drm_device *dev = dev_priv->dev;
1139         int reg, i;
1140         u32 val;
1141
1142         if (IS_VALLEYVIEW(dev)) {
1143                 for (i = 0; i < dev_priv->num_plane; i++) {
1144                         reg = SPCNTR(pipe, i);
1145                         val = I915_READ(reg);
1146                         WARN((val & SP_ENABLE),
1147                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148                              sprite_name(pipe, i), pipe_name(pipe));
1149                 }
1150         } else if (INTEL_INFO(dev)->gen >= 7) {
1151                 reg = SPRCTL(pipe);
1152                 val = I915_READ(reg);
1153                 WARN((val & SPRITE_ENABLE),
1154                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155                      plane_name(pipe), pipe_name(pipe));
1156         } else if (INTEL_INFO(dev)->gen >= 5) {
1157                 reg = DVSCNTR(pipe);
1158                 val = I915_READ(reg);
1159                 WARN((val & DVS_ENABLE),
1160                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1161                      plane_name(pipe), pipe_name(pipe));
1162         }
1163 }
1164
1165 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166 {
1167         u32 val;
1168         bool enabled;
1169
1170         if (HAS_PCH_LPT(dev_priv->dev)) {
1171                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172                 return;
1173         }
1174
1175         val = I915_READ(PCH_DREF_CONTROL);
1176         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177                             DREF_SUPERSPREAD_SOURCE_MASK));
1178         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182                                            enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186         bool enabled;
1187
1188         reg = PCH_TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         enabled = !!(val & TRANS_ENABLE);
1191         WARN(enabled,
1192              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193              pipe_name(pipe));
1194 }
1195
1196 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197                             enum pipe pipe, u32 port_sel, u32 val)
1198 {
1199         if ((val & DP_PORT_EN) == 0)
1200                 return false;
1201
1202         if (HAS_PCH_CPT(dev_priv->dev)) {
1203                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206                         return false;
1207         } else {
1208                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209                         return false;
1210         }
1211         return true;
1212 }
1213
1214 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215                               enum pipe pipe, u32 val)
1216 {
1217         if ((val & SDVO_ENABLE) == 0)
1218                 return false;
1219
1220         if (HAS_PCH_CPT(dev_priv->dev)) {
1221                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1222                         return false;
1223         } else {
1224                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1225                         return false;
1226         }
1227         return true;
1228 }
1229
1230 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231                               enum pipe pipe, u32 val)
1232 {
1233         if ((val & LVDS_PORT_EN) == 0)
1234                 return false;
1235
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247                               enum pipe pipe, u32 val)
1248 {
1249         if ((val & ADPA_DAC_ENABLE) == 0)
1250                 return false;
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253                         return false;
1254         } else {
1255                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256                         return false;
1257         }
1258         return true;
1259 }
1260
1261 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1262                                    enum pipe pipe, int reg, u32 port_sel)
1263 {
1264         u32 val = I915_READ(reg);
1265         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1266              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1267              reg, pipe_name(pipe));
1268
1269         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270              && (val & DP_PIPEB_SELECT),
1271              "IBX PCH dp port still using transcoder B\n");
1272 }
1273
1274 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275                                      enum pipe pipe, int reg)
1276 {
1277         u32 val = I915_READ(reg);
1278         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1279              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1280              reg, pipe_name(pipe));
1281
1282         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1283              && (val & SDVO_PIPE_B_SELECT),
1284              "IBX PCH hdmi port still using transcoder B\n");
1285 }
1286
1287 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288                                       enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1296
1297         reg = PCH_ADPA;
1298         val = I915_READ(reg);
1299         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1300              "PCH VGA enabled on transcoder %c, should be disabled\n",
1301              pipe_name(pipe));
1302
1303         reg = PCH_LVDS;
1304         val = I915_READ(reg);
1305         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1306              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1307              pipe_name(pipe));
1308
1309         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1312 }
1313
1314 /**
1315  * intel_enable_pll - enable a PLL
1316  * @dev_priv: i915 private structure
1317  * @pipe: pipe PLL to enable
1318  *
1319  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1320  * make sure the PLL reg is writable first though, since the panel write
1321  * protect mechanism may be enabled.
1322  *
1323  * Note!  This is for pre-ILK only.
1324  *
1325  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1326  */
1327 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328 {
1329         int reg;
1330         u32 val;
1331
1332         assert_pipe_disabled(dev_priv, pipe);
1333
1334         /* No really, not for ILK+ */
1335         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1336
1337         /* PLL is protected by panel, make sure we can write it */
1338         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339                 assert_panel_unlocked(dev_priv, pipe);
1340
1341         reg = DPLL(pipe);
1342         val = I915_READ(reg);
1343         val |= DPLL_VCO_ENABLE;
1344
1345         /* We do this three times for luck */
1346         I915_WRITE(reg, val);
1347         POSTING_READ(reg);
1348         udelay(150); /* wait for warmup */
1349         I915_WRITE(reg, val);
1350         POSTING_READ(reg);
1351         udelay(150); /* wait for warmup */
1352         I915_WRITE(reg, val);
1353         POSTING_READ(reg);
1354         udelay(150); /* wait for warmup */
1355 }
1356
1357 /**
1358  * intel_disable_pll - disable a PLL
1359  * @dev_priv: i915 private structure
1360  * @pipe: pipe PLL to disable
1361  *
1362  * Disable the PLL for @pipe, making sure the pipe is off first.
1363  *
1364  * Note!  This is for pre-ILK only.
1365  */
1366 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367 {
1368         int reg;
1369         u32 val;
1370
1371         /* Don't disable pipe A or pipe A PLLs if needed */
1372         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373                 return;
1374
1375         /* Make sure the pipe isn't still relying on us */
1376         assert_pipe_disabled(dev_priv, pipe);
1377
1378         reg = DPLL(pipe);
1379         val = I915_READ(reg);
1380         val &= ~DPLL_VCO_ENABLE;
1381         I915_WRITE(reg, val);
1382         POSTING_READ(reg);
1383 }
1384
1385 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386 {
1387         u32 port_mask;
1388
1389         if (!port)
1390                 port_mask = DPLL_PORTB_READY_MASK;
1391         else
1392                 port_mask = DPLL_PORTC_READY_MASK;
1393
1394         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396                      'B' + port, I915_READ(DPLL(0)));
1397 }
1398
1399 /**
1400  * ironlake_enable_pch_pll - enable PCH PLL
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe PLL to enable
1403  *
1404  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405  * drives the transcoder clock.
1406  */
1407 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1408 {
1409         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1410         struct intel_pch_pll *pll;
1411         int reg;
1412         u32 val;
1413
1414         /* PCH PLLs only available on ILK, SNB and IVB */
1415         BUG_ON(dev_priv->info->gen < 5);
1416         pll = intel_crtc->pch_pll;
1417         if (pll == NULL)
1418                 return;
1419
1420         if (WARN_ON(pll->refcount == 0))
1421                 return;
1422
1423         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424                       pll->pll_reg, pll->active, pll->on,
1425                       intel_crtc->base.base.id);
1426
1427         /* PCH refclock must be enabled first */
1428         assert_pch_refclk_enabled(dev_priv);
1429
1430         if (pll->active++) {
1431                 WARN_ON(!pll->on);
1432                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1433                 return;
1434         }
1435         WARN_ON(pll->on);
1436
1437         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1438
1439         reg = pll->pll_reg;
1440         val = I915_READ(reg);
1441         val |= DPLL_VCO_ENABLE;
1442         I915_WRITE(reg, val);
1443         POSTING_READ(reg);
1444         udelay(200);
1445
1446         pll->on = true;
1447 }
1448
1449 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1450 {
1451         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1452         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1453         int reg;
1454         u32 val;
1455
1456         /* PCH only available on ILK+ */
1457         BUG_ON(dev_priv->info->gen < 5);
1458         if (pll == NULL)
1459                return;
1460
1461         if (WARN_ON(pll->refcount == 0))
1462                 return;
1463
1464         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1465                       pll->pll_reg, pll->active, pll->on,
1466                       intel_crtc->base.base.id);
1467
1468         if (WARN_ON(pll->active == 0)) {
1469                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1470                 return;
1471         }
1472
1473         assert_pch_pll_enabled(dev_priv, pll, NULL);
1474         WARN_ON(!pll->on);
1475         if (--pll->active)
1476                 return;
1477
1478         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1479
1480         /* Make sure transcoder isn't still depending on us */
1481         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1482
1483         reg = pll->pll_reg;
1484         val = I915_READ(reg);
1485         val &= ~DPLL_VCO_ENABLE;
1486         I915_WRITE(reg, val);
1487         POSTING_READ(reg);
1488         udelay(200);
1489
1490         pll->on = false;
1491 }
1492
1493 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1494                                            enum pipe pipe)
1495 {
1496         struct drm_device *dev = dev_priv->dev;
1497         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1498         uint32_t reg, val, pipeconf_val;
1499
1500         /* PCH only available on ILK+ */
1501         BUG_ON(dev_priv->info->gen < 5);
1502
1503         /* Make sure PCH DPLL is enabled */
1504         assert_pch_pll_enabled(dev_priv,
1505                                to_intel_crtc(crtc)->pch_pll,
1506                                to_intel_crtc(crtc));
1507
1508         /* FDI must be feeding us bits for PCH ports */
1509         assert_fdi_tx_enabled(dev_priv, pipe);
1510         assert_fdi_rx_enabled(dev_priv, pipe);
1511
1512         if (HAS_PCH_CPT(dev)) {
1513                 /* Workaround: Set the timing override bit before enabling the
1514                  * pch transcoder. */
1515                 reg = TRANS_CHICKEN2(pipe);
1516                 val = I915_READ(reg);
1517                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1518                 I915_WRITE(reg, val);
1519         }
1520
1521         reg = PCH_TRANSCONF(pipe);
1522         val = I915_READ(reg);
1523         pipeconf_val = I915_READ(PIPECONF(pipe));
1524
1525         if (HAS_PCH_IBX(dev_priv->dev)) {
1526                 /*
1527                  * make the BPC in transcoder be consistent with
1528                  * that in pipeconf reg.
1529                  */
1530                 val &= ~PIPECONF_BPC_MASK;
1531                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1532         }
1533
1534         val &= ~TRANS_INTERLACE_MASK;
1535         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1536                 if (HAS_PCH_IBX(dev_priv->dev) &&
1537                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1538                         val |= TRANS_LEGACY_INTERLACED_ILK;
1539                 else
1540                         val |= TRANS_INTERLACED;
1541         else
1542                 val |= TRANS_PROGRESSIVE;
1543
1544         I915_WRITE(reg, val | TRANS_ENABLE);
1545         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1546                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1547 }
1548
1549 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1550                                       enum transcoder cpu_transcoder)
1551 {
1552         u32 val, pipeconf_val;
1553
1554         /* PCH only available on ILK+ */
1555         BUG_ON(dev_priv->info->gen < 5);
1556
1557         /* FDI must be feeding us bits for PCH ports */
1558         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1559         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1560
1561         /* Workaround: set timing override bit. */
1562         val = I915_READ(_TRANSA_CHICKEN2);
1563         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1564         I915_WRITE(_TRANSA_CHICKEN2, val);
1565
1566         val = TRANS_ENABLE;
1567         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1568
1569         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1570             PIPECONF_INTERLACED_ILK)
1571                 val |= TRANS_INTERLACED;
1572         else
1573                 val |= TRANS_PROGRESSIVE;
1574
1575         I915_WRITE(LPT_TRANSCONF, val);
1576         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1577                 DRM_ERROR("Failed to enable PCH transcoder\n");
1578 }
1579
1580 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                             enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         uint32_t reg, val;
1585
1586         /* FDI relies on the transcoder */
1587         assert_fdi_tx_disabled(dev_priv, pipe);
1588         assert_fdi_rx_disabled(dev_priv, pipe);
1589
1590         /* Ports must be off as well */
1591         assert_pch_ports_disabled(dev_priv, pipe);
1592
1593         reg = PCH_TRANSCONF(pipe);
1594         val = I915_READ(reg);
1595         val &= ~TRANS_ENABLE;
1596         I915_WRITE(reg, val);
1597         /* wait for PCH transcoder off, transcoder state */
1598         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1599                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1600
1601         if (!HAS_PCH_IBX(dev)) {
1602                 /* Workaround: Clear the timing override chicken bit again. */
1603                 reg = TRANS_CHICKEN2(pipe);
1604                 val = I915_READ(reg);
1605                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1606                 I915_WRITE(reg, val);
1607         }
1608 }
1609
1610 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1611 {
1612         u32 val;
1613
1614         val = I915_READ(LPT_TRANSCONF);
1615         val &= ~TRANS_ENABLE;
1616         I915_WRITE(LPT_TRANSCONF, val);
1617         /* wait for PCH transcoder off, transcoder state */
1618         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1619                 DRM_ERROR("Failed to disable PCH transcoder\n");
1620
1621         /* Workaround: clear timing override bit. */
1622         val = I915_READ(_TRANSA_CHICKEN2);
1623         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1624         I915_WRITE(_TRANSA_CHICKEN2, val);
1625 }
1626
1627 /**
1628  * intel_enable_pipe - enable a pipe, asserting requirements
1629  * @dev_priv: i915 private structure
1630  * @pipe: pipe to enable
1631  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1632  *
1633  * Enable @pipe, making sure that various hardware specific requirements
1634  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1635  *
1636  * @pipe should be %PIPE_A or %PIPE_B.
1637  *
1638  * Will wait until the pipe is actually running (i.e. first vblank) before
1639  * returning.
1640  */
1641 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1642                               bool pch_port)
1643 {
1644         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1645                                                                       pipe);
1646         enum pipe pch_transcoder;
1647         int reg;
1648         u32 val;
1649
1650         assert_planes_disabled(dev_priv, pipe);
1651         assert_sprites_disabled(dev_priv, pipe);
1652
1653         if (HAS_PCH_LPT(dev_priv->dev))
1654                 pch_transcoder = TRANSCODER_A;
1655         else
1656                 pch_transcoder = pipe;
1657
1658         /*
1659          * A pipe without a PLL won't actually be able to drive bits from
1660          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1661          * need the check.
1662          */
1663         if (!HAS_PCH_SPLIT(dev_priv->dev))
1664                 assert_pll_enabled(dev_priv, pipe);
1665         else {
1666                 if (pch_port) {
1667                         /* if driving the PCH, we need FDI enabled */
1668                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1669                         assert_fdi_tx_pll_enabled(dev_priv,
1670                                                   (enum pipe) cpu_transcoder);
1671                 }
1672                 /* FIXME: assert CPU port conditions for SNB+ */
1673         }
1674
1675         reg = PIPECONF(cpu_transcoder);
1676         val = I915_READ(reg);
1677         if (val & PIPECONF_ENABLE)
1678                 return;
1679
1680         I915_WRITE(reg, val | PIPECONF_ENABLE);
1681         intel_wait_for_vblank(dev_priv->dev, pipe);
1682 }
1683
1684 /**
1685  * intel_disable_pipe - disable a pipe, asserting requirements
1686  * @dev_priv: i915 private structure
1687  * @pipe: pipe to disable
1688  *
1689  * Disable @pipe, making sure that various hardware specific requirements
1690  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1691  *
1692  * @pipe should be %PIPE_A or %PIPE_B.
1693  *
1694  * Will wait until the pipe has shut down before returning.
1695  */
1696 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1697                                enum pipe pipe)
1698 {
1699         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1700                                                                       pipe);
1701         int reg;
1702         u32 val;
1703
1704         /*
1705          * Make sure planes won't keep trying to pump pixels to us,
1706          * or we might hang the display.
1707          */
1708         assert_planes_disabled(dev_priv, pipe);
1709         assert_sprites_disabled(dev_priv, pipe);
1710
1711         /* Don't disable pipe A or pipe A PLLs if needed */
1712         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1713                 return;
1714
1715         reg = PIPECONF(cpu_transcoder);
1716         val = I915_READ(reg);
1717         if ((val & PIPECONF_ENABLE) == 0)
1718                 return;
1719
1720         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1721         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1722 }
1723
1724 /*
1725  * Plane regs are double buffered, going from enabled->disabled needs a
1726  * trigger in order to latch.  The display address reg provides this.
1727  */
1728 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1729                                       enum plane plane)
1730 {
1731         if (dev_priv->info->gen >= 4)
1732                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1733         else
1734                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1735 }
1736
1737 /**
1738  * intel_enable_plane - enable a display plane on a given pipe
1739  * @dev_priv: i915 private structure
1740  * @plane: plane to enable
1741  * @pipe: pipe being fed
1742  *
1743  * Enable @plane on @pipe, making sure that @pipe is running first.
1744  */
1745 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1746                                enum plane plane, enum pipe pipe)
1747 {
1748         int reg;
1749         u32 val;
1750
1751         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1752         assert_pipe_enabled(dev_priv, pipe);
1753
1754         reg = DSPCNTR(plane);
1755         val = I915_READ(reg);
1756         if (val & DISPLAY_PLANE_ENABLE)
1757                 return;
1758
1759         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1760         intel_flush_display_plane(dev_priv, plane);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_plane - disable a display plane
1766  * @dev_priv: i915 private structure
1767  * @plane: plane to disable
1768  * @pipe: pipe consuming the data
1769  *
1770  * Disable @plane; should be an independent operation.
1771  */
1772 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1773                                 enum plane plane, enum pipe pipe)
1774 {
1775         int reg;
1776         u32 val;
1777
1778         reg = DSPCNTR(plane);
1779         val = I915_READ(reg);
1780         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1781                 return;
1782
1783         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1784         intel_flush_display_plane(dev_priv, plane);
1785         intel_wait_for_vblank(dev_priv->dev, pipe);
1786 }
1787
1788 static bool need_vtd_wa(struct drm_device *dev)
1789 {
1790 #ifdef CONFIG_INTEL_IOMMU
1791         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1792                 return true;
1793 #endif
1794         return false;
1795 }
1796
1797 int
1798 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1799                            struct drm_i915_gem_object *obj,
1800                            struct intel_ring_buffer *pipelined)
1801 {
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803         u32 alignment;
1804         int ret;
1805
1806         switch (obj->tiling_mode) {
1807         case I915_TILING_NONE:
1808                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1809                         alignment = 128 * 1024;
1810                 else if (INTEL_INFO(dev)->gen >= 4)
1811                         alignment = 4 * 1024;
1812                 else
1813                         alignment = 64 * 1024;
1814                 break;
1815         case I915_TILING_X:
1816                 /* pin() will align the object as required by fence */
1817                 alignment = 0;
1818                 break;
1819         case I915_TILING_Y:
1820                 /* Despite that we check this in framebuffer_init userspace can
1821                  * screw us over and change the tiling after the fact. Only
1822                  * pinned buffers can't change their tiling. */
1823                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1824                 return -EINVAL;
1825         default:
1826                 BUG();
1827         }
1828
1829         /* Note that the w/a also requires 64 PTE of padding following the
1830          * bo. We currently fill all unused PTE with the shadow page and so
1831          * we should always have valid PTE following the scanout preventing
1832          * the VT-d warning.
1833          */
1834         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1835                 alignment = 256 * 1024;
1836
1837         dev_priv->mm.interruptible = false;
1838         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1839         if (ret)
1840                 goto err_interruptible;
1841
1842         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1843          * fence, whereas 965+ only requires a fence if using
1844          * framebuffer compression.  For simplicity, we always install
1845          * a fence as the cost is not that onerous.
1846          */
1847         ret = i915_gem_object_get_fence(obj);
1848         if (ret)
1849                 goto err_unpin;
1850
1851         i915_gem_object_pin_fence(obj);
1852
1853         dev_priv->mm.interruptible = true;
1854         return 0;
1855
1856 err_unpin:
1857         i915_gem_object_unpin(obj);
1858 err_interruptible:
1859         dev_priv->mm.interruptible = true;
1860         return ret;
1861 }
1862
1863 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1864 {
1865         i915_gem_object_unpin_fence(obj);
1866         i915_gem_object_unpin(obj);
1867 }
1868
1869 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1870  * is assumed to be a power-of-two. */
1871 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1872                                              unsigned int tiling_mode,
1873                                              unsigned int cpp,
1874                                              unsigned int pitch)
1875 {
1876         if (tiling_mode != I915_TILING_NONE) {
1877                 unsigned int tile_rows, tiles;
1878
1879                 tile_rows = *y / 8;
1880                 *y %= 8;
1881
1882                 tiles = *x / (512/cpp);
1883                 *x %= 512/cpp;
1884
1885                 return tile_rows * pitch * 8 + tiles * 4096;
1886         } else {
1887                 unsigned int offset;
1888
1889                 offset = *y * pitch + *x * cpp;
1890                 *y = 0;
1891                 *x = (offset & 4095) / cpp;
1892                 return offset & -4096;
1893         }
1894 }
1895
1896 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1897                              int x, int y)
1898 {
1899         struct drm_device *dev = crtc->dev;
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1902         struct intel_framebuffer *intel_fb;
1903         struct drm_i915_gem_object *obj;
1904         int plane = intel_crtc->plane;
1905         unsigned long linear_offset;
1906         u32 dspcntr;
1907         u32 reg;
1908
1909         switch (plane) {
1910         case 0:
1911         case 1:
1912                 break;
1913         default:
1914                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1915                 return -EINVAL;
1916         }
1917
1918         intel_fb = to_intel_framebuffer(fb);
1919         obj = intel_fb->obj;
1920
1921         reg = DSPCNTR(plane);
1922         dspcntr = I915_READ(reg);
1923         /* Mask out pixel format bits in case we change it */
1924         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1925         switch (fb->pixel_format) {
1926         case DRM_FORMAT_C8:
1927                 dspcntr |= DISPPLANE_8BPP;
1928                 break;
1929         case DRM_FORMAT_XRGB1555:
1930         case DRM_FORMAT_ARGB1555:
1931                 dspcntr |= DISPPLANE_BGRX555;
1932                 break;
1933         case DRM_FORMAT_RGB565:
1934                 dspcntr |= DISPPLANE_BGRX565;
1935                 break;
1936         case DRM_FORMAT_XRGB8888:
1937         case DRM_FORMAT_ARGB8888:
1938                 dspcntr |= DISPPLANE_BGRX888;
1939                 break;
1940         case DRM_FORMAT_XBGR8888:
1941         case DRM_FORMAT_ABGR8888:
1942                 dspcntr |= DISPPLANE_RGBX888;
1943                 break;
1944         case DRM_FORMAT_XRGB2101010:
1945         case DRM_FORMAT_ARGB2101010:
1946                 dspcntr |= DISPPLANE_BGRX101010;
1947                 break;
1948         case DRM_FORMAT_XBGR2101010:
1949         case DRM_FORMAT_ABGR2101010:
1950                 dspcntr |= DISPPLANE_RGBX101010;
1951                 break;
1952         default:
1953                 BUG();
1954         }
1955
1956         if (INTEL_INFO(dev)->gen >= 4) {
1957                 if (obj->tiling_mode != I915_TILING_NONE)
1958                         dspcntr |= DISPPLANE_TILED;
1959                 else
1960                         dspcntr &= ~DISPPLANE_TILED;
1961         }
1962
1963         if (IS_G4X(dev))
1964                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1965
1966         I915_WRITE(reg, dspcntr);
1967
1968         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1969
1970         if (INTEL_INFO(dev)->gen >= 4) {
1971                 intel_crtc->dspaddr_offset =
1972                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1973                                                        fb->bits_per_pixel / 8,
1974                                                        fb->pitches[0]);
1975                 linear_offset -= intel_crtc->dspaddr_offset;
1976         } else {
1977                 intel_crtc->dspaddr_offset = linear_offset;
1978         }
1979
1980         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1981                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1982         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1983         if (INTEL_INFO(dev)->gen >= 4) {
1984                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1985                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1986                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1987                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1988         } else
1989                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1990         POSTING_READ(reg);
1991
1992         return 0;
1993 }
1994
1995 static int ironlake_update_plane(struct drm_crtc *crtc,
1996                                  struct drm_framebuffer *fb, int x, int y)
1997 {
1998         struct drm_device *dev = crtc->dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2001         struct intel_framebuffer *intel_fb;
2002         struct drm_i915_gem_object *obj;
2003         int plane = intel_crtc->plane;
2004         unsigned long linear_offset;
2005         u32 dspcntr;
2006         u32 reg;
2007
2008         switch (plane) {
2009         case 0:
2010         case 1:
2011         case 2:
2012                 break;
2013         default:
2014                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2015                 return -EINVAL;
2016         }
2017
2018         intel_fb = to_intel_framebuffer(fb);
2019         obj = intel_fb->obj;
2020
2021         reg = DSPCNTR(plane);
2022         dspcntr = I915_READ(reg);
2023         /* Mask out pixel format bits in case we change it */
2024         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2025         switch (fb->pixel_format) {
2026         case DRM_FORMAT_C8:
2027                 dspcntr |= DISPPLANE_8BPP;
2028                 break;
2029         case DRM_FORMAT_RGB565:
2030                 dspcntr |= DISPPLANE_BGRX565;
2031                 break;
2032         case DRM_FORMAT_XRGB8888:
2033         case DRM_FORMAT_ARGB8888:
2034                 dspcntr |= DISPPLANE_BGRX888;
2035                 break;
2036         case DRM_FORMAT_XBGR8888:
2037         case DRM_FORMAT_ABGR8888:
2038                 dspcntr |= DISPPLANE_RGBX888;
2039                 break;
2040         case DRM_FORMAT_XRGB2101010:
2041         case DRM_FORMAT_ARGB2101010:
2042                 dspcntr |= DISPPLANE_BGRX101010;
2043                 break;
2044         case DRM_FORMAT_XBGR2101010:
2045         case DRM_FORMAT_ABGR2101010:
2046                 dspcntr |= DISPPLANE_RGBX101010;
2047                 break;
2048         default:
2049                 BUG();
2050         }
2051
2052         if (obj->tiling_mode != I915_TILING_NONE)
2053                 dspcntr |= DISPPLANE_TILED;
2054         else
2055                 dspcntr &= ~DISPPLANE_TILED;
2056
2057         /* must disable */
2058         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2059
2060         I915_WRITE(reg, dspcntr);
2061
2062         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2063         intel_crtc->dspaddr_offset =
2064                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2065                                                fb->bits_per_pixel / 8,
2066                                                fb->pitches[0]);
2067         linear_offset -= intel_crtc->dspaddr_offset;
2068
2069         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2070                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2071         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2072         I915_MODIFY_DISPBASE(DSPSURF(plane),
2073                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2074         if (IS_HASWELL(dev)) {
2075                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2076         } else {
2077                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2078                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2079         }
2080         POSTING_READ(reg);
2081
2082         return 0;
2083 }
2084
2085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2086 static int
2087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2088                            int x, int y, enum mode_set_atomic state)
2089 {
2090         struct drm_device *dev = crtc->dev;
2091         struct drm_i915_private *dev_priv = dev->dev_private;
2092
2093         if (dev_priv->display.disable_fbc)
2094                 dev_priv->display.disable_fbc(dev);
2095         intel_increase_pllclock(crtc);
2096
2097         return dev_priv->display.update_plane(crtc, fb, x, y);
2098 }
2099
2100 void intel_display_handle_reset(struct drm_device *dev)
2101 {
2102         struct drm_i915_private *dev_priv = dev->dev_private;
2103         struct drm_crtc *crtc;
2104
2105         /*
2106          * Flips in the rings have been nuked by the reset,
2107          * so complete all pending flips so that user space
2108          * will get its events and not get stuck.
2109          *
2110          * Also update the base address of all primary
2111          * planes to the the last fb to make sure we're
2112          * showing the correct fb after a reset.
2113          *
2114          * Need to make two loops over the crtcs so that we
2115          * don't try to grab a crtc mutex before the
2116          * pending_flip_queue really got woken up.
2117          */
2118
2119         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2120                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121                 enum plane plane = intel_crtc->plane;
2122
2123                 intel_prepare_page_flip(dev, plane);
2124                 intel_finish_page_flip_plane(dev, plane);
2125         }
2126
2127         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2128                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2129
2130                 mutex_lock(&crtc->mutex);
2131                 if (intel_crtc->active)
2132                         dev_priv->display.update_plane(crtc, crtc->fb,
2133                                                        crtc->x, crtc->y);
2134                 mutex_unlock(&crtc->mutex);
2135         }
2136 }
2137
2138 static int
2139 intel_finish_fb(struct drm_framebuffer *old_fb)
2140 {
2141         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2142         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2143         bool was_interruptible = dev_priv->mm.interruptible;
2144         int ret;
2145
2146         /* Big Hammer, we also need to ensure that any pending
2147          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2148          * current scanout is retired before unpinning the old
2149          * framebuffer.
2150          *
2151          * This should only fail upon a hung GPU, in which case we
2152          * can safely continue.
2153          */
2154         dev_priv->mm.interruptible = false;
2155         ret = i915_gem_object_finish_gpu(obj);
2156         dev_priv->mm.interruptible = was_interruptible;
2157
2158         return ret;
2159 }
2160
2161 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2162 {
2163         struct drm_device *dev = crtc->dev;
2164         struct drm_i915_master_private *master_priv;
2165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2166
2167         if (!dev->primary->master)
2168                 return;
2169
2170         master_priv = dev->primary->master->driver_priv;
2171         if (!master_priv->sarea_priv)
2172                 return;
2173
2174         switch (intel_crtc->pipe) {
2175         case 0:
2176                 master_priv->sarea_priv->pipeA_x = x;
2177                 master_priv->sarea_priv->pipeA_y = y;
2178                 break;
2179         case 1:
2180                 master_priv->sarea_priv->pipeB_x = x;
2181                 master_priv->sarea_priv->pipeB_y = y;
2182                 break;
2183         default:
2184                 break;
2185         }
2186 }
2187
2188 static int
2189 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2190                     struct drm_framebuffer *fb)
2191 {
2192         struct drm_device *dev = crtc->dev;
2193         struct drm_i915_private *dev_priv = dev->dev_private;
2194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2195         struct drm_framebuffer *old_fb;
2196         int ret;
2197
2198         /* no fb bound */
2199         if (!fb) {
2200                 DRM_ERROR("No FB bound\n");
2201                 return 0;
2202         }
2203
2204         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2205                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2206                           plane_name(intel_crtc->plane),
2207                           INTEL_INFO(dev)->num_pipes);
2208                 return -EINVAL;
2209         }
2210
2211         mutex_lock(&dev->struct_mutex);
2212         ret = intel_pin_and_fence_fb_obj(dev,
2213                                          to_intel_framebuffer(fb)->obj,
2214                                          NULL);
2215         if (ret != 0) {
2216                 mutex_unlock(&dev->struct_mutex);
2217                 DRM_ERROR("pin & fence failed\n");
2218                 return ret;
2219         }
2220
2221         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2222         if (ret) {
2223                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2224                 mutex_unlock(&dev->struct_mutex);
2225                 DRM_ERROR("failed to update base address\n");
2226                 return ret;
2227         }
2228
2229         old_fb = crtc->fb;
2230         crtc->fb = fb;
2231         crtc->x = x;
2232         crtc->y = y;
2233
2234         if (old_fb) {
2235                 if (intel_crtc->active && old_fb != fb)
2236                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2237                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2238         }
2239
2240         intel_update_fbc(dev);
2241         mutex_unlock(&dev->struct_mutex);
2242
2243         intel_crtc_update_sarea_pos(crtc, x, y);
2244
2245         return 0;
2246 }
2247
2248 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_private *dev_priv = dev->dev_private;
2252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253         int pipe = intel_crtc->pipe;
2254         u32 reg, temp;
2255
2256         /* enable normal train */
2257         reg = FDI_TX_CTL(pipe);
2258         temp = I915_READ(reg);
2259         if (IS_IVYBRIDGE(dev)) {
2260                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2261                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2262         } else {
2263                 temp &= ~FDI_LINK_TRAIN_NONE;
2264                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2265         }
2266         I915_WRITE(reg, temp);
2267
2268         reg = FDI_RX_CTL(pipe);
2269         temp = I915_READ(reg);
2270         if (HAS_PCH_CPT(dev)) {
2271                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2272                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2273         } else {
2274                 temp &= ~FDI_LINK_TRAIN_NONE;
2275                 temp |= FDI_LINK_TRAIN_NONE;
2276         }
2277         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2278
2279         /* wait one idle pattern time */
2280         POSTING_READ(reg);
2281         udelay(1000);
2282
2283         /* IVB wants error correction enabled */
2284         if (IS_IVYBRIDGE(dev))
2285                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2286                            FDI_FE_ERRC_ENABLE);
2287 }
2288
2289 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2290 {
2291         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2292 }
2293
2294 static void ivb_modeset_global_resources(struct drm_device *dev)
2295 {
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *pipe_B_crtc =
2298                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2299         struct intel_crtc *pipe_C_crtc =
2300                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2301         uint32_t temp;
2302
2303         /*
2304          * When everything is off disable fdi C so that we could enable fdi B
2305          * with all lanes. Note that we don't care about enabled pipes without
2306          * an enabled pch encoder.
2307          */
2308         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2309             !pipe_has_enabled_pch(pipe_C_crtc)) {
2310                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2311                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2312
2313                 temp = I915_READ(SOUTH_CHICKEN1);
2314                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2315                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2316                 I915_WRITE(SOUTH_CHICKEN1, temp);
2317         }
2318 }
2319
2320 /* The FDI link training functions for ILK/Ibexpeak. */
2321 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2322 {
2323         struct drm_device *dev = crtc->dev;
2324         struct drm_i915_private *dev_priv = dev->dev_private;
2325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326         int pipe = intel_crtc->pipe;
2327         int plane = intel_crtc->plane;
2328         u32 reg, temp, tries;
2329
2330         /* FDI needs bits from pipe & plane first */
2331         assert_pipe_enabled(dev_priv, pipe);
2332         assert_plane_enabled(dev_priv, plane);
2333
2334         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2335            for train result */
2336         reg = FDI_RX_IMR(pipe);
2337         temp = I915_READ(reg);
2338         temp &= ~FDI_RX_SYMBOL_LOCK;
2339         temp &= ~FDI_RX_BIT_LOCK;
2340         I915_WRITE(reg, temp);
2341         I915_READ(reg);
2342         udelay(150);
2343
2344         /* enable CPU FDI TX and PCH FDI RX */
2345         reg = FDI_TX_CTL(pipe);
2346         temp = I915_READ(reg);
2347         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2348         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2349         temp &= ~FDI_LINK_TRAIN_NONE;
2350         temp |= FDI_LINK_TRAIN_PATTERN_1;
2351         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         temp &= ~FDI_LINK_TRAIN_NONE;
2356         temp |= FDI_LINK_TRAIN_PATTERN_1;
2357         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2358
2359         POSTING_READ(reg);
2360         udelay(150);
2361
2362         /* Ironlake workaround, enable clock pointer after FDI enable*/
2363         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2364         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2365                    FDI_RX_PHASE_SYNC_POINTER_EN);
2366
2367         reg = FDI_RX_IIR(pipe);
2368         for (tries = 0; tries < 5; tries++) {
2369                 temp = I915_READ(reg);
2370                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2371
2372                 if ((temp & FDI_RX_BIT_LOCK)) {
2373                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2374                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2375                         break;
2376                 }
2377         }
2378         if (tries == 5)
2379                 DRM_ERROR("FDI train 1 fail!\n");
2380
2381         /* Train 2 */
2382         reg = FDI_TX_CTL(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_LINK_TRAIN_NONE;
2385         temp |= FDI_LINK_TRAIN_PATTERN_2;
2386         I915_WRITE(reg, temp);
2387
2388         reg = FDI_RX_CTL(pipe);
2389         temp = I915_READ(reg);
2390         temp &= ~FDI_LINK_TRAIN_NONE;
2391         temp |= FDI_LINK_TRAIN_PATTERN_2;
2392         I915_WRITE(reg, temp);
2393
2394         POSTING_READ(reg);
2395         udelay(150);
2396
2397         reg = FDI_RX_IIR(pipe);
2398         for (tries = 0; tries < 5; tries++) {
2399                 temp = I915_READ(reg);
2400                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2401
2402                 if (temp & FDI_RX_SYMBOL_LOCK) {
2403                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2404                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2405                         break;
2406                 }
2407         }
2408         if (tries == 5)
2409                 DRM_ERROR("FDI train 2 fail!\n");
2410
2411         DRM_DEBUG_KMS("FDI train done\n");
2412
2413 }
2414
2415 static const int snb_b_fdi_train_param[] = {
2416         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2417         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2418         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2419         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2420 };
2421
2422 /* The FDI link training functions for SNB/Cougarpoint. */
2423 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2424 {
2425         struct drm_device *dev = crtc->dev;
2426         struct drm_i915_private *dev_priv = dev->dev_private;
2427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428         int pipe = intel_crtc->pipe;
2429         u32 reg, temp, i, retry;
2430
2431         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432            for train result */
2433         reg = FDI_RX_IMR(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~FDI_RX_SYMBOL_LOCK;
2436         temp &= ~FDI_RX_BIT_LOCK;
2437         I915_WRITE(reg, temp);
2438
2439         POSTING_READ(reg);
2440         udelay(150);
2441
2442         /* enable CPU FDI TX and PCH FDI RX */
2443         reg = FDI_TX_CTL(pipe);
2444         temp = I915_READ(reg);
2445         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2446         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2447         temp &= ~FDI_LINK_TRAIN_NONE;
2448         temp |= FDI_LINK_TRAIN_PATTERN_1;
2449         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450         /* SNB-B */
2451         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2452         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2453
2454         I915_WRITE(FDI_RX_MISC(pipe),
2455                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2456
2457         reg = FDI_RX_CTL(pipe);
2458         temp = I915_READ(reg);
2459         if (HAS_PCH_CPT(dev)) {
2460                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2461                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2462         } else {
2463                 temp &= ~FDI_LINK_TRAIN_NONE;
2464                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2465         }
2466         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467
2468         POSTING_READ(reg);
2469         udelay(150);
2470
2471         for (i = 0; i < 4; i++) {
2472                 reg = FDI_TX_CTL(pipe);
2473                 temp = I915_READ(reg);
2474                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2475                 temp |= snb_b_fdi_train_param[i];
2476                 I915_WRITE(reg, temp);
2477
2478                 POSTING_READ(reg);
2479                 udelay(500);
2480
2481                 for (retry = 0; retry < 5; retry++) {
2482                         reg = FDI_RX_IIR(pipe);
2483                         temp = I915_READ(reg);
2484                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485                         if (temp & FDI_RX_BIT_LOCK) {
2486                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2487                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2488                                 break;
2489                         }
2490                         udelay(50);
2491                 }
2492                 if (retry < 5)
2493                         break;
2494         }
2495         if (i == 4)
2496                 DRM_ERROR("FDI train 1 fail!\n");
2497
2498         /* Train 2 */
2499         reg = FDI_TX_CTL(pipe);
2500         temp = I915_READ(reg);
2501         temp &= ~FDI_LINK_TRAIN_NONE;
2502         temp |= FDI_LINK_TRAIN_PATTERN_2;
2503         if (IS_GEN6(dev)) {
2504                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2505                 /* SNB-B */
2506                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2507         }
2508         I915_WRITE(reg, temp);
2509
2510         reg = FDI_RX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         if (HAS_PCH_CPT(dev)) {
2513                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2514                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2515         } else {
2516                 temp &= ~FDI_LINK_TRAIN_NONE;
2517                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2518         }
2519         I915_WRITE(reg, temp);
2520
2521         POSTING_READ(reg);
2522         udelay(150);
2523
2524         for (i = 0; i < 4; i++) {
2525                 reg = FDI_TX_CTL(pipe);
2526                 temp = I915_READ(reg);
2527                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528                 temp |= snb_b_fdi_train_param[i];
2529                 I915_WRITE(reg, temp);
2530
2531                 POSTING_READ(reg);
2532                 udelay(500);
2533
2534                 for (retry = 0; retry < 5; retry++) {
2535                         reg = FDI_RX_IIR(pipe);
2536                         temp = I915_READ(reg);
2537                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2538                         if (temp & FDI_RX_SYMBOL_LOCK) {
2539                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2540                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541                                 break;
2542                         }
2543                         udelay(50);
2544                 }
2545                 if (retry < 5)
2546                         break;
2547         }
2548         if (i == 4)
2549                 DRM_ERROR("FDI train 2 fail!\n");
2550
2551         DRM_DEBUG_KMS("FDI train done.\n");
2552 }
2553
2554 /* Manual link training for Ivy Bridge A0 parts */
2555 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2556 {
2557         struct drm_device *dev = crtc->dev;
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560         int pipe = intel_crtc->pipe;
2561         u32 reg, temp, i;
2562
2563         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564            for train result */
2565         reg = FDI_RX_IMR(pipe);
2566         temp = I915_READ(reg);
2567         temp &= ~FDI_RX_SYMBOL_LOCK;
2568         temp &= ~FDI_RX_BIT_LOCK;
2569         I915_WRITE(reg, temp);
2570
2571         POSTING_READ(reg);
2572         udelay(150);
2573
2574         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2575                       I915_READ(FDI_RX_IIR(pipe)));
2576
2577         /* enable CPU FDI TX and PCH FDI RX */
2578         reg = FDI_TX_CTL(pipe);
2579         temp = I915_READ(reg);
2580         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2581         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2582         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2583         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2584         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2586         temp |= FDI_COMPOSITE_SYNC;
2587         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2588
2589         I915_WRITE(FDI_RX_MISC(pipe),
2590                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591
2592         reg = FDI_RX_CTL(pipe);
2593         temp = I915_READ(reg);
2594         temp &= ~FDI_LINK_TRAIN_AUTO;
2595         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597         temp |= FDI_COMPOSITE_SYNC;
2598         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600         POSTING_READ(reg);
2601         udelay(150);
2602
2603         for (i = 0; i < 4; i++) {
2604                 reg = FDI_TX_CTL(pipe);
2605                 temp = I915_READ(reg);
2606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607                 temp |= snb_b_fdi_train_param[i];
2608                 I915_WRITE(reg, temp);
2609
2610                 POSTING_READ(reg);
2611                 udelay(500);
2612
2613                 reg = FDI_RX_IIR(pipe);
2614                 temp = I915_READ(reg);
2615                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2616
2617                 if (temp & FDI_RX_BIT_LOCK ||
2618                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2619                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2621                         break;
2622                 }
2623         }
2624         if (i == 4)
2625                 DRM_ERROR("FDI train 1 fail!\n");
2626
2627         /* Train 2 */
2628         reg = FDI_TX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2631         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2632         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2633         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2634         I915_WRITE(reg, temp);
2635
2636         reg = FDI_RX_CTL(pipe);
2637         temp = I915_READ(reg);
2638         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2639         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2640         I915_WRITE(reg, temp);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 reg = FDI_RX_IIR(pipe);
2656                 temp = I915_READ(reg);
2657                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659                 if (temp & FDI_RX_SYMBOL_LOCK) {
2660                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2661                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2662                         break;
2663                 }
2664         }
2665         if (i == 4)
2666                 DRM_ERROR("FDI train 2 fail!\n");
2667
2668         DRM_DEBUG_KMS("FDI train done.\n");
2669 }
2670
2671 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2672 {
2673         struct drm_device *dev = intel_crtc->base.dev;
2674         struct drm_i915_private *dev_priv = dev->dev_private;
2675         int pipe = intel_crtc->pipe;
2676         u32 reg, temp;
2677
2678
2679         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2680         reg = FDI_RX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2683         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2684         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2685         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2686
2687         POSTING_READ(reg);
2688         udelay(200);
2689
2690         /* Switch from Rawclk to PCDclk */
2691         temp = I915_READ(reg);
2692         I915_WRITE(reg, temp | FDI_PCDCLK);
2693
2694         POSTING_READ(reg);
2695         udelay(200);
2696
2697         /* Enable CPU FDI TX PLL, always on for Ironlake */
2698         reg = FDI_TX_CTL(pipe);
2699         temp = I915_READ(reg);
2700         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2701                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2702
2703                 POSTING_READ(reg);
2704                 udelay(100);
2705         }
2706 }
2707
2708 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2709 {
2710         struct drm_device *dev = intel_crtc->base.dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         int pipe = intel_crtc->pipe;
2713         u32 reg, temp;
2714
2715         /* Switch from PCDclk to Rawclk */
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2719
2720         /* Disable CPU FDI TX PLL */
2721         reg = FDI_TX_CTL(pipe);
2722         temp = I915_READ(reg);
2723         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2724
2725         POSTING_READ(reg);
2726         udelay(100);
2727
2728         reg = FDI_RX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2731
2732         /* Wait for the clocks to turn off. */
2733         POSTING_READ(reg);
2734         udelay(100);
2735 }
2736
2737 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2738 {
2739         struct drm_device *dev = crtc->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742         int pipe = intel_crtc->pipe;
2743         u32 reg, temp;
2744
2745         /* disable CPU FDI tx and PCH FDI rx */
2746         reg = FDI_TX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2749         POSTING_READ(reg);
2750
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         temp &= ~(0x7 << 16);
2754         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2755         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2756
2757         POSTING_READ(reg);
2758         udelay(100);
2759
2760         /* Ironlake workaround, disable clock pointer after downing FDI */
2761         if (HAS_PCH_IBX(dev)) {
2762                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2763         }
2764
2765         /* still set train pattern 1 */
2766         reg = FDI_TX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~FDI_LINK_TRAIN_NONE;
2769         temp |= FDI_LINK_TRAIN_PATTERN_1;
2770         I915_WRITE(reg, temp);
2771
2772         reg = FDI_RX_CTL(pipe);
2773         temp = I915_READ(reg);
2774         if (HAS_PCH_CPT(dev)) {
2775                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2776                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2777         } else {
2778                 temp &= ~FDI_LINK_TRAIN_NONE;
2779                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2780         }
2781         /* BPC in FDI rx is consistent with that in PIPECONF */
2782         temp &= ~(0x07 << 16);
2783         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2784         I915_WRITE(reg, temp);
2785
2786         POSTING_READ(reg);
2787         udelay(100);
2788 }
2789
2790 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2791 {
2792         struct drm_device *dev = crtc->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795         unsigned long flags;
2796         bool pending;
2797
2798         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2799             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2800                 return false;
2801
2802         spin_lock_irqsave(&dev->event_lock, flags);
2803         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2804         spin_unlock_irqrestore(&dev->event_lock, flags);
2805
2806         return pending;
2807 }
2808
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813
2814         if (crtc->fb == NULL)
2815                 return;
2816
2817         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2818
2819         wait_event(dev_priv->pending_flip_queue,
2820                    !intel_crtc_has_pending_flip(crtc));
2821
2822         mutex_lock(&dev->struct_mutex);
2823         intel_finish_fb(crtc->fb);
2824         mutex_unlock(&dev->struct_mutex);
2825 }
2826
2827 /* Program iCLKIP clock to the desired frequency */
2828 static void lpt_program_iclkip(struct drm_crtc *crtc)
2829 {
2830         struct drm_device *dev = crtc->dev;
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2833         u32 temp;
2834
2835         mutex_lock(&dev_priv->dpio_lock);
2836
2837         /* It is necessary to ungate the pixclk gate prior to programming
2838          * the divisors, and gate it back when it is done.
2839          */
2840         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2841
2842         /* Disable SSCCTL */
2843         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2844                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2845                                 SBI_SSCCTL_DISABLE,
2846                         SBI_ICLK);
2847
2848         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2849         if (crtc->mode.clock == 20000) {
2850                 auxdiv = 1;
2851                 divsel = 0x41;
2852                 phaseinc = 0x20;
2853         } else {
2854                 /* The iCLK virtual clock root frequency is in MHz,
2855                  * but the crtc->mode.clock in in KHz. To get the divisors,
2856                  * it is necessary to divide one by another, so we
2857                  * convert the virtual clock precision to KHz here for higher
2858                  * precision.
2859                  */
2860                 u32 iclk_virtual_root_freq = 172800 * 1000;
2861                 u32 iclk_pi_range = 64;
2862                 u32 desired_divisor, msb_divisor_value, pi_value;
2863
2864                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2865                 msb_divisor_value = desired_divisor / iclk_pi_range;
2866                 pi_value = desired_divisor % iclk_pi_range;
2867
2868                 auxdiv = 0;
2869                 divsel = msb_divisor_value - 2;
2870                 phaseinc = pi_value;
2871         }
2872
2873         /* This should not happen with any sane values */
2874         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2875                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2876         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2877                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2878
2879         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2880                         crtc->mode.clock,
2881                         auxdiv,
2882                         divsel,
2883                         phasedir,
2884                         phaseinc);
2885
2886         /* Program SSCDIVINTPHASE6 */
2887         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2888         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2889         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2890         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2891         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2892         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2893         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2894         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2895
2896         /* Program SSCAUXDIV */
2897         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2898         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2899         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2900         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2901
2902         /* Enable modulator and associated divider */
2903         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2904         temp &= ~SBI_SSCCTL_DISABLE;
2905         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2906
2907         /* Wait for initialization time */
2908         udelay(24);
2909
2910         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2911
2912         mutex_unlock(&dev_priv->dpio_lock);
2913 }
2914
2915 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2916                                                 enum pipe pch_transcoder)
2917 {
2918         struct drm_device *dev = crtc->base.dev;
2919         struct drm_i915_private *dev_priv = dev->dev_private;
2920         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2921
2922         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2923                    I915_READ(HTOTAL(cpu_transcoder)));
2924         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2925                    I915_READ(HBLANK(cpu_transcoder)));
2926         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2927                    I915_READ(HSYNC(cpu_transcoder)));
2928
2929         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2930                    I915_READ(VTOTAL(cpu_transcoder)));
2931         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2932                    I915_READ(VBLANK(cpu_transcoder)));
2933         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2934                    I915_READ(VSYNC(cpu_transcoder)));
2935         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2936                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2937 }
2938
2939 /*
2940  * Enable PCH resources required for PCH ports:
2941  *   - PCH PLLs
2942  *   - FDI training & RX/TX
2943  *   - update transcoder timings
2944  *   - DP transcoding bits
2945  *   - transcoder
2946  */
2947 static void ironlake_pch_enable(struct drm_crtc *crtc)
2948 {
2949         struct drm_device *dev = crtc->dev;
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2952         int pipe = intel_crtc->pipe;
2953         u32 reg, temp;
2954
2955         assert_pch_transcoder_disabled(dev_priv, pipe);
2956
2957         /* Write the TU size bits before fdi link training, so that error
2958          * detection works. */
2959         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2960                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2961
2962         /* For PCH output, training FDI link */
2963         dev_priv->display.fdi_link_train(crtc);
2964
2965         /* XXX: pch pll's can be enabled any time before we enable the PCH
2966          * transcoder, and we actually should do this to not upset any PCH
2967          * transcoder that already use the clock when we share it.
2968          *
2969          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2970          * unconditionally resets the pll - we need that to have the right LVDS
2971          * enable sequence. */
2972         ironlake_enable_pch_pll(intel_crtc);
2973
2974         if (HAS_PCH_CPT(dev)) {
2975                 u32 sel;
2976
2977                 temp = I915_READ(PCH_DPLL_SEL);
2978                 switch (pipe) {
2979                 default:
2980                 case 0:
2981                         temp |= TRANSA_DPLL_ENABLE;
2982                         sel = TRANSA_DPLLB_SEL;
2983                         break;
2984                 case 1:
2985                         temp |= TRANSB_DPLL_ENABLE;
2986                         sel = TRANSB_DPLLB_SEL;
2987                         break;
2988                 case 2:
2989                         temp |= TRANSC_DPLL_ENABLE;
2990                         sel = TRANSC_DPLLB_SEL;
2991                         break;
2992                 }
2993                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2994                         temp |= sel;
2995                 else
2996                         temp &= ~sel;
2997                 I915_WRITE(PCH_DPLL_SEL, temp);
2998         }
2999
3000         /* set transcoder timing, panel must allow it */
3001         assert_panel_unlocked(dev_priv, pipe);
3002         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3003
3004         intel_fdi_normal_train(crtc);
3005
3006         /* For PCH DP, enable TRANS_DP_CTL */
3007         if (HAS_PCH_CPT(dev) &&
3008             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3009              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3010                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3011                 reg = TRANS_DP_CTL(pipe);
3012                 temp = I915_READ(reg);
3013                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3014                           TRANS_DP_SYNC_MASK |
3015                           TRANS_DP_BPC_MASK);
3016                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3017                          TRANS_DP_ENH_FRAMING);
3018                 temp |= bpc << 9; /* same format but at 11:9 */
3019
3020                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3021                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3022                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3023                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3024
3025                 switch (intel_trans_dp_port_sel(crtc)) {
3026                 case PCH_DP_B:
3027                         temp |= TRANS_DP_PORT_SEL_B;
3028                         break;
3029                 case PCH_DP_C:
3030                         temp |= TRANS_DP_PORT_SEL_C;
3031                         break;
3032                 case PCH_DP_D:
3033                         temp |= TRANS_DP_PORT_SEL_D;
3034                         break;
3035                 default:
3036                         BUG();
3037                 }
3038
3039                 I915_WRITE(reg, temp);
3040         }
3041
3042         ironlake_enable_pch_transcoder(dev_priv, pipe);
3043 }
3044
3045 static void lpt_pch_enable(struct drm_crtc *crtc)
3046 {
3047         struct drm_device *dev = crtc->dev;
3048         struct drm_i915_private *dev_priv = dev->dev_private;
3049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3050         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3051
3052         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3053
3054         lpt_program_iclkip(crtc);
3055
3056         /* Set transcoder timing. */
3057         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3058
3059         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3060 }
3061
3062 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3063 {
3064         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3065
3066         if (pll == NULL)
3067                 return;
3068
3069         if (pll->refcount == 0) {
3070                 WARN(1, "bad PCH PLL refcount\n");
3071                 return;
3072         }
3073
3074         if (--pll->refcount == 0) {
3075                 WARN_ON(pll->on);
3076                 WARN_ON(pll->active);
3077         }
3078
3079         intel_crtc->pch_pll = NULL;
3080 }
3081
3082 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3083 {
3084         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3085         struct intel_pch_pll *pll;
3086         int i;
3087
3088         pll = intel_crtc->pch_pll;
3089         if (pll) {
3090                 DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
3091                               intel_crtc->base.base.id, pll->pll_reg);
3092                 intel_put_pch_pll(intel_crtc);
3093         }
3094
3095         if (HAS_PCH_IBX(dev_priv->dev)) {
3096                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3097                 i = intel_crtc->pipe;
3098                 pll = &dev_priv->pch_plls[i];
3099
3100                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3101                               intel_crtc->base.base.id, pll->pll_reg);
3102
3103                 goto found;
3104         }
3105
3106         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3107                 pll = &dev_priv->pch_plls[i];
3108
3109                 /* Only want to check enabled timings first */
3110                 if (pll->refcount == 0)
3111                         continue;
3112
3113                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3114                     fp == I915_READ(pll->fp0_reg)) {
3115                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3116                                       intel_crtc->base.base.id,
3117                                       pll->pll_reg, pll->refcount, pll->active);
3118
3119                         goto found;
3120                 }
3121         }
3122
3123         /* Ok no matching timings, maybe there's a free one? */
3124         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3125                 pll = &dev_priv->pch_plls[i];
3126                 if (pll->refcount == 0) {
3127                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3128                                       intel_crtc->base.base.id, pll->pll_reg);
3129                         goto found;
3130                 }
3131         }
3132
3133         return NULL;
3134
3135 found:
3136         intel_crtc->pch_pll = pll;
3137         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3138         if (pll->active == 0) {
3139                 DRM_DEBUG_DRIVER("setting up pll %d\n", i);
3140                 WARN_ON(pll->on);
3141                 assert_pch_pll_disabled(dev_priv, pll, NULL);
3142
3143                 /* Wait for the clocks to stabilize before rewriting the regs */
3144                 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3145                 POSTING_READ(pll->pll_reg);
3146                 udelay(150);
3147
3148                 I915_WRITE(pll->fp0_reg, fp);
3149                 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3150         }
3151         pll->refcount++;
3152
3153         return pll;
3154 }
3155
3156 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3157 {
3158         struct drm_i915_private *dev_priv = dev->dev_private;
3159         int dslreg = PIPEDSL(pipe);
3160         u32 temp;
3161
3162         temp = I915_READ(dslreg);
3163         udelay(500);
3164         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3165                 if (wait_for(I915_READ(dslreg) != temp, 5))
3166                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3167         }
3168 }
3169
3170 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3171 {
3172         struct drm_device *dev = crtc->base.dev;
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         int pipe = crtc->pipe;
3175
3176         if (crtc->config.pch_pfit.size) {
3177                 /* Force use of hard-coded filter coefficients
3178                  * as some pre-programmed values are broken,
3179                  * e.g. x201.
3180                  */
3181                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3182                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3183                                                  PF_PIPE_SEL_IVB(pipe));
3184                 else
3185                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3186                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3187                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3188         }
3189 }
3190
3191 static void intel_enable_planes(struct drm_crtc *crtc)
3192 {
3193         struct drm_device *dev = crtc->dev;
3194         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3195         struct intel_plane *intel_plane;
3196
3197         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3198                 if (intel_plane->pipe == pipe)
3199                         intel_plane_restore(&intel_plane->base);
3200 }
3201
3202 static void intel_disable_planes(struct drm_crtc *crtc)
3203 {
3204         struct drm_device *dev = crtc->dev;
3205         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3206         struct intel_plane *intel_plane;
3207
3208         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3209                 if (intel_plane->pipe == pipe)
3210                         intel_plane_disable(&intel_plane->base);
3211 }
3212
3213 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3214 {
3215         struct drm_device *dev = crtc->dev;
3216         struct drm_i915_private *dev_priv = dev->dev_private;
3217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218         struct intel_encoder *encoder;
3219         int pipe = intel_crtc->pipe;
3220         int plane = intel_crtc->plane;
3221         u32 temp;
3222
3223         WARN_ON(!crtc->enabled);
3224
3225         if (intel_crtc->active)
3226                 return;
3227
3228         intel_crtc->active = true;
3229
3230         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3231         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3232
3233         intel_update_watermarks(dev);
3234
3235         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3236                 temp = I915_READ(PCH_LVDS);
3237                 if ((temp & LVDS_PORT_EN) == 0)
3238                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3239         }
3240
3241
3242         if (intel_crtc->config.has_pch_encoder) {
3243                 /* Note: FDI PLL enabling _must_ be done before we enable the
3244                  * cpu pipes, hence this is separate from all the other fdi/pch
3245                  * enabling. */
3246                 ironlake_fdi_pll_enable(intel_crtc);
3247         } else {
3248                 assert_fdi_tx_disabled(dev_priv, pipe);
3249                 assert_fdi_rx_disabled(dev_priv, pipe);
3250         }
3251
3252         for_each_encoder_on_crtc(dev, crtc, encoder)
3253                 if (encoder->pre_enable)
3254                         encoder->pre_enable(encoder);
3255
3256         /* Enable panel fitting for LVDS */
3257         ironlake_pfit_enable(intel_crtc);
3258
3259         /*
3260          * On ILK+ LUT must be loaded before the pipe is running but with
3261          * clocks enabled
3262          */
3263         intel_crtc_load_lut(crtc);
3264
3265         intel_enable_pipe(dev_priv, pipe,
3266                           intel_crtc->config.has_pch_encoder);
3267         intel_enable_plane(dev_priv, plane, pipe);
3268         intel_enable_planes(crtc);
3269         intel_crtc_update_cursor(crtc, true);
3270
3271         if (intel_crtc->config.has_pch_encoder)
3272                 ironlake_pch_enable(crtc);
3273
3274         mutex_lock(&dev->struct_mutex);
3275         intel_update_fbc(dev);
3276         mutex_unlock(&dev->struct_mutex);
3277
3278         for_each_encoder_on_crtc(dev, crtc, encoder)
3279                 encoder->enable(encoder);
3280
3281         if (HAS_PCH_CPT(dev))
3282                 cpt_verify_modeset(dev, intel_crtc->pipe);
3283
3284         /*
3285          * There seems to be a race in PCH platform hw (at least on some
3286          * outputs) where an enabled pipe still completes any pageflip right
3287          * away (as if the pipe is off) instead of waiting for vblank. As soon
3288          * as the first vblank happend, everything works as expected. Hence just
3289          * wait for one vblank before returning to avoid strange things
3290          * happening.
3291          */
3292         intel_wait_for_vblank(dev, intel_crtc->pipe);
3293 }
3294
3295 /* IPS only exists on ULT machines and is tied to pipe A. */
3296 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3297 {
3298         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3299 }
3300
3301 static void hsw_enable_ips(struct intel_crtc *crtc)
3302 {
3303         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3304
3305         if (!crtc->config.ips_enabled)
3306                 return;
3307
3308         /* We can only enable IPS after we enable a plane and wait for a vblank.
3309          * We guarantee that the plane is enabled by calling intel_enable_ips
3310          * only after intel_enable_plane. And intel_enable_plane already waits
3311          * for a vblank, so all we need to do here is to enable the IPS bit. */
3312         assert_plane_enabled(dev_priv, crtc->plane);
3313         I915_WRITE(IPS_CTL, IPS_ENABLE);
3314 }
3315
3316 static void hsw_disable_ips(struct intel_crtc *crtc)
3317 {
3318         struct drm_device *dev = crtc->base.dev;
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320
3321         if (!crtc->config.ips_enabled)
3322                 return;
3323
3324         assert_plane_enabled(dev_priv, crtc->plane);
3325         I915_WRITE(IPS_CTL, 0);
3326
3327         /* We need to wait for a vblank before we can disable the plane. */
3328         intel_wait_for_vblank(dev, crtc->pipe);
3329 }
3330
3331 static void haswell_crtc_enable(struct drm_crtc *crtc)
3332 {
3333         struct drm_device *dev = crtc->dev;
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336         struct intel_encoder *encoder;
3337         int pipe = intel_crtc->pipe;
3338         int plane = intel_crtc->plane;
3339
3340         WARN_ON(!crtc->enabled);
3341
3342         if (intel_crtc->active)
3343                 return;
3344
3345         intel_crtc->active = true;
3346
3347         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3348         if (intel_crtc->config.has_pch_encoder)
3349                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3350
3351         intel_update_watermarks(dev);
3352
3353         if (intel_crtc->config.has_pch_encoder)
3354                 dev_priv->display.fdi_link_train(crtc);
3355
3356         for_each_encoder_on_crtc(dev, crtc, encoder)
3357                 if (encoder->pre_enable)
3358                         encoder->pre_enable(encoder);
3359
3360         intel_ddi_enable_pipe_clock(intel_crtc);
3361
3362         /* Enable panel fitting for eDP */
3363         ironlake_pfit_enable(intel_crtc);
3364
3365         /*
3366          * On ILK+ LUT must be loaded before the pipe is running but with
3367          * clocks enabled
3368          */
3369         intel_crtc_load_lut(crtc);
3370
3371         intel_ddi_set_pipe_settings(crtc);
3372         intel_ddi_enable_transcoder_func(crtc);
3373
3374         intel_enable_pipe(dev_priv, pipe,
3375                           intel_crtc->config.has_pch_encoder);
3376         intel_enable_plane(dev_priv, plane, pipe);
3377         intel_enable_planes(crtc);
3378         intel_crtc_update_cursor(crtc, true);
3379
3380         hsw_enable_ips(intel_crtc);
3381
3382         if (intel_crtc->config.has_pch_encoder)
3383                 lpt_pch_enable(crtc);
3384
3385         mutex_lock(&dev->struct_mutex);
3386         intel_update_fbc(dev);
3387         mutex_unlock(&dev->struct_mutex);
3388
3389         for_each_encoder_on_crtc(dev, crtc, encoder)
3390                 encoder->enable(encoder);
3391
3392         /*
3393          * There seems to be a race in PCH platform hw (at least on some
3394          * outputs) where an enabled pipe still completes any pageflip right
3395          * away (as if the pipe is off) instead of waiting for vblank. As soon
3396          * as the first vblank happend, everything works as expected. Hence just
3397          * wait for one vblank before returning to avoid strange things
3398          * happening.
3399          */
3400         intel_wait_for_vblank(dev, intel_crtc->pipe);
3401 }
3402
3403 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3404 {
3405         struct drm_device *dev = crtc->base.dev;
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407         int pipe = crtc->pipe;
3408
3409         /* To avoid upsetting the power well on haswell only disable the pfit if
3410          * it's in use. The hw state code will make sure we get this right. */
3411         if (crtc->config.pch_pfit.size) {
3412                 I915_WRITE(PF_CTL(pipe), 0);
3413                 I915_WRITE(PF_WIN_POS(pipe), 0);
3414                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3415         }
3416 }
3417
3418 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3419 {
3420         struct drm_device *dev = crtc->dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423         struct intel_encoder *encoder;
3424         int pipe = intel_crtc->pipe;
3425         int plane = intel_crtc->plane;
3426         u32 reg, temp;
3427
3428
3429         if (!intel_crtc->active)
3430                 return;
3431
3432         for_each_encoder_on_crtc(dev, crtc, encoder)
3433                 encoder->disable(encoder);
3434
3435         intel_crtc_wait_for_pending_flips(crtc);
3436         drm_vblank_off(dev, pipe);
3437
3438         if (dev_priv->cfb_plane == plane)
3439                 intel_disable_fbc(dev);
3440
3441         intel_crtc_update_cursor(crtc, false);
3442         intel_disable_planes(crtc);
3443         intel_disable_plane(dev_priv, plane, pipe);
3444
3445         if (intel_crtc->config.has_pch_encoder)
3446                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3447
3448         intel_disable_pipe(dev_priv, pipe);
3449
3450         ironlake_pfit_disable(intel_crtc);
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 if (encoder->post_disable)
3454                         encoder->post_disable(encoder);
3455
3456         if (intel_crtc->config.has_pch_encoder) {
3457                 ironlake_fdi_disable(crtc);
3458
3459                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3460                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3461
3462                 if (HAS_PCH_CPT(dev)) {
3463                         /* disable TRANS_DP_CTL */
3464                         reg = TRANS_DP_CTL(pipe);
3465                         temp = I915_READ(reg);
3466                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3467                                   TRANS_DP_PORT_SEL_MASK);
3468                         temp |= TRANS_DP_PORT_SEL_NONE;
3469                         I915_WRITE(reg, temp);
3470
3471                         /* disable DPLL_SEL */
3472                         temp = I915_READ(PCH_DPLL_SEL);
3473                         switch (pipe) {
3474                         case 0:
3475                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3476                                 break;
3477                         case 1:
3478                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3479                                 break;
3480                         case 2:
3481                                 /* C shares PLL A or B */
3482                                 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3483                                 break;
3484                         default:
3485                                 BUG(); /* wtf */
3486                         }
3487                         I915_WRITE(PCH_DPLL_SEL, temp);
3488                 }
3489
3490                 /* disable PCH DPLL */
3491                 intel_disable_pch_pll(intel_crtc);
3492
3493                 ironlake_fdi_pll_disable(intel_crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void haswell_crtc_disable(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509         struct intel_encoder *encoder;
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3513
3514         if (!intel_crtc->active)
3515                 return;
3516
3517         for_each_encoder_on_crtc(dev, crtc, encoder)
3518                 encoder->disable(encoder);
3519
3520         intel_crtc_wait_for_pending_flips(crtc);
3521         drm_vblank_off(dev, pipe);
3522
3523         /* FBC must be disabled before disabling the plane on HSW. */
3524         if (dev_priv->cfb_plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         hsw_disable_ips(intel_crtc);
3528
3529         intel_crtc_update_cursor(crtc, false);
3530         intel_disable_planes(crtc);
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (intel_crtc->config.has_pch_encoder)
3534                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3538
3539         ironlake_pfit_disable(intel_crtc);
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_pch_pll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         intel_ddi_put_crtc_pll(crtc);
3570 }
3571
3572 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573 {
3574         if (!enable && intel_crtc->overlay) {
3575                 struct drm_device *dev = intel_crtc->base.dev;
3576                 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578                 mutex_lock(&dev->struct_mutex);
3579                 dev_priv->mm.interruptible = false;
3580                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581                 dev_priv->mm.interruptible = true;
3582                 mutex_unlock(&dev->struct_mutex);
3583         }
3584
3585         /* Let userspace switch the overlay on again. In most cases userspace
3586          * has to recompute where to put it anyway.
3587          */
3588 }
3589
3590 /**
3591  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3592  * cursor plane briefly if not already running after enabling the display
3593  * plane.
3594  * This workaround avoids occasional blank screens when self refresh is
3595  * enabled.
3596  */
3597 static void
3598 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3599 {
3600         u32 cntl = I915_READ(CURCNTR(pipe));
3601
3602         if ((cntl & CURSOR_MODE) == 0) {
3603                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3604
3605                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3606                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3607                 intel_wait_for_vblank(dev_priv->dev, pipe);
3608                 I915_WRITE(CURCNTR(pipe), cntl);
3609                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3611         }
3612 }
3613
3614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->base.dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc_config *pipe_config = &crtc->config;
3619
3620         if (!crtc->config.gmch_pfit.control)
3621                 return;
3622
3623         /*
3624          * The panel fitter should only be adjusted whilst the pipe is disabled,
3625          * according to register description and PRM.
3626          */
3627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3628         assert_pipe_disabled(dev_priv, crtc->pipe);
3629
3630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3632
3633         /* Border color in case we don't scale up to the full screen. Black by
3634          * default, change to something else for debugging. */
3635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3636 }
3637
3638 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         struct intel_encoder *encoder;
3644         int pipe = intel_crtc->pipe;
3645         int plane = intel_crtc->plane;
3646
3647         WARN_ON(!crtc->enabled);
3648
3649         if (intel_crtc->active)
3650                 return;
3651
3652         intel_crtc->active = true;
3653         intel_update_watermarks(dev);
3654
3655         mutex_lock(&dev_priv->dpio_lock);
3656
3657         for_each_encoder_on_crtc(dev, crtc, encoder)
3658                 if (encoder->pre_pll_enable)
3659                         encoder->pre_pll_enable(encoder);
3660
3661         intel_enable_pll(dev_priv, pipe);
3662
3663         for_each_encoder_on_crtc(dev, crtc, encoder)
3664                 if (encoder->pre_enable)
3665                         encoder->pre_enable(encoder);
3666
3667         /* VLV wants encoder enabling _before_ the pipe is up. */
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->enable(encoder);
3670
3671         /* Enable panel fitting for eDP */
3672         i9xx_pfit_enable(intel_crtc);
3673
3674         intel_crtc_load_lut(crtc);
3675
3676         intel_enable_pipe(dev_priv, pipe, false);
3677         intel_enable_plane(dev_priv, plane, pipe);
3678         intel_enable_planes(crtc);
3679         intel_crtc_update_cursor(crtc, true);
3680
3681         intel_update_fbc(dev);
3682
3683         mutex_unlock(&dev_priv->dpio_lock);
3684 }
3685
3686 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3687 {
3688         struct drm_device *dev = crtc->dev;
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3691         struct intel_encoder *encoder;
3692         int pipe = intel_crtc->pipe;
3693         int plane = intel_crtc->plane;
3694
3695         WARN_ON(!crtc->enabled);
3696
3697         if (intel_crtc->active)
3698                 return;
3699
3700         intel_crtc->active = true;
3701         intel_update_watermarks(dev);
3702
3703         intel_enable_pll(dev_priv, pipe);
3704
3705         for_each_encoder_on_crtc(dev, crtc, encoder)
3706                 if (encoder->pre_enable)
3707                         encoder->pre_enable(encoder);
3708
3709         /* Enable panel fitting for LVDS */
3710         i9xx_pfit_enable(intel_crtc);
3711
3712         intel_crtc_load_lut(crtc);
3713
3714         intel_enable_pipe(dev_priv, pipe, false);
3715         intel_enable_plane(dev_priv, plane, pipe);
3716         intel_enable_planes(crtc);
3717         /* The fixup needs to happen before cursor is enabled */
3718         if (IS_G4X(dev))
3719                 g4x_fixup_plane(dev_priv, pipe);
3720         intel_crtc_update_cursor(crtc, true);
3721
3722         /* Give the overlay scaler a chance to enable if it's on this pipe */
3723         intel_crtc_dpms_overlay(intel_crtc, true);
3724
3725         intel_update_fbc(dev);
3726
3727         for_each_encoder_on_crtc(dev, crtc, encoder)
3728                 encoder->enable(encoder);
3729 }
3730
3731 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->base.dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736         if (!crtc->config.gmch_pfit.control)
3737                 return;
3738
3739         assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3742                          I915_READ(PFIT_CONTROL));
3743         I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745
3746 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3747 {
3748         struct drm_device *dev = crtc->dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         struct intel_encoder *encoder;
3752         int pipe = intel_crtc->pipe;
3753         int plane = intel_crtc->plane;
3754
3755         if (!intel_crtc->active)
3756                 return;
3757
3758         for_each_encoder_on_crtc(dev, crtc, encoder)
3759                 encoder->disable(encoder);
3760
3761         /* Give the overlay scaler a chance to disable if it's on this pipe */
3762         intel_crtc_wait_for_pending_flips(crtc);
3763         drm_vblank_off(dev, pipe);
3764
3765         if (dev_priv->cfb_plane == plane)
3766                 intel_disable_fbc(dev);
3767
3768         intel_crtc_dpms_overlay(intel_crtc, false);
3769         intel_crtc_update_cursor(crtc, false);
3770         intel_disable_planes(crtc);
3771         intel_disable_plane(dev_priv, plane, pipe);
3772
3773         intel_disable_pipe(dev_priv, pipe);
3774
3775         i9xx_pfit_disable(intel_crtc);
3776
3777         for_each_encoder_on_crtc(dev, crtc, encoder)
3778                 if (encoder->post_disable)
3779                         encoder->post_disable(encoder);
3780
3781         intel_disable_pll(dev_priv, pipe);
3782
3783         intel_crtc->active = false;
3784         intel_update_fbc(dev);
3785         intel_update_watermarks(dev);
3786 }
3787
3788 static void i9xx_crtc_off(struct drm_crtc *crtc)
3789 {
3790 }
3791
3792 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793                                     bool enabled)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_master_private *master_priv;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         int pipe = intel_crtc->pipe;
3799
3800         if (!dev->primary->master)
3801                 return;
3802
3803         master_priv = dev->primary->master->driver_priv;
3804         if (!master_priv->sarea_priv)
3805                 return;
3806
3807         switch (pipe) {
3808         case 0:
3809                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811                 break;
3812         case 1:
3813                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815                 break;
3816         default:
3817                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3818                 break;
3819         }
3820 }
3821
3822 /**
3823  * Sets the power management mode of the pipe and plane.
3824  */
3825 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_encoder *intel_encoder;
3830         bool enable = false;
3831
3832         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833                 enable |= intel_encoder->connectors_active;
3834
3835         if (enable)
3836                 dev_priv->display.crtc_enable(crtc);
3837         else
3838                 dev_priv->display.crtc_disable(crtc);
3839
3840         intel_crtc_update_sarea(crtc, enable);
3841 }
3842
3843 static void intel_crtc_disable(struct drm_crtc *crtc)
3844 {
3845         struct drm_device *dev = crtc->dev;
3846         struct drm_connector *connector;
3847         struct drm_i915_private *dev_priv = dev->dev_private;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849
3850         /* crtc should still be enabled when we disable it. */
3851         WARN_ON(!crtc->enabled);
3852
3853         dev_priv->display.crtc_disable(crtc);
3854         intel_crtc->eld_vld = false;
3855         intel_crtc_update_sarea(crtc, false);
3856         dev_priv->display.off(crtc);
3857
3858         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3860
3861         if (crtc->fb) {
3862                 mutex_lock(&dev->struct_mutex);
3863                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3864                 mutex_unlock(&dev->struct_mutex);
3865                 crtc->fb = NULL;
3866         }
3867
3868         /* Update computed state. */
3869         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870                 if (!connector->encoder || !connector->encoder->crtc)
3871                         continue;
3872
3873                 if (connector->encoder->crtc != crtc)
3874                         continue;
3875
3876                 connector->dpms = DRM_MODE_DPMS_OFF;
3877                 to_intel_encoder(connector->encoder)->connectors_active = false;
3878         }
3879 }
3880
3881 void intel_modeset_disable(struct drm_device *dev)
3882 {
3883         struct drm_crtc *crtc;
3884
3885         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3886                 if (crtc->enabled)
3887                         intel_crtc_disable(crtc);
3888         }
3889 }
3890
3891 void intel_encoder_destroy(struct drm_encoder *encoder)
3892 {
3893         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3894
3895         drm_encoder_cleanup(encoder);
3896         kfree(intel_encoder);
3897 }
3898
3899 /* Simple dpms helper for encodres with just one connector, no cloning and only
3900  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901  * state of the entire output pipe. */
3902 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3903 {
3904         if (mode == DRM_MODE_DPMS_ON) {
3905                 encoder->connectors_active = true;
3906
3907                 intel_crtc_update_dpms(encoder->base.crtc);
3908         } else {
3909                 encoder->connectors_active = false;
3910
3911                 intel_crtc_update_dpms(encoder->base.crtc);
3912         }
3913 }
3914
3915 /* Cross check the actual hw state with our own modeset state tracking (and it's
3916  * internal consistency). */
3917 static void intel_connector_check_state(struct intel_connector *connector)
3918 {
3919         if (connector->get_hw_state(connector)) {
3920                 struct intel_encoder *encoder = connector->encoder;
3921                 struct drm_crtc *crtc;
3922                 bool encoder_enabled;
3923                 enum pipe pipe;
3924
3925                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926                               connector->base.base.id,
3927                               drm_get_connector_name(&connector->base));
3928
3929                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930                      "wrong connector dpms state\n");
3931                 WARN(connector->base.encoder != &encoder->base,
3932                      "active connector not linked to encoder\n");
3933                 WARN(!encoder->connectors_active,
3934                      "encoder->connectors_active not set\n");
3935
3936                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937                 WARN(!encoder_enabled, "encoder not enabled\n");
3938                 if (WARN_ON(!encoder->base.crtc))
3939                         return;
3940
3941                 crtc = encoder->base.crtc;
3942
3943                 WARN(!crtc->enabled, "crtc not enabled\n");
3944                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946                      "encoder active on the wrong pipe\n");
3947         }
3948 }
3949
3950 /* Even simpler default implementation, if there's really no special case to
3951  * consider. */
3952 void intel_connector_dpms(struct drm_connector *connector, int mode)
3953 {
3954         struct intel_encoder *encoder = intel_attached_encoder(connector);
3955
3956         /* All the simple cases only support two dpms states. */
3957         if (mode != DRM_MODE_DPMS_ON)
3958                 mode = DRM_MODE_DPMS_OFF;
3959
3960         if (mode == connector->dpms)
3961                 return;
3962
3963         connector->dpms = mode;
3964
3965         /* Only need to change hw state when actually enabled */
3966         if (encoder->base.crtc)
3967                 intel_encoder_dpms(encoder, mode);
3968         else
3969                 WARN_ON(encoder->connectors_active != false);
3970
3971         intel_modeset_check_state(connector->dev);
3972 }
3973
3974 /* Simple connector->get_hw_state implementation for encoders that support only
3975  * one connector and no cloning and hence the encoder state determines the state
3976  * of the connector. */
3977 bool intel_connector_get_hw_state(struct intel_connector *connector)
3978 {
3979         enum pipe pipe = 0;
3980         struct intel_encoder *encoder = connector->encoder;
3981
3982         return encoder->get_hw_state(encoder, &pipe);
3983 }
3984
3985 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3986                                      struct intel_crtc_config *pipe_config)
3987 {
3988         struct drm_i915_private *dev_priv = dev->dev_private;
3989         struct intel_crtc *pipe_B_crtc =
3990                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3991
3992         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3993                       pipe_name(pipe), pipe_config->fdi_lanes);
3994         if (pipe_config->fdi_lanes > 4) {
3995                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3996                               pipe_name(pipe), pipe_config->fdi_lanes);
3997                 return false;
3998         }
3999
4000         if (IS_HASWELL(dev)) {
4001                 if (pipe_config->fdi_lanes > 2) {
4002                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4003                                       pipe_config->fdi_lanes);
4004                         return false;
4005                 } else {
4006                         return true;
4007                 }
4008         }
4009
4010         if (INTEL_INFO(dev)->num_pipes == 2)
4011                 return true;
4012
4013         /* Ivybridge 3 pipe is really complicated */
4014         switch (pipe) {
4015         case PIPE_A:
4016                 return true;
4017         case PIPE_B:
4018                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4019                     pipe_config->fdi_lanes > 2) {
4020                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4021                                       pipe_name(pipe), pipe_config->fdi_lanes);
4022                         return false;
4023                 }
4024                 return true;
4025         case PIPE_C:
4026                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4027                     pipe_B_crtc->config.fdi_lanes <= 2) {
4028                         if (pipe_config->fdi_lanes > 2) {
4029                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030                                               pipe_name(pipe), pipe_config->fdi_lanes);
4031                                 return false;
4032                         }
4033                 } else {
4034                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4035                         return false;
4036                 }
4037                 return true;
4038         default:
4039                 BUG();
4040         }
4041 }
4042
4043 #define RETRY 1
4044 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4045                                        struct intel_crtc_config *pipe_config)
4046 {
4047         struct drm_device *dev = intel_crtc->base.dev;
4048         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4049         int lane, link_bw, fdi_dotclock;
4050         bool setup_ok, needs_recompute = false;
4051
4052 retry:
4053         /* FDI is a binary signal running at ~2.7GHz, encoding
4054          * each output octet as 10 bits. The actual frequency
4055          * is stored as a divider into a 100MHz clock, and the
4056          * mode pixel clock is stored in units of 1KHz.
4057          * Hence the bw of each lane in terms of the mode signal
4058          * is:
4059          */
4060         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4061
4062         fdi_dotclock = adjusted_mode->clock;
4063         fdi_dotclock /= pipe_config->pixel_multiplier;
4064
4065         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4066                                            pipe_config->pipe_bpp);
4067
4068         pipe_config->fdi_lanes = lane;
4069
4070         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4071                                link_bw, &pipe_config->fdi_m_n);
4072
4073         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4074                                             intel_crtc->pipe, pipe_config);
4075         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4076                 pipe_config->pipe_bpp -= 2*3;
4077                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4078                               pipe_config->pipe_bpp);
4079                 needs_recompute = true;
4080                 pipe_config->bw_constrained = true;
4081
4082                 goto retry;
4083         }
4084
4085         if (needs_recompute)
4086                 return RETRY;
4087
4088         return setup_ok ? 0 : -EINVAL;
4089 }
4090
4091 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4092                                    struct intel_crtc_config *pipe_config)
4093 {
4094         pipe_config->ips_enabled = i915_enable_ips &&
4095                                    hsw_crtc_supports_ips(crtc) &&
4096                                    pipe_config->pipe_bpp == 24;
4097 }
4098
4099 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4100                                      struct intel_crtc_config *pipe_config)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105
4106         if (HAS_PCH_SPLIT(dev)) {
4107                 /* FDI link clock is fixed at 2.7G */
4108                 if (pipe_config->requested_mode.clock * 3
4109                     > IRONLAKE_FDI_FREQ * 4)
4110                         return -EINVAL;
4111         }
4112
4113         /* All interlaced capable intel hw wants timings in frames. Note though
4114          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4115          * timings, so we need to be careful not to clobber these.*/
4116         if (!pipe_config->timings_set)
4117                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4118
4119         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4120          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4121          */
4122         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4123                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4124                 return -EINVAL;
4125
4126         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4127                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4128         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4129                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4130                  * for lvds. */
4131                 pipe_config->pipe_bpp = 8*3;
4132         }
4133
4134         if (IS_HASWELL(dev))
4135                 hsw_compute_ips_config(intel_crtc, pipe_config);
4136
4137         if (pipe_config->has_pch_encoder)
4138                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4139
4140         return 0;
4141 }
4142
4143 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4144 {
4145         return 400000; /* FIXME */
4146 }
4147
4148 static int i945_get_display_clock_speed(struct drm_device *dev)
4149 {
4150         return 400000;
4151 }
4152
4153 static int i915_get_display_clock_speed(struct drm_device *dev)
4154 {
4155         return 333000;
4156 }
4157
4158 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4159 {
4160         return 200000;
4161 }
4162
4163 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4164 {
4165         u16 gcfgc = 0;
4166
4167         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4168
4169         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4170                 return 133000;
4171         else {
4172                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4173                 case GC_DISPLAY_CLOCK_333_MHZ:
4174                         return 333000;
4175                 default:
4176                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4177                         return 190000;
4178                 }
4179         }
4180 }
4181
4182 static int i865_get_display_clock_speed(struct drm_device *dev)
4183 {
4184         return 266000;
4185 }
4186
4187 static int i855_get_display_clock_speed(struct drm_device *dev)
4188 {
4189         u16 hpllcc = 0;
4190         /* Assume that the hardware is in the high speed state.  This
4191          * should be the default.
4192          */
4193         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4194         case GC_CLOCK_133_200:
4195         case GC_CLOCK_100_200:
4196                 return 200000;
4197         case GC_CLOCK_166_250:
4198                 return 250000;
4199         case GC_CLOCK_100_133:
4200                 return 133000;
4201         }
4202
4203         /* Shouldn't happen */
4204         return 0;
4205 }
4206
4207 static int i830_get_display_clock_speed(struct drm_device *dev)
4208 {
4209         return 133000;
4210 }
4211
4212 static void
4213 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4214 {
4215         while (*num > DATA_LINK_M_N_MASK ||
4216                *den > DATA_LINK_M_N_MASK) {
4217                 *num >>= 1;
4218                 *den >>= 1;
4219         }
4220 }
4221
4222 static void compute_m_n(unsigned int m, unsigned int n,
4223                         uint32_t *ret_m, uint32_t *ret_n)
4224 {
4225         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4226         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4227         intel_reduce_m_n_ratio(ret_m, ret_n);
4228 }
4229
4230 void
4231 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4232                        int pixel_clock, int link_clock,
4233                        struct intel_link_m_n *m_n)
4234 {
4235         m_n->tu = 64;
4236
4237         compute_m_n(bits_per_pixel * pixel_clock,
4238                     link_clock * nlanes * 8,
4239                     &m_n->gmch_m, &m_n->gmch_n);
4240
4241         compute_m_n(pixel_clock, link_clock,
4242                     &m_n->link_m, &m_n->link_n);
4243 }
4244
4245 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4246 {
4247         if (i915_panel_use_ssc >= 0)
4248                 return i915_panel_use_ssc != 0;
4249         return dev_priv->vbt.lvds_use_ssc
4250                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4251 }
4252
4253 static int vlv_get_refclk(struct drm_crtc *crtc)
4254 {
4255         struct drm_device *dev = crtc->dev;
4256         struct drm_i915_private *dev_priv = dev->dev_private;
4257         int refclk = 27000; /* for DP & HDMI */
4258
4259         return 100000; /* only one validated so far */
4260
4261         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4262                 refclk = 96000;
4263         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4264                 if (intel_panel_use_ssc(dev_priv))
4265                         refclk = 100000;
4266                 else
4267                         refclk = 96000;
4268         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4269                 refclk = 100000;
4270         }
4271
4272         return refclk;
4273 }
4274
4275 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4276 {
4277         struct drm_device *dev = crtc->dev;
4278         struct drm_i915_private *dev_priv = dev->dev_private;
4279         int refclk;
4280
4281         if (IS_VALLEYVIEW(dev)) {
4282                 refclk = vlv_get_refclk(crtc);
4283         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4284             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4285                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4286                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4287                               refclk / 1000);
4288         } else if (!IS_GEN2(dev)) {
4289                 refclk = 96000;
4290         } else {
4291                 refclk = 48000;
4292         }
4293
4294         return refclk;
4295 }
4296
4297 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4298 {
4299         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4300 }
4301
4302 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4303 {
4304         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4305 }
4306
4307 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4308                                      intel_clock_t *reduced_clock)
4309 {
4310         struct drm_device *dev = crtc->base.dev;
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         int pipe = crtc->pipe;
4313         u32 fp, fp2 = 0;
4314
4315         if (IS_PINEVIEW(dev)) {
4316                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4317                 if (reduced_clock)
4318                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4319         } else {
4320                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4321                 if (reduced_clock)
4322                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4323         }
4324
4325         I915_WRITE(FP0(pipe), fp);
4326
4327         crtc->lowfreq_avail = false;
4328         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4329             reduced_clock && i915_powersave) {
4330                 I915_WRITE(FP1(pipe), fp2);
4331                 crtc->lowfreq_avail = true;
4332         } else {
4333                 I915_WRITE(FP1(pipe), fp);
4334         }
4335 }
4336
4337 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4338 {
4339         u32 reg_val;
4340
4341         /*
4342          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4343          * and set it to a reasonable value instead.
4344          */
4345         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4346         reg_val &= 0xffffff00;
4347         reg_val |= 0x00000030;
4348         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4349
4350         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4351         reg_val &= 0x8cffffff;
4352         reg_val = 0x8c000000;
4353         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4354
4355         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4356         reg_val &= 0xffffff00;
4357         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4358
4359         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4360         reg_val &= 0x00ffffff;
4361         reg_val |= 0xb0000000;
4362         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4363 }
4364
4365 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4366                                          struct intel_link_m_n *m_n)
4367 {
4368         struct drm_device *dev = crtc->base.dev;
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         int pipe = crtc->pipe;
4371
4372         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4373         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4374         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4375         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4376 }
4377
4378 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4379                                          struct intel_link_m_n *m_n)
4380 {
4381         struct drm_device *dev = crtc->base.dev;
4382         struct drm_i915_private *dev_priv = dev->dev_private;
4383         int pipe = crtc->pipe;
4384         enum transcoder transcoder = crtc->config.cpu_transcoder;
4385
4386         if (INTEL_INFO(dev)->gen >= 5) {
4387                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4388                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4389                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4390                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4391         } else {
4392                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4393                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4394                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4395                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4396         }
4397 }
4398
4399 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4400 {
4401         if (crtc->config.has_pch_encoder)
4402                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4403         else
4404                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4405 }
4406
4407 static void vlv_update_pll(struct intel_crtc *crtc)
4408 {
4409         struct drm_device *dev = crtc->base.dev;
4410         struct drm_i915_private *dev_priv = dev->dev_private;
4411         struct intel_encoder *encoder;
4412         int pipe = crtc->pipe;
4413         u32 dpll, mdiv;
4414         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4415         bool is_hdmi;
4416         u32 coreclk, reg_val, dpll_md;
4417
4418         mutex_lock(&dev_priv->dpio_lock);
4419
4420         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4421
4422         bestn = crtc->config.dpll.n;
4423         bestm1 = crtc->config.dpll.m1;
4424         bestm2 = crtc->config.dpll.m2;
4425         bestp1 = crtc->config.dpll.p1;
4426         bestp2 = crtc->config.dpll.p2;
4427
4428         /* See eDP HDMI DPIO driver vbios notes doc */
4429
4430         /* PLL B needs special handling */
4431         if (pipe)
4432                 vlv_pllb_recal_opamp(dev_priv);
4433
4434         /* Set up Tx target for periodic Rcomp update */
4435         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4436
4437         /* Disable target IRef on PLL */
4438         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4439         reg_val &= 0x00ffffff;
4440         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4441
4442         /* Disable fast lock */
4443         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4444
4445         /* Set idtafcrecal before PLL is enabled */
4446         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4447         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4448         mdiv |= ((bestn << DPIO_N_SHIFT));
4449         mdiv |= (1 << DPIO_K_SHIFT);
4450
4451         /*
4452          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4453          * but we don't support that).
4454          * Note: don't use the DAC post divider as it seems unstable.
4455          */
4456         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4457         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4458
4459         mdiv |= DPIO_ENABLE_CALIBRATION;
4460         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4461
4462         /* Set HBR and RBR LPF coefficients */
4463         if (crtc->config.port_clock == 162000 ||
4464             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4465                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4466                                  0x005f0021);
4467         else
4468                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4469                                  0x00d0000f);
4470
4471         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4472             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4473                 /* Use SSC source */
4474                 if (!pipe)
4475                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4476                                          0x0df40000);
4477                 else
4478                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4479                                          0x0df70000);
4480         } else { /* HDMI or VGA */
4481                 /* Use bend source */
4482                 if (!pipe)
4483                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4484                                          0x0df70000);
4485                 else
4486                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4487                                          0x0df40000);
4488         }
4489
4490         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4491         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4492         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4493             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4494                 coreclk |= 0x01000000;
4495         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4496
4497         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4498
4499         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4500                 if (encoder->pre_pll_enable)
4501                         encoder->pre_pll_enable(encoder);
4502
4503         /* Enable DPIO clock input */
4504         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4505                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4506         if (pipe)
4507                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4508
4509         dpll |= DPLL_VCO_ENABLE;
4510         I915_WRITE(DPLL(pipe), dpll);
4511         POSTING_READ(DPLL(pipe));
4512         udelay(150);
4513
4514         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4515                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4516
4517         dpll_md = (crtc->config.pixel_multiplier - 1)
4518                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4519         I915_WRITE(DPLL_MD(pipe), dpll_md);
4520         POSTING_READ(DPLL_MD(pipe));
4521
4522         if (crtc->config.has_dp_encoder)
4523                 intel_dp_set_m_n(crtc);
4524
4525         mutex_unlock(&dev_priv->dpio_lock);
4526 }
4527
4528 static void i9xx_update_pll(struct intel_crtc *crtc,
4529                             intel_clock_t *reduced_clock,
4530                             int num_connectors)
4531 {
4532         struct drm_device *dev = crtc->base.dev;
4533         struct drm_i915_private *dev_priv = dev->dev_private;
4534         struct intel_encoder *encoder;
4535         int pipe = crtc->pipe;
4536         u32 dpll;
4537         bool is_sdvo;
4538         struct dpll *clock = &crtc->config.dpll;
4539
4540         i9xx_update_pll_dividers(crtc, reduced_clock);
4541
4542         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4543                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4544
4545         dpll = DPLL_VGA_MODE_DIS;
4546
4547         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4548                 dpll |= DPLLB_MODE_LVDS;
4549         else
4550                 dpll |= DPLLB_MODE_DAC_SERIAL;
4551
4552         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4553                 dpll |= (crtc->config.pixel_multiplier - 1)
4554                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4555         }
4556
4557         if (is_sdvo)
4558                 dpll |= DPLL_DVO_HIGH_SPEED;
4559
4560         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4561                 dpll |= DPLL_DVO_HIGH_SPEED;
4562
4563         /* compute bitmask from p1 value */
4564         if (IS_PINEVIEW(dev))
4565                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4566         else {
4567                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4568                 if (IS_G4X(dev) && reduced_clock)
4569                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4570         }
4571         switch (clock->p2) {
4572         case 5:
4573                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4574                 break;
4575         case 7:
4576                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4577                 break;
4578         case 10:
4579                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4580                 break;
4581         case 14:
4582                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4583                 break;
4584         }
4585         if (INTEL_INFO(dev)->gen >= 4)
4586                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4587
4588         if (crtc->config.sdvo_tv_clock)
4589                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4590         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4591                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4593         else
4594                 dpll |= PLL_REF_INPUT_DREFCLK;
4595
4596         dpll |= DPLL_VCO_ENABLE;
4597         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4598         POSTING_READ(DPLL(pipe));
4599         udelay(150);
4600
4601         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4602                 if (encoder->pre_pll_enable)
4603                         encoder->pre_pll_enable(encoder);
4604
4605         if (crtc->config.has_dp_encoder)
4606                 intel_dp_set_m_n(crtc);
4607
4608         I915_WRITE(DPLL(pipe), dpll);
4609
4610         /* Wait for the clocks to stabilize. */
4611         POSTING_READ(DPLL(pipe));
4612         udelay(150);
4613
4614         if (INTEL_INFO(dev)->gen >= 4) {
4615                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4616                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4617                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4618         } else {
4619                 /* The pixel multiplier can only be updated once the
4620                  * DPLL is enabled and the clocks are stable.
4621                  *
4622                  * So write it again.
4623                  */
4624                 I915_WRITE(DPLL(pipe), dpll);
4625         }
4626 }
4627
4628 static void i8xx_update_pll(struct intel_crtc *crtc,
4629                             intel_clock_t *reduced_clock,
4630                             int num_connectors)
4631 {
4632         struct drm_device *dev = crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         struct intel_encoder *encoder;
4635         int pipe = crtc->pipe;
4636         u32 dpll;
4637         struct dpll *clock = &crtc->config.dpll;
4638
4639         i9xx_update_pll_dividers(crtc, reduced_clock);
4640
4641         dpll = DPLL_VGA_MODE_DIS;
4642
4643         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4644                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4645         } else {
4646                 if (clock->p1 == 2)
4647                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4648                 else
4649                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4650                 if (clock->p2 == 4)
4651                         dpll |= PLL_P2_DIVIDE_BY_4;
4652         }
4653
4654         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4655                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4656                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4657         else
4658                 dpll |= PLL_REF_INPUT_DREFCLK;
4659
4660         dpll |= DPLL_VCO_ENABLE;
4661         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4662         POSTING_READ(DPLL(pipe));
4663         udelay(150);
4664
4665         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4666                 if (encoder->pre_pll_enable)
4667                         encoder->pre_pll_enable(encoder);
4668
4669         I915_WRITE(DPLL(pipe), dpll);
4670
4671         /* Wait for the clocks to stabilize. */
4672         POSTING_READ(DPLL(pipe));
4673         udelay(150);
4674
4675         /* The pixel multiplier can only be updated once the
4676          * DPLL is enabled and the clocks are stable.
4677          *
4678          * So write it again.
4679          */
4680         I915_WRITE(DPLL(pipe), dpll);
4681 }
4682
4683 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4684 {
4685         struct drm_device *dev = intel_crtc->base.dev;
4686         struct drm_i915_private *dev_priv = dev->dev_private;
4687         enum pipe pipe = intel_crtc->pipe;
4688         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4689         struct drm_display_mode *adjusted_mode =
4690                 &intel_crtc->config.adjusted_mode;
4691         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4692         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4693
4694         /* We need to be careful not to changed the adjusted mode, for otherwise
4695          * the hw state checker will get angry at the mismatch. */
4696         crtc_vtotal = adjusted_mode->crtc_vtotal;
4697         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4698
4699         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4700                 /* the chip adds 2 halflines automatically */
4701                 crtc_vtotal -= 1;
4702                 crtc_vblank_end -= 1;
4703                 vsyncshift = adjusted_mode->crtc_hsync_start
4704                              - adjusted_mode->crtc_htotal / 2;
4705         } else {
4706                 vsyncshift = 0;
4707         }
4708
4709         if (INTEL_INFO(dev)->gen > 3)
4710                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4711
4712         I915_WRITE(HTOTAL(cpu_transcoder),
4713                    (adjusted_mode->crtc_hdisplay - 1) |
4714                    ((adjusted_mode->crtc_htotal - 1) << 16));
4715         I915_WRITE(HBLANK(cpu_transcoder),
4716                    (adjusted_mode->crtc_hblank_start - 1) |
4717                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4718         I915_WRITE(HSYNC(cpu_transcoder),
4719                    (adjusted_mode->crtc_hsync_start - 1) |
4720                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4721
4722         I915_WRITE(VTOTAL(cpu_transcoder),
4723                    (adjusted_mode->crtc_vdisplay - 1) |
4724                    ((crtc_vtotal - 1) << 16));
4725         I915_WRITE(VBLANK(cpu_transcoder),
4726                    (adjusted_mode->crtc_vblank_start - 1) |
4727                    ((crtc_vblank_end - 1) << 16));
4728         I915_WRITE(VSYNC(cpu_transcoder),
4729                    (adjusted_mode->crtc_vsync_start - 1) |
4730                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4731
4732         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4733          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4734          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4735          * bits. */
4736         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4737             (pipe == PIPE_B || pipe == PIPE_C))
4738                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4739
4740         /* pipesrc controls the size that is scaled from, which should
4741          * always be the user's requested size.
4742          */
4743         I915_WRITE(PIPESRC(pipe),
4744                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4745 }
4746
4747 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4748                                    struct intel_crtc_config *pipe_config)
4749 {
4750         struct drm_device *dev = crtc->base.dev;
4751         struct drm_i915_private *dev_priv = dev->dev_private;
4752         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4753         uint32_t tmp;
4754
4755         tmp = I915_READ(HTOTAL(cpu_transcoder));
4756         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4757         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4758         tmp = I915_READ(HBLANK(cpu_transcoder));
4759         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4760         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4761         tmp = I915_READ(HSYNC(cpu_transcoder));
4762         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4763         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765         tmp = I915_READ(VTOTAL(cpu_transcoder));
4766         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4767         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4768         tmp = I915_READ(VBLANK(cpu_transcoder));
4769         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4770         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4771         tmp = I915_READ(VSYNC(cpu_transcoder));
4772         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4773         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4774
4775         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4776                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4777                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4778                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4779         }
4780
4781         tmp = I915_READ(PIPESRC(crtc->pipe));
4782         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4783         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4784 }
4785
4786 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4787 {
4788         struct drm_device *dev = intel_crtc->base.dev;
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         uint32_t pipeconf;
4791
4792         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4793
4794         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4795                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4796                  * core speed.
4797                  *
4798                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4799                  * pipe == 0 check?
4800                  */
4801                 if (intel_crtc->config.requested_mode.clock >
4802                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4803                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4804                 else
4805                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4806         }
4807
4808         /* only g4x and later have fancy bpc/dither controls */
4809         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4810                 pipeconf &= ~(PIPECONF_BPC_MASK |
4811                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4812
4813                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4814                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4815                         pipeconf |= PIPECONF_DITHER_EN |
4816                                     PIPECONF_DITHER_TYPE_SP;
4817
4818                 switch (intel_crtc->config.pipe_bpp) {
4819                 case 18:
4820                         pipeconf |= PIPECONF_6BPC;
4821                         break;
4822                 case 24:
4823                         pipeconf |= PIPECONF_8BPC;
4824                         break;
4825                 case 30:
4826                         pipeconf |= PIPECONF_10BPC;
4827                         break;
4828                 default:
4829                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4830                         BUG();
4831                 }
4832         }
4833
4834         if (HAS_PIPE_CXSR(dev)) {
4835                 if (intel_crtc->lowfreq_avail) {
4836                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4837                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4838                 } else {
4839                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4840                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4841                 }
4842         }
4843
4844         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4845         if (!IS_GEN2(dev) &&
4846             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4847                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4848         else
4849                 pipeconf |= PIPECONF_PROGRESSIVE;
4850
4851         if (IS_VALLEYVIEW(dev)) {
4852                 if (intel_crtc->config.limited_color_range)
4853                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4854                 else
4855                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4856         }
4857
4858         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859         POSTING_READ(PIPECONF(intel_crtc->pipe));
4860 }
4861
4862 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4863                               int x, int y,
4864                               struct drm_framebuffer *fb)
4865 {
4866         struct drm_device *dev = crtc->dev;
4867         struct drm_i915_private *dev_priv = dev->dev_private;
4868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4870         int pipe = intel_crtc->pipe;
4871         int plane = intel_crtc->plane;
4872         int refclk, num_connectors = 0;
4873         intel_clock_t clock, reduced_clock;
4874         u32 dspcntr;
4875         bool ok, has_reduced_clock = false;
4876         bool is_lvds = false;
4877         struct intel_encoder *encoder;
4878         const intel_limit_t *limit;
4879         int ret;
4880
4881         for_each_encoder_on_crtc(dev, crtc, encoder) {
4882                 switch (encoder->type) {
4883                 case INTEL_OUTPUT_LVDS:
4884                         is_lvds = true;
4885                         break;
4886                 }
4887
4888                 num_connectors++;
4889         }
4890
4891         refclk = i9xx_get_refclk(crtc, num_connectors);
4892
4893         /*
4894          * Returns a set of divisors for the desired target clock with the given
4895          * refclk, or FALSE.  The returned values represent the clock equation:
4896          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4897          */
4898         limit = intel_limit(crtc, refclk);
4899         ok = dev_priv->display.find_dpll(limit, crtc,
4900                                          intel_crtc->config.port_clock,
4901                                          refclk, NULL, &clock);
4902         if (!ok && !intel_crtc->config.clock_set) {
4903                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4904                 return -EINVAL;
4905         }
4906
4907         /* Ensure that the cursor is valid for the new mode before changing... */
4908         intel_crtc_update_cursor(crtc, true);
4909
4910         if (is_lvds && dev_priv->lvds_downclock_avail) {
4911                 /*
4912                  * Ensure we match the reduced clock's P to the target clock.
4913                  * If the clocks don't match, we can't switch the display clock
4914                  * by using the FP0/FP1. In such case we will disable the LVDS
4915                  * downclock feature.
4916                 */
4917                 has_reduced_clock =
4918                         dev_priv->display.find_dpll(limit, crtc,
4919                                                     dev_priv->lvds_downclock,
4920                                                     refclk, &clock,
4921                                                     &reduced_clock);
4922         }
4923         /* Compat-code for transition, will disappear. */
4924         if (!intel_crtc->config.clock_set) {
4925                 intel_crtc->config.dpll.n = clock.n;
4926                 intel_crtc->config.dpll.m1 = clock.m1;
4927                 intel_crtc->config.dpll.m2 = clock.m2;
4928                 intel_crtc->config.dpll.p1 = clock.p1;
4929                 intel_crtc->config.dpll.p2 = clock.p2;
4930         }
4931
4932         if (IS_GEN2(dev))
4933                 i8xx_update_pll(intel_crtc,
4934                                 has_reduced_clock ? &reduced_clock : NULL,
4935                                 num_connectors);
4936         else if (IS_VALLEYVIEW(dev))
4937                 vlv_update_pll(intel_crtc);
4938         else
4939                 i9xx_update_pll(intel_crtc,
4940                                 has_reduced_clock ? &reduced_clock : NULL,
4941                                 num_connectors);
4942
4943         /* Set up the display plane register */
4944         dspcntr = DISPPLANE_GAMMA_ENABLE;
4945
4946         if (!IS_VALLEYVIEW(dev)) {
4947                 if (pipe == 0)
4948                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4949                 else
4950                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4951         }
4952
4953         intel_set_pipe_timings(intel_crtc);
4954
4955         /* pipesrc and dspsize control the size that is scaled from,
4956          * which should always be the user's requested size.
4957          */
4958         I915_WRITE(DSPSIZE(plane),
4959                    ((mode->vdisplay - 1) << 16) |
4960                    (mode->hdisplay - 1));
4961         I915_WRITE(DSPPOS(plane), 0);
4962
4963         i9xx_set_pipeconf(intel_crtc);
4964
4965         I915_WRITE(DSPCNTR(plane), dspcntr);
4966         POSTING_READ(DSPCNTR(plane));
4967
4968         ret = intel_pipe_set_base(crtc, x, y, fb);
4969
4970         intel_update_watermarks(dev);
4971
4972         return ret;
4973 }
4974
4975 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4976                                  struct intel_crtc_config *pipe_config)
4977 {
4978         struct drm_device *dev = crtc->base.dev;
4979         struct drm_i915_private *dev_priv = dev->dev_private;
4980         uint32_t tmp;
4981
4982         tmp = I915_READ(PFIT_CONTROL);
4983
4984         if (INTEL_INFO(dev)->gen < 4) {
4985                 if (crtc->pipe != PIPE_B)
4986                         return;
4987
4988                 /* gen2/3 store dither state in pfit control, needs to match */
4989                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4990         } else {
4991                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4992                         return;
4993         }
4994
4995         if (!(tmp & PFIT_ENABLE))
4996                 return;
4997
4998         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4999         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5000         if (INTEL_INFO(dev)->gen < 5)
5001                 pipe_config->gmch_pfit.lvds_border_bits =
5002                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5003 }
5004
5005 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5006                                  struct intel_crtc_config *pipe_config)
5007 {
5008         struct drm_device *dev = crtc->base.dev;
5009         struct drm_i915_private *dev_priv = dev->dev_private;
5010         uint32_t tmp;
5011
5012         pipe_config->cpu_transcoder = crtc->pipe;
5013
5014         tmp = I915_READ(PIPECONF(crtc->pipe));
5015         if (!(tmp & PIPECONF_ENABLE))
5016                 return false;
5017
5018         intel_get_pipe_timings(crtc, pipe_config);
5019
5020         i9xx_get_pfit_config(crtc, pipe_config);
5021
5022         if (INTEL_INFO(dev)->gen >= 4) {
5023                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5024                 pipe_config->pixel_multiplier =
5025                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5026                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5027         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5028                 tmp = I915_READ(DPLL(crtc->pipe));
5029                 pipe_config->pixel_multiplier =
5030                         ((tmp & SDVO_MULTIPLIER_MASK)
5031                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5032         } else {
5033                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5034                  * port and will be fixed up in the encoder->get_config
5035                  * function. */
5036                 pipe_config->pixel_multiplier = 1;
5037         }
5038
5039         return true;
5040 }
5041
5042 static void ironlake_init_pch_refclk(struct drm_device *dev)
5043 {
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045         struct drm_mode_config *mode_config = &dev->mode_config;
5046         struct intel_encoder *encoder;
5047         u32 val, final;
5048         bool has_lvds = false;
5049         bool has_cpu_edp = false;
5050         bool has_panel = false;
5051         bool has_ck505 = false;
5052         bool can_ssc = false;
5053
5054         /* We need to take the global config into account */
5055         list_for_each_entry(encoder, &mode_config->encoder_list,
5056                             base.head) {
5057                 switch (encoder->type) {
5058                 case INTEL_OUTPUT_LVDS:
5059                         has_panel = true;
5060                         has_lvds = true;
5061                         break;
5062                 case INTEL_OUTPUT_EDP:
5063                         has_panel = true;
5064                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5065                                 has_cpu_edp = true;
5066                         break;
5067                 }
5068         }
5069
5070         if (HAS_PCH_IBX(dev)) {
5071                 has_ck505 = dev_priv->vbt.display_clock_mode;
5072                 can_ssc = has_ck505;
5073         } else {
5074                 has_ck505 = false;
5075                 can_ssc = true;
5076         }
5077
5078         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5079                       has_panel, has_lvds, has_ck505);
5080
5081         /* Ironlake: try to setup display ref clock before DPLL
5082          * enabling. This is only under driver's control after
5083          * PCH B stepping, previous chipset stepping should be
5084          * ignoring this setting.
5085          */
5086         val = I915_READ(PCH_DREF_CONTROL);
5087
5088         /* As we must carefully and slowly disable/enable each source in turn,
5089          * compute the final state we want first and check if we need to
5090          * make any changes at all.
5091          */
5092         final = val;
5093         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5094         if (has_ck505)
5095                 final |= DREF_NONSPREAD_CK505_ENABLE;
5096         else
5097                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5098
5099         final &= ~DREF_SSC_SOURCE_MASK;
5100         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5101         final &= ~DREF_SSC1_ENABLE;
5102
5103         if (has_panel) {
5104                 final |= DREF_SSC_SOURCE_ENABLE;
5105
5106                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5107                         final |= DREF_SSC1_ENABLE;
5108
5109                 if (has_cpu_edp) {
5110                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5111                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5112                         else
5113                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5114                 } else
5115                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5116         } else {
5117                 final |= DREF_SSC_SOURCE_DISABLE;
5118                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119         }
5120
5121         if (final == val)
5122                 return;
5123
5124         /* Always enable nonspread source */
5125         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5126
5127         if (has_ck505)
5128                 val |= DREF_NONSPREAD_CK505_ENABLE;
5129         else
5130                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5131
5132         if (has_panel) {
5133                 val &= ~DREF_SSC_SOURCE_MASK;
5134                 val |= DREF_SSC_SOURCE_ENABLE;
5135
5136                 /* SSC must be turned on before enabling the CPU output  */
5137                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5138                         DRM_DEBUG_KMS("Using SSC on panel\n");
5139                         val |= DREF_SSC1_ENABLE;
5140                 } else
5141                         val &= ~DREF_SSC1_ENABLE;
5142
5143                 /* Get SSC going before enabling the outputs */
5144                 I915_WRITE(PCH_DREF_CONTROL, val);
5145                 POSTING_READ(PCH_DREF_CONTROL);
5146                 udelay(200);
5147
5148                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5149
5150                 /* Enable CPU source on CPU attached eDP */
5151                 if (has_cpu_edp) {
5152                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5153                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5154                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5155                         }
5156                         else
5157                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5158                 } else
5159                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5160
5161                 I915_WRITE(PCH_DREF_CONTROL, val);
5162                 POSTING_READ(PCH_DREF_CONTROL);
5163                 udelay(200);
5164         } else {
5165                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5166
5167                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5168
5169                 /* Turn off CPU output */
5170                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5171
5172                 I915_WRITE(PCH_DREF_CONTROL, val);
5173                 POSTING_READ(PCH_DREF_CONTROL);
5174                 udelay(200);
5175
5176                 /* Turn off the SSC source */
5177                 val &= ~DREF_SSC_SOURCE_MASK;
5178                 val |= DREF_SSC_SOURCE_DISABLE;
5179
5180                 /* Turn off SSC1 */
5181                 val &= ~DREF_SSC1_ENABLE;
5182
5183                 I915_WRITE(PCH_DREF_CONTROL, val);
5184                 POSTING_READ(PCH_DREF_CONTROL);
5185                 udelay(200);
5186         }
5187
5188         BUG_ON(val != final);
5189 }
5190
5191 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5192 static void lpt_init_pch_refclk(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195         struct drm_mode_config *mode_config = &dev->mode_config;
5196         struct intel_encoder *encoder;
5197         bool has_vga = false;
5198         bool is_sdv = false;
5199         u32 tmp;
5200
5201         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5202                 switch (encoder->type) {
5203                 case INTEL_OUTPUT_ANALOG:
5204                         has_vga = true;
5205                         break;
5206                 }
5207         }
5208
5209         if (!has_vga)
5210                 return;
5211
5212         mutex_lock(&dev_priv->dpio_lock);
5213
5214         /* XXX: Rip out SDV support once Haswell ships for real. */
5215         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5216                 is_sdv = true;
5217
5218         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5219         tmp &= ~SBI_SSCCTL_DISABLE;
5220         tmp |= SBI_SSCCTL_PATHALT;
5221         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5222
5223         udelay(24);
5224
5225         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5226         tmp &= ~SBI_SSCCTL_PATHALT;
5227         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5228
5229         if (!is_sdv) {
5230                 tmp = I915_READ(SOUTH_CHICKEN2);
5231                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5232                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5233
5234                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5235                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5236                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5237
5238                 tmp = I915_READ(SOUTH_CHICKEN2);
5239                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5240                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5241
5242                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5243                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5244                                        100))
5245                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5246         }
5247
5248         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5249         tmp &= ~(0xFF << 24);
5250         tmp |= (0x12 << 24);
5251         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5252
5253         if (is_sdv) {
5254                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5255                 tmp |= 0x7FFF;
5256                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5257         }
5258
5259         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5260         tmp |= (1 << 11);
5261         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5262
5263         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5264         tmp |= (1 << 11);
5265         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5266
5267         if (is_sdv) {
5268                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5269                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5270                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5271
5272                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5273                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5274                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5275
5276                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5277                 tmp |= (0x3F << 8);
5278                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5279
5280                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5281                 tmp |= (0x3F << 8);
5282                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5283         }
5284
5285         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5286         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5287         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5288
5289         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5290         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5291         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5292
5293         if (!is_sdv) {
5294                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5295                 tmp &= ~(7 << 13);
5296                 tmp |= (5 << 13);
5297                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5298
5299                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5300                 tmp &= ~(7 << 13);
5301                 tmp |= (5 << 13);
5302                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5303         }
5304
5305         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5306         tmp &= ~0xFF;
5307         tmp |= 0x1C;
5308         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5309
5310         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5311         tmp &= ~0xFF;
5312         tmp |= 0x1C;
5313         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5314
5315         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5316         tmp &= ~(0xFF << 16);
5317         tmp |= (0x1C << 16);
5318         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5319
5320         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5321         tmp &= ~(0xFF << 16);
5322         tmp |= (0x1C << 16);
5323         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5324
5325         if (!is_sdv) {
5326                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5327                 tmp |= (1 << 27);
5328                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5329
5330                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5331                 tmp |= (1 << 27);
5332                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5333
5334                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5335                 tmp &= ~(0xF << 28);
5336                 tmp |= (4 << 28);
5337                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5338
5339                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5340                 tmp &= ~(0xF << 28);
5341                 tmp |= (4 << 28);
5342                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5343         }
5344
5345         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5346         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5347         tmp |= SBI_DBUFF0_ENABLE;
5348         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5349
5350         mutex_unlock(&dev_priv->dpio_lock);
5351 }
5352
5353 /*
5354  * Initialize reference clocks when the driver loads
5355  */
5356 void intel_init_pch_refclk(struct drm_device *dev)
5357 {
5358         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5359                 ironlake_init_pch_refclk(dev);
5360         else if (HAS_PCH_LPT(dev))
5361                 lpt_init_pch_refclk(dev);
5362 }
5363
5364 static int ironlake_get_refclk(struct drm_crtc *crtc)
5365 {
5366         struct drm_device *dev = crtc->dev;
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368         struct intel_encoder *encoder;
5369         int num_connectors = 0;
5370         bool is_lvds = false;
5371
5372         for_each_encoder_on_crtc(dev, crtc, encoder) {
5373                 switch (encoder->type) {
5374                 case INTEL_OUTPUT_LVDS:
5375                         is_lvds = true;
5376                         break;
5377                 }
5378                 num_connectors++;
5379         }
5380
5381         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5382                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5383                               dev_priv->vbt.lvds_ssc_freq);
5384                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5385         }
5386
5387         return 120000;
5388 }
5389
5390 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5391 {
5392         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394         int pipe = intel_crtc->pipe;
5395         uint32_t val;
5396
5397         val = I915_READ(PIPECONF(pipe));
5398
5399         val &= ~PIPECONF_BPC_MASK;
5400         switch (intel_crtc->config.pipe_bpp) {
5401         case 18:
5402                 val |= PIPECONF_6BPC;
5403                 break;
5404         case 24:
5405                 val |= PIPECONF_8BPC;
5406                 break;
5407         case 30:
5408                 val |= PIPECONF_10BPC;
5409                 break;
5410         case 36:
5411                 val |= PIPECONF_12BPC;
5412                 break;
5413         default:
5414                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5415                 BUG();
5416         }
5417
5418         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5419         if (intel_crtc->config.dither)
5420                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5421
5422         val &= ~PIPECONF_INTERLACE_MASK;
5423         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5424                 val |= PIPECONF_INTERLACED_ILK;
5425         else
5426                 val |= PIPECONF_PROGRESSIVE;
5427
5428         if (intel_crtc->config.limited_color_range)
5429                 val |= PIPECONF_COLOR_RANGE_SELECT;
5430         else
5431                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5432
5433         I915_WRITE(PIPECONF(pipe), val);
5434         POSTING_READ(PIPECONF(pipe));
5435 }
5436
5437 /*
5438  * Set up the pipe CSC unit.
5439  *
5440  * Currently only full range RGB to limited range RGB conversion
5441  * is supported, but eventually this should handle various
5442  * RGB<->YCbCr scenarios as well.
5443  */
5444 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5445 {
5446         struct drm_device *dev = crtc->dev;
5447         struct drm_i915_private *dev_priv = dev->dev_private;
5448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5449         int pipe = intel_crtc->pipe;
5450         uint16_t coeff = 0x7800; /* 1.0 */
5451
5452         /*
5453          * TODO: Check what kind of values actually come out of the pipe
5454          * with these coeff/postoff values and adjust to get the best
5455          * accuracy. Perhaps we even need to take the bpc value into
5456          * consideration.
5457          */
5458
5459         if (intel_crtc->config.limited_color_range)
5460                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5461
5462         /*
5463          * GY/GU and RY/RU should be the other way around according
5464          * to BSpec, but reality doesn't agree. Just set them up in
5465          * a way that results in the correct picture.
5466          */
5467         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5468         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5469
5470         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5471         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5472
5473         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5474         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5475
5476         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5477         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5478         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5479
5480         if (INTEL_INFO(dev)->gen > 6) {
5481                 uint16_t postoff = 0;
5482
5483                 if (intel_crtc->config.limited_color_range)
5484                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5485
5486                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5487                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5488                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5489
5490                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5491         } else {
5492                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5493
5494                 if (intel_crtc->config.limited_color_range)
5495                         mode |= CSC_BLACK_SCREEN_OFFSET;
5496
5497                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5498         }
5499 }
5500
5501 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5502 {
5503         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5505         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5506         uint32_t val;
5507
5508         val = I915_READ(PIPECONF(cpu_transcoder));
5509
5510         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5511         if (intel_crtc->config.dither)
5512                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5513
5514         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5515         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5516                 val |= PIPECONF_INTERLACED_ILK;
5517         else
5518                 val |= PIPECONF_PROGRESSIVE;
5519
5520         I915_WRITE(PIPECONF(cpu_transcoder), val);
5521         POSTING_READ(PIPECONF(cpu_transcoder));
5522 }
5523
5524 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5525                                     intel_clock_t *clock,
5526                                     bool *has_reduced_clock,
5527                                     intel_clock_t *reduced_clock)
5528 {
5529         struct drm_device *dev = crtc->dev;
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531         struct intel_encoder *intel_encoder;
5532         int refclk;
5533         const intel_limit_t *limit;
5534         bool ret, is_lvds = false;
5535
5536         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5537                 switch (intel_encoder->type) {
5538                 case INTEL_OUTPUT_LVDS:
5539                         is_lvds = true;
5540                         break;
5541                 }
5542         }
5543
5544         refclk = ironlake_get_refclk(crtc);
5545
5546         /*
5547          * Returns a set of divisors for the desired target clock with the given
5548          * refclk, or FALSE.  The returned values represent the clock equation:
5549          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5550          */
5551         limit = intel_limit(crtc, refclk);
5552         ret = dev_priv->display.find_dpll(limit, crtc,
5553                                           to_intel_crtc(crtc)->config.port_clock,
5554                                           refclk, NULL, clock);
5555         if (!ret)
5556                 return false;
5557
5558         if (is_lvds && dev_priv->lvds_downclock_avail) {
5559                 /*
5560                  * Ensure we match the reduced clock's P to the target clock.
5561                  * If the clocks don't match, we can't switch the display clock
5562                  * by using the FP0/FP1. In such case we will disable the LVDS
5563                  * downclock feature.
5564                 */
5565                 *has_reduced_clock =
5566                         dev_priv->display.find_dpll(limit, crtc,
5567                                                     dev_priv->lvds_downclock,
5568                                                     refclk, clock,
5569                                                     reduced_clock);
5570         }
5571
5572         return true;
5573 }
5574
5575 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5576 {
5577         struct drm_i915_private *dev_priv = dev->dev_private;
5578         uint32_t temp;
5579
5580         temp = I915_READ(SOUTH_CHICKEN1);
5581         if (temp & FDI_BC_BIFURCATION_SELECT)
5582                 return;
5583
5584         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5585         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5586
5587         temp |= FDI_BC_BIFURCATION_SELECT;
5588         DRM_DEBUG_KMS("enabling fdi C rx\n");
5589         I915_WRITE(SOUTH_CHICKEN1, temp);
5590         POSTING_READ(SOUTH_CHICKEN1);
5591 }
5592
5593 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5594 {
5595         struct drm_device *dev = intel_crtc->base.dev;
5596         struct drm_i915_private *dev_priv = dev->dev_private;
5597
5598         switch (intel_crtc->pipe) {
5599         case PIPE_A:
5600                 break;
5601         case PIPE_B:
5602                 if (intel_crtc->config.fdi_lanes > 2)
5603                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5604                 else
5605                         cpt_enable_fdi_bc_bifurcation(dev);
5606
5607                 break;
5608         case PIPE_C:
5609                 cpt_enable_fdi_bc_bifurcation(dev);
5610
5611                 break;
5612         default:
5613                 BUG();
5614         }
5615 }
5616
5617 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5618 {
5619         /*
5620          * Account for spread spectrum to avoid
5621          * oversubscribing the link. Max center spread
5622          * is 2.5%; use 5% for safety's sake.
5623          */
5624         u32 bps = target_clock * bpp * 21 / 20;
5625         return bps / (link_bw * 8) + 1;
5626 }
5627
5628 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5629 {
5630         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5631 }
5632
5633 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5634                                       u32 *fp,
5635                                       intel_clock_t *reduced_clock, u32 *fp2)
5636 {
5637         struct drm_crtc *crtc = &intel_crtc->base;
5638         struct drm_device *dev = crtc->dev;
5639         struct drm_i915_private *dev_priv = dev->dev_private;
5640         struct intel_encoder *intel_encoder;
5641         uint32_t dpll;
5642         int factor, num_connectors = 0;
5643         bool is_lvds = false, is_sdvo = false;
5644
5645         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5646                 switch (intel_encoder->type) {
5647                 case INTEL_OUTPUT_LVDS:
5648                         is_lvds = true;
5649                         break;
5650                 case INTEL_OUTPUT_SDVO:
5651                 case INTEL_OUTPUT_HDMI:
5652                         is_sdvo = true;
5653                         break;
5654                 }
5655
5656                 num_connectors++;
5657         }
5658
5659         /* Enable autotuning of the PLL clock (if permissible) */
5660         factor = 21;
5661         if (is_lvds) {
5662                 if ((intel_panel_use_ssc(dev_priv) &&
5663                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5664                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5665                         factor = 25;
5666         } else if (intel_crtc->config.sdvo_tv_clock)
5667                 factor = 20;
5668
5669         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5670                 *fp |= FP_CB_TUNE;
5671
5672         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5673                 *fp2 |= FP_CB_TUNE;
5674
5675         dpll = 0;
5676
5677         if (is_lvds)
5678                 dpll |= DPLLB_MODE_LVDS;
5679         else
5680                 dpll |= DPLLB_MODE_DAC_SERIAL;
5681
5682         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5683                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5684
5685         if (is_sdvo)
5686                 dpll |= DPLL_DVO_HIGH_SPEED;
5687         if (intel_crtc->config.has_dp_encoder)
5688                 dpll |= DPLL_DVO_HIGH_SPEED;
5689
5690         /* compute bitmask from p1 value */
5691         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5692         /* also FPA1 */
5693         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5694
5695         switch (intel_crtc->config.dpll.p2) {
5696         case 5:
5697                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5698                 break;
5699         case 7:
5700                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5701                 break;
5702         case 10:
5703                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5704                 break;
5705         case 14:
5706                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5707                 break;
5708         }
5709
5710         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5711                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5712         else
5713                 dpll |= PLL_REF_INPUT_DREFCLK;
5714
5715         return dpll;
5716 }
5717
5718 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5719                                   int x, int y,
5720                                   struct drm_framebuffer *fb)
5721 {
5722         struct drm_device *dev = crtc->dev;
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725         int pipe = intel_crtc->pipe;
5726         int plane = intel_crtc->plane;
5727         int num_connectors = 0;
5728         intel_clock_t clock, reduced_clock;
5729         u32 dpll = 0, fp = 0, fp2 = 0;
5730         bool ok, has_reduced_clock = false;
5731         bool is_lvds = false;
5732         struct intel_encoder *encoder;
5733         int ret;
5734
5735         for_each_encoder_on_crtc(dev, crtc, encoder) {
5736                 switch (encoder->type) {
5737                 case INTEL_OUTPUT_LVDS:
5738                         is_lvds = true;
5739                         break;
5740                 }
5741
5742                 num_connectors++;
5743         }
5744
5745         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5746              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5747
5748         ok = ironlake_compute_clocks(crtc, &clock,
5749                                      &has_reduced_clock, &reduced_clock);
5750         if (!ok && !intel_crtc->config.clock_set) {
5751                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5752                 return -EINVAL;
5753         }
5754         /* Compat-code for transition, will disappear. */
5755         if (!intel_crtc->config.clock_set) {
5756                 intel_crtc->config.dpll.n = clock.n;
5757                 intel_crtc->config.dpll.m1 = clock.m1;
5758                 intel_crtc->config.dpll.m2 = clock.m2;
5759                 intel_crtc->config.dpll.p1 = clock.p1;
5760                 intel_crtc->config.dpll.p2 = clock.p2;
5761         }
5762
5763         /* Ensure that the cursor is valid for the new mode before changing... */
5764         intel_crtc_update_cursor(crtc, true);
5765
5766         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5767         if (intel_crtc->config.has_pch_encoder) {
5768                 struct intel_pch_pll *pll;
5769
5770                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5771                 if (has_reduced_clock)
5772                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5773
5774                 dpll = ironlake_compute_dpll(intel_crtc,
5775                                              &fp, &reduced_clock,
5776                                              has_reduced_clock ? &fp2 : NULL);
5777
5778                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5779                 if (pll == NULL) {
5780                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5781                                          pipe_name(pipe));
5782                         return -EINVAL;
5783                 }
5784         } else
5785                 intel_put_pch_pll(intel_crtc);
5786
5787         if (intel_crtc->config.has_dp_encoder)
5788                 intel_dp_set_m_n(intel_crtc);
5789
5790         for_each_encoder_on_crtc(dev, crtc, encoder)
5791                 if (encoder->pre_pll_enable)
5792                         encoder->pre_pll_enable(encoder);
5793
5794         if (intel_crtc->pch_pll) {
5795                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5796
5797                 /* Wait for the clocks to stabilize. */
5798                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5799                 udelay(150);
5800
5801                 /* The pixel multiplier can only be updated once the
5802                  * DPLL is enabled and the clocks are stable.
5803                  *
5804                  * So write it again.
5805                  */
5806                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5807         }
5808
5809         intel_crtc->lowfreq_avail = false;
5810         if (intel_crtc->pch_pll) {
5811                 if (is_lvds && has_reduced_clock && i915_powersave) {
5812                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5813                         intel_crtc->lowfreq_avail = true;
5814                 } else {
5815                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5816                 }
5817         }
5818
5819         intel_set_pipe_timings(intel_crtc);
5820
5821         if (intel_crtc->config.has_pch_encoder) {
5822                 intel_cpu_transcoder_set_m_n(intel_crtc,
5823                                              &intel_crtc->config.fdi_m_n);
5824         }
5825
5826         if (IS_IVYBRIDGE(dev))
5827                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5828
5829         ironlake_set_pipeconf(crtc);
5830
5831         /* Set up the display plane register */
5832         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5833         POSTING_READ(DSPCNTR(plane));
5834
5835         ret = intel_pipe_set_base(crtc, x, y, fb);
5836
5837         intel_update_watermarks(dev);
5838
5839         return ret;
5840 }
5841
5842 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5843                                         struct intel_crtc_config *pipe_config)
5844 {
5845         struct drm_device *dev = crtc->base.dev;
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         enum transcoder transcoder = pipe_config->cpu_transcoder;
5848
5849         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5850         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5851         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5852                                         & ~TU_SIZE_MASK;
5853         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5854         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5855                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5856 }
5857
5858 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5859                                      struct intel_crtc_config *pipe_config)
5860 {
5861         struct drm_device *dev = crtc->base.dev;
5862         struct drm_i915_private *dev_priv = dev->dev_private;
5863         uint32_t tmp;
5864
5865         tmp = I915_READ(PF_CTL(crtc->pipe));
5866
5867         if (tmp & PF_ENABLE) {
5868                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5869                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5870
5871                 /* We currently do not free assignements of panel fitters on
5872                  * ivb/hsw (since we don't use the higher upscaling modes which
5873                  * differentiates them) so just WARN about this case for now. */
5874                 if (IS_GEN7(dev)) {
5875                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5876                                 PF_PIPE_SEL_IVB(crtc->pipe));
5877                 }
5878         }
5879 }
5880
5881 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5882                                      struct intel_crtc_config *pipe_config)
5883 {
5884         struct drm_device *dev = crtc->base.dev;
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886         uint32_t tmp;
5887
5888         pipe_config->cpu_transcoder = crtc->pipe;
5889
5890         tmp = I915_READ(PIPECONF(crtc->pipe));
5891         if (!(tmp & PIPECONF_ENABLE))
5892                 return false;
5893
5894         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5895                 pipe_config->has_pch_encoder = true;
5896
5897                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5898                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5899                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5900
5901                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5902
5903                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5904                  * since we don't have state tracking for pch clocks yet. */
5905                 pipe_config->pixel_multiplier = 1;
5906         } else {
5907                 pipe_config->pixel_multiplier = 1;
5908         }
5909
5910         intel_get_pipe_timings(crtc, pipe_config);
5911
5912         ironlake_get_pfit_config(crtc, pipe_config);
5913
5914         return true;
5915 }
5916
5917 static void haswell_modeset_global_resources(struct drm_device *dev)
5918 {
5919         bool enable = false;
5920         struct intel_crtc *crtc;
5921
5922         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5923                 if (!crtc->base.enabled)
5924                         continue;
5925
5926                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5927                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5928                         enable = true;
5929         }
5930
5931         intel_set_power_well(dev, enable);
5932 }
5933
5934 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5935                                  int x, int y,
5936                                  struct drm_framebuffer *fb)
5937 {
5938         struct drm_device *dev = crtc->dev;
5939         struct drm_i915_private *dev_priv = dev->dev_private;
5940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5941         int plane = intel_crtc->plane;
5942         int ret;
5943
5944         if (!intel_ddi_pll_mode_set(crtc))
5945                 return -EINVAL;
5946
5947         /* Ensure that the cursor is valid for the new mode before changing... */
5948         intel_crtc_update_cursor(crtc, true);
5949
5950         if (intel_crtc->config.has_dp_encoder)
5951                 intel_dp_set_m_n(intel_crtc);
5952
5953         intel_crtc->lowfreq_avail = false;
5954
5955         intel_set_pipe_timings(intel_crtc);
5956
5957         if (intel_crtc->config.has_pch_encoder) {
5958                 intel_cpu_transcoder_set_m_n(intel_crtc,
5959                                              &intel_crtc->config.fdi_m_n);
5960         }
5961
5962         haswell_set_pipeconf(crtc);
5963
5964         intel_set_pipe_csc(crtc);
5965
5966         /* Set up the display plane register */
5967         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5968         POSTING_READ(DSPCNTR(plane));
5969
5970         ret = intel_pipe_set_base(crtc, x, y, fb);
5971
5972         intel_update_watermarks(dev);
5973
5974         return ret;
5975 }
5976
5977 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5978                                     struct intel_crtc_config *pipe_config)
5979 {
5980         struct drm_device *dev = crtc->base.dev;
5981         struct drm_i915_private *dev_priv = dev->dev_private;
5982         enum intel_display_power_domain pfit_domain;
5983         uint32_t tmp;
5984
5985         pipe_config->cpu_transcoder = crtc->pipe;
5986         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5987         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5988                 enum pipe trans_edp_pipe;
5989                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5990                 default:
5991                         WARN(1, "unknown pipe linked to edp transcoder\n");
5992                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5993                 case TRANS_DDI_EDP_INPUT_A_ON:
5994                         trans_edp_pipe = PIPE_A;
5995                         break;
5996                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5997                         trans_edp_pipe = PIPE_B;
5998                         break;
5999                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6000                         trans_edp_pipe = PIPE_C;
6001                         break;
6002                 }
6003
6004                 if (trans_edp_pipe == crtc->pipe)
6005                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6006         }
6007
6008         if (!intel_display_power_enabled(dev,
6009                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6010                 return false;
6011
6012         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6013         if (!(tmp & PIPECONF_ENABLE))
6014                 return false;
6015
6016         /*
6017          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6018          * DDI E. So just check whether this pipe is wired to DDI E and whether
6019          * the PCH transcoder is on.
6020          */
6021         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6022         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6023             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6024                 pipe_config->has_pch_encoder = true;
6025
6026                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6027                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6028                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6029
6030                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6031         }
6032
6033         intel_get_pipe_timings(crtc, pipe_config);
6034
6035         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6036         if (intel_display_power_enabled(dev, pfit_domain))
6037                 ironlake_get_pfit_config(crtc, pipe_config);
6038
6039         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6040                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6041
6042         pipe_config->pixel_multiplier = 1;
6043
6044         return true;
6045 }
6046
6047 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6048                                int x, int y,
6049                                struct drm_framebuffer *fb)
6050 {
6051         struct drm_device *dev = crtc->dev;
6052         struct drm_i915_private *dev_priv = dev->dev_private;
6053         struct drm_encoder_helper_funcs *encoder_funcs;
6054         struct intel_encoder *encoder;
6055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6056         struct drm_display_mode *adjusted_mode =
6057                 &intel_crtc->config.adjusted_mode;
6058         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6059         int pipe = intel_crtc->pipe;
6060         int ret;
6061
6062         drm_vblank_pre_modeset(dev, pipe);
6063
6064         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6065
6066         drm_vblank_post_modeset(dev, pipe);
6067
6068         if (ret != 0)
6069                 return ret;
6070
6071         for_each_encoder_on_crtc(dev, crtc, encoder) {
6072                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6073                         encoder->base.base.id,
6074                         drm_get_encoder_name(&encoder->base),
6075                         mode->base.id, mode->name);
6076                 if (encoder->mode_set) {
6077                         encoder->mode_set(encoder);
6078                 } else {
6079                         encoder_funcs = encoder->base.helper_private;
6080                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6081                 }
6082         }
6083
6084         return 0;
6085 }
6086
6087 static bool intel_eld_uptodate(struct drm_connector *connector,
6088                                int reg_eldv, uint32_t bits_eldv,
6089                                int reg_elda, uint32_t bits_elda,
6090                                int reg_edid)
6091 {
6092         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6093         uint8_t *eld = connector->eld;
6094         uint32_t i;
6095
6096         i = I915_READ(reg_eldv);
6097         i &= bits_eldv;
6098
6099         if (!eld[0])
6100                 return !i;
6101
6102         if (!i)
6103                 return false;
6104
6105         i = I915_READ(reg_elda);
6106         i &= ~bits_elda;
6107         I915_WRITE(reg_elda, i);
6108
6109         for (i = 0; i < eld[2]; i++)
6110                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6111                         return false;
6112
6113         return true;
6114 }
6115
6116 static void g4x_write_eld(struct drm_connector *connector,
6117                           struct drm_crtc *crtc)
6118 {
6119         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6120         uint8_t *eld = connector->eld;
6121         uint32_t eldv;
6122         uint32_t len;
6123         uint32_t i;
6124
6125         i = I915_READ(G4X_AUD_VID_DID);
6126
6127         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6128                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6129         else
6130                 eldv = G4X_ELDV_DEVCTG;
6131
6132         if (intel_eld_uptodate(connector,
6133                                G4X_AUD_CNTL_ST, eldv,
6134                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6135                                G4X_HDMIW_HDMIEDID))
6136                 return;
6137
6138         i = I915_READ(G4X_AUD_CNTL_ST);
6139         i &= ~(eldv | G4X_ELD_ADDR);
6140         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6141         I915_WRITE(G4X_AUD_CNTL_ST, i);
6142
6143         if (!eld[0])
6144                 return;
6145
6146         len = min_t(uint8_t, eld[2], len);
6147         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6148         for (i = 0; i < len; i++)
6149                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6150
6151         i = I915_READ(G4X_AUD_CNTL_ST);
6152         i |= eldv;
6153         I915_WRITE(G4X_AUD_CNTL_ST, i);
6154 }
6155
6156 static void haswell_write_eld(struct drm_connector *connector,
6157                                      struct drm_crtc *crtc)
6158 {
6159         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6160         uint8_t *eld = connector->eld;
6161         struct drm_device *dev = crtc->dev;
6162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163         uint32_t eldv;
6164         uint32_t i;
6165         int len;
6166         int pipe = to_intel_crtc(crtc)->pipe;
6167         int tmp;
6168
6169         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6170         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6171         int aud_config = HSW_AUD_CFG(pipe);
6172         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6173
6174
6175         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6176
6177         /* Audio output enable */
6178         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6179         tmp = I915_READ(aud_cntrl_st2);
6180         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6181         I915_WRITE(aud_cntrl_st2, tmp);
6182
6183         /* Wait for 1 vertical blank */
6184         intel_wait_for_vblank(dev, pipe);
6185
6186         /* Set ELD valid state */
6187         tmp = I915_READ(aud_cntrl_st2);
6188         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6189         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6190         I915_WRITE(aud_cntrl_st2, tmp);
6191         tmp = I915_READ(aud_cntrl_st2);
6192         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6193
6194         /* Enable HDMI mode */
6195         tmp = I915_READ(aud_config);
6196         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6197         /* clear N_programing_enable and N_value_index */
6198         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6199         I915_WRITE(aud_config, tmp);
6200
6201         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6202
6203         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6204         intel_crtc->eld_vld = true;
6205
6206         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6207                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6208                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6209                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6210         } else
6211                 I915_WRITE(aud_config, 0);
6212
6213         if (intel_eld_uptodate(connector,
6214                                aud_cntrl_st2, eldv,
6215                                aud_cntl_st, IBX_ELD_ADDRESS,
6216                                hdmiw_hdmiedid))
6217                 return;
6218
6219         i = I915_READ(aud_cntrl_st2);
6220         i &= ~eldv;
6221         I915_WRITE(aud_cntrl_st2, i);
6222
6223         if (!eld[0])
6224                 return;
6225
6226         i = I915_READ(aud_cntl_st);
6227         i &= ~IBX_ELD_ADDRESS;
6228         I915_WRITE(aud_cntl_st, i);
6229         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6230         DRM_DEBUG_DRIVER("port num:%d\n", i);
6231
6232         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6233         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6234         for (i = 0; i < len; i++)
6235                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6236
6237         i = I915_READ(aud_cntrl_st2);
6238         i |= eldv;
6239         I915_WRITE(aud_cntrl_st2, i);
6240
6241 }
6242
6243 static void ironlake_write_eld(struct drm_connector *connector,
6244                                      struct drm_crtc *crtc)
6245 {
6246         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6247         uint8_t *eld = connector->eld;
6248         uint32_t eldv;
6249         uint32_t i;
6250         int len;
6251         int hdmiw_hdmiedid;
6252         int aud_config;
6253         int aud_cntl_st;
6254         int aud_cntrl_st2;
6255         int pipe = to_intel_crtc(crtc)->pipe;
6256
6257         if (HAS_PCH_IBX(connector->dev)) {
6258                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6259                 aud_config = IBX_AUD_CFG(pipe);
6260                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6261                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6262         } else {
6263                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6264                 aud_config = CPT_AUD_CFG(pipe);
6265                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6266                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6267         }
6268
6269         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6270
6271         i = I915_READ(aud_cntl_st);
6272         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6273         if (!i) {
6274                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6275                 /* operate blindly on all ports */
6276                 eldv = IBX_ELD_VALIDB;
6277                 eldv |= IBX_ELD_VALIDB << 4;
6278                 eldv |= IBX_ELD_VALIDB << 8;
6279         } else {
6280                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6281                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6282         }
6283
6284         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6285                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6286                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6287                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6288         } else
6289                 I915_WRITE(aud_config, 0);
6290
6291         if (intel_eld_uptodate(connector,
6292                                aud_cntrl_st2, eldv,
6293                                aud_cntl_st, IBX_ELD_ADDRESS,
6294                                hdmiw_hdmiedid))
6295                 return;
6296
6297         i = I915_READ(aud_cntrl_st2);
6298         i &= ~eldv;
6299         I915_WRITE(aud_cntrl_st2, i);
6300
6301         if (!eld[0])
6302                 return;
6303
6304         i = I915_READ(aud_cntl_st);
6305         i &= ~IBX_ELD_ADDRESS;
6306         I915_WRITE(aud_cntl_st, i);
6307
6308         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6309         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6310         for (i = 0; i < len; i++)
6311                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6312
6313         i = I915_READ(aud_cntrl_st2);
6314         i |= eldv;
6315         I915_WRITE(aud_cntrl_st2, i);
6316 }
6317
6318 void intel_write_eld(struct drm_encoder *encoder,
6319                      struct drm_display_mode *mode)
6320 {
6321         struct drm_crtc *crtc = encoder->crtc;
6322         struct drm_connector *connector;
6323         struct drm_device *dev = encoder->dev;
6324         struct drm_i915_private *dev_priv = dev->dev_private;
6325
6326         connector = drm_select_eld(encoder, mode);
6327         if (!connector)
6328                 return;
6329
6330         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6331                          connector->base.id,
6332                          drm_get_connector_name(connector),
6333                          connector->encoder->base.id,
6334                          drm_get_encoder_name(connector->encoder));
6335
6336         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6337
6338         if (dev_priv->display.write_eld)
6339                 dev_priv->display.write_eld(connector, crtc);
6340 }
6341
6342 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6343 void intel_crtc_load_lut(struct drm_crtc *crtc)
6344 {
6345         struct drm_device *dev = crtc->dev;
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348         enum pipe pipe = intel_crtc->pipe;
6349         int palreg = PALETTE(pipe);
6350         int i;
6351         bool reenable_ips = false;
6352
6353         /* The clocks have to be on to load the palette. */
6354         if (!crtc->enabled || !intel_crtc->active)
6355                 return;
6356
6357         if (!HAS_PCH_SPLIT(dev_priv->dev))
6358                 assert_pll_enabled(dev_priv, pipe);
6359
6360         /* use legacy palette for Ironlake */
6361         if (HAS_PCH_SPLIT(dev))
6362                 palreg = LGC_PALETTE(pipe);
6363
6364         /* Workaround : Do not read or write the pipe palette/gamma data while
6365          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6366          */
6367         if (intel_crtc->config.ips_enabled &&
6368             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6369              GAMMA_MODE_MODE_SPLIT)) {
6370                 hsw_disable_ips(intel_crtc);
6371                 reenable_ips = true;
6372         }
6373
6374         for (i = 0; i < 256; i++) {
6375                 I915_WRITE(palreg + 4 * i,
6376                            (intel_crtc->lut_r[i] << 16) |
6377                            (intel_crtc->lut_g[i] << 8) |
6378                            intel_crtc->lut_b[i]);
6379         }
6380
6381         if (reenable_ips)
6382                 hsw_enable_ips(intel_crtc);
6383 }
6384
6385 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6386 {
6387         struct drm_device *dev = crtc->dev;
6388         struct drm_i915_private *dev_priv = dev->dev_private;
6389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390         bool visible = base != 0;
6391         u32 cntl;
6392
6393         if (intel_crtc->cursor_visible == visible)
6394                 return;
6395
6396         cntl = I915_READ(_CURACNTR);
6397         if (visible) {
6398                 /* On these chipsets we can only modify the base whilst
6399                  * the cursor is disabled.
6400                  */
6401                 I915_WRITE(_CURABASE, base);
6402
6403                 cntl &= ~(CURSOR_FORMAT_MASK);
6404                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6405                 cntl |= CURSOR_ENABLE |
6406                         CURSOR_GAMMA_ENABLE |
6407                         CURSOR_FORMAT_ARGB;
6408         } else
6409                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6410         I915_WRITE(_CURACNTR, cntl);
6411
6412         intel_crtc->cursor_visible = visible;
6413 }
6414
6415 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6416 {
6417         struct drm_device *dev = crtc->dev;
6418         struct drm_i915_private *dev_priv = dev->dev_private;
6419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420         int pipe = intel_crtc->pipe;
6421         bool visible = base != 0;
6422
6423         if (intel_crtc->cursor_visible != visible) {
6424                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6425                 if (base) {
6426                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6427                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6428                         cntl |= pipe << 28; /* Connect to correct pipe */
6429                 } else {
6430                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6431                         cntl |= CURSOR_MODE_DISABLE;
6432                 }
6433                 I915_WRITE(CURCNTR(pipe), cntl);
6434
6435                 intel_crtc->cursor_visible = visible;
6436         }
6437         /* and commit changes on next vblank */
6438         I915_WRITE(CURBASE(pipe), base);
6439 }
6440
6441 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6442 {
6443         struct drm_device *dev = crtc->dev;
6444         struct drm_i915_private *dev_priv = dev->dev_private;
6445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6446         int pipe = intel_crtc->pipe;
6447         bool visible = base != 0;
6448
6449         if (intel_crtc->cursor_visible != visible) {
6450                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6451                 if (base) {
6452                         cntl &= ~CURSOR_MODE;
6453                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6454                 } else {
6455                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6456                         cntl |= CURSOR_MODE_DISABLE;
6457                 }
6458                 if (IS_HASWELL(dev))
6459                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6460                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6461
6462                 intel_crtc->cursor_visible = visible;
6463         }
6464         /* and commit changes on next vblank */
6465         I915_WRITE(CURBASE_IVB(pipe), base);
6466 }
6467
6468 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6469 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6470                                      bool on)
6471 {
6472         struct drm_device *dev = crtc->dev;
6473         struct drm_i915_private *dev_priv = dev->dev_private;
6474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6475         int pipe = intel_crtc->pipe;
6476         int x = intel_crtc->cursor_x;
6477         int y = intel_crtc->cursor_y;
6478         u32 base, pos;
6479         bool visible;
6480
6481         pos = 0;
6482
6483         if (on && crtc->enabled && crtc->fb) {
6484                 base = intel_crtc->cursor_addr;
6485                 if (x > (int) crtc->fb->width)
6486                         base = 0;
6487
6488                 if (y > (int) crtc->fb->height)
6489                         base = 0;
6490         } else
6491                 base = 0;
6492
6493         if (x < 0) {
6494                 if (x + intel_crtc->cursor_width < 0)
6495                         base = 0;
6496
6497                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6498                 x = -x;
6499         }
6500         pos |= x << CURSOR_X_SHIFT;
6501
6502         if (y < 0) {
6503                 if (y + intel_crtc->cursor_height < 0)
6504                         base = 0;
6505
6506                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6507                 y = -y;
6508         }
6509         pos |= y << CURSOR_Y_SHIFT;
6510
6511         visible = base != 0;
6512         if (!visible && !intel_crtc->cursor_visible)
6513                 return;
6514
6515         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6516                 I915_WRITE(CURPOS_IVB(pipe), pos);
6517                 ivb_update_cursor(crtc, base);
6518         } else {
6519                 I915_WRITE(CURPOS(pipe), pos);
6520                 if (IS_845G(dev) || IS_I865G(dev))
6521                         i845_update_cursor(crtc, base);
6522                 else
6523                         i9xx_update_cursor(crtc, base);
6524         }
6525 }
6526
6527 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6528                                  struct drm_file *file,
6529                                  uint32_t handle,
6530                                  uint32_t width, uint32_t height)
6531 {
6532         struct drm_device *dev = crtc->dev;
6533         struct drm_i915_private *dev_priv = dev->dev_private;
6534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6535         struct drm_i915_gem_object *obj;
6536         uint32_t addr;
6537         int ret;
6538
6539         /* if we want to turn off the cursor ignore width and height */
6540         if (!handle) {
6541                 DRM_DEBUG_KMS("cursor off\n");
6542                 addr = 0;
6543                 obj = NULL;
6544                 mutex_lock(&dev->struct_mutex);
6545                 goto finish;
6546         }
6547
6548         /* Currently we only support 64x64 cursors */
6549         if (width != 64 || height != 64) {
6550                 DRM_ERROR("we currently only support 64x64 cursors\n");
6551                 return -EINVAL;
6552         }
6553
6554         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6555         if (&obj->base == NULL)
6556                 return -ENOENT;
6557
6558         if (obj->base.size < width * height * 4) {
6559                 DRM_ERROR("buffer is to small\n");
6560                 ret = -ENOMEM;
6561                 goto fail;
6562         }
6563
6564         /* we only need to pin inside GTT if cursor is non-phy */
6565         mutex_lock(&dev->struct_mutex);
6566         if (!dev_priv->info->cursor_needs_physical) {
6567                 unsigned alignment;
6568
6569                 if (obj->tiling_mode) {
6570                         DRM_ERROR("cursor cannot be tiled\n");
6571                         ret = -EINVAL;
6572                         goto fail_locked;
6573                 }
6574
6575                 /* Note that the w/a also requires 2 PTE of padding following
6576                  * the bo. We currently fill all unused PTE with the shadow
6577                  * page and so we should always have valid PTE following the
6578                  * cursor preventing the VT-d warning.
6579                  */
6580                 alignment = 0;
6581                 if (need_vtd_wa(dev))
6582                         alignment = 64*1024;
6583
6584                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6585                 if (ret) {
6586                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6587                         goto fail_locked;
6588                 }
6589
6590                 ret = i915_gem_object_put_fence(obj);
6591                 if (ret) {
6592                         DRM_ERROR("failed to release fence for cursor");
6593                         goto fail_unpin;
6594                 }
6595
6596                 addr = obj->gtt_offset;
6597         } else {
6598                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6599                 ret = i915_gem_attach_phys_object(dev, obj,
6600                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6601                                                   align);
6602                 if (ret) {
6603                         DRM_ERROR("failed to attach phys object\n");
6604                         goto fail_locked;
6605                 }
6606                 addr = obj->phys_obj->handle->busaddr;
6607         }
6608
6609         if (IS_GEN2(dev))
6610                 I915_WRITE(CURSIZE, (height << 12) | width);
6611
6612  finish:
6613         if (intel_crtc->cursor_bo) {
6614                 if (dev_priv->info->cursor_needs_physical) {
6615                         if (intel_crtc->cursor_bo != obj)
6616                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6617                 } else
6618                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6619                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6620         }
6621
6622         mutex_unlock(&dev->struct_mutex);
6623
6624         intel_crtc->cursor_addr = addr;
6625         intel_crtc->cursor_bo = obj;
6626         intel_crtc->cursor_width = width;
6627         intel_crtc->cursor_height = height;
6628
6629         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6630
6631         return 0;
6632 fail_unpin:
6633         i915_gem_object_unpin(obj);
6634 fail_locked:
6635         mutex_unlock(&dev->struct_mutex);
6636 fail:
6637         drm_gem_object_unreference_unlocked(&obj->base);
6638         return ret;
6639 }
6640
6641 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6642 {
6643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645         intel_crtc->cursor_x = x;
6646         intel_crtc->cursor_y = y;
6647
6648         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6649
6650         return 0;
6651 }
6652
6653 /** Sets the color ramps on behalf of RandR */
6654 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6655                                  u16 blue, int regno)
6656 {
6657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6658
6659         intel_crtc->lut_r[regno] = red >> 8;
6660         intel_crtc->lut_g[regno] = green >> 8;
6661         intel_crtc->lut_b[regno] = blue >> 8;
6662 }
6663
6664 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6665                              u16 *blue, int regno)
6666 {
6667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6668
6669         *red = intel_crtc->lut_r[regno] << 8;
6670         *green = intel_crtc->lut_g[regno] << 8;
6671         *blue = intel_crtc->lut_b[regno] << 8;
6672 }
6673
6674 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6675                                  u16 *blue, uint32_t start, uint32_t size)
6676 {
6677         int end = (start + size > 256) ? 256 : start + size, i;
6678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6679
6680         for (i = start; i < end; i++) {
6681                 intel_crtc->lut_r[i] = red[i] >> 8;
6682                 intel_crtc->lut_g[i] = green[i] >> 8;
6683                 intel_crtc->lut_b[i] = blue[i] >> 8;
6684         }
6685
6686         intel_crtc_load_lut(crtc);
6687 }
6688
6689 /* VESA 640x480x72Hz mode to set on the pipe */
6690 static struct drm_display_mode load_detect_mode = {
6691         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6692                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6693 };
6694
6695 static struct drm_framebuffer *
6696 intel_framebuffer_create(struct drm_device *dev,
6697                          struct drm_mode_fb_cmd2 *mode_cmd,
6698                          struct drm_i915_gem_object *obj)
6699 {
6700         struct intel_framebuffer *intel_fb;
6701         int ret;
6702
6703         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6704         if (!intel_fb) {
6705                 drm_gem_object_unreference_unlocked(&obj->base);
6706                 return ERR_PTR(-ENOMEM);
6707         }
6708
6709         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6710         if (ret) {
6711                 drm_gem_object_unreference_unlocked(&obj->base);
6712                 kfree(intel_fb);
6713                 return ERR_PTR(ret);
6714         }
6715
6716         return &intel_fb->base;
6717 }
6718
6719 static u32
6720 intel_framebuffer_pitch_for_width(int width, int bpp)
6721 {
6722         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6723         return ALIGN(pitch, 64);
6724 }
6725
6726 static u32
6727 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6728 {
6729         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6730         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6731 }
6732
6733 static struct drm_framebuffer *
6734 intel_framebuffer_create_for_mode(struct drm_device *dev,
6735                                   struct drm_display_mode *mode,
6736                                   int depth, int bpp)
6737 {
6738         struct drm_i915_gem_object *obj;
6739         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6740
6741         obj = i915_gem_alloc_object(dev,
6742                                     intel_framebuffer_size_for_mode(mode, bpp));
6743         if (obj == NULL)
6744                 return ERR_PTR(-ENOMEM);
6745
6746         mode_cmd.width = mode->hdisplay;
6747         mode_cmd.height = mode->vdisplay;
6748         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6749                                                                 bpp);
6750         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6751
6752         return intel_framebuffer_create(dev, &mode_cmd, obj);
6753 }
6754
6755 static struct drm_framebuffer *
6756 mode_fits_in_fbdev(struct drm_device *dev,
6757                    struct drm_display_mode *mode)
6758 {
6759         struct drm_i915_private *dev_priv = dev->dev_private;
6760         struct drm_i915_gem_object *obj;
6761         struct drm_framebuffer *fb;
6762
6763         if (dev_priv->fbdev == NULL)
6764                 return NULL;
6765
6766         obj = dev_priv->fbdev->ifb.obj;
6767         if (obj == NULL)
6768                 return NULL;
6769
6770         fb = &dev_priv->fbdev->ifb.base;
6771         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6772                                                                fb->bits_per_pixel))
6773                 return NULL;
6774
6775         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6776                 return NULL;
6777
6778         return fb;
6779 }
6780
6781 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6782                                 struct drm_display_mode *mode,
6783                                 struct intel_load_detect_pipe *old)
6784 {
6785         struct intel_crtc *intel_crtc;
6786         struct intel_encoder *intel_encoder =
6787                 intel_attached_encoder(connector);
6788         struct drm_crtc *possible_crtc;
6789         struct drm_encoder *encoder = &intel_encoder->base;
6790         struct drm_crtc *crtc = NULL;
6791         struct drm_device *dev = encoder->dev;
6792         struct drm_framebuffer *fb;
6793         int i = -1;
6794
6795         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6796                       connector->base.id, drm_get_connector_name(connector),
6797                       encoder->base.id, drm_get_encoder_name(encoder));
6798
6799         /*
6800          * Algorithm gets a little messy:
6801          *
6802          *   - if the connector already has an assigned crtc, use it (but make
6803          *     sure it's on first)
6804          *
6805          *   - try to find the first unused crtc that can drive this connector,
6806          *     and use that if we find one
6807          */
6808
6809         /* See if we already have a CRTC for this connector */
6810         if (encoder->crtc) {
6811                 crtc = encoder->crtc;
6812
6813                 mutex_lock(&crtc->mutex);
6814
6815                 old->dpms_mode = connector->dpms;
6816                 old->load_detect_temp = false;
6817
6818                 /* Make sure the crtc and connector are running */
6819                 if (connector->dpms != DRM_MODE_DPMS_ON)
6820                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6821
6822                 return true;
6823         }
6824
6825         /* Find an unused one (if possible) */
6826         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6827                 i++;
6828                 if (!(encoder->possible_crtcs & (1 << i)))
6829                         continue;
6830                 if (!possible_crtc->enabled) {
6831                         crtc = possible_crtc;
6832                         break;
6833                 }
6834         }
6835
6836         /*
6837          * If we didn't find an unused CRTC, don't use any.
6838          */
6839         if (!crtc) {
6840                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6841                 return false;
6842         }
6843
6844         mutex_lock(&crtc->mutex);
6845         intel_encoder->new_crtc = to_intel_crtc(crtc);
6846         to_intel_connector(connector)->new_encoder = intel_encoder;
6847
6848         intel_crtc = to_intel_crtc(crtc);
6849         old->dpms_mode = connector->dpms;
6850         old->load_detect_temp = true;
6851         old->release_fb = NULL;
6852
6853         if (!mode)
6854                 mode = &load_detect_mode;
6855
6856         /* We need a framebuffer large enough to accommodate all accesses
6857          * that the plane may generate whilst we perform load detection.
6858          * We can not rely on the fbcon either being present (we get called
6859          * during its initialisation to detect all boot displays, or it may
6860          * not even exist) or that it is large enough to satisfy the
6861          * requested mode.
6862          */
6863         fb = mode_fits_in_fbdev(dev, mode);
6864         if (fb == NULL) {
6865                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6866                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6867                 old->release_fb = fb;
6868         } else
6869                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6870         if (IS_ERR(fb)) {
6871                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6872                 mutex_unlock(&crtc->mutex);
6873                 return false;
6874         }
6875
6876         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6877                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6878                 if (old->release_fb)
6879                         old->release_fb->funcs->destroy(old->release_fb);
6880                 mutex_unlock(&crtc->mutex);
6881                 return false;
6882         }
6883
6884         /* let the connector get through one full cycle before testing */
6885         intel_wait_for_vblank(dev, intel_crtc->pipe);
6886         return true;
6887 }
6888
6889 void intel_release_load_detect_pipe(struct drm_connector *connector,
6890                                     struct intel_load_detect_pipe *old)
6891 {
6892         struct intel_encoder *intel_encoder =
6893                 intel_attached_encoder(connector);
6894         struct drm_encoder *encoder = &intel_encoder->base;
6895         struct drm_crtc *crtc = encoder->crtc;
6896
6897         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6898                       connector->base.id, drm_get_connector_name(connector),
6899                       encoder->base.id, drm_get_encoder_name(encoder));
6900
6901         if (old->load_detect_temp) {
6902                 to_intel_connector(connector)->new_encoder = NULL;
6903                 intel_encoder->new_crtc = NULL;
6904                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6905
6906                 if (old->release_fb) {
6907                         drm_framebuffer_unregister_private(old->release_fb);
6908                         drm_framebuffer_unreference(old->release_fb);
6909                 }
6910
6911                 mutex_unlock(&crtc->mutex);
6912                 return;
6913         }
6914
6915         /* Switch crtc and encoder back off if necessary */
6916         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6917                 connector->funcs->dpms(connector, old->dpms_mode);
6918
6919         mutex_unlock(&crtc->mutex);
6920 }
6921
6922 /* Returns the clock of the currently programmed mode of the given pipe. */
6923 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6924 {
6925         struct drm_i915_private *dev_priv = dev->dev_private;
6926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927         int pipe = intel_crtc->pipe;
6928         u32 dpll = I915_READ(DPLL(pipe));
6929         u32 fp;
6930         intel_clock_t clock;
6931
6932         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6933                 fp = I915_READ(FP0(pipe));
6934         else
6935                 fp = I915_READ(FP1(pipe));
6936
6937         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6938         if (IS_PINEVIEW(dev)) {
6939                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6940                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6941         } else {
6942                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6943                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6944         }
6945
6946         if (!IS_GEN2(dev)) {
6947                 if (IS_PINEVIEW(dev))
6948                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6949                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6950                 else
6951                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6952                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6953
6954                 switch (dpll & DPLL_MODE_MASK) {
6955                 case DPLLB_MODE_DAC_SERIAL:
6956                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6957                                 5 : 10;
6958                         break;
6959                 case DPLLB_MODE_LVDS:
6960                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6961                                 7 : 14;
6962                         break;
6963                 default:
6964                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6965                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6966                         return 0;
6967                 }
6968
6969                 if (IS_PINEVIEW(dev))
6970                         pineview_clock(96000, &clock);
6971                 else
6972                         i9xx_clock(96000, &clock);
6973         } else {
6974                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6975
6976                 if (is_lvds) {
6977                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6978                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6979                         clock.p2 = 14;
6980
6981                         if ((dpll & PLL_REF_INPUT_MASK) ==
6982                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6983                                 /* XXX: might not be 66MHz */
6984                                 i9xx_clock(66000, &clock);
6985                         } else
6986                                 i9xx_clock(48000, &clock);
6987                 } else {
6988                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6989                                 clock.p1 = 2;
6990                         else {
6991                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6992                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6993                         }
6994                         if (dpll & PLL_P2_DIVIDE_BY_4)
6995                                 clock.p2 = 4;
6996                         else
6997                                 clock.p2 = 2;
6998
6999                         i9xx_clock(48000, &clock);
7000                 }
7001         }
7002
7003         /* XXX: It would be nice to validate the clocks, but we can't reuse
7004          * i830PllIsValid() because it relies on the xf86_config connector
7005          * configuration being accurate, which it isn't necessarily.
7006          */
7007
7008         return clock.dot;
7009 }
7010
7011 /** Returns the currently programmed mode of the given pipe. */
7012 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7013                                              struct drm_crtc *crtc)
7014 {
7015         struct drm_i915_private *dev_priv = dev->dev_private;
7016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7018         struct drm_display_mode *mode;
7019         int htot = I915_READ(HTOTAL(cpu_transcoder));
7020         int hsync = I915_READ(HSYNC(cpu_transcoder));
7021         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7022         int vsync = I915_READ(VSYNC(cpu_transcoder));
7023
7024         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7025         if (!mode)
7026                 return NULL;
7027
7028         mode->clock = intel_crtc_clock_get(dev, crtc);
7029         mode->hdisplay = (htot & 0xffff) + 1;
7030         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7031         mode->hsync_start = (hsync & 0xffff) + 1;
7032         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7033         mode->vdisplay = (vtot & 0xffff) + 1;
7034         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7035         mode->vsync_start = (vsync & 0xffff) + 1;
7036         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7037
7038         drm_mode_set_name(mode);
7039
7040         return mode;
7041 }
7042
7043 static void intel_increase_pllclock(struct drm_crtc *crtc)
7044 {
7045         struct drm_device *dev = crtc->dev;
7046         drm_i915_private_t *dev_priv = dev->dev_private;
7047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048         int pipe = intel_crtc->pipe;
7049         int dpll_reg = DPLL(pipe);
7050         int dpll;
7051
7052         if (HAS_PCH_SPLIT(dev))
7053                 return;
7054
7055         if (!dev_priv->lvds_downclock_avail)
7056                 return;
7057
7058         dpll = I915_READ(dpll_reg);
7059         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7060                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7061
7062                 assert_panel_unlocked(dev_priv, pipe);
7063
7064                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7065                 I915_WRITE(dpll_reg, dpll);
7066                 intel_wait_for_vblank(dev, pipe);
7067
7068                 dpll = I915_READ(dpll_reg);
7069                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7070                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7071         }
7072 }
7073
7074 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7075 {
7076         struct drm_device *dev = crtc->dev;
7077         drm_i915_private_t *dev_priv = dev->dev_private;
7078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079
7080         if (HAS_PCH_SPLIT(dev))
7081                 return;
7082
7083         if (!dev_priv->lvds_downclock_avail)
7084                 return;
7085
7086         /*
7087          * Since this is called by a timer, we should never get here in
7088          * the manual case.
7089          */
7090         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7091                 int pipe = intel_crtc->pipe;
7092                 int dpll_reg = DPLL(pipe);
7093                 int dpll;
7094
7095                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7096
7097                 assert_panel_unlocked(dev_priv, pipe);
7098
7099                 dpll = I915_READ(dpll_reg);
7100                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7101                 I915_WRITE(dpll_reg, dpll);
7102                 intel_wait_for_vblank(dev, pipe);
7103                 dpll = I915_READ(dpll_reg);
7104                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7105                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7106         }
7107
7108 }
7109
7110 void intel_mark_busy(struct drm_device *dev)
7111 {
7112         i915_update_gfx_val(dev->dev_private);
7113 }
7114
7115 void intel_mark_idle(struct drm_device *dev)
7116 {
7117         struct drm_crtc *crtc;
7118
7119         if (!i915_powersave)
7120                 return;
7121
7122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7123                 if (!crtc->fb)
7124                         continue;
7125
7126                 intel_decrease_pllclock(crtc);
7127         }
7128 }
7129
7130 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7131                         struct intel_ring_buffer *ring)
7132 {
7133         struct drm_device *dev = obj->base.dev;
7134         struct drm_crtc *crtc;
7135
7136         if (!i915_powersave)
7137                 return;
7138
7139         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7140                 if (!crtc->fb)
7141                         continue;
7142
7143                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7144                         continue;
7145
7146                 intel_increase_pllclock(crtc);
7147                 if (ring && intel_fbc_enabled(dev))
7148                         ring->fbc_dirty = true;
7149         }
7150 }
7151
7152 static void intel_crtc_destroy(struct drm_crtc *crtc)
7153 {
7154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7155         struct drm_device *dev = crtc->dev;
7156         struct intel_unpin_work *work;
7157         unsigned long flags;
7158
7159         spin_lock_irqsave(&dev->event_lock, flags);
7160         work = intel_crtc->unpin_work;
7161         intel_crtc->unpin_work = NULL;
7162         spin_unlock_irqrestore(&dev->event_lock, flags);
7163
7164         if (work) {
7165                 cancel_work_sync(&work->work);
7166                 kfree(work);
7167         }
7168
7169         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7170
7171         drm_crtc_cleanup(crtc);
7172
7173         kfree(intel_crtc);
7174 }
7175
7176 static void intel_unpin_work_fn(struct work_struct *__work)
7177 {
7178         struct intel_unpin_work *work =
7179                 container_of(__work, struct intel_unpin_work, work);
7180         struct drm_device *dev = work->crtc->dev;
7181
7182         mutex_lock(&dev->struct_mutex);
7183         intel_unpin_fb_obj(work->old_fb_obj);
7184         drm_gem_object_unreference(&work->pending_flip_obj->base);
7185         drm_gem_object_unreference(&work->old_fb_obj->base);
7186
7187         intel_update_fbc(dev);
7188         mutex_unlock(&dev->struct_mutex);
7189
7190         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7191         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7192
7193         kfree(work);
7194 }
7195
7196 static void do_intel_finish_page_flip(struct drm_device *dev,
7197                                       struct drm_crtc *crtc)
7198 {
7199         drm_i915_private_t *dev_priv = dev->dev_private;
7200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7201         struct intel_unpin_work *work;
7202         unsigned long flags;
7203
7204         /* Ignore early vblank irqs */
7205         if (intel_crtc == NULL)
7206                 return;
7207
7208         spin_lock_irqsave(&dev->event_lock, flags);
7209         work = intel_crtc->unpin_work;
7210
7211         /* Ensure we don't miss a work->pending update ... */
7212         smp_rmb();
7213
7214         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7215                 spin_unlock_irqrestore(&dev->event_lock, flags);
7216                 return;
7217         }
7218
7219         /* and that the unpin work is consistent wrt ->pending. */
7220         smp_rmb();
7221
7222         intel_crtc->unpin_work = NULL;
7223
7224         if (work->event)
7225                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7226
7227         drm_vblank_put(dev, intel_crtc->pipe);
7228
7229         spin_unlock_irqrestore(&dev->event_lock, flags);
7230
7231         wake_up_all(&dev_priv->pending_flip_queue);
7232
7233         queue_work(dev_priv->wq, &work->work);
7234
7235         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7236 }
7237
7238 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7239 {
7240         drm_i915_private_t *dev_priv = dev->dev_private;
7241         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7242
7243         do_intel_finish_page_flip(dev, crtc);
7244 }
7245
7246 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7247 {
7248         drm_i915_private_t *dev_priv = dev->dev_private;
7249         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7250
7251         do_intel_finish_page_flip(dev, crtc);
7252 }
7253
7254 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7255 {
7256         drm_i915_private_t *dev_priv = dev->dev_private;
7257         struct intel_crtc *intel_crtc =
7258                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7259         unsigned long flags;
7260
7261         /* NB: An MMIO update of the plane base pointer will also
7262          * generate a page-flip completion irq, i.e. every modeset
7263          * is also accompanied by a spurious intel_prepare_page_flip().
7264          */
7265         spin_lock_irqsave(&dev->event_lock, flags);
7266         if (intel_crtc->unpin_work)
7267                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7268         spin_unlock_irqrestore(&dev->event_lock, flags);
7269 }
7270
7271 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7272 {
7273         /* Ensure that the work item is consistent when activating it ... */
7274         smp_wmb();
7275         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7276         /* and that it is marked active as soon as the irq could fire. */
7277         smp_wmb();
7278 }
7279
7280 static int intel_gen2_queue_flip(struct drm_device *dev,
7281                                  struct drm_crtc *crtc,
7282                                  struct drm_framebuffer *fb,
7283                                  struct drm_i915_gem_object *obj)
7284 {
7285         struct drm_i915_private *dev_priv = dev->dev_private;
7286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7287         u32 flip_mask;
7288         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7289         int ret;
7290
7291         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7292         if (ret)
7293                 goto err;
7294
7295         ret = intel_ring_begin(ring, 6);
7296         if (ret)
7297                 goto err_unpin;
7298
7299         /* Can't queue multiple flips, so wait for the previous
7300          * one to finish before executing the next.
7301          */
7302         if (intel_crtc->plane)
7303                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7304         else
7305                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7306         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7307         intel_ring_emit(ring, MI_NOOP);
7308         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7309                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7310         intel_ring_emit(ring, fb->pitches[0]);
7311         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7312         intel_ring_emit(ring, 0); /* aux display base address, unused */
7313
7314         intel_mark_page_flip_active(intel_crtc);
7315         intel_ring_advance(ring);
7316         return 0;
7317
7318 err_unpin:
7319         intel_unpin_fb_obj(obj);
7320 err:
7321         return ret;
7322 }
7323
7324 static int intel_gen3_queue_flip(struct drm_device *dev,
7325                                  struct drm_crtc *crtc,
7326                                  struct drm_framebuffer *fb,
7327                                  struct drm_i915_gem_object *obj)
7328 {
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7331         u32 flip_mask;
7332         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7333         int ret;
7334
7335         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7336         if (ret)
7337                 goto err;
7338
7339         ret = intel_ring_begin(ring, 6);
7340         if (ret)
7341                 goto err_unpin;
7342
7343         if (intel_crtc->plane)
7344                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7345         else
7346                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7347         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7348         intel_ring_emit(ring, MI_NOOP);
7349         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7350                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7351         intel_ring_emit(ring, fb->pitches[0]);
7352         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7353         intel_ring_emit(ring, MI_NOOP);
7354
7355         intel_mark_page_flip_active(intel_crtc);
7356         intel_ring_advance(ring);
7357         return 0;
7358
7359 err_unpin:
7360         intel_unpin_fb_obj(obj);
7361 err:
7362         return ret;
7363 }
7364
7365 static int intel_gen4_queue_flip(struct drm_device *dev,
7366                                  struct drm_crtc *crtc,
7367                                  struct drm_framebuffer *fb,
7368                                  struct drm_i915_gem_object *obj)
7369 {
7370         struct drm_i915_private *dev_priv = dev->dev_private;
7371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7372         uint32_t pf, pipesrc;
7373         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7374         int ret;
7375
7376         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7377         if (ret)
7378                 goto err;
7379
7380         ret = intel_ring_begin(ring, 4);
7381         if (ret)
7382                 goto err_unpin;
7383
7384         /* i965+ uses the linear or tiled offsets from the
7385          * Display Registers (which do not change across a page-flip)
7386          * so we need only reprogram the base address.
7387          */
7388         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7389                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7390         intel_ring_emit(ring, fb->pitches[0]);
7391         intel_ring_emit(ring,
7392                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7393                         obj->tiling_mode);
7394
7395         /* XXX Enabling the panel-fitter across page-flip is so far
7396          * untested on non-native modes, so ignore it for now.
7397          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7398          */
7399         pf = 0;
7400         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7401         intel_ring_emit(ring, pf | pipesrc);
7402
7403         intel_mark_page_flip_active(intel_crtc);
7404         intel_ring_advance(ring);
7405         return 0;
7406
7407 err_unpin:
7408         intel_unpin_fb_obj(obj);
7409 err:
7410         return ret;
7411 }
7412
7413 static int intel_gen6_queue_flip(struct drm_device *dev,
7414                                  struct drm_crtc *crtc,
7415                                  struct drm_framebuffer *fb,
7416                                  struct drm_i915_gem_object *obj)
7417 {
7418         struct drm_i915_private *dev_priv = dev->dev_private;
7419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7420         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7421         uint32_t pf, pipesrc;
7422         int ret;
7423
7424         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7425         if (ret)
7426                 goto err;
7427
7428         ret = intel_ring_begin(ring, 4);
7429         if (ret)
7430                 goto err_unpin;
7431
7432         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7433                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7434         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7435         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7436
7437         /* Contrary to the suggestions in the documentation,
7438          * "Enable Panel Fitter" does not seem to be required when page
7439          * flipping with a non-native mode, and worse causes a normal
7440          * modeset to fail.
7441          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7442          */
7443         pf = 0;
7444         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7445         intel_ring_emit(ring, pf | pipesrc);
7446
7447         intel_mark_page_flip_active(intel_crtc);
7448         intel_ring_advance(ring);
7449         return 0;
7450
7451 err_unpin:
7452         intel_unpin_fb_obj(obj);
7453 err:
7454         return ret;
7455 }
7456
7457 /*
7458  * On gen7 we currently use the blit ring because (in early silicon at least)
7459  * the render ring doesn't give us interrpts for page flip completion, which
7460  * means clients will hang after the first flip is queued.  Fortunately the
7461  * blit ring generates interrupts properly, so use it instead.
7462  */
7463 static int intel_gen7_queue_flip(struct drm_device *dev,
7464                                  struct drm_crtc *crtc,
7465                                  struct drm_framebuffer *fb,
7466                                  struct drm_i915_gem_object *obj)
7467 {
7468         struct drm_i915_private *dev_priv = dev->dev_private;
7469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7470         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7471         uint32_t plane_bit = 0;
7472         int ret;
7473
7474         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7475         if (ret)
7476                 goto err;
7477
7478         switch(intel_crtc->plane) {
7479         case PLANE_A:
7480                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7481                 break;
7482         case PLANE_B:
7483                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7484                 break;
7485         case PLANE_C:
7486                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7487                 break;
7488         default:
7489                 WARN_ONCE(1, "unknown plane in flip command\n");
7490                 ret = -ENODEV;
7491                 goto err_unpin;
7492         }
7493
7494         ret = intel_ring_begin(ring, 4);
7495         if (ret)
7496                 goto err_unpin;
7497
7498         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7499         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7500         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7501         intel_ring_emit(ring, (MI_NOOP));
7502
7503         intel_mark_page_flip_active(intel_crtc);
7504         intel_ring_advance(ring);
7505         return 0;
7506
7507 err_unpin:
7508         intel_unpin_fb_obj(obj);
7509 err:
7510         return ret;
7511 }
7512
7513 static int intel_default_queue_flip(struct drm_device *dev,
7514                                     struct drm_crtc *crtc,
7515                                     struct drm_framebuffer *fb,
7516                                     struct drm_i915_gem_object *obj)
7517 {
7518         return -ENODEV;
7519 }
7520
7521 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7522                                 struct drm_framebuffer *fb,
7523                                 struct drm_pending_vblank_event *event)
7524 {
7525         struct drm_device *dev = crtc->dev;
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         struct drm_framebuffer *old_fb = crtc->fb;
7528         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7530         struct intel_unpin_work *work;
7531         unsigned long flags;
7532         int ret;
7533
7534         /* Can't change pixel format via MI display flips. */
7535         if (fb->pixel_format != crtc->fb->pixel_format)
7536                 return -EINVAL;
7537
7538         /*
7539          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7540          * Note that pitch changes could also affect these register.
7541          */
7542         if (INTEL_INFO(dev)->gen > 3 &&
7543             (fb->offsets[0] != crtc->fb->offsets[0] ||
7544              fb->pitches[0] != crtc->fb->pitches[0]))
7545                 return -EINVAL;
7546
7547         work = kzalloc(sizeof *work, GFP_KERNEL);
7548         if (work == NULL)
7549                 return -ENOMEM;
7550
7551         work->event = event;
7552         work->crtc = crtc;
7553         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7554         INIT_WORK(&work->work, intel_unpin_work_fn);
7555
7556         ret = drm_vblank_get(dev, intel_crtc->pipe);
7557         if (ret)
7558                 goto free_work;
7559
7560         /* We borrow the event spin lock for protecting unpin_work */
7561         spin_lock_irqsave(&dev->event_lock, flags);
7562         if (intel_crtc->unpin_work) {
7563                 spin_unlock_irqrestore(&dev->event_lock, flags);
7564                 kfree(work);
7565                 drm_vblank_put(dev, intel_crtc->pipe);
7566
7567                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7568                 return -EBUSY;
7569         }
7570         intel_crtc->unpin_work = work;
7571         spin_unlock_irqrestore(&dev->event_lock, flags);
7572
7573         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7574                 flush_workqueue(dev_priv->wq);
7575
7576         ret = i915_mutex_lock_interruptible(dev);
7577         if (ret)
7578                 goto cleanup;
7579
7580         /* Reference the objects for the scheduled work. */
7581         drm_gem_object_reference(&work->old_fb_obj->base);
7582         drm_gem_object_reference(&obj->base);
7583
7584         crtc->fb = fb;
7585
7586         work->pending_flip_obj = obj;
7587
7588         work->enable_stall_check = true;
7589
7590         atomic_inc(&intel_crtc->unpin_work_count);
7591         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7592
7593         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7594         if (ret)
7595                 goto cleanup_pending;
7596
7597         intel_disable_fbc(dev);
7598         intel_mark_fb_busy(obj, NULL);
7599         mutex_unlock(&dev->struct_mutex);
7600
7601         trace_i915_flip_request(intel_crtc->plane, obj);
7602
7603         return 0;
7604
7605 cleanup_pending:
7606         atomic_dec(&intel_crtc->unpin_work_count);
7607         crtc->fb = old_fb;
7608         drm_gem_object_unreference(&work->old_fb_obj->base);
7609         drm_gem_object_unreference(&obj->base);
7610         mutex_unlock(&dev->struct_mutex);
7611
7612 cleanup:
7613         spin_lock_irqsave(&dev->event_lock, flags);
7614         intel_crtc->unpin_work = NULL;
7615         spin_unlock_irqrestore(&dev->event_lock, flags);
7616
7617         drm_vblank_put(dev, intel_crtc->pipe);
7618 free_work:
7619         kfree(work);
7620
7621         return ret;
7622 }
7623
7624 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7625         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7626         .load_lut = intel_crtc_load_lut,
7627 };
7628
7629 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7630                                   struct drm_crtc *crtc)
7631 {
7632         struct drm_device *dev;
7633         struct drm_crtc *tmp;
7634         int crtc_mask = 1;
7635
7636         WARN(!crtc, "checking null crtc?\n");
7637
7638         dev = crtc->dev;
7639
7640         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7641                 if (tmp == crtc)
7642                         break;
7643                 crtc_mask <<= 1;
7644         }
7645
7646         if (encoder->possible_crtcs & crtc_mask)
7647                 return true;
7648         return false;
7649 }
7650
7651 /**
7652  * intel_modeset_update_staged_output_state
7653  *
7654  * Updates the staged output configuration state, e.g. after we've read out the
7655  * current hw state.
7656  */
7657 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7658 {
7659         struct intel_encoder *encoder;
7660         struct intel_connector *connector;
7661
7662         list_for_each_entry(connector, &dev->mode_config.connector_list,
7663                             base.head) {
7664                 connector->new_encoder =
7665                         to_intel_encoder(connector->base.encoder);
7666         }
7667
7668         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7669                             base.head) {
7670                 encoder->new_crtc =
7671                         to_intel_crtc(encoder->base.crtc);
7672         }
7673 }
7674
7675 /**
7676  * intel_modeset_commit_output_state
7677  *
7678  * This function copies the stage display pipe configuration to the real one.
7679  */
7680 static void intel_modeset_commit_output_state(struct drm_device *dev)
7681 {
7682         struct intel_encoder *encoder;
7683         struct intel_connector *connector;
7684
7685         list_for_each_entry(connector, &dev->mode_config.connector_list,
7686                             base.head) {
7687                 connector->base.encoder = &connector->new_encoder->base;
7688         }
7689
7690         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7691                             base.head) {
7692                 encoder->base.crtc = &encoder->new_crtc->base;
7693         }
7694 }
7695
7696 static void
7697 connected_sink_compute_bpp(struct intel_connector * connector,
7698                            struct intel_crtc_config *pipe_config)
7699 {
7700         int bpp = pipe_config->pipe_bpp;
7701
7702         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7703                 connector->base.base.id,
7704                 drm_get_connector_name(&connector->base));
7705
7706         /* Don't use an invalid EDID bpc value */
7707         if (connector->base.display_info.bpc &&
7708             connector->base.display_info.bpc * 3 < bpp) {
7709                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7710                               bpp, connector->base.display_info.bpc*3);
7711                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7712         }
7713
7714         /* Clamp bpp to 8 on screens without EDID 1.4 */
7715         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7716                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7717                               bpp);
7718                 pipe_config->pipe_bpp = 24;
7719         }
7720 }
7721
7722 static int
7723 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7724                           struct drm_framebuffer *fb,
7725                           struct intel_crtc_config *pipe_config)
7726 {
7727         struct drm_device *dev = crtc->base.dev;
7728         struct intel_connector *connector;
7729         int bpp;
7730
7731         switch (fb->pixel_format) {
7732         case DRM_FORMAT_C8:
7733                 bpp = 8*3; /* since we go through a colormap */
7734                 break;
7735         case DRM_FORMAT_XRGB1555:
7736         case DRM_FORMAT_ARGB1555:
7737                 /* checked in intel_framebuffer_init already */
7738                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7739                         return -EINVAL;
7740         case DRM_FORMAT_RGB565:
7741                 bpp = 6*3; /* min is 18bpp */
7742                 break;
7743         case DRM_FORMAT_XBGR8888:
7744         case DRM_FORMAT_ABGR8888:
7745                 /* checked in intel_framebuffer_init already */
7746                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7747                         return -EINVAL;
7748         case DRM_FORMAT_XRGB8888:
7749         case DRM_FORMAT_ARGB8888:
7750                 bpp = 8*3;
7751                 break;
7752         case DRM_FORMAT_XRGB2101010:
7753         case DRM_FORMAT_ARGB2101010:
7754         case DRM_FORMAT_XBGR2101010:
7755         case DRM_FORMAT_ABGR2101010:
7756                 /* checked in intel_framebuffer_init already */
7757                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7758                         return -EINVAL;
7759                 bpp = 10*3;
7760                 break;
7761         /* TODO: gen4+ supports 16 bpc floating point, too. */
7762         default:
7763                 DRM_DEBUG_KMS("unsupported depth\n");
7764                 return -EINVAL;
7765         }
7766
7767         pipe_config->pipe_bpp = bpp;
7768
7769         /* Clamp display bpp to EDID value */
7770         list_for_each_entry(connector, &dev->mode_config.connector_list,
7771                             base.head) {
7772                 if (!connector->new_encoder ||
7773                     connector->new_encoder->new_crtc != crtc)
7774                         continue;
7775
7776                 connected_sink_compute_bpp(connector, pipe_config);
7777         }
7778
7779         return bpp;
7780 }
7781
7782 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7783                                    struct intel_crtc_config *pipe_config,
7784                                    const char *context)
7785 {
7786         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7787                       context, pipe_name(crtc->pipe));
7788
7789         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7790         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7791                       pipe_config->pipe_bpp, pipe_config->dither);
7792         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7793                       pipe_config->has_pch_encoder,
7794                       pipe_config->fdi_lanes,
7795                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7796                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7797                       pipe_config->fdi_m_n.tu);
7798         DRM_DEBUG_KMS("requested mode:\n");
7799         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7800         DRM_DEBUG_KMS("adjusted mode:\n");
7801         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7802         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7803                       pipe_config->gmch_pfit.control,
7804                       pipe_config->gmch_pfit.pgm_ratios,
7805                       pipe_config->gmch_pfit.lvds_border_bits);
7806         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7807                       pipe_config->pch_pfit.pos,
7808                       pipe_config->pch_pfit.size);
7809         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7810 }
7811
7812 static bool check_encoder_cloning(struct drm_crtc *crtc)
7813 {
7814         int num_encoders = 0;
7815         bool uncloneable_encoders = false;
7816         struct intel_encoder *encoder;
7817
7818         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7819                             base.head) {
7820                 if (&encoder->new_crtc->base != crtc)
7821                         continue;
7822
7823                 num_encoders++;
7824                 if (!encoder->cloneable)
7825                         uncloneable_encoders = true;
7826         }
7827
7828         return !(num_encoders > 1 && uncloneable_encoders);
7829 }
7830
7831 static struct intel_crtc_config *
7832 intel_modeset_pipe_config(struct drm_crtc *crtc,
7833                           struct drm_framebuffer *fb,
7834                           struct drm_display_mode *mode)
7835 {
7836         struct drm_device *dev = crtc->dev;
7837         struct drm_encoder_helper_funcs *encoder_funcs;
7838         struct intel_encoder *encoder;
7839         struct intel_crtc_config *pipe_config;
7840         int plane_bpp, ret = -EINVAL;
7841         bool retry = true;
7842
7843         if (!check_encoder_cloning(crtc)) {
7844                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7845                 return ERR_PTR(-EINVAL);
7846         }
7847
7848         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7849         if (!pipe_config)
7850                 return ERR_PTR(-ENOMEM);
7851
7852         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7853         drm_mode_copy(&pipe_config->requested_mode, mode);
7854         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7855
7856         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7857          * plane pixel format and any sink constraints into account. Returns the
7858          * source plane bpp so that dithering can be selected on mismatches
7859          * after encoders and crtc also have had their say. */
7860         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7861                                               fb, pipe_config);
7862         if (plane_bpp < 0)
7863                 goto fail;
7864
7865 encoder_retry:
7866         /* Ensure the port clock defaults are reset when retrying. */
7867         pipe_config->port_clock = 0;
7868         pipe_config->pixel_multiplier = 1;
7869
7870         /* Pass our mode to the connectors and the CRTC to give them a chance to
7871          * adjust it according to limitations or connector properties, and also
7872          * a chance to reject the mode entirely.
7873          */
7874         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7875                             base.head) {
7876
7877                 if (&encoder->new_crtc->base != crtc)
7878                         continue;
7879
7880                 if (encoder->compute_config) {
7881                         if (!(encoder->compute_config(encoder, pipe_config))) {
7882                                 DRM_DEBUG_KMS("Encoder config failure\n");
7883                                 goto fail;
7884                         }
7885
7886                         continue;
7887                 }
7888
7889                 encoder_funcs = encoder->base.helper_private;
7890                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7891                                                 &pipe_config->requested_mode,
7892                                                 &pipe_config->adjusted_mode))) {
7893                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7894                         goto fail;
7895                 }
7896         }
7897
7898         /* Set default port clock if not overwritten by the encoder. Needs to be
7899          * done afterwards in case the encoder adjusts the mode. */
7900         if (!pipe_config->port_clock)
7901                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7902
7903         ret = intel_crtc_compute_config(crtc, pipe_config);
7904         if (ret < 0) {
7905                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7906                 goto fail;
7907         }
7908
7909         if (ret == RETRY) {
7910                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7911                         ret = -EINVAL;
7912                         goto fail;
7913                 }
7914
7915                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7916                 retry = false;
7917                 goto encoder_retry;
7918         }
7919
7920         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7921         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7922                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7923
7924         return pipe_config;
7925 fail:
7926         kfree(pipe_config);
7927         return ERR_PTR(ret);
7928 }
7929
7930 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7931  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7932 static void
7933 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7934                              unsigned *prepare_pipes, unsigned *disable_pipes)
7935 {
7936         struct intel_crtc *intel_crtc;
7937         struct drm_device *dev = crtc->dev;
7938         struct intel_encoder *encoder;
7939         struct intel_connector *connector;
7940         struct drm_crtc *tmp_crtc;
7941
7942         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7943
7944         /* Check which crtcs have changed outputs connected to them, these need
7945          * to be part of the prepare_pipes mask. We don't (yet) support global
7946          * modeset across multiple crtcs, so modeset_pipes will only have one
7947          * bit set at most. */
7948         list_for_each_entry(connector, &dev->mode_config.connector_list,
7949                             base.head) {
7950                 if (connector->base.encoder == &connector->new_encoder->base)
7951                         continue;
7952
7953                 if (connector->base.encoder) {
7954                         tmp_crtc = connector->base.encoder->crtc;
7955
7956                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7957                 }
7958
7959                 if (connector->new_encoder)
7960                         *prepare_pipes |=
7961                                 1 << connector->new_encoder->new_crtc->pipe;
7962         }
7963
7964         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7965                             base.head) {
7966                 if (encoder->base.crtc == &encoder->new_crtc->base)
7967                         continue;
7968
7969                 if (encoder->base.crtc) {
7970                         tmp_crtc = encoder->base.crtc;
7971
7972                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7973                 }
7974
7975                 if (encoder->new_crtc)
7976                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7977         }
7978
7979         /* Check for any pipes that will be fully disabled ... */
7980         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7981                             base.head) {
7982                 bool used = false;
7983
7984                 /* Don't try to disable disabled crtcs. */
7985                 if (!intel_crtc->base.enabled)
7986                         continue;
7987
7988                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7989                                     base.head) {
7990                         if (encoder->new_crtc == intel_crtc)
7991                                 used = true;
7992                 }
7993
7994                 if (!used)
7995                         *disable_pipes |= 1 << intel_crtc->pipe;
7996         }
7997
7998
7999         /* set_mode is also used to update properties on life display pipes. */
8000         intel_crtc = to_intel_crtc(crtc);
8001         if (crtc->enabled)
8002                 *prepare_pipes |= 1 << intel_crtc->pipe;
8003
8004         /*
8005          * For simplicity do a full modeset on any pipe where the output routing
8006          * changed. We could be more clever, but that would require us to be
8007          * more careful with calling the relevant encoder->mode_set functions.
8008          */
8009         if (*prepare_pipes)
8010                 *modeset_pipes = *prepare_pipes;
8011
8012         /* ... and mask these out. */
8013         *modeset_pipes &= ~(*disable_pipes);
8014         *prepare_pipes &= ~(*disable_pipes);
8015
8016         /*
8017          * HACK: We don't (yet) fully support global modesets. intel_set_config
8018          * obies this rule, but the modeset restore mode of
8019          * intel_modeset_setup_hw_state does not.
8020          */
8021         *modeset_pipes &= 1 << intel_crtc->pipe;
8022         *prepare_pipes &= 1 << intel_crtc->pipe;
8023
8024         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8025                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8026 }
8027
8028 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8029 {
8030         struct drm_encoder *encoder;
8031         struct drm_device *dev = crtc->dev;
8032
8033         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8034                 if (encoder->crtc == crtc)
8035                         return true;
8036
8037         return false;
8038 }
8039
8040 static void
8041 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8042 {
8043         struct intel_encoder *intel_encoder;
8044         struct intel_crtc *intel_crtc;
8045         struct drm_connector *connector;
8046
8047         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8048                             base.head) {
8049                 if (!intel_encoder->base.crtc)
8050                         continue;
8051
8052                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8053
8054                 if (prepare_pipes & (1 << intel_crtc->pipe))
8055                         intel_encoder->connectors_active = false;
8056         }
8057
8058         intel_modeset_commit_output_state(dev);
8059
8060         /* Update computed state. */
8061         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8062                             base.head) {
8063                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8064         }
8065
8066         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8067                 if (!connector->encoder || !connector->encoder->crtc)
8068                         continue;
8069
8070                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8071
8072                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8073                         struct drm_property *dpms_property =
8074                                 dev->mode_config.dpms_property;
8075
8076                         connector->dpms = DRM_MODE_DPMS_ON;
8077                         drm_object_property_set_value(&connector->base,
8078                                                          dpms_property,
8079                                                          DRM_MODE_DPMS_ON);
8080
8081                         intel_encoder = to_intel_encoder(connector->encoder);
8082                         intel_encoder->connectors_active = true;
8083                 }
8084         }
8085
8086 }
8087
8088 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8089         list_for_each_entry((intel_crtc), \
8090                             &(dev)->mode_config.crtc_list, \
8091                             base.head) \
8092                 if (mask & (1 <<(intel_crtc)->pipe))
8093
8094 static bool
8095 intel_pipe_config_compare(struct drm_device *dev,
8096                           struct intel_crtc_config *current_config,
8097                           struct intel_crtc_config *pipe_config)
8098 {
8099 #define PIPE_CONF_CHECK_I(name) \
8100         if (current_config->name != pipe_config->name) { \
8101                 DRM_ERROR("mismatch in " #name " " \
8102                           "(expected %i, found %i)\n", \
8103                           current_config->name, \
8104                           pipe_config->name); \
8105                 return false; \
8106         }
8107
8108 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8109         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8110                 DRM_ERROR("mismatch in " #name " " \
8111                           "(expected %i, found %i)\n", \
8112                           current_config->name & (mask), \
8113                           pipe_config->name & (mask)); \
8114                 return false; \
8115         }
8116
8117 #define PIPE_CONF_QUIRK(quirk)  \
8118         ((current_config->quirks | pipe_config->quirks) & (quirk))
8119
8120         PIPE_CONF_CHECK_I(cpu_transcoder);
8121
8122         PIPE_CONF_CHECK_I(has_pch_encoder);
8123         PIPE_CONF_CHECK_I(fdi_lanes);
8124         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8125         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8126         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8127         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8128         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8129
8130         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8131         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8132         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8133         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8134         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8135         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8136
8137         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8138         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8139         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8140         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8141         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8142         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8143
8144         if (!HAS_PCH_SPLIT(dev))
8145                 PIPE_CONF_CHECK_I(pixel_multiplier);
8146
8147         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8148                               DRM_MODE_FLAG_INTERLACE);
8149
8150         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8151                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8152                                       DRM_MODE_FLAG_PHSYNC);
8153                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8154                                       DRM_MODE_FLAG_NHSYNC);
8155                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8156                                       DRM_MODE_FLAG_PVSYNC);
8157                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8158                                       DRM_MODE_FLAG_NVSYNC);
8159         }
8160
8161         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8162         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8163
8164         PIPE_CONF_CHECK_I(gmch_pfit.control);
8165         /* pfit ratios are autocomputed by the hw on gen4+ */
8166         if (INTEL_INFO(dev)->gen < 4)
8167                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8168         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8169         PIPE_CONF_CHECK_I(pch_pfit.pos);
8170         PIPE_CONF_CHECK_I(pch_pfit.size);
8171
8172         PIPE_CONF_CHECK_I(ips_enabled);
8173
8174 #undef PIPE_CONF_CHECK_I
8175 #undef PIPE_CONF_CHECK_FLAGS
8176 #undef PIPE_CONF_QUIRK
8177
8178         return true;
8179 }
8180
8181 void
8182 intel_modeset_check_state(struct drm_device *dev)
8183 {
8184         drm_i915_private_t *dev_priv = dev->dev_private;
8185         struct intel_crtc *crtc;
8186         struct intel_encoder *encoder;
8187         struct intel_connector *connector;
8188         struct intel_crtc_config pipe_config;
8189
8190         list_for_each_entry(connector, &dev->mode_config.connector_list,
8191                             base.head) {
8192                 /* This also checks the encoder/connector hw state with the
8193                  * ->get_hw_state callbacks. */
8194                 intel_connector_check_state(connector);
8195
8196                 WARN(&connector->new_encoder->base != connector->base.encoder,
8197                      "connector's staged encoder doesn't match current encoder\n");
8198         }
8199
8200         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8201                             base.head) {
8202                 bool enabled = false;
8203                 bool active = false;
8204                 enum pipe pipe, tracked_pipe;
8205
8206                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8207                               encoder->base.base.id,
8208                               drm_get_encoder_name(&encoder->base));
8209
8210                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8211                      "encoder's stage crtc doesn't match current crtc\n");
8212                 WARN(encoder->connectors_active && !encoder->base.crtc,
8213                      "encoder's active_connectors set, but no crtc\n");
8214
8215                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8216                                     base.head) {
8217                         if (connector->base.encoder != &encoder->base)
8218                                 continue;
8219                         enabled = true;
8220                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8221                                 active = true;
8222                 }
8223                 WARN(!!encoder->base.crtc != enabled,
8224                      "encoder's enabled state mismatch "
8225                      "(expected %i, found %i)\n",
8226                      !!encoder->base.crtc, enabled);
8227                 WARN(active && !encoder->base.crtc,
8228                      "active encoder with no crtc\n");
8229
8230                 WARN(encoder->connectors_active != active,
8231                      "encoder's computed active state doesn't match tracked active state "
8232                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8233
8234                 active = encoder->get_hw_state(encoder, &pipe);
8235                 WARN(active != encoder->connectors_active,
8236                      "encoder's hw state doesn't match sw tracking "
8237                      "(expected %i, found %i)\n",
8238                      encoder->connectors_active, active);
8239
8240                 if (!encoder->base.crtc)
8241                         continue;
8242
8243                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8244                 WARN(active && pipe != tracked_pipe,
8245                      "active encoder's pipe doesn't match"
8246                      "(expected %i, found %i)\n",
8247                      tracked_pipe, pipe);
8248
8249         }
8250
8251         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8252                             base.head) {
8253                 bool enabled = false;
8254                 bool active = false;
8255
8256                 memset(&pipe_config, 0, sizeof(pipe_config));
8257
8258                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8259                               crtc->base.base.id);
8260
8261                 WARN(crtc->active && !crtc->base.enabled,
8262                      "active crtc, but not enabled in sw tracking\n");
8263
8264                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8265                                     base.head) {
8266                         if (encoder->base.crtc != &crtc->base)
8267                                 continue;
8268                         enabled = true;
8269                         if (encoder->connectors_active)
8270                                 active = true;
8271                 }
8272
8273                 WARN(active != crtc->active,
8274                      "crtc's computed active state doesn't match tracked active state "
8275                      "(expected %i, found %i)\n", active, crtc->active);
8276                 WARN(enabled != crtc->base.enabled,
8277                      "crtc's computed enabled state doesn't match tracked enabled state "
8278                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8279
8280                 active = dev_priv->display.get_pipe_config(crtc,
8281                                                            &pipe_config);
8282                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8283                                     base.head) {
8284                         if (encoder->base.crtc != &crtc->base)
8285                                 continue;
8286                         if (encoder->get_config)
8287                                 encoder->get_config(encoder, &pipe_config);
8288                 }
8289
8290                 WARN(crtc->active != active,
8291                      "crtc active state doesn't match with hw state "
8292                      "(expected %i, found %i)\n", crtc->active, active);
8293
8294                 if (active &&
8295                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8296                         WARN(1, "pipe state doesn't match!\n");
8297                         intel_dump_pipe_config(crtc, &pipe_config,
8298                                                "[hw state]");
8299                         intel_dump_pipe_config(crtc, &crtc->config,
8300                                                "[sw state]");
8301                 }
8302         }
8303 }
8304
8305 static int __intel_set_mode(struct drm_crtc *crtc,
8306                             struct drm_display_mode *mode,
8307                             int x, int y, struct drm_framebuffer *fb)
8308 {
8309         struct drm_device *dev = crtc->dev;
8310         drm_i915_private_t *dev_priv = dev->dev_private;
8311         struct drm_display_mode *saved_mode, *saved_hwmode;
8312         struct intel_crtc_config *pipe_config = NULL;
8313         struct intel_crtc *intel_crtc;
8314         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8315         int ret = 0;
8316
8317         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8318         if (!saved_mode)
8319                 return -ENOMEM;
8320         saved_hwmode = saved_mode + 1;
8321
8322         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8323                                      &prepare_pipes, &disable_pipes);
8324
8325         *saved_hwmode = crtc->hwmode;
8326         *saved_mode = crtc->mode;
8327
8328         /* Hack: Because we don't (yet) support global modeset on multiple
8329          * crtcs, we don't keep track of the new mode for more than one crtc.
8330          * Hence simply check whether any bit is set in modeset_pipes in all the
8331          * pieces of code that are not yet converted to deal with mutliple crtcs
8332          * changing their mode at the same time. */
8333         if (modeset_pipes) {
8334                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8335                 if (IS_ERR(pipe_config)) {
8336                         ret = PTR_ERR(pipe_config);
8337                         pipe_config = NULL;
8338
8339                         goto out;
8340                 }
8341                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8342                                        "[modeset]");
8343         }
8344
8345         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8346                 intel_crtc_disable(&intel_crtc->base);
8347
8348         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8349                 if (intel_crtc->base.enabled)
8350                         dev_priv->display.crtc_disable(&intel_crtc->base);
8351         }
8352
8353         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8354          * to set it here already despite that we pass it down the callchain.
8355          */
8356         if (modeset_pipes) {
8357                 crtc->mode = *mode;
8358                 /* mode_set/enable/disable functions rely on a correct pipe
8359                  * config. */
8360                 to_intel_crtc(crtc)->config = *pipe_config;
8361         }
8362
8363         /* Only after disabling all output pipelines that will be changed can we
8364          * update the the output configuration. */
8365         intel_modeset_update_state(dev, prepare_pipes);
8366
8367         if (dev_priv->display.modeset_global_resources)
8368                 dev_priv->display.modeset_global_resources(dev);
8369
8370         /* Set up the DPLL and any encoders state that needs to adjust or depend
8371          * on the DPLL.
8372          */
8373         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8374                 ret = intel_crtc_mode_set(&intel_crtc->base,
8375                                           x, y, fb);
8376                 if (ret)
8377                         goto done;
8378         }
8379
8380         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8381         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8382                 dev_priv->display.crtc_enable(&intel_crtc->base);
8383
8384         if (modeset_pipes) {
8385                 /* Store real post-adjustment hardware mode. */
8386                 crtc->hwmode = pipe_config->adjusted_mode;
8387
8388                 /* Calculate and store various constants which
8389                  * are later needed by vblank and swap-completion
8390                  * timestamping. They are derived from true hwmode.
8391                  */
8392                 drm_calc_timestamping_constants(crtc);
8393         }
8394
8395         /* FIXME: add subpixel order */
8396 done:
8397         if (ret && crtc->enabled) {
8398                 crtc->hwmode = *saved_hwmode;
8399                 crtc->mode = *saved_mode;
8400         }
8401
8402 out:
8403         kfree(pipe_config);
8404         kfree(saved_mode);
8405         return ret;
8406 }
8407
8408 int intel_set_mode(struct drm_crtc *crtc,
8409                      struct drm_display_mode *mode,
8410                      int x, int y, struct drm_framebuffer *fb)
8411 {
8412         int ret;
8413
8414         ret = __intel_set_mode(crtc, mode, x, y, fb);
8415
8416         if (ret == 0)
8417                 intel_modeset_check_state(crtc->dev);
8418
8419         return ret;
8420 }
8421
8422 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8423 {
8424         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8425 }
8426
8427 #undef for_each_intel_crtc_masked
8428
8429 static void intel_set_config_free(struct intel_set_config *config)
8430 {
8431         if (!config)
8432                 return;
8433
8434         kfree(config->save_connector_encoders);
8435         kfree(config->save_encoder_crtcs);
8436         kfree(config);
8437 }
8438
8439 static int intel_set_config_save_state(struct drm_device *dev,
8440                                        struct intel_set_config *config)
8441 {
8442         struct drm_encoder *encoder;
8443         struct drm_connector *connector;
8444         int count;
8445
8446         config->save_encoder_crtcs =
8447                 kcalloc(dev->mode_config.num_encoder,
8448                         sizeof(struct drm_crtc *), GFP_KERNEL);
8449         if (!config->save_encoder_crtcs)
8450                 return -ENOMEM;
8451
8452         config->save_connector_encoders =
8453                 kcalloc(dev->mode_config.num_connector,
8454                         sizeof(struct drm_encoder *), GFP_KERNEL);
8455         if (!config->save_connector_encoders)
8456                 return -ENOMEM;
8457
8458         /* Copy data. Note that driver private data is not affected.
8459          * Should anything bad happen only the expected state is
8460          * restored, not the drivers personal bookkeeping.
8461          */
8462         count = 0;
8463         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8464                 config->save_encoder_crtcs[count++] = encoder->crtc;
8465         }
8466
8467         count = 0;
8468         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8469                 config->save_connector_encoders[count++] = connector->encoder;
8470         }
8471
8472         return 0;
8473 }
8474
8475 static void intel_set_config_restore_state(struct drm_device *dev,
8476                                            struct intel_set_config *config)
8477 {
8478         struct intel_encoder *encoder;
8479         struct intel_connector *connector;
8480         int count;
8481
8482         count = 0;
8483         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8484                 encoder->new_crtc =
8485                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8486         }
8487
8488         count = 0;
8489         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8490                 connector->new_encoder =
8491                         to_intel_encoder(config->save_connector_encoders[count++]);
8492         }
8493 }
8494
8495 static void
8496 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8497                                       struct intel_set_config *config)
8498 {
8499
8500         /* We should be able to check here if the fb has the same properties
8501          * and then just flip_or_move it */
8502         if (set->crtc->fb != set->fb) {
8503                 /* If we have no fb then treat it as a full mode set */
8504                 if (set->crtc->fb == NULL) {
8505                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8506                         config->mode_changed = true;
8507                 } else if (set->fb == NULL) {
8508                         config->mode_changed = true;
8509                 } else if (set->fb->pixel_format !=
8510                            set->crtc->fb->pixel_format) {
8511                         config->mode_changed = true;
8512                 } else
8513                         config->fb_changed = true;
8514         }
8515
8516         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8517                 config->fb_changed = true;
8518
8519         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8520                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8521                 drm_mode_debug_printmodeline(&set->crtc->mode);
8522                 drm_mode_debug_printmodeline(set->mode);
8523                 config->mode_changed = true;
8524         }
8525 }
8526
8527 static int
8528 intel_modeset_stage_output_state(struct drm_device *dev,
8529                                  struct drm_mode_set *set,
8530                                  struct intel_set_config *config)
8531 {
8532         struct drm_crtc *new_crtc;
8533         struct intel_connector *connector;
8534         struct intel_encoder *encoder;
8535         int count, ro;
8536
8537         /* The upper layers ensure that we either disable a crtc or have a list
8538          * of connectors. For paranoia, double-check this. */
8539         WARN_ON(!set->fb && (set->num_connectors != 0));
8540         WARN_ON(set->fb && (set->num_connectors == 0));
8541
8542         count = 0;
8543         list_for_each_entry(connector, &dev->mode_config.connector_list,
8544                             base.head) {
8545                 /* Otherwise traverse passed in connector list and get encoders
8546                  * for them. */
8547                 for (ro = 0; ro < set->num_connectors; ro++) {
8548                         if (set->connectors[ro] == &connector->base) {
8549                                 connector->new_encoder = connector->encoder;
8550                                 break;
8551                         }
8552                 }
8553
8554                 /* If we disable the crtc, disable all its connectors. Also, if
8555                  * the connector is on the changing crtc but not on the new
8556                  * connector list, disable it. */
8557                 if ((!set->fb || ro == set->num_connectors) &&
8558                     connector->base.encoder &&
8559                     connector->base.encoder->crtc == set->crtc) {
8560                         connector->new_encoder = NULL;
8561
8562                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8563                                 connector->base.base.id,
8564                                 drm_get_connector_name(&connector->base));
8565                 }
8566
8567
8568                 if (&connector->new_encoder->base != connector->base.encoder) {
8569                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8570                         config->mode_changed = true;
8571                 }
8572         }
8573         /* connector->new_encoder is now updated for all connectors. */
8574
8575         /* Update crtc of enabled connectors. */
8576         count = 0;
8577         list_for_each_entry(connector, &dev->mode_config.connector_list,
8578                             base.head) {
8579                 if (!connector->new_encoder)
8580                         continue;
8581
8582                 new_crtc = connector->new_encoder->base.crtc;
8583
8584                 for (ro = 0; ro < set->num_connectors; ro++) {
8585                         if (set->connectors[ro] == &connector->base)
8586                                 new_crtc = set->crtc;
8587                 }
8588
8589                 /* Make sure the new CRTC will work with the encoder */
8590                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8591                                            new_crtc)) {
8592                         return -EINVAL;
8593                 }
8594                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8595
8596                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8597                         connector->base.base.id,
8598                         drm_get_connector_name(&connector->base),
8599                         new_crtc->base.id);
8600         }
8601
8602         /* Check for any encoders that needs to be disabled. */
8603         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8604                             base.head) {
8605                 list_for_each_entry(connector,
8606                                     &dev->mode_config.connector_list,
8607                                     base.head) {
8608                         if (connector->new_encoder == encoder) {
8609                                 WARN_ON(!connector->new_encoder->new_crtc);
8610
8611                                 goto next_encoder;
8612                         }
8613                 }
8614                 encoder->new_crtc = NULL;
8615 next_encoder:
8616                 /* Only now check for crtc changes so we don't miss encoders
8617                  * that will be disabled. */
8618                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8619                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8620                         config->mode_changed = true;
8621                 }
8622         }
8623         /* Now we've also updated encoder->new_crtc for all encoders. */
8624
8625         return 0;
8626 }
8627
8628 static int intel_crtc_set_config(struct drm_mode_set *set)
8629 {
8630         struct drm_device *dev;
8631         struct drm_mode_set save_set;
8632         struct intel_set_config *config;
8633         int ret;
8634
8635         BUG_ON(!set);
8636         BUG_ON(!set->crtc);
8637         BUG_ON(!set->crtc->helper_private);
8638
8639         /* Enforce sane interface api - has been abused by the fb helper. */
8640         BUG_ON(!set->mode && set->fb);
8641         BUG_ON(set->fb && set->num_connectors == 0);
8642
8643         if (set->fb) {
8644                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8645                                 set->crtc->base.id, set->fb->base.id,
8646                                 (int)set->num_connectors, set->x, set->y);
8647         } else {
8648                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8649         }
8650
8651         dev = set->crtc->dev;
8652
8653         ret = -ENOMEM;
8654         config = kzalloc(sizeof(*config), GFP_KERNEL);
8655         if (!config)
8656                 goto out_config;
8657
8658         ret = intel_set_config_save_state(dev, config);
8659         if (ret)
8660                 goto out_config;
8661
8662         save_set.crtc = set->crtc;
8663         save_set.mode = &set->crtc->mode;
8664         save_set.x = set->crtc->x;
8665         save_set.y = set->crtc->y;
8666         save_set.fb = set->crtc->fb;
8667
8668         /* Compute whether we need a full modeset, only an fb base update or no
8669          * change at all. In the future we might also check whether only the
8670          * mode changed, e.g. for LVDS where we only change the panel fitter in
8671          * such cases. */
8672         intel_set_config_compute_mode_changes(set, config);
8673
8674         ret = intel_modeset_stage_output_state(dev, set, config);
8675         if (ret)
8676                 goto fail;
8677
8678         if (config->mode_changed) {
8679                 ret = intel_set_mode(set->crtc, set->mode,
8680                                      set->x, set->y, set->fb);
8681                 if (ret) {
8682                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8683                                   set->crtc->base.id, ret);
8684                         goto fail;
8685                 }
8686         } else if (config->fb_changed) {
8687                 intel_crtc_wait_for_pending_flips(set->crtc);
8688
8689                 ret = intel_pipe_set_base(set->crtc,
8690                                           set->x, set->y, set->fb);
8691         }
8692
8693         intel_set_config_free(config);
8694
8695         return 0;
8696
8697 fail:
8698         intel_set_config_restore_state(dev, config);
8699
8700         /* Try to restore the config */
8701         if (config->mode_changed &&
8702             intel_set_mode(save_set.crtc, save_set.mode,
8703                            save_set.x, save_set.y, save_set.fb))
8704                 DRM_ERROR("failed to restore config after modeset failure\n");
8705
8706 out_config:
8707         intel_set_config_free(config);
8708         return ret;
8709 }
8710
8711 static const struct drm_crtc_funcs intel_crtc_funcs = {
8712         .cursor_set = intel_crtc_cursor_set,
8713         .cursor_move = intel_crtc_cursor_move,
8714         .gamma_set = intel_crtc_gamma_set,
8715         .set_config = intel_crtc_set_config,
8716         .destroy = intel_crtc_destroy,
8717         .page_flip = intel_crtc_page_flip,
8718 };
8719
8720 static void intel_cpu_pll_init(struct drm_device *dev)
8721 {
8722         if (HAS_DDI(dev))
8723                 intel_ddi_pll_init(dev);
8724 }
8725
8726 static void intel_pch_pll_init(struct drm_device *dev)
8727 {
8728         drm_i915_private_t *dev_priv = dev->dev_private;
8729         int i;
8730
8731         if (dev_priv->num_pch_pll == 0) {
8732                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8733                 return;
8734         }
8735
8736         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8737                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8738                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8739                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8740         }
8741 }
8742
8743 static void intel_crtc_init(struct drm_device *dev, int pipe)
8744 {
8745         drm_i915_private_t *dev_priv = dev->dev_private;
8746         struct intel_crtc *intel_crtc;
8747         int i;
8748
8749         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8750         if (intel_crtc == NULL)
8751                 return;
8752
8753         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8754
8755         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8756         for (i = 0; i < 256; i++) {
8757                 intel_crtc->lut_r[i] = i;
8758                 intel_crtc->lut_g[i] = i;
8759                 intel_crtc->lut_b[i] = i;
8760         }
8761
8762         /* Swap pipes & planes for FBC on pre-965 */
8763         intel_crtc->pipe = pipe;
8764         intel_crtc->plane = pipe;
8765         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8766                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8767                 intel_crtc->plane = !pipe;
8768         }
8769
8770         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8771                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8772         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8773         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8774
8775         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8776 }
8777
8778 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8779                                 struct drm_file *file)
8780 {
8781         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8782         struct drm_mode_object *drmmode_obj;
8783         struct intel_crtc *crtc;
8784
8785         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8786                 return -ENODEV;
8787
8788         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8789                         DRM_MODE_OBJECT_CRTC);
8790
8791         if (!drmmode_obj) {
8792                 DRM_ERROR("no such CRTC id\n");
8793                 return -EINVAL;
8794         }
8795
8796         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8797         pipe_from_crtc_id->pipe = crtc->pipe;
8798
8799         return 0;
8800 }
8801
8802 static int intel_encoder_clones(struct intel_encoder *encoder)
8803 {
8804         struct drm_device *dev = encoder->base.dev;
8805         struct intel_encoder *source_encoder;
8806         int index_mask = 0;
8807         int entry = 0;
8808
8809         list_for_each_entry(source_encoder,
8810                             &dev->mode_config.encoder_list, base.head) {
8811
8812                 if (encoder == source_encoder)
8813                         index_mask |= (1 << entry);
8814
8815                 /* Intel hw has only one MUX where enocoders could be cloned. */
8816                 if (encoder->cloneable && source_encoder->cloneable)
8817                         index_mask |= (1 << entry);
8818
8819                 entry++;
8820         }
8821
8822         return index_mask;
8823 }
8824
8825 static bool has_edp_a(struct drm_device *dev)
8826 {
8827         struct drm_i915_private *dev_priv = dev->dev_private;
8828
8829         if (!IS_MOBILE(dev))
8830                 return false;
8831
8832         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8833                 return false;
8834
8835         if (IS_GEN5(dev) &&
8836             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8837                 return false;
8838
8839         return true;
8840 }
8841
8842 static void intel_setup_outputs(struct drm_device *dev)
8843 {
8844         struct drm_i915_private *dev_priv = dev->dev_private;
8845         struct intel_encoder *encoder;
8846         bool dpd_is_edp = false;
8847         bool has_lvds;
8848
8849         has_lvds = intel_lvds_init(dev);
8850         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8851                 /* disable the panel fitter on everything but LVDS */
8852                 I915_WRITE(PFIT_CONTROL, 0);
8853         }
8854
8855         if (!IS_ULT(dev))
8856                 intel_crt_init(dev);
8857
8858         if (HAS_DDI(dev)) {
8859                 int found;
8860
8861                 /* Haswell uses DDI functions to detect digital outputs */
8862                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8863                 /* DDI A only supports eDP */
8864                 if (found)
8865                         intel_ddi_init(dev, PORT_A);
8866
8867                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8868                  * register */
8869                 found = I915_READ(SFUSE_STRAP);
8870
8871                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8872                         intel_ddi_init(dev, PORT_B);
8873                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8874                         intel_ddi_init(dev, PORT_C);
8875                 if (found & SFUSE_STRAP_DDID_DETECTED)
8876                         intel_ddi_init(dev, PORT_D);
8877         } else if (HAS_PCH_SPLIT(dev)) {
8878                 int found;
8879                 dpd_is_edp = intel_dpd_is_edp(dev);
8880
8881                 if (has_edp_a(dev))
8882                         intel_dp_init(dev, DP_A, PORT_A);
8883
8884                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8885                         /* PCH SDVOB multiplex with HDMIB */
8886                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8887                         if (!found)
8888                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8889                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8890                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8891                 }
8892
8893                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8894                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8895
8896                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8897                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8898
8899                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8900                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8901
8902                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8903                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8904         } else if (IS_VALLEYVIEW(dev)) {
8905                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8906                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8907                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8908
8909                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8910                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8911                                         PORT_B);
8912                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8913                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8914                 }
8915         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8916                 bool found = false;
8917
8918                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8919                         DRM_DEBUG_KMS("probing SDVOB\n");
8920                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8921                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8922                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8923                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8924                         }
8925
8926                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8927                                 intel_dp_init(dev, DP_B, PORT_B);
8928                 }
8929
8930                 /* Before G4X SDVOC doesn't have its own detect register */
8931
8932                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8933                         DRM_DEBUG_KMS("probing SDVOC\n");
8934                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8935                 }
8936
8937                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8938
8939                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8940                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8941                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8942                         }
8943                         if (SUPPORTS_INTEGRATED_DP(dev))
8944                                 intel_dp_init(dev, DP_C, PORT_C);
8945                 }
8946
8947                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8948                     (I915_READ(DP_D) & DP_DETECTED))
8949                         intel_dp_init(dev, DP_D, PORT_D);
8950         } else if (IS_GEN2(dev))
8951                 intel_dvo_init(dev);
8952
8953         if (SUPPORTS_TV(dev))
8954                 intel_tv_init(dev);
8955
8956         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8957                 encoder->base.possible_crtcs = encoder->crtc_mask;
8958                 encoder->base.possible_clones =
8959                         intel_encoder_clones(encoder);
8960         }
8961
8962         intel_init_pch_refclk(dev);
8963
8964         drm_helper_move_panel_connectors_to_head(dev);
8965 }
8966
8967 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8968 {
8969         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8970
8971         drm_framebuffer_cleanup(fb);
8972         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8973
8974         kfree(intel_fb);
8975 }
8976
8977 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8978                                                 struct drm_file *file,
8979                                                 unsigned int *handle)
8980 {
8981         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8982         struct drm_i915_gem_object *obj = intel_fb->obj;
8983
8984         return drm_gem_handle_create(file, &obj->base, handle);
8985 }
8986
8987 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8988         .destroy = intel_user_framebuffer_destroy,
8989         .create_handle = intel_user_framebuffer_create_handle,
8990 };
8991
8992 int intel_framebuffer_init(struct drm_device *dev,
8993                            struct intel_framebuffer *intel_fb,
8994                            struct drm_mode_fb_cmd2 *mode_cmd,
8995                            struct drm_i915_gem_object *obj)
8996 {
8997         int ret;
8998
8999         if (obj->tiling_mode == I915_TILING_Y) {
9000                 DRM_DEBUG("hardware does not support tiling Y\n");
9001                 return -EINVAL;
9002         }
9003
9004         if (mode_cmd->pitches[0] & 63) {
9005                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9006                           mode_cmd->pitches[0]);
9007                 return -EINVAL;
9008         }
9009
9010         /* FIXME <= Gen4 stride limits are bit unclear */
9011         if (mode_cmd->pitches[0] > 32768) {
9012                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9013                           mode_cmd->pitches[0]);
9014                 return -EINVAL;
9015         }
9016
9017         if (obj->tiling_mode != I915_TILING_NONE &&
9018             mode_cmd->pitches[0] != obj->stride) {
9019                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9020                           mode_cmd->pitches[0], obj->stride);
9021                 return -EINVAL;
9022         }
9023
9024         /* Reject formats not supported by any plane early. */
9025         switch (mode_cmd->pixel_format) {
9026         case DRM_FORMAT_C8:
9027         case DRM_FORMAT_RGB565:
9028         case DRM_FORMAT_XRGB8888:
9029         case DRM_FORMAT_ARGB8888:
9030                 break;
9031         case DRM_FORMAT_XRGB1555:
9032         case DRM_FORMAT_ARGB1555:
9033                 if (INTEL_INFO(dev)->gen > 3) {
9034                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9035                         return -EINVAL;
9036                 }
9037                 break;
9038         case DRM_FORMAT_XBGR8888:
9039         case DRM_FORMAT_ABGR8888:
9040         case DRM_FORMAT_XRGB2101010:
9041         case DRM_FORMAT_ARGB2101010:
9042         case DRM_FORMAT_XBGR2101010:
9043         case DRM_FORMAT_ABGR2101010:
9044                 if (INTEL_INFO(dev)->gen < 4) {
9045                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9046                         return -EINVAL;
9047                 }
9048                 break;
9049         case DRM_FORMAT_YUYV:
9050         case DRM_FORMAT_UYVY:
9051         case DRM_FORMAT_YVYU:
9052         case DRM_FORMAT_VYUY:
9053                 if (INTEL_INFO(dev)->gen < 5) {
9054                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9055                         return -EINVAL;
9056                 }
9057                 break;
9058         default:
9059                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
9060                 return -EINVAL;
9061         }
9062
9063         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9064         if (mode_cmd->offsets[0] != 0)
9065                 return -EINVAL;
9066
9067         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9068         intel_fb->obj = obj;
9069
9070         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9071         if (ret) {
9072                 DRM_ERROR("framebuffer init failed %d\n", ret);
9073                 return ret;
9074         }
9075
9076         return 0;
9077 }
9078
9079 static struct drm_framebuffer *
9080 intel_user_framebuffer_create(struct drm_device *dev,
9081                               struct drm_file *filp,
9082                               struct drm_mode_fb_cmd2 *mode_cmd)
9083 {
9084         struct drm_i915_gem_object *obj;
9085
9086         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9087                                                 mode_cmd->handles[0]));
9088         if (&obj->base == NULL)
9089                 return ERR_PTR(-ENOENT);
9090
9091         return intel_framebuffer_create(dev, mode_cmd, obj);
9092 }
9093
9094 static const struct drm_mode_config_funcs intel_mode_funcs = {
9095         .fb_create = intel_user_framebuffer_create,
9096         .output_poll_changed = intel_fb_output_poll_changed,
9097 };
9098
9099 /* Set up chip specific display functions */
9100 static void intel_init_display(struct drm_device *dev)
9101 {
9102         struct drm_i915_private *dev_priv = dev->dev_private;
9103
9104         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9105                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9106         else if (IS_VALLEYVIEW(dev))
9107                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9108         else if (IS_PINEVIEW(dev))
9109                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9110         else
9111                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9112
9113         if (HAS_DDI(dev)) {
9114                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9115                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9116                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9117                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9118                 dev_priv->display.off = haswell_crtc_off;
9119                 dev_priv->display.update_plane = ironlake_update_plane;
9120         } else if (HAS_PCH_SPLIT(dev)) {
9121                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9122                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9123                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9124                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9125                 dev_priv->display.off = ironlake_crtc_off;
9126                 dev_priv->display.update_plane = ironlake_update_plane;
9127         } else if (IS_VALLEYVIEW(dev)) {
9128                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9129                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9130                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9131                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9132                 dev_priv->display.off = i9xx_crtc_off;
9133                 dev_priv->display.update_plane = i9xx_update_plane;
9134         } else {
9135                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9136                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9137                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9138                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9139                 dev_priv->display.off = i9xx_crtc_off;
9140                 dev_priv->display.update_plane = i9xx_update_plane;
9141         }
9142
9143         /* Returns the core display clock speed */
9144         if (IS_VALLEYVIEW(dev))
9145                 dev_priv->display.get_display_clock_speed =
9146                         valleyview_get_display_clock_speed;
9147         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9148                 dev_priv->display.get_display_clock_speed =
9149                         i945_get_display_clock_speed;
9150         else if (IS_I915G(dev))
9151                 dev_priv->display.get_display_clock_speed =
9152                         i915_get_display_clock_speed;
9153         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9154                 dev_priv->display.get_display_clock_speed =
9155                         i9xx_misc_get_display_clock_speed;
9156         else if (IS_I915GM(dev))
9157                 dev_priv->display.get_display_clock_speed =
9158                         i915gm_get_display_clock_speed;
9159         else if (IS_I865G(dev))
9160                 dev_priv->display.get_display_clock_speed =
9161                         i865_get_display_clock_speed;
9162         else if (IS_I85X(dev))
9163                 dev_priv->display.get_display_clock_speed =
9164                         i855_get_display_clock_speed;
9165         else /* 852, 830 */
9166                 dev_priv->display.get_display_clock_speed =
9167                         i830_get_display_clock_speed;
9168
9169         if (HAS_PCH_SPLIT(dev)) {
9170                 if (IS_GEN5(dev)) {
9171                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9172                         dev_priv->display.write_eld = ironlake_write_eld;
9173                 } else if (IS_GEN6(dev)) {
9174                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9175                         dev_priv->display.write_eld = ironlake_write_eld;
9176                 } else if (IS_IVYBRIDGE(dev)) {
9177                         /* FIXME: detect B0+ stepping and use auto training */
9178                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9179                         dev_priv->display.write_eld = ironlake_write_eld;
9180                         dev_priv->display.modeset_global_resources =
9181                                 ivb_modeset_global_resources;
9182                 } else if (IS_HASWELL(dev)) {
9183                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9184                         dev_priv->display.write_eld = haswell_write_eld;
9185                         dev_priv->display.modeset_global_resources =
9186                                 haswell_modeset_global_resources;
9187                 }
9188         } else if (IS_G4X(dev)) {
9189                 dev_priv->display.write_eld = g4x_write_eld;
9190         }
9191
9192         /* Default just returns -ENODEV to indicate unsupported */
9193         dev_priv->display.queue_flip = intel_default_queue_flip;
9194
9195         switch (INTEL_INFO(dev)->gen) {
9196         case 2:
9197                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9198                 break;
9199
9200         case 3:
9201                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9202                 break;
9203
9204         case 4:
9205         case 5:
9206                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9207                 break;
9208
9209         case 6:
9210                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9211                 break;
9212         case 7:
9213                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9214                 break;
9215         }
9216 }
9217
9218 /*
9219  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9220  * resume, or other times.  This quirk makes sure that's the case for
9221  * affected systems.
9222  */
9223 static void quirk_pipea_force(struct drm_device *dev)
9224 {
9225         struct drm_i915_private *dev_priv = dev->dev_private;
9226
9227         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9228         DRM_INFO("applying pipe a force quirk\n");
9229 }
9230
9231 /*
9232  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9233  */
9234 static void quirk_ssc_force_disable(struct drm_device *dev)
9235 {
9236         struct drm_i915_private *dev_priv = dev->dev_private;
9237         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9238         DRM_INFO("applying lvds SSC disable quirk\n");
9239 }
9240
9241 /*
9242  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9243  * brightness value
9244  */
9245 static void quirk_invert_brightness(struct drm_device *dev)
9246 {
9247         struct drm_i915_private *dev_priv = dev->dev_private;
9248         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9249         DRM_INFO("applying inverted panel brightness quirk\n");
9250 }
9251
9252 struct intel_quirk {
9253         int device;
9254         int subsystem_vendor;
9255         int subsystem_device;
9256         void (*hook)(struct drm_device *dev);
9257 };
9258
9259 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9260 struct intel_dmi_quirk {
9261         void (*hook)(struct drm_device *dev);
9262         const struct dmi_system_id (*dmi_id_list)[];
9263 };
9264
9265 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9266 {
9267         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9268         return 1;
9269 }
9270
9271 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9272         {
9273                 .dmi_id_list = &(const struct dmi_system_id[]) {
9274                         {
9275                                 .callback = intel_dmi_reverse_brightness,
9276                                 .ident = "NCR Corporation",
9277                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9278                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9279                                 },
9280                         },
9281                         { }  /* terminating entry */
9282                 },
9283                 .hook = quirk_invert_brightness,
9284         },
9285 };
9286
9287 static struct intel_quirk intel_quirks[] = {
9288         /* HP Mini needs pipe A force quirk (LP: #322104) */
9289         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9290
9291         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9292         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9293
9294         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9295         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9296
9297         /* 830/845 need to leave pipe A & dpll A up */
9298         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9299         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9300
9301         /* Lenovo U160 cannot use SSC on LVDS */
9302         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9303
9304         /* Sony Vaio Y cannot use SSC on LVDS */
9305         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9306
9307         /* Acer Aspire 5734Z must invert backlight brightness */
9308         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9309
9310         /* Acer/eMachines G725 */
9311         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9312
9313         /* Acer/eMachines e725 */
9314         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9315
9316         /* Acer/Packard Bell NCL20 */
9317         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9318
9319         /* Acer Aspire 4736Z */
9320         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9321 };
9322
9323 static void intel_init_quirks(struct drm_device *dev)
9324 {
9325         struct pci_dev *d = dev->pdev;
9326         int i;
9327
9328         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9329                 struct intel_quirk *q = &intel_quirks[i];
9330
9331                 if (d->device == q->device &&
9332                     (d->subsystem_vendor == q->subsystem_vendor ||
9333                      q->subsystem_vendor == PCI_ANY_ID) &&
9334                     (d->subsystem_device == q->subsystem_device ||
9335                      q->subsystem_device == PCI_ANY_ID))
9336                         q->hook(dev);
9337         }
9338         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9339                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9340                         intel_dmi_quirks[i].hook(dev);
9341         }
9342 }
9343
9344 /* Disable the VGA plane that we never use */
9345 static void i915_disable_vga(struct drm_device *dev)
9346 {
9347         struct drm_i915_private *dev_priv = dev->dev_private;
9348         u8 sr1;
9349         u32 vga_reg = i915_vgacntrl_reg(dev);
9350
9351         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9352         outb(SR01, VGA_SR_INDEX);
9353         sr1 = inb(VGA_SR_DATA);
9354         outb(sr1 | 1<<5, VGA_SR_DATA);
9355         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9356         udelay(300);
9357
9358         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9359         POSTING_READ(vga_reg);
9360 }
9361
9362 void intel_modeset_init_hw(struct drm_device *dev)
9363 {
9364         intel_init_power_well(dev);
9365
9366         intel_prepare_ddi(dev);
9367
9368         intel_init_clock_gating(dev);
9369
9370         mutex_lock(&dev->struct_mutex);
9371         intel_enable_gt_powersave(dev);
9372         mutex_unlock(&dev->struct_mutex);
9373 }
9374
9375 void intel_modeset_suspend_hw(struct drm_device *dev)
9376 {
9377         intel_suspend_hw(dev);
9378 }
9379
9380 void intel_modeset_init(struct drm_device *dev)
9381 {
9382         struct drm_i915_private *dev_priv = dev->dev_private;
9383         int i, j, ret;
9384
9385         drm_mode_config_init(dev);
9386
9387         dev->mode_config.min_width = 0;
9388         dev->mode_config.min_height = 0;
9389
9390         dev->mode_config.preferred_depth = 24;
9391         dev->mode_config.prefer_shadow = 1;
9392
9393         dev->mode_config.funcs = &intel_mode_funcs;
9394
9395         intel_init_quirks(dev);
9396
9397         intel_init_pm(dev);
9398
9399         if (INTEL_INFO(dev)->num_pipes == 0)
9400                 return;
9401
9402         intel_init_display(dev);
9403
9404         if (IS_GEN2(dev)) {
9405                 dev->mode_config.max_width = 2048;
9406                 dev->mode_config.max_height = 2048;
9407         } else if (IS_GEN3(dev)) {
9408                 dev->mode_config.max_width = 4096;
9409                 dev->mode_config.max_height = 4096;
9410         } else {
9411                 dev->mode_config.max_width = 8192;
9412                 dev->mode_config.max_height = 8192;
9413         }
9414         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9415
9416         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9417                       INTEL_INFO(dev)->num_pipes,
9418                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9419
9420         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9421                 intel_crtc_init(dev, i);
9422                 for (j = 0; j < dev_priv->num_plane; j++) {
9423                         ret = intel_plane_init(dev, i, j);
9424                         if (ret)
9425                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9426                                               pipe_name(i), sprite_name(i, j), ret);
9427                 }
9428         }
9429
9430         intel_cpu_pll_init(dev);
9431         intel_pch_pll_init(dev);
9432
9433         /* Just disable it once at startup */
9434         i915_disable_vga(dev);
9435         intel_setup_outputs(dev);
9436
9437         /* Just in case the BIOS is doing something questionable. */
9438         intel_disable_fbc(dev);
9439 }
9440
9441 static void
9442 intel_connector_break_all_links(struct intel_connector *connector)
9443 {
9444         connector->base.dpms = DRM_MODE_DPMS_OFF;
9445         connector->base.encoder = NULL;
9446         connector->encoder->connectors_active = false;
9447         connector->encoder->base.crtc = NULL;
9448 }
9449
9450 static void intel_enable_pipe_a(struct drm_device *dev)
9451 {
9452         struct intel_connector *connector;
9453         struct drm_connector *crt = NULL;
9454         struct intel_load_detect_pipe load_detect_temp;
9455
9456         /* We can't just switch on the pipe A, we need to set things up with a
9457          * proper mode and output configuration. As a gross hack, enable pipe A
9458          * by enabling the load detect pipe once. */
9459         list_for_each_entry(connector,
9460                             &dev->mode_config.connector_list,
9461                             base.head) {
9462                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9463                         crt = &connector->base;
9464                         break;
9465                 }
9466         }
9467
9468         if (!crt)
9469                 return;
9470
9471         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9472                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9473
9474
9475 }
9476
9477 static bool
9478 intel_check_plane_mapping(struct intel_crtc *crtc)
9479 {
9480         struct drm_device *dev = crtc->base.dev;
9481         struct drm_i915_private *dev_priv = dev->dev_private;
9482         u32 reg, val;
9483
9484         if (INTEL_INFO(dev)->num_pipes == 1)
9485                 return true;
9486
9487         reg = DSPCNTR(!crtc->plane);
9488         val = I915_READ(reg);
9489
9490         if ((val & DISPLAY_PLANE_ENABLE) &&
9491             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9492                 return false;
9493
9494         return true;
9495 }
9496
9497 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9498 {
9499         struct drm_device *dev = crtc->base.dev;
9500         struct drm_i915_private *dev_priv = dev->dev_private;
9501         u32 reg;
9502
9503         /* Clear any frame start delays used for debugging left by the BIOS */
9504         reg = PIPECONF(crtc->config.cpu_transcoder);
9505         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9506
9507         /* We need to sanitize the plane -> pipe mapping first because this will
9508          * disable the crtc (and hence change the state) if it is wrong. Note
9509          * that gen4+ has a fixed plane -> pipe mapping.  */
9510         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9511                 struct intel_connector *connector;
9512                 bool plane;
9513
9514                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9515                               crtc->base.base.id);
9516
9517                 /* Pipe has the wrong plane attached and the plane is active.
9518                  * Temporarily change the plane mapping and disable everything
9519                  * ...  */
9520                 plane = crtc->plane;
9521                 crtc->plane = !plane;
9522                 dev_priv->display.crtc_disable(&crtc->base);
9523                 crtc->plane = plane;
9524
9525                 /* ... and break all links. */
9526                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9527                                     base.head) {
9528                         if (connector->encoder->base.crtc != &crtc->base)
9529                                 continue;
9530
9531                         intel_connector_break_all_links(connector);
9532                 }
9533
9534                 WARN_ON(crtc->active);
9535                 crtc->base.enabled = false;
9536         }
9537
9538         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9539             crtc->pipe == PIPE_A && !crtc->active) {
9540                 /* BIOS forgot to enable pipe A, this mostly happens after
9541                  * resume. Force-enable the pipe to fix this, the update_dpms
9542                  * call below we restore the pipe to the right state, but leave
9543                  * the required bits on. */
9544                 intel_enable_pipe_a(dev);
9545         }
9546
9547         /* Adjust the state of the output pipe according to whether we
9548          * have active connectors/encoders. */
9549         intel_crtc_update_dpms(&crtc->base);
9550
9551         if (crtc->active != crtc->base.enabled) {
9552                 struct intel_encoder *encoder;
9553
9554                 /* This can happen either due to bugs in the get_hw_state
9555                  * functions or because the pipe is force-enabled due to the
9556                  * pipe A quirk. */
9557                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9558                               crtc->base.base.id,
9559                               crtc->base.enabled ? "enabled" : "disabled",
9560                               crtc->active ? "enabled" : "disabled");
9561
9562                 crtc->base.enabled = crtc->active;
9563
9564                 /* Because we only establish the connector -> encoder ->
9565                  * crtc links if something is active, this means the
9566                  * crtc is now deactivated. Break the links. connector
9567                  * -> encoder links are only establish when things are
9568                  *  actually up, hence no need to break them. */
9569                 WARN_ON(crtc->active);
9570
9571                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9572                         WARN_ON(encoder->connectors_active);
9573                         encoder->base.crtc = NULL;
9574                 }
9575         }
9576 }
9577
9578 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9579 {
9580         struct intel_connector *connector;
9581         struct drm_device *dev = encoder->base.dev;
9582
9583         /* We need to check both for a crtc link (meaning that the
9584          * encoder is active and trying to read from a pipe) and the
9585          * pipe itself being active. */
9586         bool has_active_crtc = encoder->base.crtc &&
9587                 to_intel_crtc(encoder->base.crtc)->active;
9588
9589         if (encoder->connectors_active && !has_active_crtc) {
9590                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9591                               encoder->base.base.id,
9592                               drm_get_encoder_name(&encoder->base));
9593
9594                 /* Connector is active, but has no active pipe. This is
9595                  * fallout from our resume register restoring. Disable
9596                  * the encoder manually again. */
9597                 if (encoder->base.crtc) {
9598                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9599                                       encoder->base.base.id,
9600                                       drm_get_encoder_name(&encoder->base));
9601                         encoder->disable(encoder);
9602                 }
9603
9604                 /* Inconsistent output/port/pipe state happens presumably due to
9605                  * a bug in one of the get_hw_state functions. Or someplace else
9606                  * in our code, like the register restore mess on resume. Clamp
9607                  * things to off as a safer default. */
9608                 list_for_each_entry(connector,
9609                                     &dev->mode_config.connector_list,
9610                                     base.head) {
9611                         if (connector->encoder != encoder)
9612                                 continue;
9613
9614                         intel_connector_break_all_links(connector);
9615                 }
9616         }
9617         /* Enabled encoders without active connectors will be fixed in
9618          * the crtc fixup. */
9619 }
9620
9621 void i915_redisable_vga(struct drm_device *dev)
9622 {
9623         struct drm_i915_private *dev_priv = dev->dev_private;
9624         u32 vga_reg = i915_vgacntrl_reg(dev);
9625
9626         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9627                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9628                 i915_disable_vga(dev);
9629         }
9630 }
9631
9632 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9633  * and i915 state tracking structures. */
9634 void intel_modeset_setup_hw_state(struct drm_device *dev,
9635                                   bool force_restore)
9636 {
9637         struct drm_i915_private *dev_priv = dev->dev_private;
9638         enum pipe pipe;
9639         struct drm_plane *plane;
9640         struct intel_crtc *crtc;
9641         struct intel_encoder *encoder;
9642         struct intel_connector *connector;
9643
9644         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9645                             base.head) {
9646                 memset(&crtc->config, 0, sizeof(crtc->config));
9647
9648                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9649                                                                  &crtc->config);
9650
9651                 crtc->base.enabled = crtc->active;
9652
9653                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9654                               crtc->base.base.id,
9655                               crtc->active ? "enabled" : "disabled");
9656         }
9657
9658         if (HAS_DDI(dev))
9659                 intel_ddi_setup_hw_pll_state(dev);
9660
9661         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9662                             base.head) {
9663                 pipe = 0;
9664
9665                 if (encoder->get_hw_state(encoder, &pipe)) {
9666                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9667                         encoder->base.crtc = &crtc->base;
9668                         if (encoder->get_config)
9669                                 encoder->get_config(encoder, &crtc->config);
9670                 } else {
9671                         encoder->base.crtc = NULL;
9672                 }
9673
9674                 encoder->connectors_active = false;
9675                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9676                               encoder->base.base.id,
9677                               drm_get_encoder_name(&encoder->base),
9678                               encoder->base.crtc ? "enabled" : "disabled",
9679                               pipe);
9680         }
9681
9682         list_for_each_entry(connector, &dev->mode_config.connector_list,
9683                             base.head) {
9684                 if (connector->get_hw_state(connector)) {
9685                         connector->base.dpms = DRM_MODE_DPMS_ON;
9686                         connector->encoder->connectors_active = true;
9687                         connector->base.encoder = &connector->encoder->base;
9688                 } else {
9689                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9690                         connector->base.encoder = NULL;
9691                 }
9692                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9693                               connector->base.base.id,
9694                               drm_get_connector_name(&connector->base),
9695                               connector->base.encoder ? "enabled" : "disabled");
9696         }
9697
9698         /* HW state is read out, now we need to sanitize this mess. */
9699         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9700                             base.head) {
9701                 intel_sanitize_encoder(encoder);
9702         }
9703
9704         for_each_pipe(pipe) {
9705                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9706                 intel_sanitize_crtc(crtc);
9707                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9708         }
9709
9710         if (force_restore) {
9711                 /*
9712                  * We need to use raw interfaces for restoring state to avoid
9713                  * checking (bogus) intermediate states.
9714                  */
9715                 for_each_pipe(pipe) {
9716                         struct drm_crtc *crtc =
9717                                 dev_priv->pipe_to_crtc_mapping[pipe];
9718
9719                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9720                                          crtc->fb);
9721                 }
9722                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9723                         intel_plane_restore(plane);
9724
9725                 i915_redisable_vga(dev);
9726         } else {
9727                 intel_modeset_update_staged_output_state(dev);
9728         }
9729
9730         intel_modeset_check_state(dev);
9731
9732         drm_mode_config_reset(dev);
9733 }
9734
9735 void intel_modeset_gem_init(struct drm_device *dev)
9736 {
9737         intel_modeset_init_hw(dev);
9738
9739         intel_setup_overlay(dev);
9740
9741         intel_modeset_setup_hw_state(dev, false);
9742 }
9743
9744 void intel_modeset_cleanup(struct drm_device *dev)
9745 {
9746         struct drm_i915_private *dev_priv = dev->dev_private;
9747         struct drm_crtc *crtc;
9748         struct intel_crtc *intel_crtc;
9749
9750         /*
9751          * Interrupts and polling as the first thing to avoid creating havoc.
9752          * Too much stuff here (turning of rps, connectors, ...) would
9753          * experience fancy races otherwise.
9754          */
9755         drm_irq_uninstall(dev);
9756         cancel_work_sync(&dev_priv->hotplug_work);
9757         /*
9758          * Due to the hpd irq storm handling the hotplug work can re-arm the
9759          * poll handlers. Hence disable polling after hpd handling is shut down.
9760          */
9761         drm_kms_helper_poll_fini(dev);
9762
9763         mutex_lock(&dev->struct_mutex);
9764
9765         intel_unregister_dsm_handler();
9766
9767         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9768                 /* Skip inactive CRTCs */
9769                 if (!crtc->fb)
9770                         continue;
9771
9772                 intel_crtc = to_intel_crtc(crtc);
9773                 intel_increase_pllclock(crtc);
9774         }
9775
9776         intel_disable_fbc(dev);
9777
9778         intel_disable_gt_powersave(dev);
9779
9780         ironlake_teardown_rc6(dev);
9781
9782         mutex_unlock(&dev->struct_mutex);
9783
9784         /* flush any delayed tasks or pending work */
9785         flush_scheduled_work();
9786
9787         /* destroy backlight, if any, before the connectors */
9788         intel_panel_destroy_backlight(dev);
9789
9790         drm_mode_config_cleanup(dev);
9791
9792         intel_cleanup_overlay(dev);
9793 }
9794
9795 /*
9796  * Return which encoder is currently attached for connector.
9797  */
9798 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9799 {
9800         return &intel_attached_encoder(connector)->base;
9801 }
9802
9803 void intel_connector_attach_encoder(struct intel_connector *connector,
9804                                     struct intel_encoder *encoder)
9805 {
9806         connector->encoder = encoder;
9807         drm_mode_connector_attach_encoder(&connector->base,
9808                                           &encoder->base);
9809 }
9810
9811 /*
9812  * set vga decode state - true == enable VGA decode
9813  */
9814 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9815 {
9816         struct drm_i915_private *dev_priv = dev->dev_private;
9817         u16 gmch_ctrl;
9818
9819         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9820         if (state)
9821                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9822         else
9823                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9824         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9825         return 0;
9826 }
9827
9828 #ifdef CONFIG_DEBUG_FS
9829 #include <linux/seq_file.h>
9830
9831 struct intel_display_error_state {
9832
9833         u32 power_well_driver;
9834
9835         struct intel_cursor_error_state {
9836                 u32 control;
9837                 u32 position;
9838                 u32 base;
9839                 u32 size;
9840         } cursor[I915_MAX_PIPES];
9841
9842         struct intel_pipe_error_state {
9843                 enum transcoder cpu_transcoder;
9844                 u32 conf;
9845                 u32 source;
9846
9847                 u32 htotal;
9848                 u32 hblank;
9849                 u32 hsync;
9850                 u32 vtotal;
9851                 u32 vblank;
9852                 u32 vsync;
9853         } pipe[I915_MAX_PIPES];
9854
9855         struct intel_plane_error_state {
9856                 u32 control;
9857                 u32 stride;
9858                 u32 size;
9859                 u32 pos;
9860                 u32 addr;
9861                 u32 surface;
9862                 u32 tile_offset;
9863         } plane[I915_MAX_PIPES];
9864 };
9865
9866 struct intel_display_error_state *
9867 intel_display_capture_error_state(struct drm_device *dev)
9868 {
9869         drm_i915_private_t *dev_priv = dev->dev_private;
9870         struct intel_display_error_state *error;
9871         enum transcoder cpu_transcoder;
9872         int i;
9873
9874         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9875         if (error == NULL)
9876                 return NULL;
9877
9878         if (HAS_POWER_WELL(dev))
9879                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9880
9881         for_each_pipe(i) {
9882                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9883                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9884
9885                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9886                         error->cursor[i].control = I915_READ(CURCNTR(i));
9887                         error->cursor[i].position = I915_READ(CURPOS(i));
9888                         error->cursor[i].base = I915_READ(CURBASE(i));
9889                 } else {
9890                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9891                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9892                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9893                 }
9894
9895                 error->plane[i].control = I915_READ(DSPCNTR(i));
9896                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9897                 if (INTEL_INFO(dev)->gen <= 3) {
9898                         error->plane[i].size = I915_READ(DSPSIZE(i));
9899                         error->plane[i].pos = I915_READ(DSPPOS(i));
9900                 }
9901                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9902                         error->plane[i].addr = I915_READ(DSPADDR(i));
9903                 if (INTEL_INFO(dev)->gen >= 4) {
9904                         error->plane[i].surface = I915_READ(DSPSURF(i));
9905                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9906                 }
9907
9908                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9909                 error->pipe[i].source = I915_READ(PIPESRC(i));
9910                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9911                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9912                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9913                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9914                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9915                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9916         }
9917
9918         /* In the code above we read the registers without checking if the power
9919          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9920          * prevent the next I915_WRITE from detecting it and printing an error
9921          * message. */
9922         if (HAS_POWER_WELL(dev))
9923                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9924
9925         return error;
9926 }
9927
9928 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9929
9930 void
9931 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9932                                 struct drm_device *dev,
9933                                 struct intel_display_error_state *error)
9934 {
9935         int i;
9936
9937         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9938         if (HAS_POWER_WELL(dev))
9939                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9940                            error->power_well_driver);
9941         for_each_pipe(i) {
9942                 err_printf(m, "Pipe [%d]:\n", i);
9943                 err_printf(m, "  CPU transcoder: %c\n",
9944                            transcoder_name(error->pipe[i].cpu_transcoder));
9945                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9946                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9947                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9948                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9949                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9950                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9951                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9952                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9953
9954                 err_printf(m, "Plane [%d]:\n", i);
9955                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9956                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9957                 if (INTEL_INFO(dev)->gen <= 3) {
9958                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9959                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9960                 }
9961                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9962                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9963                 if (INTEL_INFO(dev)->gen >= 4) {
9964                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9965                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9966                 }
9967
9968                 err_printf(m, "Cursor [%d]:\n", i);
9969                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9970                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9971                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9972         }
9973 }
9974 #endif