drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  71                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  72                         mutex_lock(&rdev->pm.mutex);
  73                         radeon_pm_update_profile(rdev);
  74                         radeon_pm_set_clocks(rdev);
  75                         mutex_unlock(&rdev->pm.mutex);
  76                 }
  77         }
  78 }
  79
  80 static void radeon_pm_update_profile(struct radeon_device *rdev)
  81 {
  82         switch (rdev->pm.profile) {
  83         case PM_PROFILE_DEFAULT:
  84                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  85                 break;
  86         case PM_PROFILE_AUTO:
  87                 if (power_supply_is_system_supplied() > 0) {
  88                         if (rdev->pm.active_crtc_count > 1)
  89                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  90                         else
  91                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  92                 } else {
  93                         if (rdev->pm.active_crtc_count > 1)
  94                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  95                         else
  96                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  97                 }
  98                 break;
  99         case PM_PROFILE_LOW:
 100                 if (rdev->pm.active_crtc_count > 1)
 101                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 102                 else
 103                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 104                 break;
 105         case PM_PROFILE_MID:
 106                 if (rdev->pm.active_crtc_count > 1)
 107                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 108                 else
 109                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 110                 break;
 111         case PM_PROFILE_HIGH:
 112                 if (rdev->pm.active_crtc_count > 1)
 113                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 114                 else
 115                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 116                 break;
 117         }
 118
 119         if (rdev->pm.active_crtc_count == 0) {
 120                 rdev->pm.requested_power_state_index =
 121                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 122                 rdev->pm.requested_clock_mode_index =
 123                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 124         } else {
 125                 rdev->pm.requested_power_state_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 127                 rdev->pm.requested_clock_mode_index =
 128                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 129         }
 130 }
 131
 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 133 {
 134         struct radeon_bo *bo, *n;
 135
 136         if (list_empty(&rdev->gem.objects))
 137                 return;
 138
 139         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 140                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 141                         ttm_bo_unmap_virtual(&bo->tbo);
 142         }
 143 }
 144
 145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 146 {
 147         if (rdev->pm.active_crtcs) {
 148                 rdev->pm.vblank_sync = false;
 149                 wait_event_timeout(
 150                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 151                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 152         }
 153 }
 154
 155 static void radeon_set_power_state(struct radeon_device *rdev)
 156 {
 157         u32 sclk, mclk;
 158         bool misc_after = false;
 159
 160         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 161             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 162                 return;
 163
 164         if (radeon_gui_idle(rdev)) {
 165                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 166                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 167                 if (sclk > rdev->pm.default_sclk)
 168                         sclk = rdev->pm.default_sclk;
 169
 170                 /* starting with BTC, there is one state that is used for both
 171                  * MH and SH.  Difference is that we always use the high clock index for
 172                  * mclk and vddci.
 173                  */
 174                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 175                     (rdev->family >= CHIP_BARTS) &&
 176                     rdev->pm.active_crtc_count &&
 177                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 178                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 179                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 180                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 181                 else
 182                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 183                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 184
 185                 if (mclk > rdev->pm.default_mclk)
 186                         mclk = rdev->pm.default_mclk;
 187
 188                 /* upvolt before raising clocks, downvolt after lowering clocks */
 189                 if (sclk < rdev->pm.current_sclk)
 190                         misc_after = true;
 191
 192                 radeon_sync_with_vblank(rdev);
 193
 194                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 195                         if (!radeon_pm_in_vbl(rdev))
 196                                 return;
 197                 }
 198
 199                 radeon_pm_prepare(rdev);
 200
 201                 if (!misc_after)
 202                         /* voltage, pcie lanes, etc.*/
 203                         radeon_pm_misc(rdev);
 204
 205                 /* set engine clock */
 206                 if (sclk != rdev->pm.current_sclk) {
 207                         radeon_pm_debug_check_in_vbl(rdev, false);
 208                         radeon_set_engine_clock(rdev, sclk);
 209                         radeon_pm_debug_check_in_vbl(rdev, true);
 210                         rdev->pm.current_sclk = sclk;
 211                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 212                 }
 213
 214                 /* set memory clock */
 215                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_memory_clock(rdev, mclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_mclk = mclk;
 220                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 221                 }
 222
 223                 if (misc_after)
 224                         /* voltage, pcie lanes, etc.*/
 225                         radeon_pm_misc(rdev);
 226
 227                 radeon_pm_finish(rdev);
 228
 229                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 230                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 231         } else
 232                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 233 }
 234
 235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 236 {
 237         int i, r;
 238
 239         /* no need to take locks, etc. if nothing's going to change */
 240         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 241             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 242                 return;
 243
 244         mutex_lock(&rdev->ddev->struct_mutex);
 245         down_write(&rdev->pm.mclk_lock);
 246         mutex_lock(&rdev->ring_lock);
 247
 248         /* wait for the rings to drain */
 249         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 250                 struct radeon_ring *ring = &rdev->ring[i];
 251                 if (!ring->ready) {
 252                         continue;
 253                 }
 254                 r = radeon_fence_wait_empty_locked(rdev, i);
 255                 if (r) {
 256                         /* needs a GPU reset dont reset here */
 257                         mutex_unlock(&rdev->ring_lock);
 258                         up_write(&rdev->pm.mclk_lock);
 259                         mutex_unlock(&rdev->ddev->struct_mutex);
 260                         return;
 261                 }
 262         }
 263
 264         radeon_unmap_vram_bos(rdev);
 265
 266         if (rdev->irq.installed) {
 267                 for (i = 0; i < rdev->num_crtc; i++) {
 268                         if (rdev->pm.active_crtcs & (1 << i)) {
 269                                 rdev->pm.req_vblank |= (1 << i);
 270                                 drm_vblank_get(rdev->ddev, i);
 271                         }
 272                 }
 273         }
 274
 275         radeon_set_power_state(rdev);
 276
 277         if (rdev->irq.installed) {
 278                 for (i = 0; i < rdev->num_crtc; i++) {
 279                         if (rdev->pm.req_vblank & (1 << i)) {
 280                                 rdev->pm.req_vblank &= ~(1 << i);
 281                                 drm_vblank_put(rdev->ddev, i);
 282                         }
 283                 }
 284         }
 285
 286         /* update display watermarks based on new power state */
 287         radeon_update_bandwidth_info(rdev);
 288         if (rdev->pm.active_crtc_count)
 289                 radeon_bandwidth_update(rdev);
 290
 291         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 292
 293         mutex_unlock(&rdev->ring_lock);
 294         up_write(&rdev->pm.mclk_lock);
 295         mutex_unlock(&rdev->ddev->struct_mutex);
 296 }
 297
 298 static void radeon_pm_print_states(struct radeon_device *rdev)
 299 {
 300         int i, j;
 301         struct radeon_power_state *power_state;
 302         struct radeon_pm_clock_info *clock_info;
 303
 304         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 305         for (i = 0; i < rdev->pm.num_power_states; i++) {
 306                 power_state = &rdev->pm.power_state[i];
 307                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 308                         radeon_pm_state_type_name[power_state->type]);
 309                 if (i == rdev->pm.default_power_state_index)
 310                         DRM_DEBUG_DRIVER("\tDefault");
 311                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 312                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 313                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 314                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 315                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 316                 for (j = 0; j < power_state->num_clock_modes; j++) {
 317                         clock_info = &(power_state->clock_info[j]);
 318                         if (rdev->flags & RADEON_IS_IGP)
 319                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 320                                                  j,
 321                                                  clock_info->sclk * 10);
 322                         else
 323                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 324                                                  j,
 325                                                  clock_info->sclk * 10,
 326                                                  clock_info->mclk * 10,
 327                                                  clock_info->voltage.voltage);
 328                 }
 329         }
 330 }
 331
 332 static ssize_t radeon_get_pm_profile(struct device *dev,
 333                                      struct device_attribute *attr,
 334                                      char *buf)
 335 {
 336         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 337         struct radeon_device *rdev = ddev->dev_private;
 338         int cp = rdev->pm.profile;
 339
 340         return snprintf(buf, PAGE_SIZE, "%s\n",
 341                         (cp == PM_PROFILE_AUTO) ? "auto" :
 342                         (cp == PM_PROFILE_LOW) ? "low" :
 343                         (cp == PM_PROFILE_MID) ? "mid" :
 344                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 345 }
 346
 347 static ssize_t radeon_set_pm_profile(struct device *dev,
 348                                      struct device_attribute *attr,
 349                                      const char *buf,
 350                                      size_t count)
 351 {
 352         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 353         struct radeon_device *rdev = ddev->dev_private;
 354
 355         mutex_lock(&rdev->pm.mutex);
 356         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 357                 if (strncmp("default", buf, strlen("default")) == 0)
 358                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 359                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 360                         rdev->pm.profile = PM_PROFILE_AUTO;
 361                 else if (strncmp("low", buf, strlen("low")) == 0)
 362                         rdev->pm.profile = PM_PROFILE_LOW;
 363                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 364                         rdev->pm.profile = PM_PROFILE_MID;
 365                 else if (strncmp("high", buf, strlen("high")) == 0)
 366                         rdev->pm.profile = PM_PROFILE_HIGH;
 367                 else {
 368                         count = -EINVAL;
 369                         goto fail;
 370                 }
 371                 radeon_pm_update_profile(rdev);
 372                 radeon_pm_set_clocks(rdev);
 373         } else
 374                 count = -EINVAL;
 375
 376 fail:
 377         mutex_unlock(&rdev->pm.mutex);
 378
 379         return count;
 380 }
 381
 382 static ssize_t radeon_get_pm_method(struct device *dev,
 383                                     struct device_attribute *attr,
 384                                     char *buf)
 385 {
 386         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 387         struct radeon_device *rdev = ddev->dev_private;
 388         int pm = rdev->pm.pm_method;
 389
 390         return snprintf(buf, PAGE_SIZE, "%s\n",
 391                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 392                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 393 }
 394
 395 static ssize_t radeon_set_pm_method(struct device *dev,
 396                                     struct device_attribute *attr,
 397                                     const char *buf,
 398                                     size_t count)
 399 {
 400         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 401         struct radeon_device *rdev = ddev->dev_private;
 402
 403         /* we don't support the legacy modes with dpm */
 404         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 405                 count = -EINVAL;
 406                 goto fail;
 407         }
 408
 409         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 410                 mutex_lock(&rdev->pm.mutex);
 411                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 412                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 413                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 414                 mutex_unlock(&rdev->pm.mutex);
 415         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 416                 mutex_lock(&rdev->pm.mutex);
 417                 /* disable dynpm */
 418                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 419                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 420                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 421                 mutex_unlock(&rdev->pm.mutex);
 422                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 423         } else {
 424                 count = -EINVAL;
 425                 goto fail;
 426         }
 427         radeon_pm_compute_clocks(rdev);
 428 fail:
 429         return count;
 430 }
 431
 432 static ssize_t radeon_get_dpm_state(struct device *dev,
 433                                     struct device_attribute *attr,
 434                                     char *buf)
 435 {
 436         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 437         struct radeon_device *rdev = ddev->dev_private;
 438         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s\n",
 441                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 442                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 443 }
 444
 445 static ssize_t radeon_set_dpm_state(struct device *dev,
 446                                     struct device_attribute *attr,
 447                                     const char *buf,
 448                                     size_t count)
 449 {
 450         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 451         struct radeon_device *rdev = ddev->dev_private;
 452
 453         mutex_lock(&rdev->pm.mutex);
 454         if (strncmp("battery", buf, strlen("battery")) == 0)
 455                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 456         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 457                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 458         else if (strncmp("performance", buf, strlen("performance")) == 0)
 459                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 460         else {
 461                 mutex_unlock(&rdev->pm.mutex);
 462                 count = -EINVAL;
 463                 goto fail;
 464         }
 465         mutex_unlock(&rdev->pm.mutex);
 466         radeon_pm_compute_clocks(rdev);
 467 fail:
 468         return count;
 469 }
 470
 471 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 472                                                        struct device_attribute *attr,
 473                                                        char *buf)
 474 {
 475         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 476         struct radeon_device *rdev = ddev->dev_private;
 477         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 478
 479         return snprintf(buf, PAGE_SIZE, "%s\n",
 480                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 481                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 482 }
 483
 484 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 485                                                        struct device_attribute *attr,
 486                                                        const char *buf,
 487                                                        size_t count)
 488 {
 489         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 490         struct radeon_device *rdev = ddev->dev_private;
 491         enum radeon_dpm_forced_level level;
 492         int ret = 0;
 493
 494         mutex_lock(&rdev->pm.mutex);
 495         if (strncmp("low", buf, strlen("low")) == 0) {
 496                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 497         } else if (strncmp("high", buf, strlen("high")) == 0) {
 498                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 499         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 500                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 501         } else {
 502                 mutex_unlock(&rdev->pm.mutex);
 503                 count = -EINVAL;
 504                 goto fail;
 505         }
 506         if (rdev->asic->dpm.force_performance_level) {
 507                 ret = radeon_dpm_force_performance_level(rdev, level);
 508                 if (ret)
 509                         count = -EINVAL;
 510         }
 511         mutex_unlock(&rdev->pm.mutex);
 512 fail:
 513         return count;
 514 }
 515
 516 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 517 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 518 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 519 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 520                    radeon_get_dpm_forced_performance_level,
 521                    radeon_set_dpm_forced_performance_level);
 522
 523 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 524                                       struct device_attribute *attr,
 525                                       char *buf)
 526 {
 527         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 528         struct radeon_device *rdev = ddev->dev_private;
 529         int temp;
 530
 531         if (rdev->asic->pm.get_temperature)
 532                 temp = radeon_get_temperature(rdev);
 533         else
 534                 temp = 0;
 535
 536         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 537 }
 538
 539 static ssize_t radeon_hwmon_show_name(struct device *dev,
 540                                       struct device_attribute *attr,
 541                                       char *buf)
 542 {
 543         return sprintf(buf, "radeon\n");
 544 }
 545
 546 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 547 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 548
 549 static struct attribute *hwmon_attributes[] = {
 550         &sensor_dev_attr_temp1_input.dev_attr.attr,
 551         &sensor_dev_attr_name.dev_attr.attr,
 552         NULL
 553 };
 554
 555 static const struct attribute_group hwmon_attrgroup = {
 556         .attrs = hwmon_attributes,
 557 };
 558
 559 static int radeon_hwmon_init(struct radeon_device *rdev)
 560 {
 561         int err = 0;
 562
 563         rdev->pm.int_hwmon_dev = NULL;
 564
 565         switch (rdev->pm.int_thermal_type) {
 566         case THERMAL_TYPE_RV6XX:
 567         case THERMAL_TYPE_RV770:
 568         case THERMAL_TYPE_EVERGREEN:
 569         case THERMAL_TYPE_NI:
 570         case THERMAL_TYPE_SUMO:
 571         case THERMAL_TYPE_SI:
 572                 if (rdev->asic->pm.get_temperature == NULL)
 573                         return err;
 574                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 575                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 576                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 577                         dev_err(rdev->dev,
 578                                 "Unable to register hwmon device: %d\n", err);
 579                         break;
 580                 }
 581                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 582                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 583                                          &hwmon_attrgroup);
 584                 if (err) {
 585                         dev_err(rdev->dev,
 586                                 "Unable to create hwmon sysfs file: %d\n", err);
 587                         hwmon_device_unregister(rdev->dev);
 588                 }
 589                 break;
 590         default:
 591                 break;
 592         }
 593
 594         return err;
 595 }
 596
 597 static void radeon_hwmon_fini(struct radeon_device *rdev)
 598 {
 599         if (rdev->pm.int_hwmon_dev) {
 600                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 601                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 602         }
 603 }
 604
 605 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 606 {
 607         struct radeon_device *rdev =
 608                 container_of(work, struct radeon_device,
 609                              pm.dpm.thermal.work);
 610         /* switch to the thermal state */
 611         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 612
 613         if (!rdev->pm.dpm_enabled)
 614                 return;
 615
 616         if (rdev->asic->pm.get_temperature) {
 617                 int temp = radeon_get_temperature(rdev);
 618
 619                 if (temp < rdev->pm.dpm.thermal.min_temp)
 620                         /* switch back the user state */
 621                         dpm_state = rdev->pm.dpm.user_state;
 622         } else {
 623                 if (rdev->pm.dpm.thermal.high_to_low)
 624                         /* switch back the user state */
 625                         dpm_state = rdev->pm.dpm.user_state;
 626         }
 627         radeon_dpm_enable_power_state(rdev, dpm_state);
 628 }
 629
 630 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 631                                                      enum radeon_pm_state_type dpm_state)
 632 {
 633         int i;
 634         struct radeon_ps *ps;
 635         u32 ui_class;
 636         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 637                 true : false;
 638
 639         /* check if the vblank period is too short to adjust the mclk */
 640         if (single_display && rdev->asic->dpm.vblank_too_short) {
 641                 if (radeon_dpm_vblank_too_short(rdev))
 642                         single_display = false;
 643         }
 644
 645         /* certain older asics have a separare 3D performance state,
 646          * so try that first if the user selected performance
 647          */
 648         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 649                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 650         /* balanced states don't exist at the moment */
 651         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 652                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 653
 654 restart_search:
 655         /* Pick the best power state based on current conditions */
 656         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 657                 ps = &rdev->pm.dpm.ps[i];
 658                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 659                 switch (dpm_state) {
 660                 /* user states */
 661                 case POWER_STATE_TYPE_BATTERY:
 662                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 663                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 664                                         if (single_display)
 665                                                 return ps;
 666                                 } else
 667                                         return ps;
 668                         }
 669                         break;
 670                 case POWER_STATE_TYPE_BALANCED:
 671                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 672                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 673                                         if (single_display)
 674                                                 return ps;
 675                                 } else
 676                                         return ps;
 677                         }
 678                         break;
 679                 case POWER_STATE_TYPE_PERFORMANCE:
 680                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 681                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 682                                         if (single_display)
 683                                                 return ps;
 684                                 } else
 685                                         return ps;
 686                         }
 687                         break;
 688                 /* internal states */
 689                 case POWER_STATE_TYPE_INTERNAL_UVD:
 690                         return rdev->pm.dpm.uvd_ps;
 691                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 692                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 693                                 return ps;
 694                         break;
 695                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 696                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 697                                 return ps;
 698                         break;
 699                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 700                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 701                                 return ps;
 702                         break;
 703                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 704                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 705                                 return ps;
 706                         break;
 707                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 708                         return rdev->pm.dpm.boot_ps;
 709                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 710                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 711                                 return ps;
 712                         break;
 713                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 714                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 715                                 return ps;
 716                         break;
 717                 case POWER_STATE_TYPE_INTERNAL_ULV:
 718                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 719                                 return ps;
 720                         break;
 721                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 722                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 723                                 return ps;
 724                         break;
 725                 default:
 726                         break;
 727                 }
 728         }
 729         /* use a fallback state if we didn't match */
 730         switch (dpm_state) {
 731         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 732         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 733         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 734         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 735                 return rdev->pm.dpm.uvd_ps;
 736         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 737                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 738                 goto restart_search;
 739         case POWER_STATE_TYPE_INTERNAL_ACPI:
 740                 dpm_state = POWER_STATE_TYPE_BATTERY;
 741                 goto restart_search;
 742         case POWER_STATE_TYPE_BATTERY:
 743         case POWER_STATE_TYPE_BALANCED:
 744         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 745                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 746                 goto restart_search;
 747         default:
 748                 break;
 749         }
 750
 751         return NULL;
 752 }
 753
 754 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 755 {
 756         int i;
 757         struct radeon_ps *ps;
 758         enum radeon_pm_state_type dpm_state;
 759         int ret;
 760
 761         /* if dpm init failed */
 762         if (!rdev->pm.dpm_enabled)
 763                 return;
 764
 765         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 766                 /* add other state override checks here */
 767                 if ((!rdev->pm.dpm.thermal_active) &&
 768                     (!rdev->pm.dpm.uvd_active))
 769                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 770         }
 771         dpm_state = rdev->pm.dpm.state;
 772
 773         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 774         if (ps)
 775                 rdev->pm.dpm.requested_ps = ps;
 776         else
 777                 return;
 778
 779         /* no need to reprogram if nothing changed unless we are on BTC+ */
 780         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 781                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 782                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 783                          * all we need to do is update the display configuration.
 784                          */
 785                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 786                                 /* update display watermarks based on new power state */
 787                                 radeon_bandwidth_update(rdev);
 788                                 /* update displays */
 789                                 radeon_dpm_display_configuration_changed(rdev);
 790                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 791                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 792                         }
 793                         return;
 794                 } else {
 795                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 796                          * nothing to do, if the num crtcs is > 1 and state is the same,
 797                          * update display configuration.
 798                          */
 799                         if (rdev->pm.dpm.new_active_crtcs ==
 800                             rdev->pm.dpm.current_active_crtcs) {
 801                                 return;
 802                         } else {
 803                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 804                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 805                                         /* update display watermarks based on new power state */
 806                                         radeon_bandwidth_update(rdev);
 807                                         /* update displays */
 808                                         radeon_dpm_display_configuration_changed(rdev);
 809                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 810                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 811                                         return;
 812                                 }
 813                         }
 814                 }
 815         }
 816
 817         printk("switching from power state:\n");
 818         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 819         printk("switching to power state:\n");
 820         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 821
 822         mutex_lock(&rdev->ddev->struct_mutex);
 823         down_write(&rdev->pm.mclk_lock);
 824         mutex_lock(&rdev->ring_lock);
 825
 826         ret = radeon_dpm_pre_set_power_state(rdev);
 827         if (ret)
 828                 goto done;
 829
 830         /* update display watermarks based on new power state */
 831         radeon_bandwidth_update(rdev);
 832         /* update displays */
 833         radeon_dpm_display_configuration_changed(rdev);
 834
 835         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 836         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 837
 838         /* wait for the rings to drain */
 839         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 840                 struct radeon_ring *ring = &rdev->ring[i];
 841                 if (ring->ready)
 842                         radeon_fence_wait_empty_locked(rdev, i);
 843         }
 844
 845         /* program the new power state */
 846         radeon_dpm_set_power_state(rdev);
 847
 848         /* update current power state */
 849         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 850
 851         radeon_dpm_post_set_power_state(rdev);
 852
 853 done:
 854         mutex_unlock(&rdev->ring_lock);
 855         up_write(&rdev->pm.mclk_lock);
 856         mutex_unlock(&rdev->ddev->struct_mutex);
 857 }
 858
 859 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
 860                                    enum radeon_pm_state_type dpm_state)
 861 {
 862         if (!rdev->pm.dpm_enabled)
 863                 return;
 864
 865         mutex_lock(&rdev->pm.mutex);
 866         switch (dpm_state) {
 867         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 868                 rdev->pm.dpm.thermal_active = true;
 869                 break;
 870         case POWER_STATE_TYPE_INTERNAL_UVD:
 871         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 872         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 873         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 874         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 875                 rdev->pm.dpm.uvd_active = true;
 876                 break;
 877         default:
 878                 rdev->pm.dpm.thermal_active = false;
 879                 rdev->pm.dpm.uvd_active = false;
 880                 break;
 881         }
 882         rdev->pm.dpm.state = dpm_state;
 883         mutex_unlock(&rdev->pm.mutex);
 884         radeon_pm_compute_clocks(rdev);
 885 }
 886
 887 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 888 {
 889         mutex_lock(&rdev->pm.mutex);
 890         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 891                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 892                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 893         }
 894         mutex_unlock(&rdev->pm.mutex);
 895
 896         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 897 }
 898
 899 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 900 {
 901         mutex_lock(&rdev->pm.mutex);
 902         /* disable dpm */
 903         radeon_dpm_disable(rdev);
 904         /* reset the power state */
 905         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 906         rdev->pm.dpm_enabled = false;
 907         mutex_unlock(&rdev->pm.mutex);
 908 }
 909
 910 void radeon_pm_suspend(struct radeon_device *rdev)
 911 {
 912         if (rdev->pm.pm_method == PM_METHOD_DPM)
 913                 radeon_pm_suspend_dpm(rdev);
 914         else
 915                 radeon_pm_suspend_old(rdev);
 916 }
 917
 918 static void radeon_pm_resume_old(struct radeon_device *rdev)
 919 {
 920         /* set up the default clocks if the MC ucode is loaded */
 921         if ((rdev->family >= CHIP_BARTS) &&
 922             (rdev->family <= CHIP_HAINAN) &&
 923             rdev->mc_fw) {
 924                 if (rdev->pm.default_vddc)
 925                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 926                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 927                 if (rdev->pm.default_vddci)
 928                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 929                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 930                 if (rdev->pm.default_sclk)
 931                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 932                 if (rdev->pm.default_mclk)
 933                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 934         }
 935         /* asic init will reset the default power state */
 936         mutex_lock(&rdev->pm.mutex);
 937         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 938         rdev->pm.current_clock_mode_index = 0;
 939         rdev->pm.current_sclk = rdev->pm.default_sclk;
 940         rdev->pm.current_mclk = rdev->pm.default_mclk;
 941         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 942         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 943         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 944             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 945                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 946                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 947                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 948         }
 949         mutex_unlock(&rdev->pm.mutex);
 950         radeon_pm_compute_clocks(rdev);
 951 }
 952
 953 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
 954 {
 955         int ret;
 956
 957         /* asic init will reset to the boot state */
 958         mutex_lock(&rdev->pm.mutex);
 959         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 960         radeon_dpm_setup_asic(rdev);
 961         ret = radeon_dpm_enable(rdev);
 962         mutex_unlock(&rdev->pm.mutex);
 963         if (ret) {
 964                 DRM_ERROR("radeon: dpm resume failed\n");
 965                 if ((rdev->family >= CHIP_BARTS) &&
 966                     (rdev->family <= CHIP_HAINAN) &&
 967                     rdev->mc_fw) {
 968                         if (rdev->pm.default_vddc)
 969                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 970                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 971                         if (rdev->pm.default_vddci)
 972                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 973                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 974                         if (rdev->pm.default_sclk)
 975                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 976                         if (rdev->pm.default_mclk)
 977                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 978                 }
 979         } else {
 980                 rdev->pm.dpm_enabled = true;
 981                 radeon_pm_compute_clocks(rdev);
 982         }
 983 }
 984
 985 void radeon_pm_resume(struct radeon_device *rdev)
 986 {
 987         if (rdev->pm.pm_method == PM_METHOD_DPM)
 988                 radeon_pm_resume_dpm(rdev);
 989         else
 990                 radeon_pm_resume_old(rdev);
 991 }
 992
 993 static int radeon_pm_init_old(struct radeon_device *rdev)
 994 {
 995         int ret;
 996
 997         rdev->pm.profile = PM_PROFILE_DEFAULT;
 998         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 999         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1000         rdev->pm.dynpm_can_upclock = true;
1001         rdev->pm.dynpm_can_downclock = true;
1002         rdev->pm.default_sclk = rdev->clock.default_sclk;
1003         rdev->pm.default_mclk = rdev->clock.default_mclk;
1004         rdev->pm.current_sclk = rdev->clock.default_sclk;
1005         rdev->pm.current_mclk = rdev->clock.default_mclk;
1006         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1007
1008         if (rdev->bios) {
1009                 if (rdev->is_atom_bios)
1010                         radeon_atombios_get_power_modes(rdev);
1011                 else
1012                         radeon_combios_get_power_modes(rdev);
1013                 radeon_pm_print_states(rdev);
1014                 radeon_pm_init_profile(rdev);
1015                 /* set up the default clocks if the MC ucode is loaded */
1016                 if ((rdev->family >= CHIP_BARTS) &&
1017                     (rdev->family <= CHIP_HAINAN) &&
1018                     rdev->mc_fw) {
1019                         if (rdev->pm.default_vddc)
1020                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1021                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1022                         if (rdev->pm.default_vddci)
1023                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1024                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1025                         if (rdev->pm.default_sclk)
1026                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1027                         if (rdev->pm.default_mclk)
1028                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1029                 }
1030         }
1031
1032         /* set up the internal thermal sensor if applicable */
1033         ret = radeon_hwmon_init(rdev);
1034         if (ret)
1035                 return ret;
1036
1037         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1038
1039         if (rdev->pm.num_power_states > 1) {
1040                 /* where's the best place to put these? */
1041                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1042                 if (ret)
1043                         DRM_ERROR("failed to create device file for power profile\n");
1044                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1045                 if (ret)
1046                         DRM_ERROR("failed to create device file for power method\n");
1047
1048                 if (radeon_debugfs_pm_init(rdev)) {
1049                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1050                 }
1051
1052                 DRM_INFO("radeon: power management initialized\n");
1053         }
1054
1055         return 0;
1056 }
1057
1058 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1059 {
1060         int i;
1061
1062         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1063                 printk("== power state %d ==\n", i);
1064                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1065         }
1066 }
1067
1068 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1069 {
1070         int ret;
1071
1072         /* default to performance state */
1073         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1074         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1075         rdev->pm.default_sclk = rdev->clock.default_sclk;
1076         rdev->pm.default_mclk = rdev->clock.default_mclk;
1077         rdev->pm.current_sclk = rdev->clock.default_sclk;
1078         rdev->pm.current_mclk = rdev->clock.default_mclk;
1079         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1080
1081         if (rdev->bios && rdev->is_atom_bios)
1082                 radeon_atombios_get_power_modes(rdev);
1083         else
1084                 return -EINVAL;
1085
1086         /* set up the internal thermal sensor if applicable */
1087         ret = radeon_hwmon_init(rdev);
1088         if (ret)
1089                 return ret;
1090
1091         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1092         mutex_lock(&rdev->pm.mutex);
1093         radeon_dpm_init(rdev);
1094         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1095         radeon_dpm_print_power_states(rdev);
1096         radeon_dpm_setup_asic(rdev);
1097         ret = radeon_dpm_enable(rdev);
1098         mutex_unlock(&rdev->pm.mutex);
1099         if (ret) {
1100                 rdev->pm.dpm_enabled = false;
1101                 if ((rdev->family >= CHIP_BARTS) &&
1102                     (rdev->family <= CHIP_HAINAN) &&
1103                     rdev->mc_fw) {
1104                         if (rdev->pm.default_vddc)
1105                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1106                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1107                         if (rdev->pm.default_vddci)
1108                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1109                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1110                         if (rdev->pm.default_sclk)
1111                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1112                         if (rdev->pm.default_mclk)
1113                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1114                 }
1115                 DRM_ERROR("radeon: dpm initialization failed\n");
1116                 return ret;
1117         }
1118         rdev->pm.dpm_enabled = true;
1119         radeon_pm_compute_clocks(rdev);
1120
1121         if (rdev->pm.num_power_states > 1) {
1122                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1123                 if (ret)
1124                         DRM_ERROR("failed to create device file for dpm state\n");
1125                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1126                 if (ret)
1127                         DRM_ERROR("failed to create device file for dpm state\n");
1128                 /* XXX: these are noops for dpm but are here for backwards compat */
1129                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1130                 if (ret)
1131                         DRM_ERROR("failed to create device file for power profile\n");
1132                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1133                 if (ret)
1134                         DRM_ERROR("failed to create device file for power method\n");
1135
1136                 if (radeon_debugfs_pm_init(rdev)) {
1137                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1138                 }
1139
1140                 DRM_INFO("radeon: dpm initialized\n");
1141         }
1142
1143         return 0;
1144 }
1145
1146 int radeon_pm_init(struct radeon_device *rdev)
1147 {
1148         /* enable dpm on rv6xx+ */
1149         switch (rdev->family) {
1150         case CHIP_RV610:
1151         case CHIP_RV630:
1152         case CHIP_RV620:
1153         case CHIP_RV635:
1154         case CHIP_RV670:
1155         case CHIP_RS780:
1156         case CHIP_RS880:
1157         case CHIP_RV770:
1158         case CHIP_RV730:
1159         case CHIP_RV710:
1160         case CHIP_RV740:
1161         case CHIP_CEDAR:
1162         case CHIP_REDWOOD:
1163         case CHIP_JUNIPER:
1164         case CHIP_CYPRESS:
1165         case CHIP_HEMLOCK:
1166         case CHIP_PALM:
1167         case CHIP_SUMO:
1168         case CHIP_SUMO2:
1169         case CHIP_BARTS:
1170         case CHIP_TURKS:
1171         case CHIP_CAICOS:
1172         case CHIP_CAYMAN:
1173         case CHIP_ARUBA:
1174         case CHIP_TAHITI:
1175         case CHIP_PITCAIRN:
1176         case CHIP_VERDE:
1177         case CHIP_OLAND:
1178         case CHIP_HAINAN:
1179                 if (radeon_dpm == 1)
1180                         rdev->pm.pm_method = PM_METHOD_DPM;
1181                 else
1182                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1183                 break;
1184         default:
1185                 /* default to profile method */
1186                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1187                 break;
1188         }
1189
1190         if (rdev->pm.pm_method == PM_METHOD_DPM)
1191                 return radeon_pm_init_dpm(rdev);
1192         else
1193                 return radeon_pm_init_old(rdev);
1194 }
1195
1196 static void radeon_pm_fini_old(struct radeon_device *rdev)
1197 {
1198         if (rdev->pm.num_power_states > 1) {
1199                 mutex_lock(&rdev->pm.mutex);
1200                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1201                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1202                         radeon_pm_update_profile(rdev);
1203                         radeon_pm_set_clocks(rdev);
1204                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1205                         /* reset default clocks */
1206                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1207                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1208                         radeon_pm_set_clocks(rdev);
1209                 }
1210                 mutex_unlock(&rdev->pm.mutex);
1211
1212                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1213
1214                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1215                 device_remove_file(rdev->dev, &dev_attr_power_method);
1216         }
1217
1218         if (rdev->pm.power_state)
1219                 kfree(rdev->pm.power_state);
1220
1221         radeon_hwmon_fini(rdev);
1222 }
1223
1224 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1225 {
1226         if (rdev->pm.num_power_states > 1) {
1227                 mutex_lock(&rdev->pm.mutex);
1228                 radeon_dpm_disable(rdev);
1229                 mutex_unlock(&rdev->pm.mutex);
1230
1231                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1232                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1233                 /* XXX backwards compat */
1234                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1235                 device_remove_file(rdev->dev, &dev_attr_power_method);
1236         }
1237         radeon_dpm_fini(rdev);
1238
1239         if (rdev->pm.power_state)
1240                 kfree(rdev->pm.power_state);
1241
1242         radeon_hwmon_fini(rdev);
1243 }
1244
1245 void radeon_pm_fini(struct radeon_device *rdev)
1246 {
1247         if (rdev->pm.pm_method == PM_METHOD_DPM)
1248                 radeon_pm_fini_dpm(rdev);
1249         else
1250                 radeon_pm_fini_old(rdev);
1251 }
1252
1253 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1254 {
1255         struct drm_device *ddev = rdev->ddev;
1256         struct drm_crtc *crtc;
1257         struct radeon_crtc *radeon_crtc;
1258
1259         if (rdev->pm.num_power_states < 2)
1260                 return;
1261
1262         mutex_lock(&rdev->pm.mutex);
1263
1264         rdev->pm.active_crtcs = 0;
1265         rdev->pm.active_crtc_count = 0;
1266         list_for_each_entry(crtc,
1267                 &ddev->mode_config.crtc_list, head) {
1268                 radeon_crtc = to_radeon_crtc(crtc);
1269                 if (radeon_crtc->enabled) {
1270                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1271                         rdev->pm.active_crtc_count++;
1272                 }
1273         }
1274
1275         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1276                 radeon_pm_update_profile(rdev);
1277                 radeon_pm_set_clocks(rdev);
1278         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1279                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1280                         if (rdev->pm.active_crtc_count > 1) {
1281                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1282                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1283
1284                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1285                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1286                                         radeon_pm_get_dynpm_state(rdev);
1287                                         radeon_pm_set_clocks(rdev);
1288
1289                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1290                                 }
1291                         } else if (rdev->pm.active_crtc_count == 1) {
1292                                 /* TODO: Increase clocks if needed for current mode */
1293
1294                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1295                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1296                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1297                                         radeon_pm_get_dynpm_state(rdev);
1298                                         radeon_pm_set_clocks(rdev);
1299
1300                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1301                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1302                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1303                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1304                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1305                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1306                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1307                                 }
1308                         } else { /* count == 0 */
1309                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1310                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1311
1312                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1313                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1314                                         radeon_pm_get_dynpm_state(rdev);
1315                                         radeon_pm_set_clocks(rdev);
1316                                 }
1317                         }
1318                 }
1319         }
1320
1321         mutex_unlock(&rdev->pm.mutex);
1322 }
1323
1324 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1325 {
1326         struct drm_device *ddev = rdev->ddev;
1327         struct drm_crtc *crtc;
1328         struct radeon_crtc *radeon_crtc;
1329
1330         mutex_lock(&rdev->pm.mutex);
1331
1332         /* update active crtc counts */
1333         rdev->pm.dpm.new_active_crtcs = 0;
1334         rdev->pm.dpm.new_active_crtc_count = 0;
1335         list_for_each_entry(crtc,
1336                 &ddev->mode_config.crtc_list, head) {
1337                 radeon_crtc = to_radeon_crtc(crtc);
1338                 if (crtc->enabled) {
1339                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1340                         rdev->pm.dpm.new_active_crtc_count++;
1341                 }
1342         }
1343
1344         /* update battery/ac status */
1345         if (power_supply_is_system_supplied() > 0)
1346                 rdev->pm.dpm.ac_power = true;
1347         else
1348                 rdev->pm.dpm.ac_power = false;
1349
1350         radeon_dpm_change_power_state_locked(rdev);
1351
1352         mutex_unlock(&rdev->pm.mutex);
1353
1354 }
1355
1356 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1357 {
1358         if (rdev->pm.pm_method == PM_METHOD_DPM)
1359                 radeon_pm_compute_clocks_dpm(rdev);
1360         else
1361                 radeon_pm_compute_clocks_old(rdev);
1362 }
1363
1364 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1365 {
1366         int  crtc, vpos, hpos, vbl_status;
1367         bool in_vbl = true;
1368
1369         /* Iterate over all active crtc's. All crtc's must be in vblank,
1370          * otherwise return in_vbl == false.
1371          */
1372         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1373                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1374                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1375                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1376                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1377                                 in_vbl = false;
1378                 }
1379         }
1380
1381         return in_vbl;
1382 }
1383
1384 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1385 {
1386         u32 stat_crtc = 0;
1387         bool in_vbl = radeon_pm_in_vbl(rdev);
1388
1389         if (in_vbl == false)
1390                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1391                          finish ? "exit" : "entry");
1392         return in_vbl;
1393 }
1394
1395 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1396 {
1397         struct radeon_device *rdev;
1398         int resched;
1399         rdev = container_of(work, struct radeon_device,
1400                                 pm.dynpm_idle_work.work);
1401
1402         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1403         mutex_lock(&rdev->pm.mutex);
1404         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1405                 int not_processed = 0;
1406                 int i;
1407
1408                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1409                         struct radeon_ring *ring = &rdev->ring[i];
1410
1411                         if (ring->ready) {
1412                                 not_processed += radeon_fence_count_emitted(rdev, i);
1413                                 if (not_processed >= 3)
1414                                         break;
1415                         }
1416                 }
1417
1418                 if (not_processed >= 3) { /* should upclock */
1419                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1420                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1421                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1422                                    rdev->pm.dynpm_can_upclock) {
1423                                 rdev->pm.dynpm_planned_action =
1424                                         DYNPM_ACTION_UPCLOCK;
1425                                 rdev->pm.dynpm_action_timeout = jiffies +
1426                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1427                         }
1428                 } else if (not_processed == 0) { /* should downclock */
1429                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1430                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1431                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1432                                    rdev->pm.dynpm_can_downclock) {
1433                                 rdev->pm.dynpm_planned_action =
1434                                         DYNPM_ACTION_DOWNCLOCK;
1435                                 rdev->pm.dynpm_action_timeout = jiffies +
1436                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1437                         }
1438                 }
1439
1440                 /* Note, radeon_pm_set_clocks is called with static_switch set
1441                  * to false since we want to wait for vbl to avoid flicker.
1442                  */
1443                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1444                     jiffies > rdev->pm.dynpm_action_timeout) {
1445                         radeon_pm_get_dynpm_state(rdev);
1446                         radeon_pm_set_clocks(rdev);
1447                 }
1448
1449                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1450                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1451         }
1452         mutex_unlock(&rdev->pm.mutex);
1453         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1454 }
1455
1456 /*
1457  * Debugfs info
1458  */
1459 #if defined(CONFIG_DEBUG_FS)
1460
1461 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1462 {
1463         struct drm_info_node *node = (struct drm_info_node *) m->private;
1464         struct drm_device *dev = node->minor->dev;
1465         struct radeon_device *rdev = dev->dev_private;
1466
1467         if (rdev->pm.dpm_enabled) {
1468                 mutex_lock(&rdev->pm.mutex);
1469                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1470                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1471                 else
1472                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1473                 mutex_unlock(&rdev->pm.mutex);
1474         } else {
1475                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1476                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1477                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1478                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1479                 else
1480                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1481                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1482                 if (rdev->asic->pm.get_memory_clock)
1483                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1484                 if (rdev->pm.current_vddc)
1485                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1486                 if (rdev->asic->pm.get_pcie_lanes)
1487                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1488         }
1489
1490         return 0;
1491 }
1492
1493 static struct drm_info_list radeon_pm_info_list[] = {
1494         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1495 };
1496 #endif
1497
1498 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1499 {
1500 #if defined(CONFIG_DEBUG_FS)
1501         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1502 #else
1503         return 0;
1504 #endif
1505 }