drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family >= CHIP_R600) {
 126                 rdev->pciep_rreg = &r600_pciep_rreg;
 127                 rdev->pciep_wreg = &r600_pciep_wreg;
 128         }
 129 }
 130
 131
 132 /* helper to disable agp */
 133 /**
 134  * radeon_agp_disable - AGP disable helper function
 135  *
 136  * @rdev: radeon device pointer
 137  *
 138  * Removes AGP flags and changes the gart callbacks on AGP
 139  * cards when using the internal gart rather than AGP (all asics).
 140  */
 141 void radeon_agp_disable(struct radeon_device *rdev)
 142 {
 143         rdev->flags &= ~RADEON_IS_AGP;
 144         if (rdev->family >= CHIP_R600) {
 145                 DRM_INFO("Forcing AGP to PCIE mode\n");
 146                 rdev->flags |= RADEON_IS_PCIE;
 147         } else if (rdev->family >= CHIP_RV515 ||
 148                         rdev->family == CHIP_RV380 ||
 149                         rdev->family == CHIP_RV410 ||
 150                         rdev->family == CHIP_R423) {
 151                 DRM_INFO("Forcing AGP to PCIE mode\n");
 152                 rdev->flags |= RADEON_IS_PCIE;
 153                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 154                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 155         } else {
 156                 DRM_INFO("Forcing AGP to PCI mode\n");
 157                 rdev->flags |= RADEON_IS_PCI;
 158                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 159                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 160         }
 161         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 162 }
 163
 164 /*
 165  * ASIC
 166  */
 167 static struct radeon_asic r100_asic = {
 168         .init = &r100_init,
 169         .fini = &r100_fini,
 170         .suspend = &r100_suspend,
 171         .resume = &r100_resume,
 172         .vga_set_state = &r100_vga_set_state,
 173         .asic_reset = &r100_asic_reset,
 174         .ioctl_wait_idle = NULL,
 175         .gui_idle = &r100_gui_idle,
 176         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 177         .gart = {
 178                 .tlb_flush = &r100_pci_gart_tlb_flush,
 179                 .set_page = &r100_pci_gart_set_page,
 180         },
 181         .ring = {
 182                 [RADEON_RING_TYPE_GFX_INDEX] = {
 183                         .ib_execute = &r100_ring_ib_execute,
 184                         .emit_fence = &r100_fence_ring_emit,
 185                         .emit_semaphore = &r100_semaphore_ring_emit,
 186                         .cs_parse = &r100_cs_parse,
 187                         .ring_start = &r100_ring_start,
 188                         .ring_test = &r100_ring_test,
 189                         .ib_test = &r100_ib_test,
 190                         .is_lockup = &r100_gpu_is_lockup,
 191                 }
 192         },
 193         .irq = {
 194                 .set = &r100_irq_set,
 195                 .process = &r100_irq_process,
 196         },
 197         .display = {
 198                 .bandwidth_update = &r100_bandwidth_update,
 199                 .get_vblank_counter = &r100_get_vblank_counter,
 200                 .wait_for_vblank = &r100_wait_for_vblank,
 201                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 202                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 203         },
 204         .copy = {
 205                 .blit = &r100_copy_blit,
 206                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 207                 .dma = NULL,
 208                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 209                 .copy = &r100_copy_blit,
 210                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 211         },
 212         .surface = {
 213                 .set_reg = r100_set_surface_reg,
 214                 .clear_reg = r100_clear_surface_reg,
 215         },
 216         .hpd = {
 217                 .init = &r100_hpd_init,
 218                 .fini = &r100_hpd_fini,
 219                 .sense = &r100_hpd_sense,
 220                 .set_polarity = &r100_hpd_set_polarity,
 221         },
 222         .pm = {
 223                 .misc = &r100_pm_misc,
 224                 .prepare = &r100_pm_prepare,
 225                 .finish = &r100_pm_finish,
 226                 .init_profile = &r100_pm_init_profile,
 227                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 228                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 229                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 230                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 231                 .set_memory_clock = NULL,
 232                 .get_pcie_lanes = NULL,
 233                 .set_pcie_lanes = NULL,
 234                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 235         },
 236         .pflip = {
 237                 .pre_page_flip = &r100_pre_page_flip,
 238                 .page_flip = &r100_page_flip,
 239                 .post_page_flip = &r100_post_page_flip,
 240         },
 241 };
 242
 243 static struct radeon_asic r200_asic = {
 244         .init = &r100_init,
 245         .fini = &r100_fini,
 246         .suspend = &r100_suspend,
 247         .resume = &r100_resume,
 248         .vga_set_state = &r100_vga_set_state,
 249         .asic_reset = &r100_asic_reset,
 250         .ioctl_wait_idle = NULL,
 251         .gui_idle = &r100_gui_idle,
 252         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 253         .gart = {
 254                 .tlb_flush = &r100_pci_gart_tlb_flush,
 255                 .set_page = &r100_pci_gart_set_page,
 256         },
 257         .ring = {
 258                 [RADEON_RING_TYPE_GFX_INDEX] = {
 259                         .ib_execute = &r100_ring_ib_execute,
 260                         .emit_fence = &r100_fence_ring_emit,
 261                         .emit_semaphore = &r100_semaphore_ring_emit,
 262                         .cs_parse = &r100_cs_parse,
 263                         .ring_start = &r100_ring_start,
 264                         .ring_test = &r100_ring_test,
 265                         .ib_test = &r100_ib_test,
 266                         .is_lockup = &r100_gpu_is_lockup,
 267                 }
 268         },
 269         .irq = {
 270                 .set = &r100_irq_set,
 271                 .process = &r100_irq_process,
 272         },
 273         .display = {
 274                 .bandwidth_update = &r100_bandwidth_update,
 275                 .get_vblank_counter = &r100_get_vblank_counter,
 276                 .wait_for_vblank = &r100_wait_for_vblank,
 277                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 278                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 279         },
 280         .copy = {
 281                 .blit = &r100_copy_blit,
 282                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 283                 .dma = &r200_copy_dma,
 284                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 285                 .copy = &r100_copy_blit,
 286                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 287         },
 288         .surface = {
 289                 .set_reg = r100_set_surface_reg,
 290                 .clear_reg = r100_clear_surface_reg,
 291         },
 292         .hpd = {
 293                 .init = &r100_hpd_init,
 294                 .fini = &r100_hpd_fini,
 295                 .sense = &r100_hpd_sense,
 296                 .set_polarity = &r100_hpd_set_polarity,
 297         },
 298         .pm = {
 299                 .misc = &r100_pm_misc,
 300                 .prepare = &r100_pm_prepare,
 301                 .finish = &r100_pm_finish,
 302                 .init_profile = &r100_pm_init_profile,
 303                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 304                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 305                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 306                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 307                 .set_memory_clock = NULL,
 308                 .get_pcie_lanes = NULL,
 309                 .set_pcie_lanes = NULL,
 310                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 311         },
 312         .pflip = {
 313                 .pre_page_flip = &r100_pre_page_flip,
 314                 .page_flip = &r100_page_flip,
 315                 .post_page_flip = &r100_post_page_flip,
 316         },
 317 };
 318
 319 static struct radeon_asic r300_asic = {
 320         .init = &r300_init,
 321         .fini = &r300_fini,
 322         .suspend = &r300_suspend,
 323         .resume = &r300_resume,
 324         .vga_set_state = &r100_vga_set_state,
 325         .asic_reset = &r300_asic_reset,
 326         .ioctl_wait_idle = NULL,
 327         .gui_idle = &r100_gui_idle,
 328         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 329         .gart = {
 330                 .tlb_flush = &r100_pci_gart_tlb_flush,
 331                 .set_page = &r100_pci_gart_set_page,
 332         },
 333         .ring = {
 334                 [RADEON_RING_TYPE_GFX_INDEX] = {
 335                         .ib_execute = &r100_ring_ib_execute,
 336                         .emit_fence = &r300_fence_ring_emit,
 337                         .emit_semaphore = &r100_semaphore_ring_emit,
 338                         .cs_parse = &r300_cs_parse,
 339                         .ring_start = &r300_ring_start,
 340                         .ring_test = &r100_ring_test,
 341                         .ib_test = &r100_ib_test,
 342                         .is_lockup = &r100_gpu_is_lockup,
 343                 }
 344         },
 345         .irq = {
 346                 .set = &r100_irq_set,
 347                 .process = &r100_irq_process,
 348         },
 349         .display = {
 350                 .bandwidth_update = &r100_bandwidth_update,
 351                 .get_vblank_counter = &r100_get_vblank_counter,
 352                 .wait_for_vblank = &r100_wait_for_vblank,
 353                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 354                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 355         },
 356         .copy = {
 357                 .blit = &r100_copy_blit,
 358                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 359                 .dma = &r200_copy_dma,
 360                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 361                 .copy = &r100_copy_blit,
 362                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 363         },
 364         .surface = {
 365                 .set_reg = r100_set_surface_reg,
 366                 .clear_reg = r100_clear_surface_reg,
 367         },
 368         .hpd = {
 369                 .init = &r100_hpd_init,
 370                 .fini = &r100_hpd_fini,
 371                 .sense = &r100_hpd_sense,
 372                 .set_polarity = &r100_hpd_set_polarity,
 373         },
 374         .pm = {
 375                 .misc = &r100_pm_misc,
 376                 .prepare = &r100_pm_prepare,
 377                 .finish = &r100_pm_finish,
 378                 .init_profile = &r100_pm_init_profile,
 379                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 380                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 381                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 382                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 383                 .set_memory_clock = NULL,
 384                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 385                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 386                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 387         },
 388         .pflip = {
 389                 .pre_page_flip = &r100_pre_page_flip,
 390                 .page_flip = &r100_page_flip,
 391                 .post_page_flip = &r100_post_page_flip,
 392         },
 393 };
 394
 395 static struct radeon_asic r300_asic_pcie = {
 396         .init = &r300_init,
 397         .fini = &r300_fini,
 398         .suspend = &r300_suspend,
 399         .resume = &r300_resume,
 400         .vga_set_state = &r100_vga_set_state,
 401         .asic_reset = &r300_asic_reset,
 402         .ioctl_wait_idle = NULL,
 403         .gui_idle = &r100_gui_idle,
 404         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 405         .gart = {
 406                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 407                 .set_page = &rv370_pcie_gart_set_page,
 408         },
 409         .ring = {
 410                 [RADEON_RING_TYPE_GFX_INDEX] = {
 411                         .ib_execute = &r100_ring_ib_execute,
 412                         .emit_fence = &r300_fence_ring_emit,
 413                         .emit_semaphore = &r100_semaphore_ring_emit,
 414                         .cs_parse = &r300_cs_parse,
 415                         .ring_start = &r300_ring_start,
 416                         .ring_test = &r100_ring_test,
 417                         .ib_test = &r100_ib_test,
 418                         .is_lockup = &r100_gpu_is_lockup,
 419                 }
 420         },
 421         .irq = {
 422                 .set = &r100_irq_set,
 423                 .process = &r100_irq_process,
 424         },
 425         .display = {
 426                 .bandwidth_update = &r100_bandwidth_update,
 427                 .get_vblank_counter = &r100_get_vblank_counter,
 428                 .wait_for_vblank = &r100_wait_for_vblank,
 429                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 430                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 431         },
 432         .copy = {
 433                 .blit = &r100_copy_blit,
 434                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 435                 .dma = &r200_copy_dma,
 436                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 437                 .copy = &r100_copy_blit,
 438                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 439         },
 440         .surface = {
 441                 .set_reg = r100_set_surface_reg,
 442                 .clear_reg = r100_clear_surface_reg,
 443         },
 444         .hpd = {
 445                 .init = &r100_hpd_init,
 446                 .fini = &r100_hpd_fini,
 447                 .sense = &r100_hpd_sense,
 448                 .set_polarity = &r100_hpd_set_polarity,
 449         },
 450         .pm = {
 451                 .misc = &r100_pm_misc,
 452                 .prepare = &r100_pm_prepare,
 453                 .finish = &r100_pm_finish,
 454                 .init_profile = &r100_pm_init_profile,
 455                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 456                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 457                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 458                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 459                 .set_memory_clock = NULL,
 460                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 461                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 462                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 463         },
 464         .pflip = {
 465                 .pre_page_flip = &r100_pre_page_flip,
 466                 .page_flip = &r100_page_flip,
 467                 .post_page_flip = &r100_post_page_flip,
 468         },
 469 };
 470
 471 static struct radeon_asic r420_asic = {
 472         .init = &r420_init,
 473         .fini = &r420_fini,
 474         .suspend = &r420_suspend,
 475         .resume = &r420_resume,
 476         .vga_set_state = &r100_vga_set_state,
 477         .asic_reset = &r300_asic_reset,
 478         .ioctl_wait_idle = NULL,
 479         .gui_idle = &r100_gui_idle,
 480         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 481         .gart = {
 482                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 483                 .set_page = &rv370_pcie_gart_set_page,
 484         },
 485         .ring = {
 486                 [RADEON_RING_TYPE_GFX_INDEX] = {
 487                         .ib_execute = &r100_ring_ib_execute,
 488                         .emit_fence = &r300_fence_ring_emit,
 489                         .emit_semaphore = &r100_semaphore_ring_emit,
 490                         .cs_parse = &r300_cs_parse,
 491                         .ring_start = &r300_ring_start,
 492                         .ring_test = &r100_ring_test,
 493                         .ib_test = &r100_ib_test,
 494                         .is_lockup = &r100_gpu_is_lockup,
 495                 }
 496         },
 497         .irq = {
 498                 .set = &r100_irq_set,
 499                 .process = &r100_irq_process,
 500         },
 501         .display = {
 502                 .bandwidth_update = &r100_bandwidth_update,
 503                 .get_vblank_counter = &r100_get_vblank_counter,
 504                 .wait_for_vblank = &r100_wait_for_vblank,
 505                 .set_backlight_level = &atombios_set_backlight_level,
 506                 .get_backlight_level = &atombios_get_backlight_level,
 507         },
 508         .copy = {
 509                 .blit = &r100_copy_blit,
 510                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 511                 .dma = &r200_copy_dma,
 512                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 513                 .copy = &r100_copy_blit,
 514                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 515         },
 516         .surface = {
 517                 .set_reg = r100_set_surface_reg,
 518                 .clear_reg = r100_clear_surface_reg,
 519         },
 520         .hpd = {
 521                 .init = &r100_hpd_init,
 522                 .fini = &r100_hpd_fini,
 523                 .sense = &r100_hpd_sense,
 524                 .set_polarity = &r100_hpd_set_polarity,
 525         },
 526         .pm = {
 527                 .misc = &r100_pm_misc,
 528                 .prepare = &r100_pm_prepare,
 529                 .finish = &r100_pm_finish,
 530                 .init_profile = &r420_pm_init_profile,
 531                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 532                 .get_engine_clock = &radeon_atom_get_engine_clock,
 533                 .set_engine_clock = &radeon_atom_set_engine_clock,
 534                 .get_memory_clock = &radeon_atom_get_memory_clock,
 535                 .set_memory_clock = &radeon_atom_set_memory_clock,
 536                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 537                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 538                 .set_clock_gating = &radeon_atom_set_clock_gating,
 539         },
 540         .pflip = {
 541                 .pre_page_flip = &r100_pre_page_flip,
 542                 .page_flip = &r100_page_flip,
 543                 .post_page_flip = &r100_post_page_flip,
 544         },
 545 };
 546
 547 static struct radeon_asic rs400_asic = {
 548         .init = &rs400_init,
 549         .fini = &rs400_fini,
 550         .suspend = &rs400_suspend,
 551         .resume = &rs400_resume,
 552         .vga_set_state = &r100_vga_set_state,
 553         .asic_reset = &r300_asic_reset,
 554         .ioctl_wait_idle = NULL,
 555         .gui_idle = &r100_gui_idle,
 556         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 557         .gart = {
 558                 .tlb_flush = &rs400_gart_tlb_flush,
 559                 .set_page = &rs400_gart_set_page,
 560         },
 561         .ring = {
 562                 [RADEON_RING_TYPE_GFX_INDEX] = {
 563                         .ib_execute = &r100_ring_ib_execute,
 564                         .emit_fence = &r300_fence_ring_emit,
 565                         .emit_semaphore = &r100_semaphore_ring_emit,
 566                         .cs_parse = &r300_cs_parse,
 567                         .ring_start = &r300_ring_start,
 568                         .ring_test = &r100_ring_test,
 569                         .ib_test = &r100_ib_test,
 570                         .is_lockup = &r100_gpu_is_lockup,
 571                 }
 572         },
 573         .irq = {
 574                 .set = &r100_irq_set,
 575                 .process = &r100_irq_process,
 576         },
 577         .display = {
 578                 .bandwidth_update = &r100_bandwidth_update,
 579                 .get_vblank_counter = &r100_get_vblank_counter,
 580                 .wait_for_vblank = &r100_wait_for_vblank,
 581                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 582                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 583         },
 584         .copy = {
 585                 .blit = &r100_copy_blit,
 586                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 587                 .dma = &r200_copy_dma,
 588                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 589                 .copy = &r100_copy_blit,
 590                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 591         },
 592         .surface = {
 593                 .set_reg = r100_set_surface_reg,
 594                 .clear_reg = r100_clear_surface_reg,
 595         },
 596         .hpd = {
 597                 .init = &r100_hpd_init,
 598                 .fini = &r100_hpd_fini,
 599                 .sense = &r100_hpd_sense,
 600                 .set_polarity = &r100_hpd_set_polarity,
 601         },
 602         .pm = {
 603                 .misc = &r100_pm_misc,
 604                 .prepare = &r100_pm_prepare,
 605                 .finish = &r100_pm_finish,
 606                 .init_profile = &r100_pm_init_profile,
 607                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 608                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 609                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 610                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 611                 .set_memory_clock = NULL,
 612                 .get_pcie_lanes = NULL,
 613                 .set_pcie_lanes = NULL,
 614                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 615         },
 616         .pflip = {
 617                 .pre_page_flip = &r100_pre_page_flip,
 618                 .page_flip = &r100_page_flip,
 619                 .post_page_flip = &r100_post_page_flip,
 620         },
 621 };
 622
 623 static struct radeon_asic rs600_asic = {
 624         .init = &rs600_init,
 625         .fini = &rs600_fini,
 626         .suspend = &rs600_suspend,
 627         .resume = &rs600_resume,
 628         .vga_set_state = &r100_vga_set_state,
 629         .asic_reset = &rs600_asic_reset,
 630         .ioctl_wait_idle = NULL,
 631         .gui_idle = &r100_gui_idle,
 632         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 633         .gart = {
 634                 .tlb_flush = &rs600_gart_tlb_flush,
 635                 .set_page = &rs600_gart_set_page,
 636         },
 637         .ring = {
 638                 [RADEON_RING_TYPE_GFX_INDEX] = {
 639                         .ib_execute = &r100_ring_ib_execute,
 640                         .emit_fence = &r300_fence_ring_emit,
 641                         .emit_semaphore = &r100_semaphore_ring_emit,
 642                         .cs_parse = &r300_cs_parse,
 643                         .ring_start = &r300_ring_start,
 644                         .ring_test = &r100_ring_test,
 645                         .ib_test = &r100_ib_test,
 646                         .is_lockup = &r100_gpu_is_lockup,
 647                 }
 648         },
 649         .irq = {
 650                 .set = &rs600_irq_set,
 651                 .process = &rs600_irq_process,
 652         },
 653         .display = {
 654                 .bandwidth_update = &rs600_bandwidth_update,
 655                 .get_vblank_counter = &rs600_get_vblank_counter,
 656                 .wait_for_vblank = &avivo_wait_for_vblank,
 657                 .set_backlight_level = &atombios_set_backlight_level,
 658                 .get_backlight_level = &atombios_get_backlight_level,
 659         },
 660         .copy = {
 661                 .blit = &r100_copy_blit,
 662                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 663                 .dma = &r200_copy_dma,
 664                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 665                 .copy = &r100_copy_blit,
 666                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 667         },
 668         .surface = {
 669                 .set_reg = r100_set_surface_reg,
 670                 .clear_reg = r100_clear_surface_reg,
 671         },
 672         .hpd = {
 673                 .init = &rs600_hpd_init,
 674                 .fini = &rs600_hpd_fini,
 675                 .sense = &rs600_hpd_sense,
 676                 .set_polarity = &rs600_hpd_set_polarity,
 677         },
 678         .pm = {
 679                 .misc = &rs600_pm_misc,
 680                 .prepare = &rs600_pm_prepare,
 681                 .finish = &rs600_pm_finish,
 682                 .init_profile = &r420_pm_init_profile,
 683                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 684                 .get_engine_clock = &radeon_atom_get_engine_clock,
 685                 .set_engine_clock = &radeon_atom_set_engine_clock,
 686                 .get_memory_clock = &radeon_atom_get_memory_clock,
 687                 .set_memory_clock = &radeon_atom_set_memory_clock,
 688                 .get_pcie_lanes = NULL,
 689                 .set_pcie_lanes = NULL,
 690                 .set_clock_gating = &radeon_atom_set_clock_gating,
 691         },
 692         .pflip = {
 693                 .pre_page_flip = &rs600_pre_page_flip,
 694                 .page_flip = &rs600_page_flip,
 695                 .post_page_flip = &rs600_post_page_flip,
 696         },
 697 };
 698
 699 static struct radeon_asic rs690_asic = {
 700         .init = &rs690_init,
 701         .fini = &rs690_fini,
 702         .suspend = &rs690_suspend,
 703         .resume = &rs690_resume,
 704         .vga_set_state = &r100_vga_set_state,
 705         .asic_reset = &rs600_asic_reset,
 706         .ioctl_wait_idle = NULL,
 707         .gui_idle = &r100_gui_idle,
 708         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 709         .gart = {
 710                 .tlb_flush = &rs400_gart_tlb_flush,
 711                 .set_page = &rs400_gart_set_page,
 712         },
 713         .ring = {
 714                 [RADEON_RING_TYPE_GFX_INDEX] = {
 715                         .ib_execute = &r100_ring_ib_execute,
 716                         .emit_fence = &r300_fence_ring_emit,
 717                         .emit_semaphore = &r100_semaphore_ring_emit,
 718                         .cs_parse = &r300_cs_parse,
 719                         .ring_start = &r300_ring_start,
 720                         .ring_test = &r100_ring_test,
 721                         .ib_test = &r100_ib_test,
 722                         .is_lockup = &r100_gpu_is_lockup,
 723                 }
 724         },
 725         .irq = {
 726                 .set = &rs600_irq_set,
 727                 .process = &rs600_irq_process,
 728         },
 729         .display = {
 730                 .get_vblank_counter = &rs600_get_vblank_counter,
 731                 .bandwidth_update = &rs690_bandwidth_update,
 732                 .wait_for_vblank = &avivo_wait_for_vblank,
 733                 .set_backlight_level = &atombios_set_backlight_level,
 734                 .get_backlight_level = &atombios_get_backlight_level,
 735         },
 736         .copy = {
 737                 .blit = &r100_copy_blit,
 738                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 739                 .dma = &r200_copy_dma,
 740                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 741                 .copy = &r200_copy_dma,
 742                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 743         },
 744         .surface = {
 745                 .set_reg = r100_set_surface_reg,
 746                 .clear_reg = r100_clear_surface_reg,
 747         },
 748         .hpd = {
 749                 .init = &rs600_hpd_init,
 750                 .fini = &rs600_hpd_fini,
 751                 .sense = &rs600_hpd_sense,
 752                 .set_polarity = &rs600_hpd_set_polarity,
 753         },
 754         .pm = {
 755                 .misc = &rs600_pm_misc,
 756                 .prepare = &rs600_pm_prepare,
 757                 .finish = &rs600_pm_finish,
 758                 .init_profile = &r420_pm_init_profile,
 759                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 760                 .get_engine_clock = &radeon_atom_get_engine_clock,
 761                 .set_engine_clock = &radeon_atom_set_engine_clock,
 762                 .get_memory_clock = &radeon_atom_get_memory_clock,
 763                 .set_memory_clock = &radeon_atom_set_memory_clock,
 764                 .get_pcie_lanes = NULL,
 765                 .set_pcie_lanes = NULL,
 766                 .set_clock_gating = &radeon_atom_set_clock_gating,
 767         },
 768         .pflip = {
 769                 .pre_page_flip = &rs600_pre_page_flip,
 770                 .page_flip = &rs600_page_flip,
 771                 .post_page_flip = &rs600_post_page_flip,
 772         },
 773 };
 774
 775 static struct radeon_asic rv515_asic = {
 776         .init = &rv515_init,
 777         .fini = &rv515_fini,
 778         .suspend = &rv515_suspend,
 779         .resume = &rv515_resume,
 780         .vga_set_state = &r100_vga_set_state,
 781         .asic_reset = &rs600_asic_reset,
 782         .ioctl_wait_idle = NULL,
 783         .gui_idle = &r100_gui_idle,
 784         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 785         .gart = {
 786                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 787                 .set_page = &rv370_pcie_gart_set_page,
 788         },
 789         .ring = {
 790                 [RADEON_RING_TYPE_GFX_INDEX] = {
 791                         .ib_execute = &r100_ring_ib_execute,
 792                         .emit_fence = &r300_fence_ring_emit,
 793                         .emit_semaphore = &r100_semaphore_ring_emit,
 794                         .cs_parse = &r300_cs_parse,
 795                         .ring_start = &rv515_ring_start,
 796                         .ring_test = &r100_ring_test,
 797                         .ib_test = &r100_ib_test,
 798                         .is_lockup = &r100_gpu_is_lockup,
 799                 }
 800         },
 801         .irq = {
 802                 .set = &rs600_irq_set,
 803                 .process = &rs600_irq_process,
 804         },
 805         .display = {
 806                 .get_vblank_counter = &rs600_get_vblank_counter,
 807                 .bandwidth_update = &rv515_bandwidth_update,
 808                 .wait_for_vblank = &avivo_wait_for_vblank,
 809                 .set_backlight_level = &atombios_set_backlight_level,
 810                 .get_backlight_level = &atombios_get_backlight_level,
 811         },
 812         .copy = {
 813                 .blit = &r100_copy_blit,
 814                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 815                 .dma = &r200_copy_dma,
 816                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 817                 .copy = &r100_copy_blit,
 818                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 819         },
 820         .surface = {
 821                 .set_reg = r100_set_surface_reg,
 822                 .clear_reg = r100_clear_surface_reg,
 823         },
 824         .hpd = {
 825                 .init = &rs600_hpd_init,
 826                 .fini = &rs600_hpd_fini,
 827                 .sense = &rs600_hpd_sense,
 828                 .set_polarity = &rs600_hpd_set_polarity,
 829         },
 830         .pm = {
 831                 .misc = &rs600_pm_misc,
 832                 .prepare = &rs600_pm_prepare,
 833                 .finish = &rs600_pm_finish,
 834                 .init_profile = &r420_pm_init_profile,
 835                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 836                 .get_engine_clock = &radeon_atom_get_engine_clock,
 837                 .set_engine_clock = &radeon_atom_set_engine_clock,
 838                 .get_memory_clock = &radeon_atom_get_memory_clock,
 839                 .set_memory_clock = &radeon_atom_set_memory_clock,
 840                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 841                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 842                 .set_clock_gating = &radeon_atom_set_clock_gating,
 843         },
 844         .pflip = {
 845                 .pre_page_flip = &rs600_pre_page_flip,
 846                 .page_flip = &rs600_page_flip,
 847                 .post_page_flip = &rs600_post_page_flip,
 848         },
 849 };
 850
 851 static struct radeon_asic r520_asic = {
 852         .init = &r520_init,
 853         .fini = &rv515_fini,
 854         .suspend = &rv515_suspend,
 855         .resume = &r520_resume,
 856         .vga_set_state = &r100_vga_set_state,
 857         .asic_reset = &rs600_asic_reset,
 858         .ioctl_wait_idle = NULL,
 859         .gui_idle = &r100_gui_idle,
 860         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 861         .gart = {
 862                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 863                 .set_page = &rv370_pcie_gart_set_page,
 864         },
 865         .ring = {
 866                 [RADEON_RING_TYPE_GFX_INDEX] = {
 867                         .ib_execute = &r100_ring_ib_execute,
 868                         .emit_fence = &r300_fence_ring_emit,
 869                         .emit_semaphore = &r100_semaphore_ring_emit,
 870                         .cs_parse = &r300_cs_parse,
 871                         .ring_start = &rv515_ring_start,
 872                         .ring_test = &r100_ring_test,
 873                         .ib_test = &r100_ib_test,
 874                         .is_lockup = &r100_gpu_is_lockup,
 875                 }
 876         },
 877         .irq = {
 878                 .set = &rs600_irq_set,
 879                 .process = &rs600_irq_process,
 880         },
 881         .display = {
 882                 .bandwidth_update = &rv515_bandwidth_update,
 883                 .get_vblank_counter = &rs600_get_vblank_counter,
 884                 .wait_for_vblank = &avivo_wait_for_vblank,
 885                 .set_backlight_level = &atombios_set_backlight_level,
 886                 .get_backlight_level = &atombios_get_backlight_level,
 887         },
 888         .copy = {
 889                 .blit = &r100_copy_blit,
 890                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 891                 .dma = &r200_copy_dma,
 892                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 893                 .copy = &r100_copy_blit,
 894                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 895         },
 896         .surface = {
 897                 .set_reg = r100_set_surface_reg,
 898                 .clear_reg = r100_clear_surface_reg,
 899         },
 900         .hpd = {
 901                 .init = &rs600_hpd_init,
 902                 .fini = &rs600_hpd_fini,
 903                 .sense = &rs600_hpd_sense,
 904                 .set_polarity = &rs600_hpd_set_polarity,
 905         },
 906         .pm = {
 907                 .misc = &rs600_pm_misc,
 908                 .prepare = &rs600_pm_prepare,
 909                 .finish = &rs600_pm_finish,
 910                 .init_profile = &r420_pm_init_profile,
 911                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 912                 .get_engine_clock = &radeon_atom_get_engine_clock,
 913                 .set_engine_clock = &radeon_atom_set_engine_clock,
 914                 .get_memory_clock = &radeon_atom_get_memory_clock,
 915                 .set_memory_clock = &radeon_atom_set_memory_clock,
 916                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 917                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 918                 .set_clock_gating = &radeon_atom_set_clock_gating,
 919         },
 920         .pflip = {
 921                 .pre_page_flip = &rs600_pre_page_flip,
 922                 .page_flip = &rs600_page_flip,
 923                 .post_page_flip = &rs600_post_page_flip,
 924         },
 925 };
 926
 927 static struct radeon_asic r600_asic = {
 928         .init = &r600_init,
 929         .fini = &r600_fini,
 930         .suspend = &r600_suspend,
 931         .resume = &r600_resume,
 932         .vga_set_state = &r600_vga_set_state,
 933         .asic_reset = &r600_asic_reset,
 934         .ioctl_wait_idle = r600_ioctl_wait_idle,
 935         .gui_idle = &r600_gui_idle,
 936         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 937         .get_xclk = &r600_get_xclk,
 938         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 939         .gart = {
 940                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 941                 .set_page = &rs600_gart_set_page,
 942         },
 943         .ring = {
 944                 [RADEON_RING_TYPE_GFX_INDEX] = {
 945                         .ib_execute = &r600_ring_ib_execute,
 946                         .emit_fence = &r600_fence_ring_emit,
 947                         .emit_semaphore = &r600_semaphore_ring_emit,
 948                         .cs_parse = &r600_cs_parse,
 949                         .ring_test = &r600_ring_test,
 950                         .ib_test = &r600_ib_test,
 951                         .is_lockup = &r600_gfx_is_lockup,
 952                 },
 953                 [R600_RING_TYPE_DMA_INDEX] = {
 954                         .ib_execute = &r600_dma_ring_ib_execute,
 955                         .emit_fence = &r600_dma_fence_ring_emit,
 956                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 957                         .cs_parse = &r600_dma_cs_parse,
 958                         .ring_test = &r600_dma_ring_test,
 959                         .ib_test = &r600_dma_ib_test,
 960                         .is_lockup = &r600_dma_is_lockup,
 961                 }
 962         },
 963         .irq = {
 964                 .set = &r600_irq_set,
 965                 .process = &r600_irq_process,
 966         },
 967         .display = {
 968                 .bandwidth_update = &rv515_bandwidth_update,
 969                 .get_vblank_counter = &rs600_get_vblank_counter,
 970                 .wait_for_vblank = &avivo_wait_for_vblank,
 971                 .set_backlight_level = &atombios_set_backlight_level,
 972                 .get_backlight_level = &atombios_get_backlight_level,
 973         },
 974         .copy = {
 975                 .blit = &r600_copy_blit,
 976                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 977                 .dma = &r600_copy_dma,
 978                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 979                 .copy = &r600_copy_dma,
 980                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
 981         },
 982         .surface = {
 983                 .set_reg = r600_set_surface_reg,
 984                 .clear_reg = r600_clear_surface_reg,
 985         },
 986         .hpd = {
 987                 .init = &r600_hpd_init,
 988                 .fini = &r600_hpd_fini,
 989                 .sense = &r600_hpd_sense,
 990                 .set_polarity = &r600_hpd_set_polarity,
 991         },
 992         .pm = {
 993                 .misc = &r600_pm_misc,
 994                 .prepare = &rs600_pm_prepare,
 995                 .finish = &rs600_pm_finish,
 996                 .init_profile = &r600_pm_init_profile,
 997                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 998                 .get_engine_clock = &radeon_atom_get_engine_clock,
 999                 .set_engine_clock = &radeon_atom_set_engine_clock,
1000                 .get_memory_clock = &radeon_atom_get_memory_clock,
1001                 .set_memory_clock = &radeon_atom_set_memory_clock,
1002                 .get_pcie_lanes = &r600_get_pcie_lanes,
1003                 .set_pcie_lanes = &r600_set_pcie_lanes,
1004                 .set_clock_gating = NULL,
1005         },
1006         .pflip = {
1007                 .pre_page_flip = &rs600_pre_page_flip,
1008                 .page_flip = &rs600_page_flip,
1009                 .post_page_flip = &rs600_post_page_flip,
1010         },
1011 };
1012
1013 static struct radeon_asic rs780_asic = {
1014         .init = &r600_init,
1015         .fini = &r600_fini,
1016         .suspend = &r600_suspend,
1017         .resume = &r600_resume,
1018         .vga_set_state = &r600_vga_set_state,
1019         .asic_reset = &r600_asic_reset,
1020         .ioctl_wait_idle = r600_ioctl_wait_idle,
1021         .gui_idle = &r600_gui_idle,
1022         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1023         .get_xclk = &r600_get_xclk,
1024         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1025         .gart = {
1026                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1027                 .set_page = &rs600_gart_set_page,
1028         },
1029         .ring = {
1030                 [RADEON_RING_TYPE_GFX_INDEX] = {
1031                         .ib_execute = &r600_ring_ib_execute,
1032                         .emit_fence = &r600_fence_ring_emit,
1033                         .emit_semaphore = &r600_semaphore_ring_emit,
1034                         .cs_parse = &r600_cs_parse,
1035                         .ring_test = &r600_ring_test,
1036                         .ib_test = &r600_ib_test,
1037                         .is_lockup = &r600_gfx_is_lockup,
1038                 },
1039                 [R600_RING_TYPE_DMA_INDEX] = {
1040                         .ib_execute = &r600_dma_ring_ib_execute,
1041                         .emit_fence = &r600_dma_fence_ring_emit,
1042                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1043                         .cs_parse = &r600_dma_cs_parse,
1044                         .ring_test = &r600_dma_ring_test,
1045                         .ib_test = &r600_dma_ib_test,
1046                         .is_lockup = &r600_dma_is_lockup,
1047                 }
1048         },
1049         .irq = {
1050                 .set = &r600_irq_set,
1051                 .process = &r600_irq_process,
1052         },
1053         .display = {
1054                 .bandwidth_update = &rs690_bandwidth_update,
1055                 .get_vblank_counter = &rs600_get_vblank_counter,
1056                 .wait_for_vblank = &avivo_wait_for_vblank,
1057                 .set_backlight_level = &atombios_set_backlight_level,
1058                 .get_backlight_level = &atombios_get_backlight_level,
1059         },
1060         .copy = {
1061                 .blit = &r600_copy_blit,
1062                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1063                 .dma = &r600_copy_dma,
1064                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1065                 .copy = &r600_copy_dma,
1066                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1067         },
1068         .surface = {
1069                 .set_reg = r600_set_surface_reg,
1070                 .clear_reg = r600_clear_surface_reg,
1071         },
1072         .hpd = {
1073                 .init = &r600_hpd_init,
1074                 .fini = &r600_hpd_fini,
1075                 .sense = &r600_hpd_sense,
1076                 .set_polarity = &r600_hpd_set_polarity,
1077         },
1078         .pm = {
1079                 .misc = &r600_pm_misc,
1080                 .prepare = &rs600_pm_prepare,
1081                 .finish = &rs600_pm_finish,
1082                 .init_profile = &rs780_pm_init_profile,
1083                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1084                 .get_engine_clock = &radeon_atom_get_engine_clock,
1085                 .set_engine_clock = &radeon_atom_set_engine_clock,
1086                 .get_memory_clock = NULL,
1087                 .set_memory_clock = NULL,
1088                 .get_pcie_lanes = NULL,
1089                 .set_pcie_lanes = NULL,
1090                 .set_clock_gating = NULL,
1091         },
1092         .pflip = {
1093                 .pre_page_flip = &rs600_pre_page_flip,
1094                 .page_flip = &rs600_page_flip,
1095                 .post_page_flip = &rs600_post_page_flip,
1096         },
1097 };
1098
1099 static struct radeon_asic rv770_asic = {
1100         .init = &rv770_init,
1101         .fini = &rv770_fini,
1102         .suspend = &rv770_suspend,
1103         .resume = &rv770_resume,
1104         .asic_reset = &r600_asic_reset,
1105         .vga_set_state = &r600_vga_set_state,
1106         .ioctl_wait_idle = r600_ioctl_wait_idle,
1107         .gui_idle = &r600_gui_idle,
1108         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1109         .get_xclk = &rv770_get_xclk,
1110         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1111         .gart = {
1112                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1113                 .set_page = &rs600_gart_set_page,
1114         },
1115         .ring = {
1116                 [RADEON_RING_TYPE_GFX_INDEX] = {
1117                         .ib_execute = &r600_ring_ib_execute,
1118                         .emit_fence = &r600_fence_ring_emit,
1119                         .emit_semaphore = &r600_semaphore_ring_emit,
1120                         .cs_parse = &r600_cs_parse,
1121                         .ring_test = &r600_ring_test,
1122                         .ib_test = &r600_ib_test,
1123                         .is_lockup = &r600_gfx_is_lockup,
1124                 },
1125                 [R600_RING_TYPE_DMA_INDEX] = {
1126                         .ib_execute = &r600_dma_ring_ib_execute,
1127                         .emit_fence = &r600_dma_fence_ring_emit,
1128                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1129                         .cs_parse = &r600_dma_cs_parse,
1130                         .ring_test = &r600_dma_ring_test,
1131                         .ib_test = &r600_dma_ib_test,
1132                         .is_lockup = &r600_dma_is_lockup,
1133                 },
1134                 [R600_RING_TYPE_UVD_INDEX] = {
1135                         .ib_execute = &r600_uvd_ib_execute,
1136                         .emit_fence = &r600_uvd_fence_emit,
1137                         .emit_semaphore = &r600_uvd_semaphore_emit,
1138                         .cs_parse = &radeon_uvd_cs_parse,
1139                         .ring_test = &r600_uvd_ring_test,
1140                         .ib_test = &r600_uvd_ib_test,
1141                         .is_lockup = &radeon_ring_test_lockup,
1142                 }
1143         },
1144         .irq = {
1145                 .set = &r600_irq_set,
1146                 .process = &r600_irq_process,
1147         },
1148         .display = {
1149                 .bandwidth_update = &rv515_bandwidth_update,
1150                 .get_vblank_counter = &rs600_get_vblank_counter,
1151                 .wait_for_vblank = &avivo_wait_for_vblank,
1152                 .set_backlight_level = &atombios_set_backlight_level,
1153                 .get_backlight_level = &atombios_get_backlight_level,
1154         },
1155         .copy = {
1156                 .blit = &r600_copy_blit,
1157                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1158                 .dma = &rv770_copy_dma,
1159                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1160                 .copy = &rv770_copy_dma,
1161                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1162         },
1163         .surface = {
1164                 .set_reg = r600_set_surface_reg,
1165                 .clear_reg = r600_clear_surface_reg,
1166         },
1167         .hpd = {
1168                 .init = &r600_hpd_init,
1169                 .fini = &r600_hpd_fini,
1170                 .sense = &r600_hpd_sense,
1171                 .set_polarity = &r600_hpd_set_polarity,
1172         },
1173         .pm = {
1174                 .misc = &rv770_pm_misc,
1175                 .prepare = &rs600_pm_prepare,
1176                 .finish = &rs600_pm_finish,
1177                 .init_profile = &r600_pm_init_profile,
1178                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1179                 .get_engine_clock = &radeon_atom_get_engine_clock,
1180                 .set_engine_clock = &radeon_atom_set_engine_clock,
1181                 .get_memory_clock = &radeon_atom_get_memory_clock,
1182                 .set_memory_clock = &radeon_atom_set_memory_clock,
1183                 .get_pcie_lanes = &r600_get_pcie_lanes,
1184                 .set_pcie_lanes = &r600_set_pcie_lanes,
1185                 .set_clock_gating = &radeon_atom_set_clock_gating,
1186         },
1187         .pflip = {
1188                 .pre_page_flip = &rs600_pre_page_flip,
1189                 .page_flip = &rv770_page_flip,
1190                 .post_page_flip = &rs600_post_page_flip,
1191         },
1192 };
1193
1194 static struct radeon_asic evergreen_asic = {
1195         .init = &evergreen_init,
1196         .fini = &evergreen_fini,
1197         .suspend = &evergreen_suspend,
1198         .resume = &evergreen_resume,
1199         .asic_reset = &evergreen_asic_reset,
1200         .vga_set_state = &r600_vga_set_state,
1201         .ioctl_wait_idle = r600_ioctl_wait_idle,
1202         .gui_idle = &r600_gui_idle,
1203         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1204         .get_xclk = &rv770_get_xclk,
1205         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1206         .gart = {
1207                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1208                 .set_page = &rs600_gart_set_page,
1209         },
1210         .ring = {
1211                 [RADEON_RING_TYPE_GFX_INDEX] = {
1212                         .ib_execute = &evergreen_ring_ib_execute,
1213                         .emit_fence = &r600_fence_ring_emit,
1214                         .emit_semaphore = &r600_semaphore_ring_emit,
1215                         .cs_parse = &evergreen_cs_parse,
1216                         .ring_test = &r600_ring_test,
1217                         .ib_test = &r600_ib_test,
1218                         .is_lockup = &evergreen_gfx_is_lockup,
1219                 },
1220                 [R600_RING_TYPE_DMA_INDEX] = {
1221                         .ib_execute = &evergreen_dma_ring_ib_execute,
1222                         .emit_fence = &evergreen_dma_fence_ring_emit,
1223                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1224                         .cs_parse = &evergreen_dma_cs_parse,
1225                         .ring_test = &r600_dma_ring_test,
1226                         .ib_test = &r600_dma_ib_test,
1227                         .is_lockup = &evergreen_dma_is_lockup,
1228                 },
1229                 [R600_RING_TYPE_UVD_INDEX] = {
1230                         .ib_execute = &r600_uvd_ib_execute,
1231                         .emit_fence = &r600_uvd_fence_emit,
1232                         .emit_semaphore = &r600_uvd_semaphore_emit,
1233                         .cs_parse = &radeon_uvd_cs_parse,
1234                         .ring_test = &r600_uvd_ring_test,
1235                         .ib_test = &r600_uvd_ib_test,
1236                         .is_lockup = &radeon_ring_test_lockup,
1237                 }
1238         },
1239         .irq = {
1240                 .set = &evergreen_irq_set,
1241                 .process = &evergreen_irq_process,
1242         },
1243         .display = {
1244                 .bandwidth_update = &evergreen_bandwidth_update,
1245                 .get_vblank_counter = &evergreen_get_vblank_counter,
1246                 .wait_for_vblank = &dce4_wait_for_vblank,
1247                 .set_backlight_level = &atombios_set_backlight_level,
1248                 .get_backlight_level = &atombios_get_backlight_level,
1249         },
1250         .copy = {
1251                 .blit = &r600_copy_blit,
1252                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1253                 .dma = &evergreen_copy_dma,
1254                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1255                 .copy = &evergreen_copy_dma,
1256                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1257         },
1258         .surface = {
1259                 .set_reg = r600_set_surface_reg,
1260                 .clear_reg = r600_clear_surface_reg,
1261         },
1262         .hpd = {
1263                 .init = &evergreen_hpd_init,
1264                 .fini = &evergreen_hpd_fini,
1265                 .sense = &evergreen_hpd_sense,
1266                 .set_polarity = &evergreen_hpd_set_polarity,
1267         },
1268         .pm = {
1269                 .misc = &evergreen_pm_misc,
1270                 .prepare = &evergreen_pm_prepare,
1271                 .finish = &evergreen_pm_finish,
1272                 .init_profile = &r600_pm_init_profile,
1273                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1274                 .get_engine_clock = &radeon_atom_get_engine_clock,
1275                 .set_engine_clock = &radeon_atom_set_engine_clock,
1276                 .get_memory_clock = &radeon_atom_get_memory_clock,
1277                 .set_memory_clock = &radeon_atom_set_memory_clock,
1278                 .get_pcie_lanes = &r600_get_pcie_lanes,
1279                 .set_pcie_lanes = &r600_set_pcie_lanes,
1280                 .set_clock_gating = NULL,
1281         },
1282         .pflip = {
1283                 .pre_page_flip = &evergreen_pre_page_flip,
1284                 .page_flip = &evergreen_page_flip,
1285                 .post_page_flip = &evergreen_post_page_flip,
1286         },
1287 };
1288
1289 static struct radeon_asic sumo_asic = {
1290         .init = &evergreen_init,
1291         .fini = &evergreen_fini,
1292         .suspend = &evergreen_suspend,
1293         .resume = &evergreen_resume,
1294         .asic_reset = &evergreen_asic_reset,
1295         .vga_set_state = &r600_vga_set_state,
1296         .ioctl_wait_idle = r600_ioctl_wait_idle,
1297         .gui_idle = &r600_gui_idle,
1298         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1299         .get_xclk = &r600_get_xclk,
1300         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1301         .gart = {
1302                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1303                 .set_page = &rs600_gart_set_page,
1304         },
1305         .ring = {
1306                 [RADEON_RING_TYPE_GFX_INDEX] = {
1307                         .ib_execute = &evergreen_ring_ib_execute,
1308                         .emit_fence = &r600_fence_ring_emit,
1309                         .emit_semaphore = &r600_semaphore_ring_emit,
1310                         .cs_parse = &evergreen_cs_parse,
1311                         .ring_test = &r600_ring_test,
1312                         .ib_test = &r600_ib_test,
1313                         .is_lockup = &evergreen_gfx_is_lockup,
1314                 },
1315                 [R600_RING_TYPE_DMA_INDEX] = {
1316                         .ib_execute = &evergreen_dma_ring_ib_execute,
1317                         .emit_fence = &evergreen_dma_fence_ring_emit,
1318                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1319                         .cs_parse = &evergreen_dma_cs_parse,
1320                         .ring_test = &r600_dma_ring_test,
1321                         .ib_test = &r600_dma_ib_test,
1322                         .is_lockup = &evergreen_dma_is_lockup,
1323                 },
1324                 [R600_RING_TYPE_UVD_INDEX] = {
1325                         .ib_execute = &r600_uvd_ib_execute,
1326                         .emit_fence = &r600_uvd_fence_emit,
1327                         .emit_semaphore = &r600_uvd_semaphore_emit,
1328                         .cs_parse = &radeon_uvd_cs_parse,
1329                         .ring_test = &r600_uvd_ring_test,
1330                         .ib_test = &r600_uvd_ib_test,
1331                         .is_lockup = &radeon_ring_test_lockup,
1332                 }
1333         },
1334         .irq = {
1335                 .set = &evergreen_irq_set,
1336                 .process = &evergreen_irq_process,
1337         },
1338         .display = {
1339                 .bandwidth_update = &evergreen_bandwidth_update,
1340                 .get_vblank_counter = &evergreen_get_vblank_counter,
1341                 .wait_for_vblank = &dce4_wait_for_vblank,
1342                 .set_backlight_level = &atombios_set_backlight_level,
1343                 .get_backlight_level = &atombios_get_backlight_level,
1344         },
1345         .copy = {
1346                 .blit = &r600_copy_blit,
1347                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1348                 .dma = &evergreen_copy_dma,
1349                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1350                 .copy = &evergreen_copy_dma,
1351                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1352         },
1353         .surface = {
1354                 .set_reg = r600_set_surface_reg,
1355                 .clear_reg = r600_clear_surface_reg,
1356         },
1357         .hpd = {
1358                 .init = &evergreen_hpd_init,
1359                 .fini = &evergreen_hpd_fini,
1360                 .sense = &evergreen_hpd_sense,
1361                 .set_polarity = &evergreen_hpd_set_polarity,
1362         },
1363         .pm = {
1364                 .misc = &evergreen_pm_misc,
1365                 .prepare = &evergreen_pm_prepare,
1366                 .finish = &evergreen_pm_finish,
1367                 .init_profile = &sumo_pm_init_profile,
1368                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1369                 .get_engine_clock = &radeon_atom_get_engine_clock,
1370                 .set_engine_clock = &radeon_atom_set_engine_clock,
1371                 .get_memory_clock = NULL,
1372                 .set_memory_clock = NULL,
1373                 .get_pcie_lanes = NULL,
1374                 .set_pcie_lanes = NULL,
1375                 .set_clock_gating = NULL,
1376         },
1377         .pflip = {
1378                 .pre_page_flip = &evergreen_pre_page_flip,
1379                 .page_flip = &evergreen_page_flip,
1380                 .post_page_flip = &evergreen_post_page_flip,
1381         },
1382 };
1383
1384 static struct radeon_asic btc_asic = {
1385         .init = &evergreen_init,
1386         .fini = &evergreen_fini,
1387         .suspend = &evergreen_suspend,
1388         .resume = &evergreen_resume,
1389         .asic_reset = &evergreen_asic_reset,
1390         .vga_set_state = &r600_vga_set_state,
1391         .ioctl_wait_idle = r600_ioctl_wait_idle,
1392         .gui_idle = &r600_gui_idle,
1393         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394         .get_xclk = &rv770_get_xclk,
1395         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1396         .gart = {
1397                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398                 .set_page = &rs600_gart_set_page,
1399         },
1400         .ring = {
1401                 [RADEON_RING_TYPE_GFX_INDEX] = {
1402                         .ib_execute = &evergreen_ring_ib_execute,
1403                         .emit_fence = &r600_fence_ring_emit,
1404                         .emit_semaphore = &r600_semaphore_ring_emit,
1405                         .cs_parse = &evergreen_cs_parse,
1406                         .ring_test = &r600_ring_test,
1407                         .ib_test = &r600_ib_test,
1408                         .is_lockup = &evergreen_gfx_is_lockup,
1409                 },
1410                 [R600_RING_TYPE_DMA_INDEX] = {
1411                         .ib_execute = &evergreen_dma_ring_ib_execute,
1412                         .emit_fence = &evergreen_dma_fence_ring_emit,
1413                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1414                         .cs_parse = &evergreen_dma_cs_parse,
1415                         .ring_test = &r600_dma_ring_test,
1416                         .ib_test = &r600_dma_ib_test,
1417                         .is_lockup = &evergreen_dma_is_lockup,
1418                 },
1419                 [R600_RING_TYPE_UVD_INDEX] = {
1420                         .ib_execute = &r600_uvd_ib_execute,
1421                         .emit_fence = &r600_uvd_fence_emit,
1422                         .emit_semaphore = &r600_uvd_semaphore_emit,
1423                         .cs_parse = &radeon_uvd_cs_parse,
1424                         .ring_test = &r600_uvd_ring_test,
1425                         .ib_test = &r600_uvd_ib_test,
1426                         .is_lockup = &radeon_ring_test_lockup,
1427                 }
1428         },
1429         .irq = {
1430                 .set = &evergreen_irq_set,
1431                 .process = &evergreen_irq_process,
1432         },
1433         .display = {
1434                 .bandwidth_update = &evergreen_bandwidth_update,
1435                 .get_vblank_counter = &evergreen_get_vblank_counter,
1436                 .wait_for_vblank = &dce4_wait_for_vblank,
1437                 .set_backlight_level = &atombios_set_backlight_level,
1438                 .get_backlight_level = &atombios_get_backlight_level,
1439         },
1440         .copy = {
1441                 .blit = &r600_copy_blit,
1442                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1443                 .dma = &evergreen_copy_dma,
1444                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1445                 .copy = &evergreen_copy_dma,
1446                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1447         },
1448         .surface = {
1449                 .set_reg = r600_set_surface_reg,
1450                 .clear_reg = r600_clear_surface_reg,
1451         },
1452         .hpd = {
1453                 .init = &evergreen_hpd_init,
1454                 .fini = &evergreen_hpd_fini,
1455                 .sense = &evergreen_hpd_sense,
1456                 .set_polarity = &evergreen_hpd_set_polarity,
1457         },
1458         .pm = {
1459                 .misc = &evergreen_pm_misc,
1460                 .prepare = &evergreen_pm_prepare,
1461                 .finish = &evergreen_pm_finish,
1462                 .init_profile = &btc_pm_init_profile,
1463                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1464                 .get_engine_clock = &radeon_atom_get_engine_clock,
1465                 .set_engine_clock = &radeon_atom_set_engine_clock,
1466                 .get_memory_clock = &radeon_atom_get_memory_clock,
1467                 .set_memory_clock = &radeon_atom_set_memory_clock,
1468                 .get_pcie_lanes = NULL,
1469                 .set_pcie_lanes = NULL,
1470                 .set_clock_gating = NULL,
1471         },
1472         .pflip = {
1473                 .pre_page_flip = &evergreen_pre_page_flip,
1474                 .page_flip = &evergreen_page_flip,
1475                 .post_page_flip = &evergreen_post_page_flip,
1476         },
1477 };
1478
1479 static struct radeon_asic cayman_asic = {
1480         .init = &cayman_init,
1481         .fini = &cayman_fini,
1482         .suspend = &cayman_suspend,
1483         .resume = &cayman_resume,
1484         .asic_reset = &cayman_asic_reset,
1485         .vga_set_state = &r600_vga_set_state,
1486         .ioctl_wait_idle = r600_ioctl_wait_idle,
1487         .gui_idle = &r600_gui_idle,
1488         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1489         .get_xclk = &rv770_get_xclk,
1490         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1491         .gart = {
1492                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1493                 .set_page = &rs600_gart_set_page,
1494         },
1495         .vm = {
1496                 .init = &cayman_vm_init,
1497                 .fini = &cayman_vm_fini,
1498                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1499                 .set_page = &cayman_vm_set_page,
1500         },
1501         .ring = {
1502                 [RADEON_RING_TYPE_GFX_INDEX] = {
1503                         .ib_execute = &cayman_ring_ib_execute,
1504                         .ib_parse = &evergreen_ib_parse,
1505                         .emit_fence = &cayman_fence_ring_emit,
1506                         .emit_semaphore = &r600_semaphore_ring_emit,
1507                         .cs_parse = &evergreen_cs_parse,
1508                         .ring_test = &r600_ring_test,
1509                         .ib_test = &r600_ib_test,
1510                         .is_lockup = &cayman_gfx_is_lockup,
1511                         .vm_flush = &cayman_vm_flush,
1512                 },
1513                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1514                         .ib_execute = &cayman_ring_ib_execute,
1515                         .ib_parse = &evergreen_ib_parse,
1516                         .emit_fence = &cayman_fence_ring_emit,
1517                         .emit_semaphore = &r600_semaphore_ring_emit,
1518                         .cs_parse = &evergreen_cs_parse,
1519                         .ring_test = &r600_ring_test,
1520                         .ib_test = &r600_ib_test,
1521                         .is_lockup = &cayman_gfx_is_lockup,
1522                         .vm_flush = &cayman_vm_flush,
1523                 },
1524                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1525                         .ib_execute = &cayman_ring_ib_execute,
1526                         .ib_parse = &evergreen_ib_parse,
1527                         .emit_fence = &cayman_fence_ring_emit,
1528                         .emit_semaphore = &r600_semaphore_ring_emit,
1529                         .cs_parse = &evergreen_cs_parse,
1530                         .ring_test = &r600_ring_test,
1531                         .ib_test = &r600_ib_test,
1532                         .is_lockup = &cayman_gfx_is_lockup,
1533                         .vm_flush = &cayman_vm_flush,
1534                 },
1535                 [R600_RING_TYPE_DMA_INDEX] = {
1536                         .ib_execute = &cayman_dma_ring_ib_execute,
1537                         .ib_parse = &evergreen_dma_ib_parse,
1538                         .emit_fence = &evergreen_dma_fence_ring_emit,
1539                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1540                         .cs_parse = &evergreen_dma_cs_parse,
1541                         .ring_test = &r600_dma_ring_test,
1542                         .ib_test = &r600_dma_ib_test,
1543                         .is_lockup = &cayman_dma_is_lockup,
1544                         .vm_flush = &cayman_dma_vm_flush,
1545                 },
1546                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1547                         .ib_execute = &cayman_dma_ring_ib_execute,
1548                         .ib_parse = &evergreen_dma_ib_parse,
1549                         .emit_fence = &evergreen_dma_fence_ring_emit,
1550                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1551                         .cs_parse = &evergreen_dma_cs_parse,
1552                         .ring_test = &r600_dma_ring_test,
1553                         .ib_test = &r600_dma_ib_test,
1554                         .is_lockup = &cayman_dma_is_lockup,
1555                         .vm_flush = &cayman_dma_vm_flush,
1556                 },
1557                 [R600_RING_TYPE_UVD_INDEX] = {
1558                         .ib_execute = &r600_uvd_ib_execute,
1559                         .emit_fence = &r600_uvd_fence_emit,
1560                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1561                         .cs_parse = &radeon_uvd_cs_parse,
1562                         .ring_test = &r600_uvd_ring_test,
1563                         .ib_test = &r600_uvd_ib_test,
1564                         .is_lockup = &radeon_ring_test_lockup,
1565                 }
1566         },
1567         .irq = {
1568                 .set = &evergreen_irq_set,
1569                 .process = &evergreen_irq_process,
1570         },
1571         .display = {
1572                 .bandwidth_update = &evergreen_bandwidth_update,
1573                 .get_vblank_counter = &evergreen_get_vblank_counter,
1574                 .wait_for_vblank = &dce4_wait_for_vblank,
1575                 .set_backlight_level = &atombios_set_backlight_level,
1576                 .get_backlight_level = &atombios_get_backlight_level,
1577         },
1578         .copy = {
1579                 .blit = &r600_copy_blit,
1580                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1581                 .dma = &evergreen_copy_dma,
1582                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1583                 .copy = &evergreen_copy_dma,
1584                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1585         },
1586         .surface = {
1587                 .set_reg = r600_set_surface_reg,
1588                 .clear_reg = r600_clear_surface_reg,
1589         },
1590         .hpd = {
1591                 .init = &evergreen_hpd_init,
1592                 .fini = &evergreen_hpd_fini,
1593                 .sense = &evergreen_hpd_sense,
1594                 .set_polarity = &evergreen_hpd_set_polarity,
1595         },
1596         .pm = {
1597                 .misc = &evergreen_pm_misc,
1598                 .prepare = &evergreen_pm_prepare,
1599                 .finish = &evergreen_pm_finish,
1600                 .init_profile = &btc_pm_init_profile,
1601                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1602                 .get_engine_clock = &radeon_atom_get_engine_clock,
1603                 .set_engine_clock = &radeon_atom_set_engine_clock,
1604                 .get_memory_clock = &radeon_atom_get_memory_clock,
1605                 .set_memory_clock = &radeon_atom_set_memory_clock,
1606                 .get_pcie_lanes = NULL,
1607                 .set_pcie_lanes = NULL,
1608                 .set_clock_gating = NULL,
1609         },
1610         .pflip = {
1611                 .pre_page_flip = &evergreen_pre_page_flip,
1612                 .page_flip = &evergreen_page_flip,
1613                 .post_page_flip = &evergreen_post_page_flip,
1614         },
1615 };
1616
1617 static struct radeon_asic trinity_asic = {
1618         .init = &cayman_init,
1619         .fini = &cayman_fini,
1620         .suspend = &cayman_suspend,
1621         .resume = &cayman_resume,
1622         .asic_reset = &cayman_asic_reset,
1623         .vga_set_state = &r600_vga_set_state,
1624         .ioctl_wait_idle = r600_ioctl_wait_idle,
1625         .gui_idle = &r600_gui_idle,
1626         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1627         .get_xclk = &r600_get_xclk,
1628         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1629         .gart = {
1630                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1631                 .set_page = &rs600_gart_set_page,
1632         },
1633         .vm = {
1634                 .init = &cayman_vm_init,
1635                 .fini = &cayman_vm_fini,
1636                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1637                 .set_page = &cayman_vm_set_page,
1638         },
1639         .ring = {
1640                 [RADEON_RING_TYPE_GFX_INDEX] = {
1641                         .ib_execute = &cayman_ring_ib_execute,
1642                         .ib_parse = &evergreen_ib_parse,
1643                         .emit_fence = &cayman_fence_ring_emit,
1644                         .emit_semaphore = &r600_semaphore_ring_emit,
1645                         .cs_parse = &evergreen_cs_parse,
1646                         .ring_test = &r600_ring_test,
1647                         .ib_test = &r600_ib_test,
1648                         .is_lockup = &cayman_gfx_is_lockup,
1649                         .vm_flush = &cayman_vm_flush,
1650                 },
1651                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1652                         .ib_execute = &cayman_ring_ib_execute,
1653                         .ib_parse = &evergreen_ib_parse,
1654                         .emit_fence = &cayman_fence_ring_emit,
1655                         .emit_semaphore = &r600_semaphore_ring_emit,
1656                         .cs_parse = &evergreen_cs_parse,
1657                         .ring_test = &r600_ring_test,
1658                         .ib_test = &r600_ib_test,
1659                         .is_lockup = &cayman_gfx_is_lockup,
1660                         .vm_flush = &cayman_vm_flush,
1661                 },
1662                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1663                         .ib_execute = &cayman_ring_ib_execute,
1664                         .ib_parse = &evergreen_ib_parse,
1665                         .emit_fence = &cayman_fence_ring_emit,
1666                         .emit_semaphore = &r600_semaphore_ring_emit,
1667                         .cs_parse = &evergreen_cs_parse,
1668                         .ring_test = &r600_ring_test,
1669                         .ib_test = &r600_ib_test,
1670                         .is_lockup = &cayman_gfx_is_lockup,
1671                         .vm_flush = &cayman_vm_flush,
1672                 },
1673                 [R600_RING_TYPE_DMA_INDEX] = {
1674                         .ib_execute = &cayman_dma_ring_ib_execute,
1675                         .ib_parse = &evergreen_dma_ib_parse,
1676                         .emit_fence = &evergreen_dma_fence_ring_emit,
1677                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1678                         .cs_parse = &evergreen_dma_cs_parse,
1679                         .ring_test = &r600_dma_ring_test,
1680                         .ib_test = &r600_dma_ib_test,
1681                         .is_lockup = &cayman_dma_is_lockup,
1682                         .vm_flush = &cayman_dma_vm_flush,
1683                 },
1684                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1685                         .ib_execute = &cayman_dma_ring_ib_execute,
1686                         .ib_parse = &evergreen_dma_ib_parse,
1687                         .emit_fence = &evergreen_dma_fence_ring_emit,
1688                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1689                         .cs_parse = &evergreen_dma_cs_parse,
1690                         .ring_test = &r600_dma_ring_test,
1691                         .ib_test = &r600_dma_ib_test,
1692                         .is_lockup = &cayman_dma_is_lockup,
1693                         .vm_flush = &cayman_dma_vm_flush,
1694                 },
1695                 [R600_RING_TYPE_UVD_INDEX] = {
1696                         .ib_execute = &r600_uvd_ib_execute,
1697                         .emit_fence = &r600_uvd_fence_emit,
1698                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1699                         .cs_parse = &radeon_uvd_cs_parse,
1700                         .ring_test = &r600_uvd_ring_test,
1701                         .ib_test = &r600_uvd_ib_test,
1702                         .is_lockup = &radeon_ring_test_lockup,
1703                 }
1704         },
1705         .irq = {
1706                 .set = &evergreen_irq_set,
1707                 .process = &evergreen_irq_process,
1708         },
1709         .display = {
1710                 .bandwidth_update = &dce6_bandwidth_update,
1711                 .get_vblank_counter = &evergreen_get_vblank_counter,
1712                 .wait_for_vblank = &dce4_wait_for_vblank,
1713                 .set_backlight_level = &atombios_set_backlight_level,
1714                 .get_backlight_level = &atombios_get_backlight_level,
1715         },
1716         .copy = {
1717                 .blit = &r600_copy_blit,
1718                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1719                 .dma = &evergreen_copy_dma,
1720                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1721                 .copy = &evergreen_copy_dma,
1722                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1723         },
1724         .surface = {
1725                 .set_reg = r600_set_surface_reg,
1726                 .clear_reg = r600_clear_surface_reg,
1727         },
1728         .hpd = {
1729                 .init = &evergreen_hpd_init,
1730                 .fini = &evergreen_hpd_fini,
1731                 .sense = &evergreen_hpd_sense,
1732                 .set_polarity = &evergreen_hpd_set_polarity,
1733         },
1734         .pm = {
1735                 .misc = &evergreen_pm_misc,
1736                 .prepare = &evergreen_pm_prepare,
1737                 .finish = &evergreen_pm_finish,
1738                 .init_profile = &sumo_pm_init_profile,
1739                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1740                 .get_engine_clock = &radeon_atom_get_engine_clock,
1741                 .set_engine_clock = &radeon_atom_set_engine_clock,
1742                 .get_memory_clock = NULL,
1743                 .set_memory_clock = NULL,
1744                 .get_pcie_lanes = NULL,
1745                 .set_pcie_lanes = NULL,
1746                 .set_clock_gating = NULL,
1747         },
1748         .pflip = {
1749                 .pre_page_flip = &evergreen_pre_page_flip,
1750                 .page_flip = &evergreen_page_flip,
1751                 .post_page_flip = &evergreen_post_page_flip,
1752         },
1753 };
1754
1755 static struct radeon_asic si_asic = {
1756         .init = &si_init,
1757         .fini = &si_fini,
1758         .suspend = &si_suspend,
1759         .resume = &si_resume,
1760         .asic_reset = &si_asic_reset,
1761         .vga_set_state = &r600_vga_set_state,
1762         .ioctl_wait_idle = r600_ioctl_wait_idle,
1763         .gui_idle = &r600_gui_idle,
1764         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1765         .get_xclk = &si_get_xclk,
1766         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1767         .gart = {
1768                 .tlb_flush = &si_pcie_gart_tlb_flush,
1769                 .set_page = &rs600_gart_set_page,
1770         },
1771         .vm = {
1772                 .init = &si_vm_init,
1773                 .fini = &si_vm_fini,
1774                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1775                 .set_page = &si_vm_set_page,
1776         },
1777         .ring = {
1778                 [RADEON_RING_TYPE_GFX_INDEX] = {
1779                         .ib_execute = &si_ring_ib_execute,
1780                         .ib_parse = &si_ib_parse,
1781                         .emit_fence = &si_fence_ring_emit,
1782                         .emit_semaphore = &r600_semaphore_ring_emit,
1783                         .cs_parse = NULL,
1784                         .ring_test = &r600_ring_test,
1785                         .ib_test = &r600_ib_test,
1786                         .is_lockup = &si_gfx_is_lockup,
1787                         .vm_flush = &si_vm_flush,
1788                 },
1789                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1790                         .ib_execute = &si_ring_ib_execute,
1791                         .ib_parse = &si_ib_parse,
1792                         .emit_fence = &si_fence_ring_emit,
1793                         .emit_semaphore = &r600_semaphore_ring_emit,
1794                         .cs_parse = NULL,
1795                         .ring_test = &r600_ring_test,
1796                         .ib_test = &r600_ib_test,
1797                         .is_lockup = &si_gfx_is_lockup,
1798                         .vm_flush = &si_vm_flush,
1799                 },
1800                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1801                         .ib_execute = &si_ring_ib_execute,
1802                         .ib_parse = &si_ib_parse,
1803                         .emit_fence = &si_fence_ring_emit,
1804                         .emit_semaphore = &r600_semaphore_ring_emit,
1805                         .cs_parse = NULL,
1806                         .ring_test = &r600_ring_test,
1807                         .ib_test = &r600_ib_test,
1808                         .is_lockup = &si_gfx_is_lockup,
1809                         .vm_flush = &si_vm_flush,
1810                 },
1811                 [R600_RING_TYPE_DMA_INDEX] = {
1812                         .ib_execute = &cayman_dma_ring_ib_execute,
1813                         .ib_parse = &evergreen_dma_ib_parse,
1814                         .emit_fence = &evergreen_dma_fence_ring_emit,
1815                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1816                         .cs_parse = NULL,
1817                         .ring_test = &r600_dma_ring_test,
1818                         .ib_test = &r600_dma_ib_test,
1819                         .is_lockup = &si_dma_is_lockup,
1820                         .vm_flush = &si_dma_vm_flush,
1821                 },
1822                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1823                         .ib_execute = &cayman_dma_ring_ib_execute,
1824                         .ib_parse = &evergreen_dma_ib_parse,
1825                         .emit_fence = &evergreen_dma_fence_ring_emit,
1826                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1827                         .cs_parse = NULL,
1828                         .ring_test = &r600_dma_ring_test,
1829                         .ib_test = &r600_dma_ib_test,
1830                         .is_lockup = &si_dma_is_lockup,
1831                         .vm_flush = &si_dma_vm_flush,
1832                 },
1833                 [R600_RING_TYPE_UVD_INDEX] = {
1834                         .ib_execute = &r600_uvd_ib_execute,
1835                         .emit_fence = &r600_uvd_fence_emit,
1836                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1837                         .cs_parse = &radeon_uvd_cs_parse,
1838                         .ring_test = &r600_uvd_ring_test,
1839                         .ib_test = &r600_uvd_ib_test,
1840                         .is_lockup = &radeon_ring_test_lockup,
1841                 }
1842         },
1843         .irq = {
1844                 .set = &si_irq_set,
1845                 .process = &si_irq_process,
1846         },
1847         .display = {
1848                 .bandwidth_update = &dce6_bandwidth_update,
1849                 .get_vblank_counter = &evergreen_get_vblank_counter,
1850                 .wait_for_vblank = &dce4_wait_for_vblank,
1851                 .set_backlight_level = &atombios_set_backlight_level,
1852                 .get_backlight_level = &atombios_get_backlight_level,
1853         },
1854         .copy = {
1855                 .blit = NULL,
1856                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1857                 .dma = &si_copy_dma,
1858                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1859                 .copy = &si_copy_dma,
1860                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1861         },
1862         .surface = {
1863                 .set_reg = r600_set_surface_reg,
1864                 .clear_reg = r600_clear_surface_reg,
1865         },
1866         .hpd = {
1867                 .init = &evergreen_hpd_init,
1868                 .fini = &evergreen_hpd_fini,
1869                 .sense = &evergreen_hpd_sense,
1870                 .set_polarity = &evergreen_hpd_set_polarity,
1871         },
1872         .pm = {
1873                 .misc = &evergreen_pm_misc,
1874                 .prepare = &evergreen_pm_prepare,
1875                 .finish = &evergreen_pm_finish,
1876                 .init_profile = &sumo_pm_init_profile,
1877                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1878                 .get_engine_clock = &radeon_atom_get_engine_clock,
1879                 .set_engine_clock = &radeon_atom_set_engine_clock,
1880                 .get_memory_clock = &radeon_atom_get_memory_clock,
1881                 .set_memory_clock = &radeon_atom_set_memory_clock,
1882                 .get_pcie_lanes = NULL,
1883                 .set_pcie_lanes = NULL,
1884                 .set_clock_gating = NULL,
1885         },
1886         .pflip = {
1887                 .pre_page_flip = &evergreen_pre_page_flip,
1888                 .page_flip = &evergreen_page_flip,
1889                 .post_page_flip = &evergreen_post_page_flip,
1890         },
1891 };
1892
1893 /**
1894  * radeon_asic_init - register asic specific callbacks
1895  *
1896  * @rdev: radeon device pointer
1897  *
1898  * Registers the appropriate asic specific callbacks for each
1899  * chip family.  Also sets other asics specific info like the number
1900  * of crtcs and the register aperture accessors (all asics).
1901  * Returns 0 for success.
1902  */
1903 int radeon_asic_init(struct radeon_device *rdev)
1904 {
1905         radeon_register_accessor_init(rdev);
1906
1907         /* set the number of crtcs */
1908         if (rdev->flags & RADEON_SINGLE_CRTC)
1909                 rdev->num_crtc = 1;
1910         else
1911                 rdev->num_crtc = 2;
1912
1913         switch (rdev->family) {
1914         case CHIP_R100:
1915         case CHIP_RV100:
1916         case CHIP_RS100:
1917         case CHIP_RV200:
1918         case CHIP_RS200:
1919                 rdev->asic = &r100_asic;
1920                 break;
1921         case CHIP_R200:
1922         case CHIP_RV250:
1923         case CHIP_RS300:
1924         case CHIP_RV280:
1925                 rdev->asic = &r200_asic;
1926                 break;
1927         case CHIP_R300:
1928         case CHIP_R350:
1929         case CHIP_RV350:
1930         case CHIP_RV380:
1931                 if (rdev->flags & RADEON_IS_PCIE)
1932                         rdev->asic = &r300_asic_pcie;
1933                 else
1934                         rdev->asic = &r300_asic;
1935                 break;
1936         case CHIP_R420:
1937         case CHIP_R423:
1938         case CHIP_RV410:
1939                 rdev->asic = &r420_asic;
1940                 /* handle macs */
1941                 if (rdev->bios == NULL) {
1942                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1943                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1944                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1945                         rdev->asic->pm.set_memory_clock = NULL;
1946                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1947                 }
1948                 break;
1949         case CHIP_RS400:
1950         case CHIP_RS480:
1951                 rdev->asic = &rs400_asic;
1952                 break;
1953         case CHIP_RS600:
1954                 rdev->asic = &rs600_asic;
1955                 break;
1956         case CHIP_RS690:
1957         case CHIP_RS740:
1958                 rdev->asic = &rs690_asic;
1959                 break;
1960         case CHIP_RV515:
1961                 rdev->asic = &rv515_asic;
1962                 break;
1963         case CHIP_R520:
1964         case CHIP_RV530:
1965         case CHIP_RV560:
1966         case CHIP_RV570:
1967         case CHIP_R580:
1968                 rdev->asic = &r520_asic;
1969                 break;
1970         case CHIP_R600:
1971         case CHIP_RV610:
1972         case CHIP_RV630:
1973         case CHIP_RV620:
1974         case CHIP_RV635:
1975         case CHIP_RV670:
1976                 rdev->asic = &r600_asic;
1977                 break;
1978         case CHIP_RS780:
1979         case CHIP_RS880:
1980                 rdev->asic = &rs780_asic;
1981                 break;
1982         case CHIP_RV770:
1983         case CHIP_RV730:
1984         case CHIP_RV710:
1985         case CHIP_RV740:
1986                 rdev->asic = &rv770_asic;
1987                 break;
1988         case CHIP_CEDAR:
1989         case CHIP_REDWOOD:
1990         case CHIP_JUNIPER:
1991         case CHIP_CYPRESS:
1992         case CHIP_HEMLOCK:
1993                 /* set num crtcs */
1994                 if (rdev->family == CHIP_CEDAR)
1995                         rdev->num_crtc = 4;
1996                 else
1997                         rdev->num_crtc = 6;
1998                 rdev->asic = &evergreen_asic;
1999                 break;
2000         case CHIP_PALM:
2001         case CHIP_SUMO:
2002         case CHIP_SUMO2:
2003                 rdev->asic = &sumo_asic;
2004                 break;
2005         case CHIP_BARTS:
2006         case CHIP_TURKS:
2007         case CHIP_CAICOS:
2008                 /* set num crtcs */
2009                 if (rdev->family == CHIP_CAICOS)
2010                         rdev->num_crtc = 4;
2011                 else
2012                         rdev->num_crtc = 6;
2013                 rdev->asic = &btc_asic;
2014                 break;
2015         case CHIP_CAYMAN:
2016                 rdev->asic = &cayman_asic;
2017                 /* set num crtcs */
2018                 rdev->num_crtc = 6;
2019                 break;
2020         case CHIP_ARUBA:
2021                 rdev->asic = &trinity_asic;
2022                 /* set num crtcs */
2023                 rdev->num_crtc = 4;
2024                 break;
2025         case CHIP_TAHITI:
2026         case CHIP_PITCAIRN:
2027         case CHIP_VERDE:
2028         case CHIP_OLAND:
2029                 rdev->asic = &si_asic;
2030                 /* set num crtcs */
2031                 if (rdev->family == CHIP_OLAND)
2032                         rdev->num_crtc = 2;
2033                 else
2034                         rdev->num_crtc = 6;
2035                 break;
2036         default:
2037                 /* FIXME: not supported yet */
2038                 return -EINVAL;
2039         }
2040
2041         if (rdev->flags & RADEON_IS_IGP) {
2042                 rdev->asic->pm.get_memory_clock = NULL;
2043                 rdev->asic->pm.set_memory_clock = NULL;
2044         }
2045
2046         return 0;
2047 }
2048