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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBNX_TYPEDEFS_H__
53 #define __CVMX_USBNX_TYPEDEFS_H__
55 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
56 #define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
57 #define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
58 #define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
59 #define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull)
60 #define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull)
61 #define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull)
62 #define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull)
63 #define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull)
64 #define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull)
65 #define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull)
66 #define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull)
67 #define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull)
68 #define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull)
69 #define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull)
70 #define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull)
71 #define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull)
72 #define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull)
73 #define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull)
74 #define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull)
75 #define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull)
76 #define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull)
77 #define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)
82 * USBN_CLK_CTL = USBN's Clock Control
84 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
86 union cvmx_usbnx_clk_ctl
89 struct cvmx_usbnx_clk_ctl_s
91 uint64_t reserved_20_63 : 44;
92 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
94 Also see the field DIVIDE. DIVIDE2<1> must currently
95 be zero because it is not implemented, so the maximum
96 ratio of eclk/hclk is currently 16.
97 The actual divide number for hclk is:
98 (DIVIDE2 + 1) * (DIVIDE + 1) */
99 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
100 generate the hclk in the USB Subsystem is held
101 in reset. This bit must be set to '0' before
102 changing the value os DIVIDE in this register.
103 The reset to the HCLK_DIVIDERis also asserted
104 when core reset is asserted. */
105 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
106 '1' USB-PHY XO block is powered-down during
108 '0' USB-PHY XO block is powered-up during
110 The value of this field must be set while POR is
112 uint64_t reserved_14_15 : 2;
113 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
114 remain powered in Suspend Mode.
115 '1' The USB-PHY XO Bias, Bandgap and PLL are
116 powered down in suspend mode.
117 The value of this field must be set while POR is
119 uint64_t p_c_sel : 2; /**< Phy clock speed select.
120 Selects the reference clock / crystal frequency.
122 '10': 48 MHz (reserved when a crystal is used)
123 '01': 24 MHz (reserved when a crystal is used)
125 The value of this field must be set while POR is
127 NOTE: if a crystal is used as a reference clock,
128 this field must be set to 12 MHz. */
129 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
130 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
131 in the USBC, for normal operation this must be '0'. */
132 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
133 to '1' transition. */
134 uint64_t por : 1; /**< Power On Reset for the PHY.
135 Resets all the PHYS registers and state machines. */
136 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
137 '0' the hclk will not be generated. SEE DIVIDE
138 field of this register. */
139 uint64_t prst : 1; /**< When this field is '0' the reset associated with
140 the phy_clk functionality in the USB Subsystem is
141 help in reset. This bit should not be set to '1'
142 until the time it takes 6 clocks (hclk or phy_clk,
143 whichever is slower) has passed. Under normal
144 operation once this bit is set to '1' it should not
146 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
147 the hclk functioanlity in the USB Subsystem is
148 held in reset.This bit should not be set to '1'
149 until 12ms after phy_clk is stable. Under normal
150 operation, once this bit is set to '1' it should
151 not be set to '0'. */
152 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
153 is the eclk frequency divided by the value of
154 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
155 DIVIDE2 of this register.
156 The hclk frequency should be less than 125Mhz.
157 After writing a value to this field the SW should
158 read the field for the value written.
159 The ENABLE field of this register should not be set
160 until AFTER this field is set and then read. */
162 struct cvmx_usbnx_clk_ctl_cn30xx
164 uint64_t reserved_18_63 : 46;
165 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
166 generate the hclk in the USB Subsystem is held
167 in reset. This bit must be set to '0' before
168 changing the value os DIVIDE in this register.
169 The reset to the HCLK_DIVIDERis also asserted
170 when core reset is asserted. */
171 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
172 '1' USB-PHY XO block is powered-down during
174 '0' USB-PHY XO block is powered-up during
176 The value of this field must be set while POR is
178 uint64_t p_rclk : 1; /**< Phy refrence clock enable.
179 '1' The PHY PLL uses the XO block output as a
182 uint64_t p_xenbn : 1; /**< Phy external clock enable.
183 '1' The XO block uses the clock from a crystal.
184 '0' The XO block uses an external clock supplied
185 on the XO pin. USB_XI should be tied to
186 ground for this usage. */
187 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
188 remain powered in Suspend Mode.
189 '1' The USB-PHY XO Bias, Bandgap and PLL are
190 powered down in suspend mode.
191 The value of this field must be set while POR is
193 uint64_t p_c_sel : 2; /**< Phy clock speed select.
194 Selects the reference clock / crystal frequency.
199 The value of this field must be set while POR is
201 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
202 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
203 in the USBC, for normal operation this must be '0'. */
204 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
205 to '1' transition. */
206 uint64_t por : 1; /**< Power On Reset for the PHY.
207 Resets all the PHYS registers and state machines. */
208 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
209 '0' the hclk will not be generated. */
210 uint64_t prst : 1; /**< When this field is '0' the reset associated with
211 the phy_clk functionality in the USB Subsystem is
212 help in reset. This bit should not be set to '1'
213 until the time it takes 6 clocks (hclk or phy_clk,
214 whichever is slower) has passed. Under normal
215 operation once this bit is set to '1' it should not
217 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
218 the hclk functioanlity in the USB Subsystem is
219 held in reset.This bit should not be set to '1'
220 until 12ms after phy_clk is stable. Under normal
221 operation, once this bit is set to '1' it should
222 not be set to '0'. */
223 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived
224 from the eclk. The eclk will be divided by the
225 value of this field +1 to determine the hclk
226 frequency. (Also see HRST of this register).
227 The hclk frequency must be less than 125 MHz. */
229 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
230 struct cvmx_usbnx_clk_ctl_cn50xx
232 uint64_t reserved_20_63 : 44;
233 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
235 Also see the field DIVIDE. DIVIDE2<1> must currently
236 be zero because it is not implemented, so the maximum
237 ratio of eclk/hclk is currently 16.
238 The actual divide number for hclk is:
239 (DIVIDE2 + 1) * (DIVIDE + 1) */
240 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
241 generate the hclk in the USB Subsystem is held
242 in reset. This bit must be set to '0' before
243 changing the value os DIVIDE in this register.
244 The reset to the HCLK_DIVIDERis also asserted
245 when core reset is asserted. */
246 uint64_t reserved_16_16 : 1;
247 uint64_t p_rtype : 2; /**< PHY reference clock type
248 '0' The USB-PHY uses a 12MHz crystal as a clock
249 source at the USB_XO and USB_XI pins
251 '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
252 at the USB_XO pin. USB_XI should be tied to
255 (bit 14 was P_XENBN on 3xxx)
256 (bit 15 was P_RCLK on 3xxx) */
257 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
258 remain powered in Suspend Mode.
259 '1' The USB-PHY XO Bias, Bandgap and PLL are
260 powered down in suspend mode.
261 The value of this field must be set while POR is
263 uint64_t p_c_sel : 2; /**< Phy clock speed select.
264 Selects the reference clock / crystal frequency.
266 '10': 48 MHz (reserved when a crystal is used)
267 '01': 24 MHz (reserved when a crystal is used)
269 The value of this field must be set while POR is
271 NOTE: if a crystal is used as a reference clock,
272 this field must be set to 12 MHz. */
273 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
274 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
275 in the USBC, for normal operation this must be '0'. */
276 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
277 to '1' transition. */
278 uint64_t por : 1; /**< Power On Reset for the PHY.
279 Resets all the PHYS registers and state machines. */
280 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
281 '0' the hclk will not be generated. SEE DIVIDE
282 field of this register. */
283 uint64_t prst : 1; /**< When this field is '0' the reset associated with
284 the phy_clk functionality in the USB Subsystem is
285 help in reset. This bit should not be set to '1'
286 until the time it takes 6 clocks (hclk or phy_clk,
287 whichever is slower) has passed. Under normal
288 operation once this bit is set to '1' it should not
290 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
291 the hclk functioanlity in the USB Subsystem is
292 held in reset.This bit should not be set to '1'
293 until 12ms after phy_clk is stable. Under normal
294 operation, once this bit is set to '1' it should
295 not be set to '0'. */
296 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
297 is the eclk frequency divided by the value of
298 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
299 DIVIDE2 of this register.
300 The hclk frequency should be less than 125Mhz.
301 After writing a value to this field the SW should
302 read the field for the value written.
303 The ENABLE field of this register should not be set
304 until AFTER this field is set and then read. */
306 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
307 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
309 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
312 * cvmx_usbn#_usbp_ctl_status
314 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
316 * Contains general control and status information for the USBN block.
318 union cvmx_usbnx_usbp_ctl_status
321 struct cvmx_usbnx_usbp_ctl_status_s
323 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
324 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
325 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
326 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
327 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
328 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
329 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
330 uint64_t otgdisable : 1; /**< OTG Block Disable */
331 uint64_t portreset : 1; /**< Per_Port Reset */
332 uint64_t drvvbus : 1; /**< Drive VBUS */
333 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
334 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
335 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
336 uint64_t bist_done : 1; /**< PHY Bist Done.
337 Asserted at the end of the PHY BIST sequence. */
338 uint64_t bist_err : 1; /**< PHY Bist Error.
339 Indicates an internal error was detected during
340 the BIST sequence. */
341 uint64_t tdata_out : 4; /**< PHY Test Data Out.
342 Presents either internaly generated signals or
343 test register contents, based upon the value of
344 test_data_out_sel. */
345 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
346 Normally should be set to zero.
347 When customers have no intent to use USB PHY
348 interface, they should:
349 - still provide 3.3V to USB_VDD33, and
350 - tie USB_REXT to 3.3V supply, and
351 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
352 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
353 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
354 with byte-counts between packets. When set to 0
355 the L2C DMA address is incremented to the next
356 4-byte aligned address after adding byte-count. */
357 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
358 set to '0' for operation. */
359 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
360 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
361 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
362 This signal enables the pull-down resistance on
363 the D+ line. '1' pull down-resistance is connected
364 to D+/ '0' pull down resistance is not connected
365 to D+. When an A/B device is acting as a host
366 (downstream-facing port), dp_pulldown and
367 dm_pulldown are enabled. This must not toggle
368 during normal opeartion. */
369 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
370 This signal enables the pull-down resistance on
371 the D- line. '1' pull down-resistance is connected
372 to D-. '0' pull down resistance is not connected
373 to D-. When an A/B device is acting as a host
374 (downstream-facing port), dp_pulldown and
375 dm_pulldown are enabled. This must not toggle
376 during normal opeartion. */
377 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
378 USB is acting as device. This field needs to be
379 set while the USB is in reset. */
380 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
381 Tunes the current supply and rise/fall output
382 times for high-speed operation.
383 [20:19] == 11: Current supply increased
385 [20:19] == 10: Current supply increased
387 [20:19] == 01: Design default.
388 [20:19] == 00: Current supply decreased
390 [22:21] == 11: Rise and fall times are increased.
391 [22:21] == 10: Design default.
392 [22:21] == 01: Rise and fall times are decreased.
393 [22:21] == 00: Rise and fall times are decreased
394 further as compared to the 01 setting. */
395 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
396 Enables or disables bit stuffing on data[15:8]
397 when bit-stuffing is enabled. */
398 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
399 Enables or disables bit stuffing on data[7:0]
400 when bit-stuffing is enabled. */
401 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
402 '1': During data transmission the receive is
404 '0': During data transmission the receive is
406 Must be '0' for normal operation. */
407 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
408 '1' The PHY's analog_test pin is enabled for the
409 input and output of applicable analog test signals.
410 '0' THe analog_test pin is disabled. */
411 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
412 Used to activate BIST in the PHY. */
413 uint64_t tdata_sel : 1; /**< Test Data Out Select.
414 '1' test_data_out[3:0] (PHY) register contents
415 are output. '0' internaly generated signals are
417 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
418 Specifies the register address for writing to or
419 reading from the PHY test interface register. */
420 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
421 This is a test bus. Data is present on [3:0],
422 and its corresponding select (enable) is present
424 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
425 This is a test signal. When the USB Core is
426 powered up (not in Susned Mode), an automatic
427 tester can use this to disable phy_clock and
428 free_clk, then re-eanable them with an aligned
430 '1': The phy_clk and free_clk outputs are
431 disabled. "0": The phy_clock and free_clk outputs
432 are available within a specific period after the
435 struct cvmx_usbnx_usbp_ctl_status_cn30xx
437 uint64_t reserved_38_63 : 26;
438 uint64_t bist_done : 1; /**< PHY Bist Done.
439 Asserted at the end of the PHY BIST sequence. */
440 uint64_t bist_err : 1; /**< PHY Bist Error.
441 Indicates an internal error was detected during
442 the BIST sequence. */
443 uint64_t tdata_out : 4; /**< PHY Test Data Out.
444 Presents either internaly generated signals or
445 test register contents, based upon the value of
446 test_data_out_sel. */
447 uint64_t reserved_30_31 : 2;
448 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
449 with byte-counts between packets. When set to 0
450 the L2C DMA address is incremented to the next
451 4-byte aligned address after adding byte-count. */
452 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
453 set to '0' for operation. */
454 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
455 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
456 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
457 This signal enables the pull-down resistance on
458 the D+ line. '1' pull down-resistance is connected
459 to D+/ '0' pull down resistance is not connected
460 to D+. When an A/B device is acting as a host
461 (downstream-facing port), dp_pulldown and
462 dm_pulldown are enabled. This must not toggle
463 during normal opeartion. */
464 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
465 This signal enables the pull-down resistance on
466 the D- line. '1' pull down-resistance is connected
467 to D-. '0' pull down resistance is not connected
468 to D-. When an A/B device is acting as a host
469 (downstream-facing port), dp_pulldown and
470 dm_pulldown are enabled. This must not toggle
471 during normal opeartion. */
472 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
473 USB is acting as device. This field needs to be
474 set while the USB is in reset. */
475 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
476 Tunes the current supply and rise/fall output
477 times for high-speed operation.
478 [20:19] == 11: Current supply increased
480 [20:19] == 10: Current supply increased
482 [20:19] == 01: Design default.
483 [20:19] == 00: Current supply decreased
485 [22:21] == 11: Rise and fall times are increased.
486 [22:21] == 10: Design default.
487 [22:21] == 01: Rise and fall times are decreased.
488 [22:21] == 00: Rise and fall times are decreased
489 further as compared to the 01 setting. */
490 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
491 Enables or disables bit stuffing on data[15:8]
492 when bit-stuffing is enabled. */
493 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
494 Enables or disables bit stuffing on data[7:0]
495 when bit-stuffing is enabled. */
496 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
497 '1': During data transmission the receive is
499 '0': During data transmission the receive is
501 Must be '0' for normal operation. */
502 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
503 '1' The PHY's analog_test pin is enabled for the
504 input and output of applicable analog test signals.
505 '0' THe analog_test pin is disabled. */
506 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
507 Used to activate BIST in the PHY. */
508 uint64_t tdata_sel : 1; /**< Test Data Out Select.
509 '1' test_data_out[3:0] (PHY) register contents
510 are output. '0' internaly generated signals are
512 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
513 Specifies the register address for writing to or
514 reading from the PHY test interface register. */
515 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
516 This is a test bus. Data is present on [3:0],
517 and its corresponding select (enable) is present
519 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
520 This is a test signal. When the USB Core is
521 powered up (not in Susned Mode), an automatic
522 tester can use this to disable phy_clock and
523 free_clk, then re-eanable them with an aligned
525 '1': The phy_clk and free_clk outputs are
526 disabled. "0": The phy_clock and free_clk outputs
527 are available within a specific period after the
530 struct cvmx_usbnx_usbp_ctl_status_cn50xx
532 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
533 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
534 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
535 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
536 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
537 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
538 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
539 uint64_t otgdisable : 1; /**< OTG Block Disable */
540 uint64_t portreset : 1; /**< Per_Port Reset */
541 uint64_t drvvbus : 1; /**< Drive VBUS */
542 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
543 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
544 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
545 uint64_t bist_done : 1; /**< PHY Bist Done.
546 Asserted at the end of the PHY BIST sequence. */
547 uint64_t bist_err : 1; /**< PHY Bist Error.
548 Indicates an internal error was detected during
549 the BIST sequence. */
550 uint64_t tdata_out : 4; /**< PHY Test Data Out.
551 Presents either internaly generated signals or
552 test register contents, based upon the value of
553 test_data_out_sel. */
554 uint64_t reserved_31_31 : 1;
555 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
556 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
557 with byte-counts between packets. When set to 0
558 the L2C DMA address is incremented to the next
559 4-byte aligned address after adding byte-count. */
560 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
561 set to '0' for operation. */
562 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
563 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
564 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
565 This signal enables the pull-down resistance on
566 the D+ line. '1' pull down-resistance is connected
567 to D+/ '0' pull down resistance is not connected
568 to D+. When an A/B device is acting as a host
569 (downstream-facing port), dp_pulldown and
570 dm_pulldown are enabled. This must not toggle
571 during normal opeartion. */
572 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
573 This signal enables the pull-down resistance on
574 the D- line. '1' pull down-resistance is connected
575 to D-. '0' pull down resistance is not connected
576 to D-. When an A/B device is acting as a host
577 (downstream-facing port), dp_pulldown and
578 dm_pulldown are enabled. This must not toggle
579 during normal opeartion. */
580 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
581 USB is acting as device. This field needs to be
582 set while the USB is in reset. */
583 uint64_t reserved_19_22 : 4;
584 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
585 Enables or disables bit stuffing on data[15:8]
586 when bit-stuffing is enabled. */
587 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
588 Enables or disables bit stuffing on data[7:0]
589 when bit-stuffing is enabled. */
590 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
591 '1': During data transmission the receive is
593 '0': During data transmission the receive is
595 Must be '0' for normal operation. */
596 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
597 '1' The PHY's analog_test pin is enabled for the
598 input and output of applicable analog test signals.
599 '0' THe analog_test pin is disabled. */
600 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
601 Used to activate BIST in the PHY. */
602 uint64_t tdata_sel : 1; /**< Test Data Out Select.
603 '1' test_data_out[3:0] (PHY) register contents
604 are output. '0' internaly generated signals are
606 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
607 Specifies the register address for writing to or
608 reading from the PHY test interface register. */
609 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
610 This is a test bus. Data is present on [3:0],
611 and its corresponding select (enable) is present
613 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
614 This is a test signal. When the USB Core is
615 powered up (not in Susned Mode), an automatic
616 tester can use this to disable phy_clock and
617 free_clk, then re-eanable them with an aligned
619 '1': The phy_clk and free_clk outputs are
620 disabled. "0": The phy_clock and free_clk outputs
621 are available within a specific period after the
624 struct cvmx_usbnx_usbp_ctl_status_cn52xx
626 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
627 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
628 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
629 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
630 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
631 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
632 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
633 uint64_t otgdisable : 1; /**< OTG Block Disable */
634 uint64_t portreset : 1; /**< Per_Port Reset */
635 uint64_t drvvbus : 1; /**< Drive VBUS */
636 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
637 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
638 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
639 uint64_t bist_done : 1; /**< PHY Bist Done.
640 Asserted at the end of the PHY BIST sequence. */
641 uint64_t bist_err : 1; /**< PHY Bist Error.
642 Indicates an internal error was detected during
643 the BIST sequence. */
644 uint64_t tdata_out : 4; /**< PHY Test Data Out.
645 Presents either internaly generated signals or
646 test register contents, based upon the value of
647 test_data_out_sel. */
648 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
649 Normally should be set to zero.
650 When customers have no intent to use USB PHY
651 interface, they should:
652 - still provide 3.3V to USB_VDD33, and
653 - tie USB_REXT to 3.3V supply, and
654 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
655 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
656 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
657 with byte-counts between packets. When set to 0
658 the L2C DMA address is incremented to the next
659 4-byte aligned address after adding byte-count. */
660 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
661 set to '0' for operation. */
662 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
663 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
664 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
665 This signal enables the pull-down resistance on
666 the D+ line. '1' pull down-resistance is connected
667 to D+/ '0' pull down resistance is not connected
668 to D+. When an A/B device is acting as a host
669 (downstream-facing port), dp_pulldown and
670 dm_pulldown are enabled. This must not toggle
671 during normal opeartion. */
672 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
673 This signal enables the pull-down resistance on
674 the D- line. '1' pull down-resistance is connected
675 to D-. '0' pull down resistance is not connected
676 to D-. When an A/B device is acting as a host
677 (downstream-facing port), dp_pulldown and
678 dm_pulldown are enabled. This must not toggle
679 during normal opeartion. */
680 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
681 USB is acting as device. This field needs to be
682 set while the USB is in reset. */
683 uint64_t reserved_19_22 : 4;
684 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
685 Enables or disables bit stuffing on data[15:8]
686 when bit-stuffing is enabled. */
687 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
688 Enables or disables bit stuffing on data[7:0]
689 when bit-stuffing is enabled. */
690 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
691 '1': During data transmission the receive is
693 '0': During data transmission the receive is
695 Must be '0' for normal operation. */
696 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
697 '1' The PHY's analog_test pin is enabled for the
698 input and output of applicable analog test signals.
699 '0' THe analog_test pin is disabled. */
700 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
701 Used to activate BIST in the PHY. */
702 uint64_t tdata_sel : 1; /**< Test Data Out Select.
703 '1' test_data_out[3:0] (PHY) register contents
704 are output. '0' internaly generated signals are
706 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
707 Specifies the register address for writing to or
708 reading from the PHY test interface register. */
709 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
710 This is a test bus. Data is present on [3:0],
711 and its corresponding select (enable) is present
713 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
714 This is a test signal. When the USB Core is
715 powered up (not in Susned Mode), an automatic
716 tester can use this to disable phy_clock and
717 free_clk, then re-eanable them with an aligned
719 '1': The phy_clk and free_clk outputs are
720 disabled. "0": The phy_clock and free_clk outputs
721 are available within a specific period after the
725 typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;
projects / linux-imx.git / blob