drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         /**
  75          * find_pll() - Find the best values for the PLL
  76          * @limit: limits for the PLL
  77          * @crtc: current CRTC
  78          * @target: target frequency in kHz
  79          * @refclk: reference clock frequency in kHz
  80          * @match_clock: if provided, @best_clock P divider must
  81          *               match the P divider from @match_clock
  82          *               used for LVDS downclocking
  83          * @best_clock: best PLL values found
  84          *
  85          * Returns true on success, false on failure.
  86          */
  87         bool (*find_pll)(const intel_limit_t *limit,
  88                          struct drm_crtc *crtc,
  89                          int target, int refclk,
  90                          intel_clock_t *match_clock,
  91                          intel_clock_t *best_clock);
  92 };
  93
  94 /* FDI */
  95 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  96
  97 int
  98 intel_pch_rawclk(struct drm_device *dev)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         WARN_ON(!HAS_PCH_SPLIT(dev));
 103
 104         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 105 }
 106
 107 static bool
 108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 109                     int target, int refclk, intel_clock_t *match_clock,
 110                     intel_clock_t *best_clock);
 111 static bool
 112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static bool
 117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 118                       int target, int refclk, intel_clock_t *match_clock,
 119                       intel_clock_t *best_clock);
 120 static bool
 121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 122                            int target, int refclk, intel_clock_t *match_clock,
 123                            intel_clock_t *best_clock);
 124
 125 static bool
 126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 127                         int target, int refclk, intel_clock_t *match_clock,
 128                         intel_clock_t *best_clock);
 129
 130 static inline u32 /* units of 100MHz */
 131 intel_fdi_link_freq(struct drm_device *dev)
 132 {
 133         if (IS_GEN5(dev)) {
 134                 struct drm_i915_private *dev_priv = dev->dev_private;
 135                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 136         } else
 137                 return 27;
 138 }
 139
 140 static const intel_limit_t intel_limits_i8xx_dvo = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 2, .max = 33 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 4, .p2_fast = 2 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i8xx_lvds = {
 155         .dot = { .min = 25000, .max = 350000 },
 156         .vco = { .min = 930000, .max = 1400000 },
 157         .n = { .min = 3, .max = 16 },
 158         .m = { .min = 96, .max = 140 },
 159         .m1 = { .min = 18, .max = 26 },
 160         .m2 = { .min = 6, .max = 16 },
 161         .p = { .min = 4, .max = 128 },
 162         .p1 = { .min = 1, .max = 6 },
 163         .p2 = { .dot_limit = 165000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_sdvo = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 8, .max = 18 },
 174         .m2 = { .min = 3, .max = 7 },
 175         .p = { .min = 5, .max = 80 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 200000,
 178                 .p2_slow = 10, .p2_fast = 5 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_lvds = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 7, .max = 98 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 112000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193         .find_pll = intel_find_best_PLL,
 194 };
 195
 196
 197 static const intel_limit_t intel_limits_g4x_sdvo = {
 198         .dot = { .min = 25000, .max = 270000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 17, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 10, .max = 30 },
 205         .p1 = { .min = 1, .max = 3},
 206         .p2 = { .dot_limit = 270000,
 207                 .p2_slow = 10,
 208                 .p2_fast = 10
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_hdmi = {
 214         .dot = { .min = 22000, .max = 400000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 16, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 5, .max = 80 },
 221         .p1 = { .min = 1, .max = 8},
 222         .p2 = { .dot_limit = 165000,
 223                 .p2_slow = 10, .p2_fast = 5 },
 224         .find_pll = intel_g4x_find_best_PLL,
 225 };
 226
 227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 228         .dot = { .min = 20000, .max = 115000 },
 229         .vco = { .min = 1750000, .max = 3500000 },
 230         .n = { .min = 1, .max = 3 },
 231         .m = { .min = 104, .max = 138 },
 232         .m1 = { .min = 17, .max = 23 },
 233         .m2 = { .min = 5, .max = 11 },
 234         .p = { .min = 28, .max = 112 },
 235         .p1 = { .min = 2, .max = 8 },
 236         .p2 = { .dot_limit = 0,
 237                 .p2_slow = 14, .p2_fast = 14
 238         },
 239         .find_pll = intel_g4x_find_best_PLL,
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 243         .dot = { .min = 80000, .max = 224000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 14, .max = 42 },
 250         .p1 = { .min = 2, .max = 6 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 7, .p2_fast = 7
 253         },
 254         .find_pll = intel_g4x_find_best_PLL,
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_display_port = {
 258         .dot = { .min = 161670, .max = 227000 },
 259         .vco = { .min = 1750000, .max = 3500000},
 260         .n = { .min = 1, .max = 2 },
 261         .m = { .min = 97, .max = 108 },
 262         .m1 = { .min = 0x10, .max = 0x12 },
 263         .m2 = { .min = 0x05, .max = 0x06 },
 264         .p = { .min = 10, .max = 20 },
 265         .p1 = { .min = 1, .max = 2},
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 10, .p2_fast = 10 },
 268         .find_pll = intel_find_pll_g4x_dp,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_find_best_PLL,
 299 };
 300
 301 /* Ironlake / Sandybridge
 302  *
 303  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 304  * the range value for them is (actual_value - 2).
 305  */
 306 static const intel_limit_t intel_limits_ironlake_dac = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 5 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 5, .max = 80 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 10, .p2_fast = 5 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 118 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 127 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 56 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 /* LVDS 100mhz refclk limits. */
 349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 28, .max = 112 },
 357         .p1 = { .min = 2, .max = 8 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 14, .p2_fast = 14 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_ironlake_display_port = {
 378         .dot = { .min = 25000, .max = 350000 },
 379         .vco = { .min = 1760000, .max = 3510000},
 380         .n = { .min = 1, .max = 2 },
 381         .m = { .min = 81, .max = 90 },
 382         .m1 = { .min = 12, .max = 22 },
 383         .m2 = { .min = 5, .max = 9 },
 384         .p = { .min = 10, .max = 20 },
 385         .p1 = { .min = 1, .max = 2},
 386         .p2 = { .dot_limit = 0,
 387                 .p2_slow = 10, .p2_fast = 10 },
 388         .find_pll = intel_find_pll_ironlake_dp,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_dac = {
 392         .dot = { .min = 25000, .max = 270000 },
 393         .vco = { .min = 4000000, .max = 6000000 },
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 22, .max = 450 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 1, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_hdmi = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 60, .max = 300 }, /* guess */
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 static const intel_limit_t intel_limits_vlv_dp = {
 420         .dot = { .min = 25000, .max = 270000 },
 421         .vco = { .min = 4000000, .max = 6000000 },
 422         .n = { .min = 1, .max = 7 },
 423         .m = { .min = 22, .max = 450 },
 424         .m1 = { .min = 2, .max = 3 },
 425         .m2 = { .min = 11, .max = 156 },
 426         .p = { .min = 10, .max = 30 },
 427         .p1 = { .min = 1, .max = 3 },
 428         .p2 = { .dot_limit = 270000,
 429                 .p2_slow = 2, .p2_fast = 20 },
 430         .find_pll = intel_vlv_find_best_pll,
 431 };
 432
 433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 436
 437         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 438                 DRM_ERROR("DPIO idle wait timed out\n");
 439                 return 0;
 440         }
 441
 442         I915_WRITE(DPIO_REG, reg);
 443         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 444                    DPIO_BYTE);
 445         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 446                 DRM_ERROR("DPIO read wait timed out\n");
 447                 return 0;
 448         }
 449
 450         return I915_READ(DPIO_DATA);
 451 }
 452
 453 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 454 {
 455         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 456
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 458                 DRM_ERROR("DPIO idle wait timed out\n");
 459                 return;
 460         }
 461
 462         I915_WRITE(DPIO_DATA, val);
 463         I915_WRITE(DPIO_REG, reg);
 464         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 465                    DPIO_BYTE);
 466         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 467                 DRM_ERROR("DPIO write wait timed out\n");
 468 }
 469
 470 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 471                                                 int refclk)
 472 {
 473         struct drm_device *dev = crtc->dev;
 474         const intel_limit_t *limit;
 475
 476         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 477                 if (intel_is_dual_link_lvds(dev)) {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_dual_lvds;
 482                 } else {
 483                         if (refclk == 100000)
 484                                 limit = &intel_limits_ironlake_single_lvds_100m;
 485                         else
 486                                 limit = &intel_limits_ironlake_single_lvds;
 487                 }
 488         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 489                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 490                 limit = &intel_limits_ironlake_display_port;
 491         else
 492                 limit = &intel_limits_ironlake_dac;
 493
 494         return limit;
 495 }
 496
 497 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 498 {
 499         struct drm_device *dev = crtc->dev;
 500         const intel_limit_t *limit;
 501
 502         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 503                 if (intel_is_dual_link_lvds(dev))
 504                         limit = &intel_limits_g4x_dual_channel_lvds;
 505                 else
 506                         limit = &intel_limits_g4x_single_channel_lvds;
 507         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 508                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 509                 limit = &intel_limits_g4x_hdmi;
 510         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 511                 limit = &intel_limits_g4x_sdvo;
 512         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 513                 limit = &intel_limits_g4x_display_port;
 514         } else /* The option is for other outputs */
 515                 limit = &intel_limits_i9xx_sdvo;
 516
 517         return limit;
 518 }
 519
 520 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 521 {
 522         struct drm_device *dev = crtc->dev;
 523         const intel_limit_t *limit;
 524
 525         if (HAS_PCH_SPLIT(dev))
 526                 limit = intel_ironlake_limit(crtc, refclk);
 527         else if (IS_G4X(dev)) {
 528                 limit = intel_g4x_limit(crtc);
 529         } else if (IS_PINEVIEW(dev)) {
 530                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 531                         limit = &intel_limits_pineview_lvds;
 532                 else
 533                         limit = &intel_limits_pineview_sdvo;
 534         } else if (IS_VALLEYVIEW(dev)) {
 535                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 536                         limit = &intel_limits_vlv_dac;
 537                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 538                         limit = &intel_limits_vlv_hdmi;
 539                 else
 540                         limit = &intel_limits_vlv_dp;
 541         } else if (!IS_GEN2(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i9xx_lvds;
 544                 else
 545                         limit = &intel_limits_i9xx_sdvo;
 546         } else {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 548                         limit = &intel_limits_i8xx_lvds;
 549                 else
 550                         limit = &intel_limits_i8xx_dvo;
 551         }
 552         return limit;
 553 }
 554
 555 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 556 static void pineview_clock(int refclk, intel_clock_t *clock)
 557 {
 558         clock->m = clock->m2 + 2;
 559         clock->p = clock->p1 * clock->p2;
 560         clock->vco = refclk * clock->m / clock->n;
 561         clock->dot = clock->vco / clock->p;
 562 }
 563
 564 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 565 {
 566         if (IS_PINEVIEW(dev)) {
 567                 pineview_clock(refclk, clock);
 568                 return;
 569         }
 570         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 571         clock->p = clock->p1 * clock->p2;
 572         clock->vco = refclk * clock->m / (clock->n + 2);
 573         clock->dot = clock->vco / clock->p;
 574 }
 575
 576 /**
 577  * Returns whether any output on the specified pipe is of the specified type
 578  */
 579 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct intel_encoder *encoder;
 583
 584         for_each_encoder_on_crtc(dev, crtc, encoder)
 585                 if (encoder->type == type)
 586                         return true;
 587
 588         return false;
 589 }
 590
 591 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 592 /**
 593  * Returns whether the given set of divisors are valid for a given refclk with
 594  * the given connectors.
 595  */
 596
 597 static bool intel_PLL_is_valid(struct drm_device *dev,
 598                                const intel_limit_t *limit,
 599                                const intel_clock_t *clock)
 600 {
 601         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 602                 INTELPllInvalid("p1 out of range\n");
 603         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 604                 INTELPllInvalid("p out of range\n");
 605         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 606                 INTELPllInvalid("m2 out of range\n");
 607         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 608                 INTELPllInvalid("m1 out of range\n");
 609         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 610                 INTELPllInvalid("m1 <= m2\n");
 611         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 612                 INTELPllInvalid("m out of range\n");
 613         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 614                 INTELPllInvalid("n out of range\n");
 615         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 616                 INTELPllInvalid("vco out of range\n");
 617         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 618          * connector, etc., rather than just a single range.
 619          */
 620         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 621                 INTELPllInvalid("dot out of range\n");
 622
 623         return true;
 624 }
 625
 626 static bool
 627 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 628                     int target, int refclk, intel_clock_t *match_clock,
 629                     intel_clock_t *best_clock)
 630
 631 {
 632         struct drm_device *dev = crtc->dev;
 633         intel_clock_t clock;
 634         int err = target;
 635
 636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 637                 /*
 638                  * For LVDS just rely on its current settings for dual-channel.
 639                  * We haven't figured out how to reliably set up different
 640                  * single/dual channel state, if we even can.
 641                  */
 642                 if (intel_is_dual_link_lvds(dev))
 643                         clock.p2 = limit->p2.p2_fast;
 644                 else
 645                         clock.p2 = limit->p2.p2_slow;
 646         } else {
 647                 if (target < limit->p2.dot_limit)
 648                         clock.p2 = limit->p2.p2_slow;
 649                 else
 650                         clock.p2 = limit->p2.p2_fast;
 651         }
 652
 653         memset(best_clock, 0, sizeof(*best_clock));
 654
 655         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 656              clock.m1++) {
 657                 for (clock.m2 = limit->m2.min;
 658                      clock.m2 <= limit->m2.max; clock.m2++) {
 659                         /* m1 is always 0 in Pineview */
 660                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 661                                 break;
 662                         for (clock.n = limit->n.min;
 663                              clock.n <= limit->n.max; clock.n++) {
 664                                 for (clock.p1 = limit->p1.min;
 665                                         clock.p1 <= limit->p1.max; clock.p1++) {
 666                                         int this_err;
 667
 668                                         intel_clock(dev, refclk, &clock);
 669                                         if (!intel_PLL_is_valid(dev, limit,
 670                                                                 &clock))
 671                                                 continue;
 672                                         if (match_clock &&
 673                                             clock.p != match_clock->p)
 674                                                 continue;
 675
 676                                         this_err = abs(clock.dot - target);
 677                                         if (this_err < err) {
 678                                                 *best_clock = clock;
 679                                                 err = this_err;
 680                                         }
 681                                 }
 682                         }
 683                 }
 684         }
 685
 686         return (err != target);
 687 }
 688
 689 static bool
 690 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 691                         int target, int refclk, intel_clock_t *match_clock,
 692                         intel_clock_t *best_clock)
 693 {
 694         struct drm_device *dev = crtc->dev;
 695         intel_clock_t clock;
 696         int max_n;
 697         bool found;
 698         /* approximately equals target * 0.00585 */
 699         int err_most = (target >> 8) + (target >> 9);
 700         found = false;
 701
 702         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 703                 int lvds_reg;
 704
 705                 if (HAS_PCH_SPLIT(dev))
 706                         lvds_reg = PCH_LVDS;
 707                 else
 708                         lvds_reg = LVDS;
 709                 if (intel_is_dual_link_lvds(dev))
 710                         clock.p2 = limit->p2.p2_fast;
 711                 else
 712                         clock.p2 = limit->p2.p2_slow;
 713         } else {
 714                 if (target < limit->p2.dot_limit)
 715                         clock.p2 = limit->p2.p2_slow;
 716                 else
 717                         clock.p2 = limit->p2.p2_fast;
 718         }
 719
 720         memset(best_clock, 0, sizeof(*best_clock));
 721         max_n = limit->n.max;
 722         /* based on hardware requirement, prefer smaller n to precision */
 723         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 724                 /* based on hardware requirement, prefere larger m1,m2 */
 725                 for (clock.m1 = limit->m1.max;
 726                      clock.m1 >= limit->m1.min; clock.m1--) {
 727                         for (clock.m2 = limit->m2.max;
 728                              clock.m2 >= limit->m2.min; clock.m2--) {
 729                                 for (clock.p1 = limit->p1.max;
 730                                      clock.p1 >= limit->p1.min; clock.p1--) {
 731                                         int this_err;
 732
 733                                         intel_clock(dev, refclk, &clock);
 734                                         if (!intel_PLL_is_valid(dev, limit,
 735                                                                 &clock))
 736                                                 continue;
 737                                         if (match_clock &&
 738                                             clock.p != match_clock->p)
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 757                            int target, int refclk, intel_clock_t *match_clock,
 758                            intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->dev;
 761         intel_clock_t clock;
 762
 763         if (target < 200000) {
 764                 clock.n = 1;
 765                 clock.p1 = 2;
 766                 clock.p2 = 10;
 767                 clock.m1 = 12;
 768                 clock.m2 = 9;
 769         } else {
 770                 clock.n = 2;
 771                 clock.p1 = 1;
 772                 clock.p2 = 10;
 773                 clock.m1 = 14;
 774                 clock.m2 = 8;
 775         }
 776         intel_clock(dev, refclk, &clock);
 777         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 778         return true;
 779 }
 780
 781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 782 static bool
 783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 784                       int target, int refclk, intel_clock_t *match_clock,
 785                       intel_clock_t *best_clock)
 786 {
 787         intel_clock_t clock;
 788         if (target < 200000) {
 789                 clock.p1 = 2;
 790                 clock.p2 = 10;
 791                 clock.n = 2;
 792                 clock.m1 = 23;
 793                 clock.m2 = 8;
 794         } else {
 795                 clock.p1 = 1;
 796                 clock.p2 = 10;
 797                 clock.n = 1;
 798                 clock.m1 = 14;
 799                 clock.m2 = 2;
 800         }
 801         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 802         clock.p = (clock.p1 * clock.p2);
 803         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 804         clock.vco = 0;
 805         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 806         return true;
 807 }
 808 static bool
 809 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                         int target, int refclk, intel_clock_t *match_clock,
 811                         intel_clock_t *best_clock)
 812 {
 813         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 814         u32 m, n, fastclk;
 815         u32 updrate, minupdate, fracbits, p;
 816         unsigned long bestppm, ppm, absppm;
 817         int dotclk, flag;
 818
 819         flag = 0;
 820         dotclk = target * 1000;
 821         bestppm = 1000000;
 822         ppm = absppm = 0;
 823         fastclk = dotclk / (2*100);
 824         updrate = 0;
 825         minupdate = 19200;
 826         fracbits = 1;
 827         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 828         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 829
 830         /* based on hardware requirement, prefer smaller n to precision */
 831         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 832                 updrate = refclk / n;
 833                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 834                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 835                                 if (p2 > 10)
 836                                         p2 = p2 - 1;
 837                                 p = p1 * p2;
 838                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 839                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 840                                         m2 = (((2*(fastclk * p * n / m1 )) +
 841                                                refclk) / (2*refclk));
 842                                         m = m1 * m2;
 843                                         vco = updrate * m;
 844                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 845                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 846                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 847                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 848                                                         bestppm = 0;
 849                                                         flag = 1;
 850                                                 }
 851                                                 if (absppm < bestppm - 10) {
 852                                                         bestppm = absppm;
 853                                                         flag = 1;
 854                                                 }
 855                                                 if (flag) {
 856                                                         bestn = n;
 857                                                         bestm1 = m1;
 858                                                         bestm2 = m2;
 859                                                         bestp1 = p1;
 860                                                         bestp2 = p2;
 861                                                         flag = 0;
 862                                                 }
 863                                         }
 864                                 }
 865                         }
 866                 }
 867         }
 868         best_clock->n = bestn;
 869         best_clock->m1 = bestm1;
 870         best_clock->m2 = bestm2;
 871         best_clock->p1 = bestp1;
 872         best_clock->p2 = bestp2;
 873
 874         return true;
 875 }
 876
 877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 878                                              enum pipe pipe)
 879 {
 880         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 882
 883         return intel_crtc->config.cpu_transcoder;
 884 }
 885
 886 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 887 {
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889         u32 frame, frame_reg = PIPEFRAME(pipe);
 890
 891         frame = I915_READ(frame_reg);
 892
 893         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 894                 DRM_DEBUG_KMS("vblank wait timed out\n");
 895 }
 896
 897 /**
 898  * intel_wait_for_vblank - wait for vblank on a given pipe
 899  * @dev: drm device
 900  * @pipe: pipe to wait for
 901  *
 902  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 903  * mode setting code.
 904  */
 905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         int pipestat_reg = PIPESTAT(pipe);
 909
 910         if (INTEL_INFO(dev)->gen >= 5) {
 911                 ironlake_wait_for_vblank(dev, pipe);
 912                 return;
 913         }
 914
 915         /* Clear existing vblank status. Note this will clear any other
 916          * sticky status fields as well.
 917          *
 918          * This races with i915_driver_irq_handler() with the result
 919          * that either function could miss a vblank event.  Here it is not
 920          * fatal, as we will either wait upon the next vblank interrupt or
 921          * timeout.  Generally speaking intel_wait_for_vblank() is only
 922          * called during modeset at which time the GPU should be idle and
 923          * should *not* be performing page flips and thus not waiting on
 924          * vblanks...
 925          * Currently, the result of us stealing a vblank from the irq
 926          * handler is that a single frame will be skipped during swapbuffers.
 927          */
 928         I915_WRITE(pipestat_reg,
 929                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 930
 931         /* Wait for vblank interrupt bit to set */
 932         if (wait_for(I915_READ(pipestat_reg) &
 933                      PIPE_VBLANK_INTERRUPT_STATUS,
 934                      50))
 935                 DRM_DEBUG_KMS("vblank wait timed out\n");
 936 }
 937
 938 /*
 939  * intel_wait_for_pipe_off - wait for pipe to turn off
 940  * @dev: drm device
 941  * @pipe: pipe to wait for
 942  *
 943  * After disabling a pipe, we can't wait for vblank in the usual way,
 944  * spinning on the vblank interrupt status bit, since we won't actually
 945  * see an interrupt when the pipe is disabled.
 946  *
 947  * On Gen4 and above:
 948  *   wait for the pipe register state bit to turn off
 949  *
 950  * Otherwise:
 951  *   wait for the display line value to settle (it usually
 952  *   ends up stopping at the start of the next frame).
 953  *
 954  */
 955 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 956 {
 957         struct drm_i915_private *dev_priv = dev->dev_private;
 958         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 959                                                                       pipe);
 960
 961         if (INTEL_INFO(dev)->gen >= 4) {
 962                 int reg = PIPECONF(cpu_transcoder);
 963
 964                 /* Wait for the Pipe State to go off */
 965                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 966                              100))
 967                         WARN(1, "pipe_off wait timed out\n");
 968         } else {
 969                 u32 last_line, line_mask;
 970                 int reg = PIPEDSL(pipe);
 971                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 972
 973                 if (IS_GEN2(dev))
 974                         line_mask = DSL_LINEMASK_GEN2;
 975                 else
 976                         line_mask = DSL_LINEMASK_GEN3;
 977
 978                 /* Wait for the display line to settle */
 979                 do {
 980                         last_line = I915_READ(reg) & line_mask;
 981                         mdelay(5);
 982                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 983                          time_after(timeout, jiffies));
 984                 if (time_after(jiffies, timeout))
 985                         WARN(1, "pipe_off wait timed out\n");
 986         }
 987 }
 988
 989 /*
 990  * ibx_digital_port_connected - is the specified port connected?
 991  * @dev_priv: i915 private structure
 992  * @port: the port to test
 993  *
 994  * Returns true if @port is connected, false otherwise.
 995  */
 996 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 997                                 struct intel_digital_port *port)
 998 {
 999         u32 bit;
1000
1001         if (HAS_PCH_IBX(dev_priv->dev)) {
1002                 switch(port->port) {
1003                 case PORT_B:
1004                         bit = SDE_PORTB_HOTPLUG;
1005                         break;
1006                 case PORT_C:
1007                         bit = SDE_PORTC_HOTPLUG;
1008                         break;
1009                 case PORT_D:
1010                         bit = SDE_PORTD_HOTPLUG;
1011                         break;
1012                 default:
1013                         return true;
1014                 }
1015         } else {
1016                 switch(port->port) {
1017                 case PORT_B:
1018                         bit = SDE_PORTB_HOTPLUG_CPT;
1019                         break;
1020                 case PORT_C:
1021                         bit = SDE_PORTC_HOTPLUG_CPT;
1022                         break;
1023                 case PORT_D:
1024                         bit = SDE_PORTD_HOTPLUG_CPT;
1025                         break;
1026                 default:
1027                         return true;
1028                 }
1029         }
1030
1031         return I915_READ(SDEISR) & bit;
1032 }
1033
1034 static const char *state_string(bool enabled)
1035 {
1036         return enabled ? "on" : "off";
1037 }
1038
1039 /* Only for pre-ILK configs */
1040 static void assert_pll(struct drm_i915_private *dev_priv,
1041                        enum pipe pipe, bool state)
1042 {
1043         int reg;
1044         u32 val;
1045         bool cur_state;
1046
1047         reg = DPLL(pipe);
1048         val = I915_READ(reg);
1049         cur_state = !!(val & DPLL_VCO_ENABLE);
1050         WARN(cur_state != state,
1051              "PLL state assertion failure (expected %s, current %s)\n",
1052              state_string(state), state_string(cur_state));
1053 }
1054 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1055 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1056
1057 /* For ILK+ */
1058 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1059                            struct intel_pch_pll *pll,
1060                            struct intel_crtc *crtc,
1061                            bool state)
1062 {
1063         u32 val;
1064         bool cur_state;
1065
1066         if (HAS_PCH_LPT(dev_priv->dev)) {
1067                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1068                 return;
1069         }
1070
1071         if (WARN (!pll,
1072                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1073                 return;
1074
1075         val = I915_READ(pll->pll_reg);
1076         cur_state = !!(val & DPLL_VCO_ENABLE);
1077         WARN(cur_state != state,
1078              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1079              pll->pll_reg, state_string(state), state_string(cur_state), val);
1080
1081         /* Make sure the selected PLL is correctly attached to the transcoder */
1082         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1083                 u32 pch_dpll;
1084
1085                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1086                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1087                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1088                           "PLL[%d] not attached to this transcoder %c: %08x\n",
1089                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
1090                         cur_state = !!(val >> (4*crtc->pipe + 3));
1091                         WARN(cur_state != state,
1092                              "PLL[%d] not %s on this transcoder %c: %08x\n",
1093                              pll->pll_reg == _PCH_DPLL_B,
1094                              state_string(state),
1095                              pipe_name(crtc->pipe),
1096                              val);
1097                 }
1098         }
1099 }
1100 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1101 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1102
1103 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1104                           enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         if (HAS_DDI(dev_priv->dev)) {
1113                 /* DDI does not have a specific FDI_TX register */
1114                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1115                 val = I915_READ(reg);
1116                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1117         } else {
1118                 reg = FDI_TX_CTL(pipe);
1119                 val = I915_READ(reg);
1120                 cur_state = !!(val & FDI_TX_ENABLE);
1121         }
1122         WARN(cur_state != state,
1123              "FDI TX state assertion failure (expected %s, current %s)\n",
1124              state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128
1129 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1130                           enum pipe pipe, bool state)
1131 {
1132         int reg;
1133         u32 val;
1134         bool cur_state;
1135
1136         reg = FDI_RX_CTL(pipe);
1137         val = I915_READ(reg);
1138         cur_state = !!(val & FDI_RX_ENABLE);
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (HAS_DDI(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         reg = FDI_RX_CTL(pipe);
1172         val = I915_READ(reg);
1173         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1174 }
1175
1176 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1177                                   enum pipe pipe)
1178 {
1179         int pp_reg, lvds_reg;
1180         u32 val;
1181         enum pipe panel_pipe = PIPE_A;
1182         bool locked = true;
1183
1184         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1185                 pp_reg = PCH_PP_CONTROL;
1186                 lvds_reg = PCH_LVDS;
1187         } else {
1188                 pp_reg = PP_CONTROL;
1189                 lvds_reg = LVDS;
1190         }
1191
1192         val = I915_READ(pp_reg);
1193         if (!(val & PANEL_POWER_ON) ||
1194             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1195                 locked = false;
1196
1197         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1198                 panel_pipe = PIPE_B;
1199
1200         WARN(panel_pipe == pipe && locked,
1201              "panel assertion failure, pipe %c regs locked\n",
1202              pipe_name(pipe));
1203 }
1204
1205 void assert_pipe(struct drm_i915_private *dev_priv,
1206                  enum pipe pipe, bool state)
1207 {
1208         int reg;
1209         u32 val;
1210         bool cur_state;
1211         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1212                                                                       pipe);
1213
1214         /* if we need the pipe A quirk it must be always on */
1215         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1216                 state = true;
1217
1218         if (!intel_using_power_well(dev_priv->dev) &&
1219             cpu_transcoder != TRANSCODER_EDP) {
1220                 cur_state = false;
1221         } else {
1222                 reg = PIPECONF(cpu_transcoder);
1223                 val = I915_READ(reg);
1224                 cur_state = !!(val & PIPECONF_ENABLE);
1225         }
1226
1227         WARN(cur_state != state,
1228              "pipe %c assertion failure (expected %s, current %s)\n",
1229              pipe_name(pipe), state_string(state), state_string(cur_state));
1230 }
1231
1232 static void assert_plane(struct drm_i915_private *dev_priv,
1233                          enum plane plane, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238
1239         reg = DSPCNTR(plane);
1240         val = I915_READ(reg);
1241         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1242         WARN(cur_state != state,
1243              "plane %c assertion failure (expected %s, current %s)\n",
1244              plane_name(plane), state_string(state), state_string(cur_state));
1245 }
1246
1247 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1248 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1249
1250 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1251                                    enum pipe pipe)
1252 {
1253         int reg, i;
1254         u32 val;
1255         int cur_pipe;
1256
1257         /* Planes are fixed to pipes on ILK+ */
1258         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1259                 reg = DSPCNTR(pipe);
1260                 val = I915_READ(reg);
1261                 WARN((val & DISPLAY_PLANE_ENABLE),
1262                      "plane %c assertion failure, should be disabled but not\n",
1263                      plane_name(pipe));
1264                 return;
1265         }
1266
1267         /* Need to check both planes against the pipe */
1268         for (i = 0; i < 2; i++) {
1269                 reg = DSPCNTR(i);
1270                 val = I915_READ(reg);
1271                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1272                         DISPPLANE_SEL_PIPE_SHIFT;
1273                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1274                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1275                      plane_name(i), pipe_name(pipe));
1276         }
1277 }
1278
1279 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1280                                     enum pipe pipe)
1281 {
1282         int reg, i;
1283         u32 val;
1284
1285         if (!IS_VALLEYVIEW(dev_priv->dev))
1286                 return;
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < dev_priv->num_plane; i++) {
1290                 reg = SPCNTR(pipe, i);
1291                 val = I915_READ(reg);
1292                 WARN((val & SP_ENABLE),
1293                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294                      sprite_name(pipe, i), pipe_name(pipe));
1295         }
1296 }
1297
1298 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1299 {
1300         u32 val;
1301         bool enabled;
1302
1303         if (HAS_PCH_LPT(dev_priv->dev)) {
1304                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1305                 return;
1306         }
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                        enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else {
1341                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1342                         return false;
1343         }
1344         return true;
1345 }
1346
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348                               enum pipe pipe, u32 val)
1349 {
1350         if ((val & SDVO_ENABLE) == 0)
1351                 return false;
1352
1353         if (HAS_PCH_CPT(dev_priv->dev)) {
1354                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1355                         return false;
1356         } else {
1357                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1358                         return false;
1359         }
1360         return true;
1361 }
1362
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364                               enum pipe pipe, u32 val)
1365 {
1366         if ((val & LVDS_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371                         return false;
1372         } else {
1373                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1374                         return false;
1375         }
1376         return true;
1377 }
1378
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380                               enum pipe pipe, u32 val)
1381 {
1382         if ((val & ADPA_DAC_ENABLE) == 0)
1383                 return false;
1384         if (HAS_PCH_CPT(dev_priv->dev)) {
1385                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395                                    enum pipe pipe, int reg, u32 port_sel)
1396 {
1397         u32 val = I915_READ(reg);
1398         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400              reg, pipe_name(pipe));
1401
1402         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403              && (val & DP_PIPEB_SELECT),
1404              "IBX PCH dp port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408                                      enum pipe pipe, int reg)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1416              && (val & SDVO_PIPE_B_SELECT),
1417              "IBX PCH hdmi port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1421                                       enum pipe pipe)
1422 {
1423         int reg;
1424         u32 val;
1425
1426         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1429
1430         reg = PCH_ADPA;
1431         val = I915_READ(reg);
1432         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433              "PCH VGA enabled on transcoder %c, should be disabled\n",
1434              pipe_name(pipe));
1435
1436         reg = PCH_LVDS;
1437         val = I915_READ(reg);
1438         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1443         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1444         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1445 }
1446
1447 /**
1448  * intel_enable_pll - enable a PLL
1449  * @dev_priv: i915 private structure
1450  * @pipe: pipe PLL to enable
1451  *
1452  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1453  * make sure the PLL reg is writable first though, since the panel write
1454  * protect mechanism may be enabled.
1455  *
1456  * Note!  This is for pre-ILK only.
1457  *
1458  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1459  */
1460 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1461 {
1462         int reg;
1463         u32 val;
1464
1465         assert_pipe_disabled(dev_priv, pipe);
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1521                 enum intel_sbi_destination destination)
1522 {
1523         u32 tmp;
1524
1525         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1526
1527         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1528                                 100)) {
1529                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1530                 return;
1531         }
1532
1533         I915_WRITE(SBI_ADDR, (reg << 16));
1534         I915_WRITE(SBI_DATA, value);
1535
1536         if (destination == SBI_ICLK)
1537                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1538         else
1539                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1540         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1541
1542         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1543                                 100)) {
1544                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1545                 return;
1546         }
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1551                enum intel_sbi_destination destination)
1552 {
1553         u32 value = 0;
1554         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1555
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 return 0;
1560         }
1561
1562         I915_WRITE(SBI_ADDR, (reg << 16));
1563
1564         if (destination == SBI_ICLK)
1565                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1566         else
1567                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1568         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1569
1570         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1571                                 100)) {
1572                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1573                 return 0;
1574         }
1575
1576         return I915_READ(SBI_DATA);
1577 }
1578
1579 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1580 {
1581         u32 port_mask;
1582
1583         if (!port)
1584                 port_mask = DPLL_PORTB_READY_MASK;
1585         else
1586                 port_mask = DPLL_PORTC_READY_MASK;
1587
1588         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1589                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1590                      'B' + port, I915_READ(DPLL(0)));
1591 }
1592
1593 /**
1594  * ironlake_enable_pch_pll - enable PCH PLL
1595  * @dev_priv: i915 private structure
1596  * @pipe: pipe PLL to enable
1597  *
1598  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1599  * drives the transcoder clock.
1600  */
1601 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1602 {
1603         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1604         struct intel_pch_pll *pll;
1605         int reg;
1606         u32 val;
1607
1608         /* PCH PLLs only available on ILK, SNB and IVB */
1609         BUG_ON(dev_priv->info->gen < 5);
1610         pll = intel_crtc->pch_pll;
1611         if (pll == NULL)
1612                 return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         /* PCH refclock must be enabled first */
1622         assert_pch_refclk_enabled(dev_priv);
1623
1624         if (pll->active++ && pll->on) {
1625                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1630
1631         reg = pll->pll_reg;
1632         val = I915_READ(reg);
1633         val |= DPLL_VCO_ENABLE;
1634         I915_WRITE(reg, val);
1635         POSTING_READ(reg);
1636         udelay(200);
1637
1638         pll->on = true;
1639 }
1640
1641 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1642 {
1643         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1644         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1645         int reg;
1646         u32 val;
1647
1648         /* PCH only available on ILK+ */
1649         BUG_ON(dev_priv->info->gen < 5);
1650         if (pll == NULL)
1651                return;
1652
1653         if (WARN_ON(pll->refcount == 0))
1654                 return;
1655
1656         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1657                       pll->pll_reg, pll->active, pll->on,
1658                       intel_crtc->base.base.id);
1659
1660         if (WARN_ON(pll->active == 0)) {
1661                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1662                 return;
1663         }
1664
1665         if (--pll->active) {
1666                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1667                 return;
1668         }
1669
1670         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1671
1672         /* Make sure transcoder isn't still depending on us */
1673         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1674
1675         reg = pll->pll_reg;
1676         val = I915_READ(reg);
1677         val &= ~DPLL_VCO_ENABLE;
1678         I915_WRITE(reg, val);
1679         POSTING_READ(reg);
1680         udelay(200);
1681
1682         pll->on = false;
1683 }
1684
1685 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1686                                            enum pipe pipe)
1687 {
1688         struct drm_device *dev = dev_priv->dev;
1689         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1690         uint32_t reg, val, pipeconf_val;
1691
1692         /* PCH only available on ILK+ */
1693         BUG_ON(dev_priv->info->gen < 5);
1694
1695         /* Make sure PCH DPLL is enabled */
1696         assert_pch_pll_enabled(dev_priv,
1697                                to_intel_crtc(crtc)->pch_pll,
1698                                to_intel_crtc(crtc));
1699
1700         /* FDI must be feeding us bits for PCH ports */
1701         assert_fdi_tx_enabled(dev_priv, pipe);
1702         assert_fdi_rx_enabled(dev_priv, pipe);
1703
1704         if (HAS_PCH_CPT(dev)) {
1705                 /* Workaround: Set the timing override bit before enabling the
1706                  * pch transcoder. */
1707                 reg = TRANS_CHICKEN2(pipe);
1708                 val = I915_READ(reg);
1709                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1710                 I915_WRITE(reg, val);
1711         }
1712
1713         reg = TRANSCONF(pipe);
1714         val = I915_READ(reg);
1715         pipeconf_val = I915_READ(PIPECONF(pipe));
1716
1717         if (HAS_PCH_IBX(dev_priv->dev)) {
1718                 /*
1719                  * make the BPC in transcoder be consistent with
1720                  * that in pipeconf reg.
1721                  */
1722                 val &= ~PIPECONF_BPC_MASK;
1723                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1724         }
1725
1726         val &= ~TRANS_INTERLACE_MASK;
1727         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1728                 if (HAS_PCH_IBX(dev_priv->dev) &&
1729                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1730                         val |= TRANS_LEGACY_INTERLACED_ILK;
1731                 else
1732                         val |= TRANS_INTERLACED;
1733         else
1734                 val |= TRANS_PROGRESSIVE;
1735
1736         I915_WRITE(reg, val | TRANS_ENABLE);
1737         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1738                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1739 }
1740
1741 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1742                                       enum transcoder cpu_transcoder)
1743 {
1744         u32 val, pipeconf_val;
1745
1746         /* PCH only available on ILK+ */
1747         BUG_ON(dev_priv->info->gen < 5);
1748
1749         /* FDI must be feeding us bits for PCH ports */
1750         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1751         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1752
1753         /* Workaround: set timing override bit. */
1754         val = I915_READ(_TRANSA_CHICKEN2);
1755         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1756         I915_WRITE(_TRANSA_CHICKEN2, val);
1757
1758         val = TRANS_ENABLE;
1759         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1760
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1762             PIPECONF_INTERLACED_ILK)
1763                 val |= TRANS_INTERLACED;
1764         else
1765                 val |= TRANS_PROGRESSIVE;
1766
1767         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1768         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1769                 DRM_ERROR("Failed to enable PCH transcoder\n");
1770 }
1771
1772 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1773                                             enum pipe pipe)
1774 {
1775         struct drm_device *dev = dev_priv->dev;
1776         uint32_t reg, val;
1777
1778         /* FDI relies on the transcoder */
1779         assert_fdi_tx_disabled(dev_priv, pipe);
1780         assert_fdi_rx_disabled(dev_priv, pipe);
1781
1782         /* Ports must be off as well */
1783         assert_pch_ports_disabled(dev_priv, pipe);
1784
1785         reg = TRANSCONF(pipe);
1786         val = I915_READ(reg);
1787         val &= ~TRANS_ENABLE;
1788         I915_WRITE(reg, val);
1789         /* wait for PCH transcoder off, transcoder state */
1790         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1791                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1792
1793         if (!HAS_PCH_IBX(dev)) {
1794                 /* Workaround: Clear the timing override chicken bit again. */
1795                 reg = TRANS_CHICKEN2(pipe);
1796                 val = I915_READ(reg);
1797                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1798                 I915_WRITE(reg, val);
1799         }
1800 }
1801
1802 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1803 {
1804         u32 val;
1805
1806         val = I915_READ(_TRANSACONF);
1807         val &= ~TRANS_ENABLE;
1808         I915_WRITE(_TRANSACONF, val);
1809         /* wait for PCH transcoder off, transcoder state */
1810         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1811                 DRM_ERROR("Failed to disable PCH transcoder\n");
1812
1813         /* Workaround: clear timing override bit. */
1814         val = I915_READ(_TRANSA_CHICKEN2);
1815         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1816         I915_WRITE(_TRANSA_CHICKEN2, val);
1817 }
1818
1819 /**
1820  * intel_enable_pipe - enable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to enable
1823  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1824  *
1825  * Enable @pipe, making sure that various hardware specific requirements
1826  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1827  *
1828  * @pipe should be %PIPE_A or %PIPE_B.
1829  *
1830  * Will wait until the pipe is actually running (i.e. first vblank) before
1831  * returning.
1832  */
1833 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1834                               bool pch_port)
1835 {
1836         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1837                                                                       pipe);
1838         enum pipe pch_transcoder;
1839         int reg;
1840         u32 val;
1841
1842         assert_planes_disabled(dev_priv, pipe);
1843         assert_sprites_disabled(dev_priv, pipe);
1844
1845         if (HAS_PCH_LPT(dev_priv->dev))
1846                 pch_transcoder = TRANSCODER_A;
1847         else
1848                 pch_transcoder = pipe;
1849
1850         /*
1851          * A pipe without a PLL won't actually be able to drive bits from
1852          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1853          * need the check.
1854          */
1855         if (!HAS_PCH_SPLIT(dev_priv->dev))
1856                 assert_pll_enabled(dev_priv, pipe);
1857         else {
1858                 if (pch_port) {
1859                         /* if driving the PCH, we need FDI enabled */
1860                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1861                         assert_fdi_tx_pll_enabled(dev_priv,
1862                                                   (enum pipe) cpu_transcoder);
1863                 }
1864                 /* FIXME: assert CPU port conditions for SNB+ */
1865         }
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if (val & PIPECONF_ENABLE)
1870                 return;
1871
1872         I915_WRITE(reg, val | PIPECONF_ENABLE);
1873         intel_wait_for_vblank(dev_priv->dev, pipe);
1874 }
1875
1876 /**
1877  * intel_disable_pipe - disable a pipe, asserting requirements
1878  * @dev_priv: i915 private structure
1879  * @pipe: pipe to disable
1880  *
1881  * Disable @pipe, making sure that various hardware specific requirements
1882  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1883  *
1884  * @pipe should be %PIPE_A or %PIPE_B.
1885  *
1886  * Will wait until the pipe has shut down before returning.
1887  */
1888 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1889                                enum pipe pipe)
1890 {
1891         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1892                                                                       pipe);
1893         int reg;
1894         u32 val;
1895
1896         /*
1897          * Make sure planes won't keep trying to pump pixels to us,
1898          * or we might hang the display.
1899          */
1900         assert_planes_disabled(dev_priv, pipe);
1901         assert_sprites_disabled(dev_priv, pipe);
1902
1903         /* Don't disable pipe A or pipe A PLLs if needed */
1904         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1905                 return;
1906
1907         reg = PIPECONF(cpu_transcoder);
1908         val = I915_READ(reg);
1909         if ((val & PIPECONF_ENABLE) == 0)
1910                 return;
1911
1912         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1913         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1914 }
1915
1916 /*
1917  * Plane regs are double buffered, going from enabled->disabled needs a
1918  * trigger in order to latch.  The display address reg provides this.
1919  */
1920 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1921                                       enum plane plane)
1922 {
1923         if (dev_priv->info->gen >= 4)
1924                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1925         else
1926                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1927 }
1928
1929 /**
1930  * intel_enable_plane - enable a display plane on a given pipe
1931  * @dev_priv: i915 private structure
1932  * @plane: plane to enable
1933  * @pipe: pipe being fed
1934  *
1935  * Enable @plane on @pipe, making sure that @pipe is running first.
1936  */
1937 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1938                                enum plane plane, enum pipe pipe)
1939 {
1940         int reg;
1941         u32 val;
1942
1943         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1944         assert_pipe_enabled(dev_priv, pipe);
1945
1946         reg = DSPCNTR(plane);
1947         val = I915_READ(reg);
1948         if (val & DISPLAY_PLANE_ENABLE)
1949                 return;
1950
1951         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1952         intel_flush_display_plane(dev_priv, plane);
1953         intel_wait_for_vblank(dev_priv->dev, pipe);
1954 }
1955
1956 /**
1957  * intel_disable_plane - disable a display plane
1958  * @dev_priv: i915 private structure
1959  * @plane: plane to disable
1960  * @pipe: pipe consuming the data
1961  *
1962  * Disable @plane; should be an independent operation.
1963  */
1964 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1965                                 enum plane plane, enum pipe pipe)
1966 {
1967         int reg;
1968         u32 val;
1969
1970         reg = DSPCNTR(plane);
1971         val = I915_READ(reg);
1972         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1973                 return;
1974
1975         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1976         intel_flush_display_plane(dev_priv, plane);
1977         intel_wait_for_vblank(dev_priv->dev, pipe);
1978 }
1979
1980 static bool need_vtd_wa(struct drm_device *dev)
1981 {
1982 #ifdef CONFIG_INTEL_IOMMU
1983         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1984                 return true;
1985 #endif
1986         return false;
1987 }
1988
1989 int
1990 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1991                            struct drm_i915_gem_object *obj,
1992                            struct intel_ring_buffer *pipelined)
1993 {
1994         struct drm_i915_private *dev_priv = dev->dev_private;
1995         u32 alignment;
1996         int ret;
1997
1998         switch (obj->tiling_mode) {
1999         case I915_TILING_NONE:
2000                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2001                         alignment = 128 * 1024;
2002                 else if (INTEL_INFO(dev)->gen >= 4)
2003                         alignment = 4 * 1024;
2004                 else
2005                         alignment = 64 * 1024;
2006                 break;
2007         case I915_TILING_X:
2008                 /* pin() will align the object as required by fence */
2009                 alignment = 0;
2010                 break;
2011         case I915_TILING_Y:
2012                 /* Despite that we check this in framebuffer_init userspace can
2013                  * screw us over and change the tiling after the fact. Only
2014                  * pinned buffers can't change their tiling. */
2015                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2016                 return -EINVAL;
2017         default:
2018                 BUG();
2019         }
2020
2021         /* Note that the w/a also requires 64 PTE of padding following the
2022          * bo. We currently fill all unused PTE with the shadow page and so
2023          * we should always have valid PTE following the scanout preventing
2024          * the VT-d warning.
2025          */
2026         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2027                 alignment = 256 * 1024;
2028
2029         dev_priv->mm.interruptible = false;
2030         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2031         if (ret)
2032                 goto err_interruptible;
2033
2034         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2035          * fence, whereas 965+ only requires a fence if using
2036          * framebuffer compression.  For simplicity, we always install
2037          * a fence as the cost is not that onerous.
2038          */
2039         ret = i915_gem_object_get_fence(obj);
2040         if (ret)
2041                 goto err_unpin;
2042
2043         i915_gem_object_pin_fence(obj);
2044
2045         dev_priv->mm.interruptible = true;
2046         return 0;
2047
2048 err_unpin:
2049         i915_gem_object_unpin(obj);
2050 err_interruptible:
2051         dev_priv->mm.interruptible = true;
2052         return ret;
2053 }
2054
2055 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2056 {
2057         i915_gem_object_unpin_fence(obj);
2058         i915_gem_object_unpin(obj);
2059 }
2060
2061 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2062  * is assumed to be a power-of-two. */
2063 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2064                                              unsigned int tiling_mode,
2065                                              unsigned int cpp,
2066                                              unsigned int pitch)
2067 {
2068         if (tiling_mode != I915_TILING_NONE) {
2069                 unsigned int tile_rows, tiles;
2070
2071                 tile_rows = *y / 8;
2072                 *y %= 8;
2073
2074                 tiles = *x / (512/cpp);
2075                 *x %= 512/cpp;
2076
2077                 return tile_rows * pitch * 8 + tiles * 4096;
2078         } else {
2079                 unsigned int offset;
2080
2081                 offset = *y * pitch + *x * cpp;
2082                 *y = 0;
2083                 *x = (offset & 4095) / cpp;
2084                 return offset & -4096;
2085         }
2086 }
2087
2088 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2089                              int x, int y)
2090 {
2091         struct drm_device *dev = crtc->dev;
2092         struct drm_i915_private *dev_priv = dev->dev_private;
2093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094         struct intel_framebuffer *intel_fb;
2095         struct drm_i915_gem_object *obj;
2096         int plane = intel_crtc->plane;
2097         unsigned long linear_offset;
2098         u32 dspcntr;
2099         u32 reg;
2100
2101         switch (plane) {
2102         case 0:
2103         case 1:
2104                 break;
2105         default:
2106                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2107                 return -EINVAL;
2108         }
2109
2110         intel_fb = to_intel_framebuffer(fb);
2111         obj = intel_fb->obj;
2112
2113         reg = DSPCNTR(plane);
2114         dspcntr = I915_READ(reg);
2115         /* Mask out pixel format bits in case we change it */
2116         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2117         switch (fb->pixel_format) {
2118         case DRM_FORMAT_C8:
2119                 dspcntr |= DISPPLANE_8BPP;
2120                 break;
2121         case DRM_FORMAT_XRGB1555:
2122         case DRM_FORMAT_ARGB1555:
2123                 dspcntr |= DISPPLANE_BGRX555;
2124                 break;
2125         case DRM_FORMAT_RGB565:
2126                 dspcntr |= DISPPLANE_BGRX565;
2127                 break;
2128         case DRM_FORMAT_XRGB8888:
2129         case DRM_FORMAT_ARGB8888:
2130                 dspcntr |= DISPPLANE_BGRX888;
2131                 break;
2132         case DRM_FORMAT_XBGR8888:
2133         case DRM_FORMAT_ABGR8888:
2134                 dspcntr |= DISPPLANE_RGBX888;
2135                 break;
2136         case DRM_FORMAT_XRGB2101010:
2137         case DRM_FORMAT_ARGB2101010:
2138                 dspcntr |= DISPPLANE_BGRX101010;
2139                 break;
2140         case DRM_FORMAT_XBGR2101010:
2141         case DRM_FORMAT_ABGR2101010:
2142                 dspcntr |= DISPPLANE_RGBX101010;
2143                 break;
2144         default:
2145                 BUG();
2146         }
2147
2148         if (INTEL_INFO(dev)->gen >= 4) {
2149                 if (obj->tiling_mode != I915_TILING_NONE)
2150                         dspcntr |= DISPPLANE_TILED;
2151                 else
2152                         dspcntr &= ~DISPPLANE_TILED;
2153         }
2154
2155         I915_WRITE(reg, dspcntr);
2156
2157         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2158
2159         if (INTEL_INFO(dev)->gen >= 4) {
2160                 intel_crtc->dspaddr_offset =
2161                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2162                                                        fb->bits_per_pixel / 8,
2163                                                        fb->pitches[0]);
2164                 linear_offset -= intel_crtc->dspaddr_offset;
2165         } else {
2166                 intel_crtc->dspaddr_offset = linear_offset;
2167         }
2168
2169         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2170                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2171         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2172         if (INTEL_INFO(dev)->gen >= 4) {
2173                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2174                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2175                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2176                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2177         } else
2178                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2179         POSTING_READ(reg);
2180
2181         return 0;
2182 }
2183
2184 static int ironlake_update_plane(struct drm_crtc *crtc,
2185                                  struct drm_framebuffer *fb, int x, int y)
2186 {
2187         struct drm_device *dev = crtc->dev;
2188         struct drm_i915_private *dev_priv = dev->dev_private;
2189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190         struct intel_framebuffer *intel_fb;
2191         struct drm_i915_gem_object *obj;
2192         int plane = intel_crtc->plane;
2193         unsigned long linear_offset;
2194         u32 dspcntr;
2195         u32 reg;
2196
2197         switch (plane) {
2198         case 0:
2199         case 1:
2200         case 2:
2201                 break;
2202         default:
2203                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2204                 return -EINVAL;
2205         }
2206
2207         intel_fb = to_intel_framebuffer(fb);
2208         obj = intel_fb->obj;
2209
2210         reg = DSPCNTR(plane);
2211         dspcntr = I915_READ(reg);
2212         /* Mask out pixel format bits in case we change it */
2213         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2214         switch (fb->pixel_format) {
2215         case DRM_FORMAT_C8:
2216                 dspcntr |= DISPPLANE_8BPP;
2217                 break;
2218         case DRM_FORMAT_RGB565:
2219                 dspcntr |= DISPPLANE_BGRX565;
2220                 break;
2221         case DRM_FORMAT_XRGB8888:
2222         case DRM_FORMAT_ARGB8888:
2223                 dspcntr |= DISPPLANE_BGRX888;
2224                 break;
2225         case DRM_FORMAT_XBGR8888:
2226         case DRM_FORMAT_ABGR8888:
2227                 dspcntr |= DISPPLANE_RGBX888;
2228                 break;
2229         case DRM_FORMAT_XRGB2101010:
2230         case DRM_FORMAT_ARGB2101010:
2231                 dspcntr |= DISPPLANE_BGRX101010;
2232                 break;
2233         case DRM_FORMAT_XBGR2101010:
2234         case DRM_FORMAT_ABGR2101010:
2235                 dspcntr |= DISPPLANE_RGBX101010;
2236                 break;
2237         default:
2238                 BUG();
2239         }
2240
2241         if (obj->tiling_mode != I915_TILING_NONE)
2242                 dspcntr |= DISPPLANE_TILED;
2243         else
2244                 dspcntr &= ~DISPPLANE_TILED;
2245
2246         /* must disable */
2247         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2248
2249         I915_WRITE(reg, dspcntr);
2250
2251         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2252         intel_crtc->dspaddr_offset =
2253                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2254                                                fb->bits_per_pixel / 8,
2255                                                fb->pitches[0]);
2256         linear_offset -= intel_crtc->dspaddr_offset;
2257
2258         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2259                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2260         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2261         I915_MODIFY_DISPBASE(DSPSURF(plane),
2262                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2263         if (IS_HASWELL(dev)) {
2264                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2265         } else {
2266                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2267                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2268         }
2269         POSTING_READ(reg);
2270
2271         return 0;
2272 }
2273
2274 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2275 static int
2276 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2277                            int x, int y, enum mode_set_atomic state)
2278 {
2279         struct drm_device *dev = crtc->dev;
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281
2282         if (dev_priv->display.disable_fbc)
2283                 dev_priv->display.disable_fbc(dev);
2284         intel_increase_pllclock(crtc);
2285
2286         return dev_priv->display.update_plane(crtc, fb, x, y);
2287 }
2288
2289 void intel_display_handle_reset(struct drm_device *dev)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         struct drm_crtc *crtc;
2293
2294         /*
2295          * Flips in the rings have been nuked by the reset,
2296          * so complete all pending flips so that user space
2297          * will get its events and not get stuck.
2298          *
2299          * Also update the base address of all primary
2300          * planes to the the last fb to make sure we're
2301          * showing the correct fb after a reset.
2302          *
2303          * Need to make two loops over the crtcs so that we
2304          * don't try to grab a crtc mutex before the
2305          * pending_flip_queue really got woken up.
2306          */
2307
2308         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2309                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2310                 enum plane plane = intel_crtc->plane;
2311
2312                 intel_prepare_page_flip(dev, plane);
2313                 intel_finish_page_flip_plane(dev, plane);
2314         }
2315
2316         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2317                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318
2319                 mutex_lock(&crtc->mutex);
2320                 if (intel_crtc->active)
2321                         dev_priv->display.update_plane(crtc, crtc->fb,
2322                                                        crtc->x, crtc->y);
2323                 mutex_unlock(&crtc->mutex);
2324         }
2325 }
2326
2327 static int
2328 intel_finish_fb(struct drm_framebuffer *old_fb)
2329 {
2330         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2331         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2332         bool was_interruptible = dev_priv->mm.interruptible;
2333         int ret;
2334
2335         /* Big Hammer, we also need to ensure that any pending
2336          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2337          * current scanout is retired before unpinning the old
2338          * framebuffer.
2339          *
2340          * This should only fail upon a hung GPU, in which case we
2341          * can safely continue.
2342          */
2343         dev_priv->mm.interruptible = false;
2344         ret = i915_gem_object_finish_gpu(obj);
2345         dev_priv->mm.interruptible = was_interruptible;
2346
2347         return ret;
2348 }
2349
2350 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2351 {
2352         struct drm_device *dev = crtc->dev;
2353         struct drm_i915_master_private *master_priv;
2354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355
2356         if (!dev->primary->master)
2357                 return;
2358
2359         master_priv = dev->primary->master->driver_priv;
2360         if (!master_priv->sarea_priv)
2361                 return;
2362
2363         switch (intel_crtc->pipe) {
2364         case 0:
2365                 master_priv->sarea_priv->pipeA_x = x;
2366                 master_priv->sarea_priv->pipeA_y = y;
2367                 break;
2368         case 1:
2369                 master_priv->sarea_priv->pipeB_x = x;
2370                 master_priv->sarea_priv->pipeB_y = y;
2371                 break;
2372         default:
2373                 break;
2374         }
2375 }
2376
2377 static int
2378 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2379                     struct drm_framebuffer *fb)
2380 {
2381         struct drm_device *dev = crtc->dev;
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2384         struct drm_framebuffer *old_fb;
2385         int ret;
2386
2387         /* no fb bound */
2388         if (!fb) {
2389                 DRM_ERROR("No FB bound\n");
2390                 return 0;
2391         }
2392
2393         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2394                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2395                           plane_name(intel_crtc->plane),
2396                           INTEL_INFO(dev)->num_pipes);
2397                 return -EINVAL;
2398         }
2399
2400         mutex_lock(&dev->struct_mutex);
2401         ret = intel_pin_and_fence_fb_obj(dev,
2402                                          to_intel_framebuffer(fb)->obj,
2403                                          NULL);
2404         if (ret != 0) {
2405                 mutex_unlock(&dev->struct_mutex);
2406                 DRM_ERROR("pin & fence failed\n");
2407                 return ret;
2408         }
2409
2410         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2411         if (ret) {
2412                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2413                 mutex_unlock(&dev->struct_mutex);
2414                 DRM_ERROR("failed to update base address\n");
2415                 return ret;
2416         }
2417
2418         old_fb = crtc->fb;
2419         crtc->fb = fb;
2420         crtc->x = x;
2421         crtc->y = y;
2422
2423         if (old_fb) {
2424                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2425                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2426         }
2427
2428         intel_update_fbc(dev);
2429         mutex_unlock(&dev->struct_mutex);
2430
2431         intel_crtc_update_sarea_pos(crtc, x, y);
2432
2433         return 0;
2434 }
2435
2436 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2437 {
2438         struct drm_device *dev = crtc->dev;
2439         struct drm_i915_private *dev_priv = dev->dev_private;
2440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2441         int pipe = intel_crtc->pipe;
2442         u32 reg, temp;
2443
2444         /* enable normal train */
2445         reg = FDI_TX_CTL(pipe);
2446         temp = I915_READ(reg);
2447         if (IS_IVYBRIDGE(dev)) {
2448                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2449                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2450         } else {
2451                 temp &= ~FDI_LINK_TRAIN_NONE;
2452                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2453         }
2454         I915_WRITE(reg, temp);
2455
2456         reg = FDI_RX_CTL(pipe);
2457         temp = I915_READ(reg);
2458         if (HAS_PCH_CPT(dev)) {
2459                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2460                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2461         } else {
2462                 temp &= ~FDI_LINK_TRAIN_NONE;
2463                 temp |= FDI_LINK_TRAIN_NONE;
2464         }
2465         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2466
2467         /* wait one idle pattern time */
2468         POSTING_READ(reg);
2469         udelay(1000);
2470
2471         /* IVB wants error correction enabled */
2472         if (IS_IVYBRIDGE(dev))
2473                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2474                            FDI_FE_ERRC_ENABLE);
2475 }
2476
2477 static void ivb_modeset_global_resources(struct drm_device *dev)
2478 {
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         struct intel_crtc *pipe_B_crtc =
2481                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2482         struct intel_crtc *pipe_C_crtc =
2483                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2484         uint32_t temp;
2485
2486         /* When everything is off disable fdi C so that we could enable fdi B
2487          * with all lanes. XXX: This misses the case where a pipe is not using
2488          * any pch resources and so doesn't need any fdi lanes. */
2489         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2490                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2491                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2492
2493                 temp = I915_READ(SOUTH_CHICKEN1);
2494                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2495                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2496                 I915_WRITE(SOUTH_CHICKEN1, temp);
2497         }
2498 }
2499
2500 /* The FDI link training functions for ILK/Ibexpeak. */
2501 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2502 {
2503         struct drm_device *dev = crtc->dev;
2504         struct drm_i915_private *dev_priv = dev->dev_private;
2505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506         int pipe = intel_crtc->pipe;
2507         int plane = intel_crtc->plane;
2508         u32 reg, temp, tries;
2509
2510         /* FDI needs bits from pipe & plane first */
2511         assert_pipe_enabled(dev_priv, pipe);
2512         assert_plane_enabled(dev_priv, plane);
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521         I915_READ(reg);
2522         udelay(150);
2523
2524         /* enable CPU FDI TX and PCH FDI RX */
2525         reg = FDI_TX_CTL(pipe);
2526         temp = I915_READ(reg);
2527         temp &= ~(7 << 19);
2528         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2529         temp &= ~FDI_LINK_TRAIN_NONE;
2530         temp |= FDI_LINK_TRAIN_PATTERN_1;
2531         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2532
2533         reg = FDI_RX_CTL(pipe);
2534         temp = I915_READ(reg);
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2538
2539         POSTING_READ(reg);
2540         udelay(150);
2541
2542         /* Ironlake workaround, enable clock pointer after FDI enable*/
2543         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2544         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2545                    FDI_RX_PHASE_SYNC_POINTER_EN);
2546
2547         reg = FDI_RX_IIR(pipe);
2548         for (tries = 0; tries < 5; tries++) {
2549                 temp = I915_READ(reg);
2550                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551
2552                 if ((temp & FDI_RX_BIT_LOCK)) {
2553                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2554                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2555                         break;
2556                 }
2557         }
2558         if (tries == 5)
2559                 DRM_ERROR("FDI train 1 fail!\n");
2560
2561         /* Train 2 */
2562         reg = FDI_TX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         I915_WRITE(reg, temp);
2567
2568         reg = FDI_RX_CTL(pipe);
2569         temp = I915_READ(reg);
2570         temp &= ~FDI_LINK_TRAIN_NONE;
2571         temp |= FDI_LINK_TRAIN_PATTERN_2;
2572         I915_WRITE(reg, temp);
2573
2574         POSTING_READ(reg);
2575         udelay(150);
2576
2577         reg = FDI_RX_IIR(pipe);
2578         for (tries = 0; tries < 5; tries++) {
2579                 temp = I915_READ(reg);
2580                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582                 if (temp & FDI_RX_SYMBOL_LOCK) {
2583                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2585                         break;
2586                 }
2587         }
2588         if (tries == 5)
2589                 DRM_ERROR("FDI train 2 fail!\n");
2590
2591         DRM_DEBUG_KMS("FDI train done\n");
2592
2593 }
2594
2595 static const int snb_b_fdi_train_param[] = {
2596         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2597         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2598         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2599         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2600 };
2601
2602 /* The FDI link training functions for SNB/Cougarpoint. */
2603 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2604 {
2605         struct drm_device *dev = crtc->dev;
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608         int pipe = intel_crtc->pipe;
2609         u32 reg, temp, i, retry;
2610
2611         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612            for train result */
2613         reg = FDI_RX_IMR(pipe);
2614         temp = I915_READ(reg);
2615         temp &= ~FDI_RX_SYMBOL_LOCK;
2616         temp &= ~FDI_RX_BIT_LOCK;
2617         I915_WRITE(reg, temp);
2618
2619         POSTING_READ(reg);
2620         udelay(150);
2621
2622         /* enable CPU FDI TX and PCH FDI RX */
2623         reg = FDI_TX_CTL(pipe);
2624         temp = I915_READ(reg);
2625         temp &= ~(7 << 19);
2626         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627         temp &= ~FDI_LINK_TRAIN_NONE;
2628         temp |= FDI_LINK_TRAIN_PATTERN_1;
2629         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630         /* SNB-B */
2631         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2633
2634         I915_WRITE(FDI_RX_MISC(pipe),
2635                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2636
2637         reg = FDI_RX_CTL(pipe);
2638         temp = I915_READ(reg);
2639         if (HAS_PCH_CPT(dev)) {
2640                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2641                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2642         } else {
2643                 temp &= ~FDI_LINK_TRAIN_NONE;
2644                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2645         }
2646         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         for (i = 0; i < 4; i++) {
2652                 reg = FDI_TX_CTL(pipe);
2653                 temp = I915_READ(reg);
2654                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655                 temp |= snb_b_fdi_train_param[i];
2656                 I915_WRITE(reg, temp);
2657
2658                 POSTING_READ(reg);
2659                 udelay(500);
2660
2661                 for (retry = 0; retry < 5; retry++) {
2662                         reg = FDI_RX_IIR(pipe);
2663                         temp = I915_READ(reg);
2664                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2665                         if (temp & FDI_RX_BIT_LOCK) {
2666                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2667                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2668                                 break;
2669                         }
2670                         udelay(50);
2671                 }
2672                 if (retry < 5)
2673                         break;
2674         }
2675         if (i == 4)
2676                 DRM_ERROR("FDI train 1 fail!\n");
2677
2678         /* Train 2 */
2679         reg = FDI_TX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~FDI_LINK_TRAIN_NONE;
2682         temp |= FDI_LINK_TRAIN_PATTERN_2;
2683         if (IS_GEN6(dev)) {
2684                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685                 /* SNB-B */
2686                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2687         }
2688         I915_WRITE(reg, temp);
2689
2690         reg = FDI_RX_CTL(pipe);
2691         temp = I915_READ(reg);
2692         if (HAS_PCH_CPT(dev)) {
2693                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2694                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2695         } else {
2696                 temp &= ~FDI_LINK_TRAIN_NONE;
2697                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2698         }
2699         I915_WRITE(reg, temp);
2700
2701         POSTING_READ(reg);
2702         udelay(150);
2703
2704         for (i = 0; i < 4; i++) {
2705                 reg = FDI_TX_CTL(pipe);
2706                 temp = I915_READ(reg);
2707                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708                 temp |= snb_b_fdi_train_param[i];
2709                 I915_WRITE(reg, temp);
2710
2711                 POSTING_READ(reg);
2712                 udelay(500);
2713
2714                 for (retry = 0; retry < 5; retry++) {
2715                         reg = FDI_RX_IIR(pipe);
2716                         temp = I915_READ(reg);
2717                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2718                         if (temp & FDI_RX_SYMBOL_LOCK) {
2719                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2720                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2721                                 break;
2722                         }
2723                         udelay(50);
2724                 }
2725                 if (retry < 5)
2726                         break;
2727         }
2728         if (i == 4)
2729                 DRM_ERROR("FDI train 2 fail!\n");
2730
2731         DRM_DEBUG_KMS("FDI train done.\n");
2732 }
2733
2734 /* Manual link training for Ivy Bridge A0 parts */
2735 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp, i;
2742
2743         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2744            for train result */
2745         reg = FDI_RX_IMR(pipe);
2746         temp = I915_READ(reg);
2747         temp &= ~FDI_RX_SYMBOL_LOCK;
2748         temp &= ~FDI_RX_BIT_LOCK;
2749         I915_WRITE(reg, temp);
2750
2751         POSTING_READ(reg);
2752         udelay(150);
2753
2754         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2755                       I915_READ(FDI_RX_IIR(pipe)));
2756
2757         /* enable CPU FDI TX and PCH FDI RX */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         temp &= ~(7 << 19);
2761         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2762         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2763         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2764         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2765         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2766         temp |= FDI_COMPOSITE_SYNC;
2767         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2768
2769         I915_WRITE(FDI_RX_MISC(pipe),
2770                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2771
2772         reg = FDI_RX_CTL(pipe);
2773         temp = I915_READ(reg);
2774         temp &= ~FDI_LINK_TRAIN_AUTO;
2775         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2776         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2777         temp |= FDI_COMPOSITE_SYNC;
2778         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2779
2780         POSTING_READ(reg);
2781         udelay(150);
2782
2783         for (i = 0; i < 4; i++) {
2784                 reg = FDI_TX_CTL(pipe);
2785                 temp = I915_READ(reg);
2786                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787                 temp |= snb_b_fdi_train_param[i];
2788                 I915_WRITE(reg, temp);
2789
2790                 POSTING_READ(reg);
2791                 udelay(500);
2792
2793                 reg = FDI_RX_IIR(pipe);
2794                 temp = I915_READ(reg);
2795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2796
2797                 if (temp & FDI_RX_BIT_LOCK ||
2798                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2799                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2800                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2801                         break;
2802                 }
2803         }
2804         if (i == 4)
2805                 DRM_ERROR("FDI train 1 fail!\n");
2806
2807         /* Train 2 */
2808         reg = FDI_TX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2811         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2812         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2813         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2814         I915_WRITE(reg, temp);
2815
2816         reg = FDI_RX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(150);
2824
2825         for (i = 0; i < 4; i++) {
2826                 reg = FDI_TX_CTL(pipe);
2827                 temp = I915_READ(reg);
2828                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2829                 temp |= snb_b_fdi_train_param[i];
2830                 I915_WRITE(reg, temp);
2831
2832                 POSTING_READ(reg);
2833                 udelay(500);
2834
2835                 reg = FDI_RX_IIR(pipe);
2836                 temp = I915_READ(reg);
2837                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2838
2839                 if (temp & FDI_RX_SYMBOL_LOCK) {
2840                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2841                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2842                         break;
2843                 }
2844         }
2845         if (i == 4)
2846                 DRM_ERROR("FDI train 2 fail!\n");
2847
2848         DRM_DEBUG_KMS("FDI train done.\n");
2849 }
2850
2851 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2852 {
2853         struct drm_device *dev = intel_crtc->base.dev;
2854         struct drm_i915_private *dev_priv = dev->dev_private;
2855         int pipe = intel_crtc->pipe;
2856         u32 reg, temp;
2857
2858
2859         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         temp &= ~((0x7 << 19) | (0x7 << 16));
2863         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2864         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2865         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2866
2867         POSTING_READ(reg);
2868         udelay(200);
2869
2870         /* Switch from Rawclk to PCDclk */
2871         temp = I915_READ(reg);
2872         I915_WRITE(reg, temp | FDI_PCDCLK);
2873
2874         POSTING_READ(reg);
2875         udelay(200);
2876
2877         /* Enable CPU FDI TX PLL, always on for Ironlake */
2878         reg = FDI_TX_CTL(pipe);
2879         temp = I915_READ(reg);
2880         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2881                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2882
2883                 POSTING_READ(reg);
2884                 udelay(100);
2885         }
2886 }
2887
2888 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2889 {
2890         struct drm_device *dev = intel_crtc->base.dev;
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         int pipe = intel_crtc->pipe;
2893         u32 reg, temp;
2894
2895         /* Switch from PCDclk to Rawclk */
2896         reg = FDI_RX_CTL(pipe);
2897         temp = I915_READ(reg);
2898         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2899
2900         /* Disable CPU FDI TX PLL */
2901         reg = FDI_TX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2904
2905         POSTING_READ(reg);
2906         udelay(100);
2907
2908         reg = FDI_RX_CTL(pipe);
2909         temp = I915_READ(reg);
2910         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2911
2912         /* Wait for the clocks to turn off. */
2913         POSTING_READ(reg);
2914         udelay(100);
2915 }
2916
2917 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2918 {
2919         struct drm_device *dev = crtc->dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922         int pipe = intel_crtc->pipe;
2923         u32 reg, temp;
2924
2925         /* disable CPU FDI tx and PCH FDI rx */
2926         reg = FDI_TX_CTL(pipe);
2927         temp = I915_READ(reg);
2928         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2929         POSTING_READ(reg);
2930
2931         reg = FDI_RX_CTL(pipe);
2932         temp = I915_READ(reg);
2933         temp &= ~(0x7 << 16);
2934         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2935         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2936
2937         POSTING_READ(reg);
2938         udelay(100);
2939
2940         /* Ironlake workaround, disable clock pointer after downing FDI */
2941         if (HAS_PCH_IBX(dev)) {
2942                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2943         }
2944
2945         /* still set train pattern 1 */
2946         reg = FDI_TX_CTL(pipe);
2947         temp = I915_READ(reg);
2948         temp &= ~FDI_LINK_TRAIN_NONE;
2949         temp |= FDI_LINK_TRAIN_PATTERN_1;
2950         I915_WRITE(reg, temp);
2951
2952         reg = FDI_RX_CTL(pipe);
2953         temp = I915_READ(reg);
2954         if (HAS_PCH_CPT(dev)) {
2955                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2956                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2957         } else {
2958                 temp &= ~FDI_LINK_TRAIN_NONE;
2959                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2960         }
2961         /* BPC in FDI rx is consistent with that in PIPECONF */
2962         temp &= ~(0x07 << 16);
2963         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2964         I915_WRITE(reg, temp);
2965
2966         POSTING_READ(reg);
2967         udelay(100);
2968 }
2969
2970 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2975         unsigned long flags;
2976         bool pending;
2977
2978         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2979             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2980                 return false;
2981
2982         spin_lock_irqsave(&dev->event_lock, flags);
2983         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2984         spin_unlock_irqrestore(&dev->event_lock, flags);
2985
2986         return pending;
2987 }
2988
2989 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2990 {
2991         struct drm_device *dev = crtc->dev;
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993
2994         if (crtc->fb == NULL)
2995                 return;
2996
2997         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2998
2999         wait_event(dev_priv->pending_flip_queue,
3000                    !intel_crtc_has_pending_flip(crtc));
3001
3002         mutex_lock(&dev->struct_mutex);
3003         intel_finish_fb(crtc->fb);
3004         mutex_unlock(&dev->struct_mutex);
3005 }
3006
3007 /* Program iCLKIP clock to the desired frequency */
3008 static void lpt_program_iclkip(struct drm_crtc *crtc)
3009 {
3010         struct drm_device *dev = crtc->dev;
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3013         u32 temp;
3014
3015         mutex_lock(&dev_priv->dpio_lock);
3016
3017         /* It is necessary to ungate the pixclk gate prior to programming
3018          * the divisors, and gate it back when it is done.
3019          */
3020         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3021
3022         /* Disable SSCCTL */
3023         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3024                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3025                                 SBI_SSCCTL_DISABLE,
3026                         SBI_ICLK);
3027
3028         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3029         if (crtc->mode.clock == 20000) {
3030                 auxdiv = 1;
3031                 divsel = 0x41;
3032                 phaseinc = 0x20;
3033         } else {
3034                 /* The iCLK virtual clock root frequency is in MHz,
3035                  * but the crtc->mode.clock in in KHz. To get the divisors,
3036                  * it is necessary to divide one by another, so we
3037                  * convert the virtual clock precision to KHz here for higher
3038                  * precision.
3039                  */
3040                 u32 iclk_virtual_root_freq = 172800 * 1000;
3041                 u32 iclk_pi_range = 64;
3042                 u32 desired_divisor, msb_divisor_value, pi_value;
3043
3044                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3045                 msb_divisor_value = desired_divisor / iclk_pi_range;
3046                 pi_value = desired_divisor % iclk_pi_range;
3047
3048                 auxdiv = 0;
3049                 divsel = msb_divisor_value - 2;
3050                 phaseinc = pi_value;
3051         }
3052
3053         /* This should not happen with any sane values */
3054         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3055                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3056         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3057                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3058
3059         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3060                         crtc->mode.clock,
3061                         auxdiv,
3062                         divsel,
3063                         phasedir,
3064                         phaseinc);
3065
3066         /* Program SSCDIVINTPHASE6 */
3067         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3068         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3069         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3070         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3071         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3072         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3073         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3074         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3075
3076         /* Program SSCAUXDIV */
3077         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3078         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3080         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3081
3082         /* Enable modulator and associated divider */
3083         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3084         temp &= ~SBI_SSCCTL_DISABLE;
3085         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3086
3087         /* Wait for initialization time */
3088         udelay(24);
3089
3090         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3091
3092         mutex_unlock(&dev_priv->dpio_lock);
3093 }
3094
3095 /*
3096  * Enable PCH resources required for PCH ports:
3097  *   - PCH PLLs
3098  *   - FDI training & RX/TX
3099  *   - update transcoder timings
3100  *   - DP transcoding bits
3101  *   - transcoder
3102  */
3103 static void ironlake_pch_enable(struct drm_crtc *crtc)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108         int pipe = intel_crtc->pipe;
3109         u32 reg, temp;
3110
3111         assert_transcoder_disabled(dev_priv, pipe);
3112
3113         /* Write the TU size bits before fdi link training, so that error
3114          * detection works. */
3115         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3116                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3117
3118         /* For PCH output, training FDI link */
3119         dev_priv->display.fdi_link_train(crtc);
3120
3121         /* XXX: pch pll's can be enabled any time before we enable the PCH
3122          * transcoder, and we actually should do this to not upset any PCH
3123          * transcoder that already use the clock when we share it.
3124          *
3125          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3126          * unconditionally resets the pll - we need that to have the right LVDS
3127          * enable sequence. */
3128         ironlake_enable_pch_pll(intel_crtc);
3129
3130         if (HAS_PCH_CPT(dev)) {
3131                 u32 sel;
3132
3133                 temp = I915_READ(PCH_DPLL_SEL);
3134                 switch (pipe) {
3135                 default:
3136                 case 0:
3137                         temp |= TRANSA_DPLL_ENABLE;
3138                         sel = TRANSA_DPLLB_SEL;
3139                         break;
3140                 case 1:
3141                         temp |= TRANSB_DPLL_ENABLE;
3142                         sel = TRANSB_DPLLB_SEL;
3143                         break;
3144                 case 2:
3145                         temp |= TRANSC_DPLL_ENABLE;
3146                         sel = TRANSC_DPLLB_SEL;
3147                         break;
3148                 }
3149                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3150                         temp |= sel;
3151                 else
3152                         temp &= ~sel;
3153                 I915_WRITE(PCH_DPLL_SEL, temp);
3154         }
3155
3156         /* set transcoder timing, panel must allow it */
3157         assert_panel_unlocked(dev_priv, pipe);
3158         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3159         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3160         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3161
3162         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3163         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3164         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3165         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3166
3167         intel_fdi_normal_train(crtc);
3168
3169         /* For PCH DP, enable TRANS_DP_CTL */
3170         if (HAS_PCH_CPT(dev) &&
3171             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3172              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3173                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3174                 reg = TRANS_DP_CTL(pipe);
3175                 temp = I915_READ(reg);
3176                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3177                           TRANS_DP_SYNC_MASK |
3178                           TRANS_DP_BPC_MASK);
3179                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3180                          TRANS_DP_ENH_FRAMING);
3181                 temp |= bpc << 9; /* same format but at 11:9 */
3182
3183                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3184                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3185                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3186                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3187
3188                 switch (intel_trans_dp_port_sel(crtc)) {
3189                 case PCH_DP_B:
3190                         temp |= TRANS_DP_PORT_SEL_B;
3191                         break;
3192                 case PCH_DP_C:
3193                         temp |= TRANS_DP_PORT_SEL_C;
3194                         break;
3195                 case PCH_DP_D:
3196                         temp |= TRANS_DP_PORT_SEL_D;
3197                         break;
3198                 default:
3199                         BUG();
3200                 }
3201
3202                 I915_WRITE(reg, temp);
3203         }
3204
3205         ironlake_enable_pch_transcoder(dev_priv, pipe);
3206 }
3207
3208 static void lpt_pch_enable(struct drm_crtc *crtc)
3209 {
3210         struct drm_device *dev = crtc->dev;
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3214
3215         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3216
3217         lpt_program_iclkip(crtc);
3218
3219         /* Set transcoder timing. */
3220         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3221         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3222         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3223
3224         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3225         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3226         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3227         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3228
3229         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3230 }
3231
3232 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3233 {
3234         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3235
3236         if (pll == NULL)
3237                 return;
3238
3239         if (pll->refcount == 0) {
3240                 WARN(1, "bad PCH PLL refcount\n");
3241                 return;
3242         }
3243
3244         --pll->refcount;
3245         intel_crtc->pch_pll = NULL;
3246 }
3247
3248 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3249 {
3250         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3251         struct intel_pch_pll *pll;
3252         int i;
3253
3254         pll = intel_crtc->pch_pll;
3255         if (pll) {
3256                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3257                               intel_crtc->base.base.id, pll->pll_reg);
3258                 goto prepare;
3259         }
3260
3261         if (HAS_PCH_IBX(dev_priv->dev)) {
3262                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3263                 i = intel_crtc->pipe;
3264                 pll = &dev_priv->pch_plls[i];
3265
3266                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3267                               intel_crtc->base.base.id, pll->pll_reg);
3268
3269                 goto found;
3270         }
3271
3272         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3273                 pll = &dev_priv->pch_plls[i];
3274
3275                 /* Only want to check enabled timings first */
3276                 if (pll->refcount == 0)
3277                         continue;
3278
3279                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3280                     fp == I915_READ(pll->fp0_reg)) {
3281                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3282                                       intel_crtc->base.base.id,
3283                                       pll->pll_reg, pll->refcount, pll->active);
3284
3285                         goto found;
3286                 }
3287         }
3288
3289         /* Ok no matching timings, maybe there's a free one? */
3290         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3291                 pll = &dev_priv->pch_plls[i];
3292                 if (pll->refcount == 0) {
3293                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3294                                       intel_crtc->base.base.id, pll->pll_reg);
3295                         goto found;
3296                 }
3297         }
3298
3299         return NULL;
3300
3301 found:
3302         intel_crtc->pch_pll = pll;
3303         pll->refcount++;
3304         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3305 prepare: /* separate function? */
3306         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3307
3308         /* Wait for the clocks to stabilize before rewriting the regs */
3309         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3310         POSTING_READ(pll->pll_reg);
3311         udelay(150);
3312
3313         I915_WRITE(pll->fp0_reg, fp);
3314         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3315         pll->on = false;
3316         return pll;
3317 }
3318
3319 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3320 {
3321         struct drm_i915_private *dev_priv = dev->dev_private;
3322         int dslreg = PIPEDSL(pipe);
3323         u32 temp;
3324
3325         temp = I915_READ(dslreg);
3326         udelay(500);
3327         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3328                 if (wait_for(I915_READ(dslreg) != temp, 5))
3329                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3330         }
3331 }
3332
3333 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3334 {
3335         struct drm_device *dev = crtc->dev;
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338         struct intel_encoder *encoder;
3339         int pipe = intel_crtc->pipe;
3340         int plane = intel_crtc->plane;
3341         u32 temp;
3342
3343         WARN_ON(!crtc->enabled);
3344
3345         if (intel_crtc->active)
3346                 return;
3347
3348         intel_crtc->active = true;
3349
3350         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3351         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3352
3353         intel_update_watermarks(dev);
3354
3355         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3356                 temp = I915_READ(PCH_LVDS);
3357                 if ((temp & LVDS_PORT_EN) == 0)
3358                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3359         }
3360
3361
3362         if (intel_crtc->config.has_pch_encoder) {
3363                 /* Note: FDI PLL enabling _must_ be done before we enable the
3364                  * cpu pipes, hence this is separate from all the other fdi/pch
3365                  * enabling. */
3366                 ironlake_fdi_pll_enable(intel_crtc);
3367         } else {
3368                 assert_fdi_tx_disabled(dev_priv, pipe);
3369                 assert_fdi_rx_disabled(dev_priv, pipe);
3370         }
3371
3372         for_each_encoder_on_crtc(dev, crtc, encoder)
3373                 if (encoder->pre_enable)
3374                         encoder->pre_enable(encoder);
3375
3376         /* Enable panel fitting for LVDS */
3377         if (dev_priv->pch_pf_size &&
3378             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3379              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3380                 /* Force use of hard-coded filter coefficients
3381                  * as some pre-programmed values are broken,
3382                  * e.g. x201.
3383                  */
3384                 if (IS_IVYBRIDGE(dev))
3385                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386                                                  PF_PIPE_SEL_IVB(pipe));
3387                 else
3388                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3389                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3390                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3391         }
3392
3393         /*
3394          * On ILK+ LUT must be loaded before the pipe is running but with
3395          * clocks enabled
3396          */
3397         intel_crtc_load_lut(crtc);
3398
3399         intel_enable_pipe(dev_priv, pipe,
3400                           intel_crtc->config.has_pch_encoder);
3401         intel_enable_plane(dev_priv, plane, pipe);
3402
3403         if (intel_crtc->config.has_pch_encoder)
3404                 ironlake_pch_enable(crtc);
3405
3406         mutex_lock(&dev->struct_mutex);
3407         intel_update_fbc(dev);
3408         mutex_unlock(&dev->struct_mutex);
3409
3410         intel_crtc_update_cursor(crtc, true);
3411
3412         for_each_encoder_on_crtc(dev, crtc, encoder)
3413                 encoder->enable(encoder);
3414
3415         if (HAS_PCH_CPT(dev))
3416                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3417
3418         /*
3419          * There seems to be a race in PCH platform hw (at least on some
3420          * outputs) where an enabled pipe still completes any pageflip right
3421          * away (as if the pipe is off) instead of waiting for vblank. As soon
3422          * as the first vblank happend, everything works as expected. Hence just
3423          * wait for one vblank before returning to avoid strange things
3424          * happening.
3425          */
3426         intel_wait_for_vblank(dev, intel_crtc->pipe);
3427 }
3428
3429 static void haswell_crtc_enable(struct drm_crtc *crtc)
3430 {
3431         struct drm_device *dev = crtc->dev;
3432         struct drm_i915_private *dev_priv = dev->dev_private;
3433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3434         struct intel_encoder *encoder;
3435         int pipe = intel_crtc->pipe;
3436         int plane = intel_crtc->plane;
3437
3438         WARN_ON(!crtc->enabled);
3439
3440         if (intel_crtc->active)
3441                 return;
3442
3443         intel_crtc->active = true;
3444
3445         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3446         if (intel_crtc->config.has_pch_encoder)
3447                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3448
3449         intel_update_watermarks(dev);
3450
3451         if (intel_crtc->config.has_pch_encoder)
3452                 dev_priv->display.fdi_link_train(crtc);
3453
3454         for_each_encoder_on_crtc(dev, crtc, encoder)
3455                 if (encoder->pre_enable)
3456                         encoder->pre_enable(encoder);
3457
3458         intel_ddi_enable_pipe_clock(intel_crtc);
3459
3460         /* Enable panel fitting for eDP */
3461         if (dev_priv->pch_pf_size &&
3462             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3463                 /* Force use of hard-coded filter coefficients
3464                  * as some pre-programmed values are broken,
3465                  * e.g. x201.
3466                  */
3467                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3468                                          PF_PIPE_SEL_IVB(pipe));
3469                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3471         }
3472
3473         /*
3474          * On ILK+ LUT must be loaded before the pipe is running but with
3475          * clocks enabled
3476          */
3477         intel_crtc_load_lut(crtc);
3478
3479         intel_ddi_set_pipe_settings(crtc);
3480         intel_ddi_enable_transcoder_func(crtc);
3481
3482         intel_enable_pipe(dev_priv, pipe,
3483                           intel_crtc->config.has_pch_encoder);
3484         intel_enable_plane(dev_priv, plane, pipe);
3485
3486         if (intel_crtc->config.has_pch_encoder)
3487                 lpt_pch_enable(crtc);
3488
3489         mutex_lock(&dev->struct_mutex);
3490         intel_update_fbc(dev);
3491         mutex_unlock(&dev->struct_mutex);
3492
3493         intel_crtc_update_cursor(crtc, true);
3494
3495         for_each_encoder_on_crtc(dev, crtc, encoder)
3496                 encoder->enable(encoder);
3497
3498         /*
3499          * There seems to be a race in PCH platform hw (at least on some
3500          * outputs) where an enabled pipe still completes any pageflip right
3501          * away (as if the pipe is off) instead of waiting for vblank. As soon
3502          * as the first vblank happend, everything works as expected. Hence just
3503          * wait for one vblank before returning to avoid strange things
3504          * happening.
3505          */
3506         intel_wait_for_vblank(dev, intel_crtc->pipe);
3507 }
3508
3509 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3510 {
3511         struct drm_device *dev = crtc->dev;
3512         struct drm_i915_private *dev_priv = dev->dev_private;
3513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514         struct intel_encoder *encoder;
3515         int pipe = intel_crtc->pipe;
3516         int plane = intel_crtc->plane;
3517         u32 reg, temp;
3518
3519
3520         if (!intel_crtc->active)
3521                 return;
3522
3523         for_each_encoder_on_crtc(dev, crtc, encoder)
3524                 encoder->disable(encoder);
3525
3526         intel_crtc_wait_for_pending_flips(crtc);
3527         drm_vblank_off(dev, pipe);
3528         intel_crtc_update_cursor(crtc, false);
3529
3530         intel_disable_plane(dev_priv, plane, pipe);
3531
3532         if (dev_priv->cfb_plane == plane)
3533                 intel_disable_fbc(dev);
3534
3535         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3536         intel_disable_pipe(dev_priv, pipe);
3537
3538         /* Disable PF */
3539         I915_WRITE(PF_CTL(pipe), 0);
3540         I915_WRITE(PF_WIN_SZ(pipe), 0);
3541
3542         for_each_encoder_on_crtc(dev, crtc, encoder)
3543                 if (encoder->post_disable)
3544                         encoder->post_disable(encoder);
3545
3546         ironlake_fdi_disable(crtc);
3547
3548         ironlake_disable_pch_transcoder(dev_priv, pipe);
3549         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3550
3551         if (HAS_PCH_CPT(dev)) {
3552                 /* disable TRANS_DP_CTL */
3553                 reg = TRANS_DP_CTL(pipe);
3554                 temp = I915_READ(reg);
3555                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3556                 temp |= TRANS_DP_PORT_SEL_NONE;
3557                 I915_WRITE(reg, temp);
3558
3559                 /* disable DPLL_SEL */
3560                 temp = I915_READ(PCH_DPLL_SEL);
3561                 switch (pipe) {
3562                 case 0:
3563                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3564                         break;
3565                 case 1:
3566                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3567                         break;
3568                 case 2:
3569                         /* C shares PLL A or B */
3570                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3571                         break;
3572                 default:
3573                         BUG(); /* wtf */
3574                 }
3575                 I915_WRITE(PCH_DPLL_SEL, temp);
3576         }
3577
3578         /* disable PCH DPLL */
3579         intel_disable_pch_pll(intel_crtc);
3580
3581         ironlake_fdi_pll_disable(intel_crtc);
3582
3583         intel_crtc->active = false;
3584         intel_update_watermarks(dev);
3585
3586         mutex_lock(&dev->struct_mutex);
3587         intel_update_fbc(dev);
3588         mutex_unlock(&dev->struct_mutex);
3589 }
3590
3591 static void haswell_crtc_disable(struct drm_crtc *crtc)
3592 {
3593         struct drm_device *dev = crtc->dev;
3594         struct drm_i915_private *dev_priv = dev->dev_private;
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         struct intel_encoder *encoder;
3597         int pipe = intel_crtc->pipe;
3598         int plane = intel_crtc->plane;
3599         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3600
3601         if (!intel_crtc->active)
3602                 return;
3603
3604         for_each_encoder_on_crtc(dev, crtc, encoder)
3605                 encoder->disable(encoder);
3606
3607         intel_crtc_wait_for_pending_flips(crtc);
3608         drm_vblank_off(dev, pipe);
3609         intel_crtc_update_cursor(crtc, false);
3610
3611         intel_disable_plane(dev_priv, plane, pipe);
3612
3613         if (dev_priv->cfb_plane == plane)
3614                 intel_disable_fbc(dev);
3615
3616         if (intel_crtc->config.has_pch_encoder)
3617                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3618         intel_disable_pipe(dev_priv, pipe);
3619
3620         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3621
3622         /* XXX: Once we have proper panel fitter state tracking implemented with
3623          * hardware state read/check support we should switch to only disable
3624          * the panel fitter when we know it's used. */
3625         if (intel_using_power_well(dev)) {
3626                 I915_WRITE(PF_CTL(pipe), 0);
3627                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3628         }
3629
3630         intel_ddi_disable_pipe_clock(intel_crtc);
3631
3632         for_each_encoder_on_crtc(dev, crtc, encoder)
3633                 if (encoder->post_disable)
3634                         encoder->post_disable(encoder);
3635
3636         if (intel_crtc->config.has_pch_encoder) {
3637                 lpt_disable_pch_transcoder(dev_priv);
3638                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3639                 intel_ddi_fdi_disable(crtc);
3640         }
3641
3642         intel_crtc->active = false;
3643         intel_update_watermarks(dev);
3644
3645         mutex_lock(&dev->struct_mutex);
3646         intel_update_fbc(dev);
3647         mutex_unlock(&dev->struct_mutex);
3648 }
3649
3650 static void ironlake_crtc_off(struct drm_crtc *crtc)
3651 {
3652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653         intel_put_pch_pll(intel_crtc);
3654 }
3655
3656 static void haswell_crtc_off(struct drm_crtc *crtc)
3657 {
3658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659
3660         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3661          * start using it. */
3662         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3663
3664         intel_ddi_put_crtc_pll(crtc);
3665 }
3666
3667 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3668 {
3669         if (!enable && intel_crtc->overlay) {
3670                 struct drm_device *dev = intel_crtc->base.dev;
3671                 struct drm_i915_private *dev_priv = dev->dev_private;
3672
3673                 mutex_lock(&dev->struct_mutex);
3674                 dev_priv->mm.interruptible = false;
3675                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3676                 dev_priv->mm.interruptible = true;
3677                 mutex_unlock(&dev->struct_mutex);
3678         }
3679
3680         /* Let userspace switch the overlay on again. In most cases userspace
3681          * has to recompute where to put it anyway.
3682          */
3683 }
3684
3685 /**
3686  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3687  * cursor plane briefly if not already running after enabling the display
3688  * plane.
3689  * This workaround avoids occasional blank screens when self refresh is
3690  * enabled.
3691  */
3692 static void
3693 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3694 {
3695         u32 cntl = I915_READ(CURCNTR(pipe));
3696
3697         if ((cntl & CURSOR_MODE) == 0) {
3698                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3699
3700                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3701                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3702                 intel_wait_for_vblank(dev_priv->dev, pipe);
3703                 I915_WRITE(CURCNTR(pipe), cntl);
3704                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3705                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3706         }
3707 }
3708
3709 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3710 {
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714         struct intel_encoder *encoder;
3715         int pipe = intel_crtc->pipe;
3716         int plane = intel_crtc->plane;
3717
3718         WARN_ON(!crtc->enabled);
3719
3720         if (intel_crtc->active)
3721                 return;
3722
3723         intel_crtc->active = true;
3724         intel_update_watermarks(dev);
3725
3726         mutex_lock(&dev_priv->dpio_lock);
3727
3728         for_each_encoder_on_crtc(dev, crtc, encoder)
3729                 if (encoder->pre_pll_enable)
3730                         encoder->pre_pll_enable(encoder);
3731
3732         intel_enable_pll(dev_priv, pipe);
3733
3734         for_each_encoder_on_crtc(dev, crtc, encoder)
3735                 if (encoder->pre_enable)
3736                         encoder->pre_enable(encoder);
3737
3738         /* VLV wants encoder enabling _before_ the pipe is up. */
3739         for_each_encoder_on_crtc(dev, crtc, encoder)
3740                 encoder->enable(encoder);
3741
3742         intel_enable_pipe(dev_priv, pipe, false);
3743         intel_enable_plane(dev_priv, plane, pipe);
3744
3745         intel_crtc_load_lut(crtc);
3746         intel_update_fbc(dev);
3747
3748         /* Give the overlay scaler a chance to enable if it's on this pipe */
3749         intel_crtc_dpms_overlay(intel_crtc, true);
3750         intel_crtc_update_cursor(crtc, true);
3751
3752         mutex_unlock(&dev_priv->dpio_lock);
3753 }
3754
3755 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3756 {
3757         struct drm_device *dev = crtc->dev;
3758         struct drm_i915_private *dev_priv = dev->dev_private;
3759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760         struct intel_encoder *encoder;
3761         int pipe = intel_crtc->pipe;
3762         int plane = intel_crtc->plane;
3763
3764         WARN_ON(!crtc->enabled);
3765
3766         if (intel_crtc->active)
3767                 return;
3768
3769         intel_crtc->active = true;
3770         intel_update_watermarks(dev);
3771
3772         intel_enable_pll(dev_priv, pipe);
3773
3774         for_each_encoder_on_crtc(dev, crtc, encoder)
3775                 if (encoder->pre_enable)
3776                         encoder->pre_enable(encoder);
3777
3778         intel_enable_pipe(dev_priv, pipe, false);
3779         intel_enable_plane(dev_priv, plane, pipe);
3780         if (IS_G4X(dev))
3781                 g4x_fixup_plane(dev_priv, pipe);
3782
3783         intel_crtc_load_lut(crtc);
3784         intel_update_fbc(dev);
3785
3786         /* Give the overlay scaler a chance to enable if it's on this pipe */
3787         intel_crtc_dpms_overlay(intel_crtc, true);
3788         intel_crtc_update_cursor(crtc, true);
3789
3790         for_each_encoder_on_crtc(dev, crtc, encoder)
3791                 encoder->enable(encoder);
3792 }
3793
3794 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3795 {
3796         struct drm_device *dev = crtc->base.dev;
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798         enum pipe pipe;
3799         uint32_t pctl = I915_READ(PFIT_CONTROL);
3800
3801         assert_pipe_disabled(dev_priv, crtc->pipe);
3802
3803         if (INTEL_INFO(dev)->gen >= 4)
3804                 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3805         else
3806                 pipe = PIPE_B;
3807
3808         if (pipe == crtc->pipe) {
3809                 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3810                 I915_WRITE(PFIT_CONTROL, 0);
3811         }
3812 }
3813
3814 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3815 {
3816         struct drm_device *dev = crtc->dev;
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819         struct intel_encoder *encoder;
3820         int pipe = intel_crtc->pipe;
3821         int plane = intel_crtc->plane;
3822
3823         if (!intel_crtc->active)
3824                 return;
3825
3826         for_each_encoder_on_crtc(dev, crtc, encoder)
3827                 encoder->disable(encoder);
3828
3829         /* Give the overlay scaler a chance to disable if it's on this pipe */
3830         intel_crtc_wait_for_pending_flips(crtc);
3831         drm_vblank_off(dev, pipe);
3832         intel_crtc_dpms_overlay(intel_crtc, false);
3833         intel_crtc_update_cursor(crtc, false);
3834
3835         if (dev_priv->cfb_plane == plane)
3836                 intel_disable_fbc(dev);
3837
3838         intel_disable_plane(dev_priv, plane, pipe);
3839         intel_disable_pipe(dev_priv, pipe);
3840
3841         i9xx_pfit_disable(intel_crtc);
3842
3843         for_each_encoder_on_crtc(dev, crtc, encoder)
3844                 if (encoder->post_disable)
3845                         encoder->post_disable(encoder);
3846
3847         intel_disable_pll(dev_priv, pipe);
3848
3849         intel_crtc->active = false;
3850         intel_update_fbc(dev);
3851         intel_update_watermarks(dev);
3852 }
3853
3854 static void i9xx_crtc_off(struct drm_crtc *crtc)
3855 {
3856 }
3857
3858 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3859                                     bool enabled)
3860 {
3861         struct drm_device *dev = crtc->dev;
3862         struct drm_i915_master_private *master_priv;
3863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864         int pipe = intel_crtc->pipe;
3865
3866         if (!dev->primary->master)
3867                 return;
3868
3869         master_priv = dev->primary->master->driver_priv;
3870         if (!master_priv->sarea_priv)
3871                 return;
3872
3873         switch (pipe) {
3874         case 0:
3875                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3876                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3877                 break;
3878         case 1:
3879                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3880                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3881                 break;
3882         default:
3883                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3884                 break;
3885         }
3886 }
3887
3888 /**
3889  * Sets the power management mode of the pipe and plane.
3890  */
3891 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3892 {
3893         struct drm_device *dev = crtc->dev;
3894         struct drm_i915_private *dev_priv = dev->dev_private;
3895         struct intel_encoder *intel_encoder;
3896         bool enable = false;
3897
3898         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3899                 enable |= intel_encoder->connectors_active;
3900
3901         if (enable)
3902                 dev_priv->display.crtc_enable(crtc);
3903         else
3904                 dev_priv->display.crtc_disable(crtc);
3905
3906         intel_crtc_update_sarea(crtc, enable);
3907 }
3908
3909 static void intel_crtc_disable(struct drm_crtc *crtc)
3910 {
3911         struct drm_device *dev = crtc->dev;
3912         struct drm_connector *connector;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915
3916         /* crtc should still be enabled when we disable it. */
3917         WARN_ON(!crtc->enabled);
3918
3919         intel_crtc->eld_vld = false;
3920         dev_priv->display.crtc_disable(crtc);
3921         intel_crtc_update_sarea(crtc, false);
3922         dev_priv->display.off(crtc);
3923
3924         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3925         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3926
3927         if (crtc->fb) {
3928                 mutex_lock(&dev->struct_mutex);
3929                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3930                 mutex_unlock(&dev->struct_mutex);
3931                 crtc->fb = NULL;
3932         }
3933
3934         /* Update computed state. */
3935         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3936                 if (!connector->encoder || !connector->encoder->crtc)
3937                         continue;
3938
3939                 if (connector->encoder->crtc != crtc)
3940                         continue;
3941
3942                 connector->dpms = DRM_MODE_DPMS_OFF;
3943                 to_intel_encoder(connector->encoder)->connectors_active = false;
3944         }
3945 }
3946
3947 void intel_modeset_disable(struct drm_device *dev)
3948 {
3949         struct drm_crtc *crtc;
3950
3951         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3952                 if (crtc->enabled)
3953                         intel_crtc_disable(crtc);
3954         }
3955 }
3956
3957 void intel_encoder_destroy(struct drm_encoder *encoder)
3958 {
3959         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3960
3961         drm_encoder_cleanup(encoder);
3962         kfree(intel_encoder);
3963 }
3964
3965 /* Simple dpms helper for encodres with just one connector, no cloning and only
3966  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3967  * state of the entire output pipe. */
3968 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3969 {
3970         if (mode == DRM_MODE_DPMS_ON) {
3971                 encoder->connectors_active = true;
3972
3973                 intel_crtc_update_dpms(encoder->base.crtc);
3974         } else {
3975                 encoder->connectors_active = false;
3976
3977                 intel_crtc_update_dpms(encoder->base.crtc);
3978         }
3979 }
3980
3981 /* Cross check the actual hw state with our own modeset state tracking (and it's
3982  * internal consistency). */
3983 static void intel_connector_check_state(struct intel_connector *connector)
3984 {
3985         if (connector->get_hw_state(connector)) {
3986                 struct intel_encoder *encoder = connector->encoder;
3987                 struct drm_crtc *crtc;
3988                 bool encoder_enabled;
3989                 enum pipe pipe;
3990
3991                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3992                               connector->base.base.id,
3993                               drm_get_connector_name(&connector->base));
3994
3995                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3996                      "wrong connector dpms state\n");
3997                 WARN(connector->base.encoder != &encoder->base,
3998                      "active connector not linked to encoder\n");
3999                 WARN(!encoder->connectors_active,
4000                      "encoder->connectors_active not set\n");
4001
4002                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4003                 WARN(!encoder_enabled, "encoder not enabled\n");
4004                 if (WARN_ON(!encoder->base.crtc))
4005                         return;
4006
4007                 crtc = encoder->base.crtc;
4008
4009                 WARN(!crtc->enabled, "crtc not enabled\n");
4010                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4011                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4012                      "encoder active on the wrong pipe\n");
4013         }
4014 }
4015
4016 /* Even simpler default implementation, if there's really no special case to
4017  * consider. */
4018 void intel_connector_dpms(struct drm_connector *connector, int mode)
4019 {
4020         struct intel_encoder *encoder = intel_attached_encoder(connector);
4021
4022         /* All the simple cases only support two dpms states. */
4023         if (mode != DRM_MODE_DPMS_ON)
4024                 mode = DRM_MODE_DPMS_OFF;
4025
4026         if (mode == connector->dpms)
4027                 return;
4028
4029         connector->dpms = mode;
4030
4031         /* Only need to change hw state when actually enabled */
4032         if (encoder->base.crtc)
4033                 intel_encoder_dpms(encoder, mode);
4034         else
4035                 WARN_ON(encoder->connectors_active != false);
4036
4037         intel_modeset_check_state(connector->dev);
4038 }
4039
4040 /* Simple connector->get_hw_state implementation for encoders that support only
4041  * one connector and no cloning and hence the encoder state determines the state
4042  * of the connector. */
4043 bool intel_connector_get_hw_state(struct intel_connector *connector)
4044 {
4045         enum pipe pipe = 0;
4046         struct intel_encoder *encoder = connector->encoder;
4047
4048         return encoder->get_hw_state(encoder, &pipe);
4049 }
4050
4051 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4052                                       struct intel_crtc_config *pipe_config)
4053 {
4054         struct drm_device *dev = crtc->dev;
4055         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4056
4057         if (HAS_PCH_SPLIT(dev)) {
4058                 /* FDI link clock is fixed at 2.7G */
4059                 if (pipe_config->requested_mode.clock * 3
4060                     > IRONLAKE_FDI_FREQ * 4)
4061                         return false;
4062         }
4063
4064         /* All interlaced capable intel hw wants timings in frames. Note though
4065          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4066          * timings, so we need to be careful not to clobber these.*/
4067         if (!pipe_config->timings_set)
4068                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4069
4070         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4071          * with a hsync front porch of 0.
4072          */
4073         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4074                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4075                 return false;
4076
4077         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4078                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4079         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4080                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4081                  * for lvds. */
4082                 pipe_config->pipe_bpp = 8*3;
4083         }
4084
4085         return true;
4086 }
4087
4088 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4089 {
4090         return 400000; /* FIXME */
4091 }
4092
4093 static int i945_get_display_clock_speed(struct drm_device *dev)
4094 {
4095         return 400000;
4096 }
4097
4098 static int i915_get_display_clock_speed(struct drm_device *dev)
4099 {
4100         return 333000;
4101 }
4102
4103 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4104 {
4105         return 200000;
4106 }
4107
4108 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4109 {
4110         u16 gcfgc = 0;
4111
4112         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4113
4114         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4115                 return 133000;
4116         else {
4117                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4118                 case GC_DISPLAY_CLOCK_333_MHZ:
4119                         return 333000;
4120                 default:
4121                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4122                         return 190000;
4123                 }
4124         }
4125 }
4126
4127 static int i865_get_display_clock_speed(struct drm_device *dev)
4128 {
4129         return 266000;
4130 }
4131
4132 static int i855_get_display_clock_speed(struct drm_device *dev)
4133 {
4134         u16 hpllcc = 0;
4135         /* Assume that the hardware is in the high speed state.  This
4136          * should be the default.
4137          */
4138         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4139         case GC_CLOCK_133_200:
4140         case GC_CLOCK_100_200:
4141                 return 200000;
4142         case GC_CLOCK_166_250:
4143                 return 250000;
4144         case GC_CLOCK_100_133:
4145                 return 133000;
4146         }
4147
4148         /* Shouldn't happen */
4149         return 0;
4150 }
4151
4152 static int i830_get_display_clock_speed(struct drm_device *dev)
4153 {
4154         return 133000;
4155 }
4156
4157 static void
4158 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4159 {
4160         while (*num > 0xffffff || *den > 0xffffff) {
4161                 *num >>= 1;
4162                 *den >>= 1;
4163         }
4164 }
4165
4166 void
4167 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4168                        int pixel_clock, int link_clock,
4169                        struct intel_link_m_n *m_n)
4170 {
4171         m_n->tu = 64;
4172         m_n->gmch_m = bits_per_pixel * pixel_clock;
4173         m_n->gmch_n = link_clock * nlanes * 8;
4174         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4175         m_n->link_m = pixel_clock;
4176         m_n->link_n = link_clock;
4177         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4178 }
4179
4180 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4181 {
4182         if (i915_panel_use_ssc >= 0)
4183                 return i915_panel_use_ssc != 0;
4184         return dev_priv->lvds_use_ssc
4185                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4186 }
4187
4188 static int vlv_get_refclk(struct drm_crtc *crtc)
4189 {
4190         struct drm_device *dev = crtc->dev;
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         int refclk = 27000; /* for DP & HDMI */
4193
4194         return 100000; /* only one validated so far */
4195
4196         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4197                 refclk = 96000;
4198         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4199                 if (intel_panel_use_ssc(dev_priv))
4200                         refclk = 100000;
4201                 else
4202                         refclk = 96000;
4203         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4204                 refclk = 100000;
4205         }
4206
4207         return refclk;
4208 }
4209
4210 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4211 {
4212         struct drm_device *dev = crtc->dev;
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         int refclk;
4215
4216         if (IS_VALLEYVIEW(dev)) {
4217                 refclk = vlv_get_refclk(crtc);
4218         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4219             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4220                 refclk = dev_priv->lvds_ssc_freq * 1000;
4221                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4222                               refclk / 1000);
4223         } else if (!IS_GEN2(dev)) {
4224                 refclk = 96000;
4225         } else {
4226                 refclk = 48000;
4227         }
4228
4229         return refclk;
4230 }
4231
4232 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4233 {
4234         unsigned dotclock = crtc->config.adjusted_mode.clock;
4235         struct dpll *clock = &crtc->config.dpll;
4236
4237         /* SDVO TV has fixed PLL values depend on its clock range,
4238            this mirrors vbios setting. */
4239         if (dotclock >= 100000 && dotclock < 140500) {
4240                 clock->p1 = 2;
4241                 clock->p2 = 10;
4242                 clock->n = 3;
4243                 clock->m1 = 16;
4244                 clock->m2 = 8;
4245         } else if (dotclock >= 140500 && dotclock <= 200000) {
4246                 clock->p1 = 1;
4247                 clock->p2 = 10;
4248                 clock->n = 6;
4249                 clock->m1 = 12;
4250                 clock->m2 = 8;
4251         }
4252
4253         crtc->config.clock_set = true;
4254 }
4255
4256 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4257                                      intel_clock_t *reduced_clock)
4258 {
4259         struct drm_device *dev = crtc->base.dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         int pipe = crtc->pipe;
4262         u32 fp, fp2 = 0;
4263         struct dpll *clock = &crtc->config.dpll;
4264
4265         if (IS_PINEVIEW(dev)) {
4266                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4267                 if (reduced_clock)
4268                         fp2 = (1 << reduced_clock->n) << 16 |
4269                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4270         } else {
4271                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4272                 if (reduced_clock)
4273                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4274                                 reduced_clock->m2;
4275         }
4276
4277         I915_WRITE(FP0(pipe), fp);
4278
4279         crtc->lowfreq_avail = false;
4280         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4281             reduced_clock && i915_powersave) {
4282                 I915_WRITE(FP1(pipe), fp2);
4283                 crtc->lowfreq_avail = true;
4284         } else {
4285                 I915_WRITE(FP1(pipe), fp);
4286         }
4287 }
4288
4289 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4290 {
4291         u32 reg_val;
4292
4293         /*
4294          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4295          * and set it to a reasonable value instead.
4296          */
4297         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4298         reg_val &= 0xffffff00;
4299         reg_val |= 0x00000030;
4300         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4303         reg_val &= 0x8cffffff;
4304         reg_val = 0x8c000000;
4305         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306
4307         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4308         reg_val &= 0xffffff00;
4309         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4310
4311         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4312         reg_val &= 0x00ffffff;
4313         reg_val |= 0xb0000000;
4314         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4315 }
4316
4317 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4318 {
4319         if (crtc->config.has_pch_encoder)
4320                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4321         else
4322                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4323 }
4324
4325 static void vlv_update_pll(struct intel_crtc *crtc)
4326 {
4327         struct drm_device *dev = crtc->base.dev;
4328         struct drm_i915_private *dev_priv = dev->dev_private;
4329         struct drm_display_mode *adjusted_mode =
4330                 &crtc->config.adjusted_mode;
4331         struct intel_encoder *encoder;
4332         int pipe = crtc->pipe;
4333         u32 dpll, mdiv;
4334         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4335         bool is_hdmi;
4336         u32 coreclk, reg_val, temp;
4337
4338         mutex_lock(&dev_priv->dpio_lock);
4339
4340         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4341
4342         bestn = crtc->config.dpll.n;
4343         bestm1 = crtc->config.dpll.m1;
4344         bestm2 = crtc->config.dpll.m2;
4345         bestp1 = crtc->config.dpll.p1;
4346         bestp2 = crtc->config.dpll.p2;
4347
4348         /* See eDP HDMI DPIO driver vbios notes doc */
4349
4350         /* PLL B needs special handling */
4351         if (pipe)
4352                 vlv_pllb_recal_opamp(dev_priv);
4353
4354         /* Set up Tx target for periodic Rcomp update */
4355         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4356
4357         /* Disable target IRef on PLL */
4358         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4359         reg_val &= 0x00ffffff;
4360         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4361
4362         /* Disable fast lock */
4363         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4364
4365         /* Set idtafcrecal before PLL is enabled */
4366         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4367         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4368         mdiv |= ((bestn << DPIO_N_SHIFT));
4369         mdiv |= (1 << DPIO_K_SHIFT);
4370         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4371             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4372             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4373                 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4374         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4375
4376         mdiv |= DPIO_ENABLE_CALIBRATION;
4377         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4378
4379         /* Set HBR and RBR LPF coefficients */
4380         if (adjusted_mode->clock == 162000 ||
4381             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4382                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4383                                  0x005f0021);
4384         else
4385                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4386                                  0x00d0000f);
4387
4388         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4389             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4390                 /* Use SSC source */
4391                 if (!pipe)
4392                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4393                                          0x0df40000);
4394                 else
4395                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4396                                          0x0df70000);
4397         } else { /* HDMI or VGA */
4398                 /* Use bend source */
4399                 if (!pipe)
4400                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4401                                          0x0df70000);
4402                 else
4403                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4404                                          0x0df40000);
4405         }
4406
4407         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4408         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4409         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4410             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4411                 coreclk |= 0x01000000;
4412         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4413
4414         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4415
4416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4417                 if (encoder->pre_pll_enable)
4418                         encoder->pre_pll_enable(encoder);
4419
4420         /* Enable DPIO clock input */
4421         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4422                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4423         if (pipe)
4424                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4425
4426         dpll |= DPLL_VCO_ENABLE;
4427         I915_WRITE(DPLL(pipe), dpll);
4428         POSTING_READ(DPLL(pipe));
4429         udelay(150);
4430
4431         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4432                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4433
4434         if (is_hdmi) {
4435                 temp = 0;
4436                 if (crtc->config.pixel_multiplier > 1) {
4437                         temp = (crtc->config.pixel_multiplier - 1)
4438                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4439                 }
4440
4441                 I915_WRITE(DPLL_MD(pipe), temp);
4442                 POSTING_READ(DPLL_MD(pipe));
4443         }
4444
4445         if (crtc->config.has_dp_encoder)
4446                 intel_dp_set_m_n(crtc);
4447
4448         mutex_unlock(&dev_priv->dpio_lock);
4449 }
4450
4451 static void i9xx_update_pll(struct intel_crtc *crtc,
4452                             intel_clock_t *reduced_clock,
4453                             int num_connectors)
4454 {
4455         struct drm_device *dev = crtc->base.dev;
4456         struct drm_i915_private *dev_priv = dev->dev_private;
4457         struct intel_encoder *encoder;
4458         int pipe = crtc->pipe;
4459         u32 dpll;
4460         bool is_sdvo;
4461         struct dpll *clock = &crtc->config.dpll;
4462
4463         i9xx_update_pll_dividers(crtc, reduced_clock);
4464
4465         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4466                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4467
4468         dpll = DPLL_VGA_MODE_DIS;
4469
4470         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4471                 dpll |= DPLLB_MODE_LVDS;
4472         else
4473                 dpll |= DPLLB_MODE_DAC_SERIAL;
4474
4475         if (is_sdvo) {
4476                 if ((crtc->config.pixel_multiplier > 1) &&
4477                     (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4478                         dpll |= (crtc->config.pixel_multiplier - 1)
4479                                 << SDVO_MULTIPLIER_SHIFT_HIRES;
4480                 }
4481                 dpll |= DPLL_DVO_HIGH_SPEED;
4482         }
4483         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4484                 dpll |= DPLL_DVO_HIGH_SPEED;
4485
4486         /* compute bitmask from p1 value */
4487         if (IS_PINEVIEW(dev))
4488                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4489         else {
4490                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4491                 if (IS_G4X(dev) && reduced_clock)
4492                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4493         }
4494         switch (clock->p2) {
4495         case 5:
4496                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4497                 break;
4498         case 7:
4499                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4500                 break;
4501         case 10:
4502                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4503                 break;
4504         case 14:
4505                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4506                 break;
4507         }
4508         if (INTEL_INFO(dev)->gen >= 4)
4509                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4510
4511         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4512                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4513         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4514                 /* XXX: just matching BIOS for now */
4515                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4516                 dpll |= 3;
4517         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4518                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4519                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4520         else
4521                 dpll |= PLL_REF_INPUT_DREFCLK;
4522
4523         dpll |= DPLL_VCO_ENABLE;
4524         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4525         POSTING_READ(DPLL(pipe));
4526         udelay(150);
4527
4528         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4529                 if (encoder->pre_pll_enable)
4530                         encoder->pre_pll_enable(encoder);
4531
4532         if (crtc->config.has_dp_encoder)
4533                 intel_dp_set_m_n(crtc);
4534
4535         I915_WRITE(DPLL(pipe), dpll);
4536
4537         /* Wait for the clocks to stabilize. */
4538         POSTING_READ(DPLL(pipe));
4539         udelay(150);
4540
4541         if (INTEL_INFO(dev)->gen >= 4) {
4542                 u32 temp = 0;
4543                 if (is_sdvo) {
4544                         temp = 0;
4545                         if (crtc->config.pixel_multiplier > 1) {
4546                                 temp = (crtc->config.pixel_multiplier - 1)
4547                                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4548                         }
4549                 }
4550                 I915_WRITE(DPLL_MD(pipe), temp);
4551         } else {
4552                 /* The pixel multiplier can only be updated once the
4553                  * DPLL is enabled and the clocks are stable.
4554                  *
4555                  * So write it again.
4556                  */
4557                 I915_WRITE(DPLL(pipe), dpll);
4558         }
4559 }
4560
4561 static void i8xx_update_pll(struct intel_crtc *crtc,
4562                             struct drm_display_mode *adjusted_mode,
4563                             intel_clock_t *reduced_clock,
4564                             int num_connectors)
4565 {
4566         struct drm_device *dev = crtc->base.dev;
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568         struct intel_encoder *encoder;
4569         int pipe = crtc->pipe;
4570         u32 dpll;
4571         struct dpll *clock = &crtc->config.dpll;
4572
4573         i9xx_update_pll_dividers(crtc, reduced_clock);
4574
4575         dpll = DPLL_VGA_MODE_DIS;
4576
4577         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4578                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4579         } else {
4580                 if (clock->p1 == 2)
4581                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4582                 else
4583                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4584                 if (clock->p2 == 4)
4585                         dpll |= PLL_P2_DIVIDE_BY_4;
4586         }
4587
4588         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4589                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4591         else
4592                 dpll |= PLL_REF_INPUT_DREFCLK;
4593
4594         dpll |= DPLL_VCO_ENABLE;
4595         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4596         POSTING_READ(DPLL(pipe));
4597         udelay(150);
4598
4599         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4600                 if (encoder->pre_pll_enable)
4601                         encoder->pre_pll_enable(encoder);
4602
4603         I915_WRITE(DPLL(pipe), dpll);
4604
4605         /* Wait for the clocks to stabilize. */
4606         POSTING_READ(DPLL(pipe));
4607         udelay(150);
4608
4609         /* The pixel multiplier can only be updated once the
4610          * DPLL is enabled and the clocks are stable.
4611          *
4612          * So write it again.
4613          */
4614         I915_WRITE(DPLL(pipe), dpll);
4615 }
4616
4617 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4618                                    struct drm_display_mode *mode,
4619                                    struct drm_display_mode *adjusted_mode)
4620 {
4621         struct drm_device *dev = intel_crtc->base.dev;
4622         struct drm_i915_private *dev_priv = dev->dev_private;
4623         enum pipe pipe = intel_crtc->pipe;
4624         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4625         uint32_t vsyncshift;
4626
4627         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4628                 /* the chip adds 2 halflines automatically */
4629                 adjusted_mode->crtc_vtotal -= 1;
4630                 adjusted_mode->crtc_vblank_end -= 1;
4631                 vsyncshift = adjusted_mode->crtc_hsync_start
4632                              - adjusted_mode->crtc_htotal / 2;
4633         } else {
4634                 vsyncshift = 0;
4635         }
4636
4637         if (INTEL_INFO(dev)->gen > 3)
4638                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4639
4640         I915_WRITE(HTOTAL(cpu_transcoder),
4641                    (adjusted_mode->crtc_hdisplay - 1) |
4642                    ((adjusted_mode->crtc_htotal - 1) << 16));
4643         I915_WRITE(HBLANK(cpu_transcoder),
4644                    (adjusted_mode->crtc_hblank_start - 1) |
4645                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4646         I915_WRITE(HSYNC(cpu_transcoder),
4647                    (adjusted_mode->crtc_hsync_start - 1) |
4648                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4649
4650         I915_WRITE(VTOTAL(cpu_transcoder),
4651                    (adjusted_mode->crtc_vdisplay - 1) |
4652                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4653         I915_WRITE(VBLANK(cpu_transcoder),
4654                    (adjusted_mode->crtc_vblank_start - 1) |
4655                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4656         I915_WRITE(VSYNC(cpu_transcoder),
4657                    (adjusted_mode->crtc_vsync_start - 1) |
4658                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4659
4660         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4661          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4662          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4663          * bits. */
4664         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4665             (pipe == PIPE_B || pipe == PIPE_C))
4666                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4667
4668         /* pipesrc controls the size that is scaled from, which should
4669          * always be the user's requested size.
4670          */
4671         I915_WRITE(PIPESRC(pipe),
4672                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4673 }
4674
4675 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4676 {
4677         struct drm_device *dev = intel_crtc->base.dev;
4678         struct drm_i915_private *dev_priv = dev->dev_private;
4679         uint32_t pipeconf;
4680
4681         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4682
4683         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4684                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4685                  * core speed.
4686                  *
4687                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4688                  * pipe == 0 check?
4689                  */
4690                 if (intel_crtc->config.requested_mode.clock >
4691                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4692                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4693                 else
4694                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4695         }
4696
4697         /* default to 8bpc */
4698         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4699         if (intel_crtc->config.has_dp_encoder) {
4700                 if (intel_crtc->config.dither) {
4701                         pipeconf |= PIPECONF_6BPC |
4702                                     PIPECONF_DITHER_EN |
4703                                     PIPECONF_DITHER_TYPE_SP;
4704                 }
4705         }
4706
4707         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4708                                                       INTEL_OUTPUT_EDP)) {
4709                 if (intel_crtc->config.dither) {
4710                         pipeconf |= PIPECONF_6BPC |
4711                                         PIPECONF_ENABLE |
4712                                         I965_PIPECONF_ACTIVE;
4713                 }
4714         }
4715
4716         if (HAS_PIPE_CXSR(dev)) {
4717                 if (intel_crtc->lowfreq_avail) {
4718                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4719                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4720                 } else {
4721                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4722                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4723                 }
4724         }
4725
4726         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4727         if (!IS_GEN2(dev) &&
4728             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4729                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4730         else
4731                 pipeconf |= PIPECONF_PROGRESSIVE;
4732
4733         if (IS_VALLEYVIEW(dev)) {
4734                 if (intel_crtc->config.limited_color_range)
4735                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4736                 else
4737                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4738         }
4739
4740         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4741         POSTING_READ(PIPECONF(intel_crtc->pipe));
4742 }
4743
4744 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4745                               int x, int y,
4746                               struct drm_framebuffer *fb)
4747 {
4748         struct drm_device *dev = crtc->dev;
4749         struct drm_i915_private *dev_priv = dev->dev_private;
4750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4751         struct drm_display_mode *adjusted_mode =
4752                 &intel_crtc->config.adjusted_mode;
4753         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4754         int pipe = intel_crtc->pipe;
4755         int plane = intel_crtc->plane;
4756         int refclk, num_connectors = 0;
4757         intel_clock_t clock, reduced_clock;
4758         u32 dspcntr;
4759         bool ok, has_reduced_clock = false, is_sdvo = false;
4760         bool is_lvds = false, is_tv = false;
4761         struct intel_encoder *encoder;
4762         const intel_limit_t *limit;
4763         int ret;
4764
4765         for_each_encoder_on_crtc(dev, crtc, encoder) {
4766                 switch (encoder->type) {
4767                 case INTEL_OUTPUT_LVDS:
4768                         is_lvds = true;
4769                         break;
4770                 case INTEL_OUTPUT_SDVO:
4771                 case INTEL_OUTPUT_HDMI:
4772                         is_sdvo = true;
4773                         if (encoder->needs_tv_clock)
4774                                 is_tv = true;
4775                         break;
4776                 case INTEL_OUTPUT_TVOUT:
4777                         is_tv = true;
4778                         break;
4779                 }
4780
4781                 num_connectors++;
4782         }
4783
4784         refclk = i9xx_get_refclk(crtc, num_connectors);
4785
4786         /*
4787          * Returns a set of divisors for the desired target clock with the given
4788          * refclk, or FALSE.  The returned values represent the clock equation:
4789          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4790          */
4791         limit = intel_limit(crtc, refclk);
4792         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4793                              &clock);
4794         if (!ok) {
4795                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4796                 return -EINVAL;
4797         }
4798
4799         /* Ensure that the cursor is valid for the new mode before changing... */
4800         intel_crtc_update_cursor(crtc, true);
4801
4802         if (is_lvds && dev_priv->lvds_downclock_avail) {
4803                 /*
4804                  * Ensure we match the reduced clock's P to the target clock.
4805                  * If the clocks don't match, we can't switch the display clock
4806                  * by using the FP0/FP1. In such case we will disable the LVDS
4807                  * downclock feature.
4808                 */
4809                 has_reduced_clock = limit->find_pll(limit, crtc,
4810                                                     dev_priv->lvds_downclock,
4811                                                     refclk,
4812                                                     &clock,
4813                                                     &reduced_clock);
4814         }
4815         /* Compat-code for transition, will disappear. */
4816         if (!intel_crtc->config.clock_set) {
4817                 intel_crtc->config.dpll.n = clock.n;
4818                 intel_crtc->config.dpll.m1 = clock.m1;
4819                 intel_crtc->config.dpll.m2 = clock.m2;
4820                 intel_crtc->config.dpll.p1 = clock.p1;
4821                 intel_crtc->config.dpll.p2 = clock.p2;
4822         }
4823
4824         if (is_sdvo && is_tv)
4825                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4826
4827         if (IS_GEN2(dev))
4828                 i8xx_update_pll(intel_crtc, adjusted_mode,
4829                                 has_reduced_clock ? &reduced_clock : NULL,
4830                                 num_connectors);
4831         else if (IS_VALLEYVIEW(dev))
4832                 vlv_update_pll(intel_crtc);
4833         else
4834                 i9xx_update_pll(intel_crtc,
4835                                 has_reduced_clock ? &reduced_clock : NULL,
4836                                 num_connectors);
4837
4838         /* Set up the display plane register */
4839         dspcntr = DISPPLANE_GAMMA_ENABLE;
4840
4841         if (!IS_VALLEYVIEW(dev)) {
4842                 if (pipe == 0)
4843                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4844                 else
4845                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4846         }
4847
4848         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4849         drm_mode_debug_printmodeline(mode);
4850
4851         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4852
4853         /* pipesrc and dspsize control the size that is scaled from,
4854          * which should always be the user's requested size.
4855          */
4856         I915_WRITE(DSPSIZE(plane),
4857                    ((mode->vdisplay - 1) << 16) |
4858                    (mode->hdisplay - 1));
4859         I915_WRITE(DSPPOS(plane), 0);
4860
4861         i9xx_set_pipeconf(intel_crtc);
4862
4863         I915_WRITE(DSPCNTR(plane), dspcntr);
4864         POSTING_READ(DSPCNTR(plane));
4865
4866         ret = intel_pipe_set_base(crtc, x, y, fb);
4867
4868         intel_update_watermarks(dev);
4869
4870         return ret;
4871 }
4872
4873 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4874                                  struct intel_crtc_config *pipe_config)
4875 {
4876         struct drm_device *dev = crtc->base.dev;
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         uint32_t tmp;
4879
4880         tmp = I915_READ(PIPECONF(crtc->pipe));
4881         if (!(tmp & PIPECONF_ENABLE))
4882                 return false;
4883
4884         return true;
4885 }
4886
4887 static void ironlake_init_pch_refclk(struct drm_device *dev)
4888 {
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         struct drm_mode_config *mode_config = &dev->mode_config;
4891         struct intel_encoder *encoder;
4892         u32 val, final;
4893         bool has_lvds = false;
4894         bool has_cpu_edp = false;
4895         bool has_pch_edp = false;
4896         bool has_panel = false;
4897         bool has_ck505 = false;
4898         bool can_ssc = false;
4899
4900         /* We need to take the global config into account */
4901         list_for_each_entry(encoder, &mode_config->encoder_list,
4902                             base.head) {
4903                 switch (encoder->type) {
4904                 case INTEL_OUTPUT_LVDS:
4905                         has_panel = true;
4906                         has_lvds = true;
4907                         break;
4908                 case INTEL_OUTPUT_EDP:
4909                         has_panel = true;
4910                         if (intel_encoder_is_pch_edp(&encoder->base))
4911                                 has_pch_edp = true;
4912                         else
4913                                 has_cpu_edp = true;
4914                         break;
4915                 }
4916         }
4917
4918         if (HAS_PCH_IBX(dev)) {
4919                 has_ck505 = dev_priv->display_clock_mode;
4920                 can_ssc = has_ck505;
4921         } else {
4922                 has_ck505 = false;
4923                 can_ssc = true;
4924         }
4925
4926         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4927                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4928                       has_ck505);
4929
4930         /* Ironlake: try to setup display ref clock before DPLL
4931          * enabling. This is only under driver's control after
4932          * PCH B stepping, previous chipset stepping should be
4933          * ignoring this setting.
4934          */
4935         val = I915_READ(PCH_DREF_CONTROL);
4936
4937         /* As we must carefully and slowly disable/enable each source in turn,
4938          * compute the final state we want first and check if we need to
4939          * make any changes at all.
4940          */
4941         final = val;
4942         final &= ~DREF_NONSPREAD_SOURCE_MASK;
4943         if (has_ck505)
4944                 final |= DREF_NONSPREAD_CK505_ENABLE;
4945         else
4946                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4947
4948         final &= ~DREF_SSC_SOURCE_MASK;
4949         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4950         final &= ~DREF_SSC1_ENABLE;
4951
4952         if (has_panel) {
4953                 final |= DREF_SSC_SOURCE_ENABLE;
4954
4955                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4956                         final |= DREF_SSC1_ENABLE;
4957
4958                 if (has_cpu_edp) {
4959                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
4960                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4961                         else
4962                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4963                 } else
4964                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4965         } else {
4966                 final |= DREF_SSC_SOURCE_DISABLE;
4967                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968         }
4969
4970         if (final == val)
4971                 return;
4972
4973         /* Always enable nonspread source */
4974         val &= ~DREF_NONSPREAD_SOURCE_MASK;
4975
4976         if (has_ck505)
4977                 val |= DREF_NONSPREAD_CK505_ENABLE;
4978         else
4979                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4980
4981         if (has_panel) {
4982                 val &= ~DREF_SSC_SOURCE_MASK;
4983                 val |= DREF_SSC_SOURCE_ENABLE;
4984
4985                 /* SSC must be turned on before enabling the CPU output  */
4986                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4987                         DRM_DEBUG_KMS("Using SSC on panel\n");
4988                         val |= DREF_SSC1_ENABLE;
4989                 } else
4990                         val &= ~DREF_SSC1_ENABLE;
4991
4992                 /* Get SSC going before enabling the outputs */
4993                 I915_WRITE(PCH_DREF_CONTROL, val);
4994                 POSTING_READ(PCH_DREF_CONTROL);
4995                 udelay(200);
4996
4997                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4998
4999                 /* Enable CPU source on CPU attached eDP */
5000                 if (has_cpu_edp) {
5001                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5002                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5003                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5004                         }
5005                         else
5006                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5007                 } else
5008                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5009
5010                 I915_WRITE(PCH_DREF_CONTROL, val);
5011                 POSTING_READ(PCH_DREF_CONTROL);
5012                 udelay(200);
5013         } else {
5014                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5015
5016                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5017
5018                 /* Turn off CPU output */
5019                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5020
5021                 I915_WRITE(PCH_DREF_CONTROL, val);
5022                 POSTING_READ(PCH_DREF_CONTROL);
5023                 udelay(200);
5024
5025                 /* Turn off the SSC source */
5026                 val &= ~DREF_SSC_SOURCE_MASK;
5027                 val |= DREF_SSC_SOURCE_DISABLE;
5028
5029                 /* Turn off SSC1 */
5030                 val &= ~DREF_SSC1_ENABLE;
5031
5032                 I915_WRITE(PCH_DREF_CONTROL, val);
5033                 POSTING_READ(PCH_DREF_CONTROL);
5034                 udelay(200);
5035         }
5036
5037         BUG_ON(val != final);
5038 }
5039
5040 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5041 static void lpt_init_pch_refclk(struct drm_device *dev)
5042 {
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         struct drm_mode_config *mode_config = &dev->mode_config;
5045         struct intel_encoder *encoder;
5046         bool has_vga = false;
5047         bool is_sdv = false;
5048         u32 tmp;
5049
5050         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5051                 switch (encoder->type) {
5052                 case INTEL_OUTPUT_ANALOG:
5053                         has_vga = true;
5054                         break;
5055                 }
5056         }
5057
5058         if (!has_vga)
5059                 return;
5060
5061         mutex_lock(&dev_priv->dpio_lock);
5062
5063         /* XXX: Rip out SDV support once Haswell ships for real. */
5064         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5065                 is_sdv = true;
5066
5067         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5068         tmp &= ~SBI_SSCCTL_DISABLE;
5069         tmp |= SBI_SSCCTL_PATHALT;
5070         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5071
5072         udelay(24);
5073
5074         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5075         tmp &= ~SBI_SSCCTL_PATHALT;
5076         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5077
5078         if (!is_sdv) {
5079                 tmp = I915_READ(SOUTH_CHICKEN2);
5080                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5081                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5082
5083                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5084                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5085                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5086
5087                 tmp = I915_READ(SOUTH_CHICKEN2);
5088                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5089                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5090
5091                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5092                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5093                                        100))
5094                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5095         }
5096
5097         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5098         tmp &= ~(0xFF << 24);
5099         tmp |= (0x12 << 24);
5100         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5101
5102         if (is_sdv) {
5103                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5104                 tmp |= 0x7FFF;
5105                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5106         }
5107
5108         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5109         tmp |= (1 << 11);
5110         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5111
5112         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5113         tmp |= (1 << 11);
5114         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5115
5116         if (is_sdv) {
5117                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5118                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5119                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5120
5121                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5122                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5123                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5124
5125                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5126                 tmp |= (0x3F << 8);
5127                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5128
5129                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5130                 tmp |= (0x3F << 8);
5131                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5132         }
5133
5134         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5135         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5136         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5137
5138         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5139         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5140         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5141
5142         if (!is_sdv) {
5143                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5144                 tmp &= ~(7 << 13);
5145                 tmp |= (5 << 13);
5146                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5147
5148                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5149                 tmp &= ~(7 << 13);
5150                 tmp |= (5 << 13);
5151                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5152         }
5153
5154         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5155         tmp &= ~0xFF;
5156         tmp |= 0x1C;
5157         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5158
5159         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5160         tmp &= ~0xFF;
5161         tmp |= 0x1C;
5162         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5163
5164         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5165         tmp &= ~(0xFF << 16);
5166         tmp |= (0x1C << 16);
5167         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5168
5169         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5170         tmp &= ~(0xFF << 16);
5171         tmp |= (0x1C << 16);
5172         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5173
5174         if (!is_sdv) {
5175                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5176                 tmp |= (1 << 27);
5177                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5178
5179                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5180                 tmp |= (1 << 27);
5181                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5182
5183                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5184                 tmp &= ~(0xF << 28);
5185                 tmp |= (4 << 28);
5186                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5187
5188                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5189                 tmp &= ~(0xF << 28);
5190                 tmp |= (4 << 28);
5191                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5192         }
5193
5194         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5195         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5196         tmp |= SBI_DBUFF0_ENABLE;
5197         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5198
5199         mutex_unlock(&dev_priv->dpio_lock);
5200 }
5201
5202 /*
5203  * Initialize reference clocks when the driver loads
5204  */
5205 void intel_init_pch_refclk(struct drm_device *dev)
5206 {
5207         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5208                 ironlake_init_pch_refclk(dev);
5209         else if (HAS_PCH_LPT(dev))
5210                 lpt_init_pch_refclk(dev);
5211 }
5212
5213 static int ironlake_get_refclk(struct drm_crtc *crtc)
5214 {
5215         struct drm_device *dev = crtc->dev;
5216         struct drm_i915_private *dev_priv = dev->dev_private;
5217         struct intel_encoder *encoder;
5218         struct intel_encoder *edp_encoder = NULL;
5219         int num_connectors = 0;
5220         bool is_lvds = false;
5221
5222         for_each_encoder_on_crtc(dev, crtc, encoder) {
5223                 switch (encoder->type) {
5224                 case INTEL_OUTPUT_LVDS:
5225                         is_lvds = true;
5226                         break;
5227                 case INTEL_OUTPUT_EDP:
5228                         edp_encoder = encoder;
5229                         break;
5230                 }
5231                 num_connectors++;
5232         }
5233
5234         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5235                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5236                               dev_priv->lvds_ssc_freq);
5237                 return dev_priv->lvds_ssc_freq * 1000;
5238         }
5239
5240         return 120000;
5241 }
5242
5243 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5244                                   struct drm_display_mode *adjusted_mode,
5245                                   bool dither)
5246 {
5247         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249         int pipe = intel_crtc->pipe;
5250         uint32_t val;
5251
5252         val = I915_READ(PIPECONF(pipe));
5253
5254         val &= ~PIPECONF_BPC_MASK;
5255         switch (intel_crtc->config.pipe_bpp) {
5256         case 18:
5257                 val |= PIPECONF_6BPC;
5258                 break;
5259         case 24:
5260                 val |= PIPECONF_8BPC;
5261                 break;
5262         case 30:
5263                 val |= PIPECONF_10BPC;
5264                 break;
5265         case 36:
5266                 val |= PIPECONF_12BPC;
5267                 break;
5268         default:
5269                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5270                 BUG();
5271         }
5272
5273         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5274         if (dither)
5275                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5276
5277         val &= ~PIPECONF_INTERLACE_MASK;
5278         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5279                 val |= PIPECONF_INTERLACED_ILK;
5280         else
5281                 val |= PIPECONF_PROGRESSIVE;
5282
5283         if (intel_crtc->config.limited_color_range)
5284                 val |= PIPECONF_COLOR_RANGE_SELECT;
5285         else
5286                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5287
5288         I915_WRITE(PIPECONF(pipe), val);
5289         POSTING_READ(PIPECONF(pipe));
5290 }
5291
5292 /*
5293  * Set up the pipe CSC unit.
5294  *
5295  * Currently only full range RGB to limited range RGB conversion
5296  * is supported, but eventually this should handle various
5297  * RGB<->YCbCr scenarios as well.
5298  */
5299 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5300 {
5301         struct drm_device *dev = crtc->dev;
5302         struct drm_i915_private *dev_priv = dev->dev_private;
5303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304         int pipe = intel_crtc->pipe;
5305         uint16_t coeff = 0x7800; /* 1.0 */
5306
5307         /*
5308          * TODO: Check what kind of values actually come out of the pipe
5309          * with these coeff/postoff values and adjust to get the best
5310          * accuracy. Perhaps we even need to take the bpc value into
5311          * consideration.
5312          */
5313
5314         if (intel_crtc->config.limited_color_range)
5315                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5316
5317         /*
5318          * GY/GU and RY/RU should be the other way around according
5319          * to BSpec, but reality doesn't agree. Just set them up in
5320          * a way that results in the correct picture.
5321          */
5322         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5323         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5324
5325         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5326         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5327
5328         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5329         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5330
5331         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5332         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5333         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5334
5335         if (INTEL_INFO(dev)->gen > 6) {
5336                 uint16_t postoff = 0;
5337
5338                 if (intel_crtc->config.limited_color_range)
5339                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5340
5341                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5342                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5343                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5344
5345                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5346         } else {
5347                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5348
5349                 if (intel_crtc->config.limited_color_range)
5350                         mode |= CSC_BLACK_SCREEN_OFFSET;
5351
5352                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5353         }
5354 }
5355
5356 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5357                                  struct drm_display_mode *adjusted_mode,
5358                                  bool dither)
5359 {
5360         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5362         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5363         uint32_t val;
5364
5365         val = I915_READ(PIPECONF(cpu_transcoder));
5366
5367         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5368         if (dither)
5369                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5370
5371         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5372         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5373                 val |= PIPECONF_INTERLACED_ILK;
5374         else
5375                 val |= PIPECONF_PROGRESSIVE;
5376
5377         I915_WRITE(PIPECONF(cpu_transcoder), val);
5378         POSTING_READ(PIPECONF(cpu_transcoder));
5379 }
5380
5381 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5382                                     struct drm_display_mode *adjusted_mode,
5383                                     intel_clock_t *clock,
5384                                     bool *has_reduced_clock,
5385                                     intel_clock_t *reduced_clock)
5386 {
5387         struct drm_device *dev = crtc->dev;
5388         struct drm_i915_private *dev_priv = dev->dev_private;
5389         struct intel_encoder *intel_encoder;
5390         int refclk;
5391         const intel_limit_t *limit;
5392         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5393
5394         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5395                 switch (intel_encoder->type) {
5396                 case INTEL_OUTPUT_LVDS:
5397                         is_lvds = true;
5398                         break;
5399                 case INTEL_OUTPUT_SDVO:
5400                 case INTEL_OUTPUT_HDMI:
5401                         is_sdvo = true;
5402                         if (intel_encoder->needs_tv_clock)
5403                                 is_tv = true;
5404                         break;
5405                 case INTEL_OUTPUT_TVOUT:
5406                         is_tv = true;
5407                         break;
5408                 }
5409         }
5410
5411         refclk = ironlake_get_refclk(crtc);
5412
5413         /*
5414          * Returns a set of divisors for the desired target clock with the given
5415          * refclk, or FALSE.  The returned values represent the clock equation:
5416          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5417          */
5418         limit = intel_limit(crtc, refclk);
5419         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5420                               clock);
5421         if (!ret)
5422                 return false;
5423
5424         if (is_lvds && dev_priv->lvds_downclock_avail) {
5425                 /*
5426                  * Ensure we match the reduced clock's P to the target clock.
5427                  * If the clocks don't match, we can't switch the display clock
5428                  * by using the FP0/FP1. In such case we will disable the LVDS
5429                  * downclock feature.
5430                 */
5431                 *has_reduced_clock = limit->find_pll(limit, crtc,
5432                                                      dev_priv->lvds_downclock,
5433                                                      refclk,
5434                                                      clock,
5435                                                      reduced_clock);
5436         }
5437
5438         if (is_sdvo && is_tv)
5439                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5440
5441         return true;
5442 }
5443
5444 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5445 {
5446         struct drm_i915_private *dev_priv = dev->dev_private;
5447         uint32_t temp;
5448
5449         temp = I915_READ(SOUTH_CHICKEN1);
5450         if (temp & FDI_BC_BIFURCATION_SELECT)
5451                 return;
5452
5453         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5454         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5455
5456         temp |= FDI_BC_BIFURCATION_SELECT;
5457         DRM_DEBUG_KMS("enabling fdi C rx\n");
5458         I915_WRITE(SOUTH_CHICKEN1, temp);
5459         POSTING_READ(SOUTH_CHICKEN1);
5460 }
5461
5462 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5463 {
5464         struct drm_device *dev = intel_crtc->base.dev;
5465         struct drm_i915_private *dev_priv = dev->dev_private;
5466         struct intel_crtc *pipe_B_crtc =
5467                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5468
5469         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5470                       pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5471         if (intel_crtc->fdi_lanes > 4) {
5472                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5473                               pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5474                 /* Clamp lanes to avoid programming the hw with bogus values. */
5475                 intel_crtc->fdi_lanes = 4;
5476
5477                 return false;
5478         }
5479
5480         if (INTEL_INFO(dev)->num_pipes == 2)
5481                 return true;
5482
5483         switch (intel_crtc->pipe) {
5484         case PIPE_A:
5485                 return true;
5486         case PIPE_B:
5487                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5488                     intel_crtc->fdi_lanes > 2) {
5489                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5490                                       pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5491                         /* Clamp lanes to avoid programming the hw with bogus values. */
5492                         intel_crtc->fdi_lanes = 2;
5493
5494                         return false;
5495                 }
5496
5497                 if (intel_crtc->fdi_lanes > 2)
5498                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5499                 else
5500                         cpt_enable_fdi_bc_bifurcation(dev);
5501
5502                 return true;
5503         case PIPE_C:
5504                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5505                         if (intel_crtc->fdi_lanes > 2) {
5506                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5507                                               pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5508                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5509                                 intel_crtc->fdi_lanes = 2;
5510
5511                                 return false;
5512                         }
5513                 } else {
5514                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5515                         return false;
5516                 }
5517
5518                 cpt_enable_fdi_bc_bifurcation(dev);
5519
5520                 return true;
5521         default:
5522                 BUG();
5523         }
5524 }
5525
5526 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5527 {
5528         /*
5529          * Account for spread spectrum to avoid
5530          * oversubscribing the link. Max center spread
5531          * is 2.5%; use 5% for safety's sake.
5532          */
5533         u32 bps = target_clock * bpp * 21 / 20;
5534         return bps / (link_bw * 8) + 1;
5535 }
5536
5537 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5538                                   struct intel_link_m_n *m_n)
5539 {
5540         struct drm_device *dev = crtc->base.dev;
5541         struct drm_i915_private *dev_priv = dev->dev_private;
5542         int pipe = crtc->pipe;
5543
5544         I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5545         I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5546         I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5547         I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5548 }
5549
5550 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5551                                   struct intel_link_m_n *m_n)
5552 {
5553         struct drm_device *dev = crtc->base.dev;
5554         struct drm_i915_private *dev_priv = dev->dev_private;
5555         int pipe = crtc->pipe;
5556         enum transcoder transcoder = crtc->config.cpu_transcoder;
5557
5558         if (INTEL_INFO(dev)->gen >= 5) {
5559                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5560                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5561                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5562                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5563         } else {
5564                 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5565                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5566                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5567                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5568         }
5569 }
5570
5571 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5572 {
5573         struct drm_device *dev = crtc->dev;
5574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575         struct drm_display_mode *adjusted_mode =
5576                 &intel_crtc->config.adjusted_mode;
5577         struct intel_link_m_n m_n = {0};
5578         int target_clock, lane, link_bw;
5579
5580         /* FDI is a binary signal running at ~2.7GHz, encoding
5581          * each output octet as 10 bits. The actual frequency
5582          * is stored as a divider into a 100MHz clock, and the
5583          * mode pixel clock is stored in units of 1KHz.
5584          * Hence the bw of each lane in terms of the mode signal
5585          * is:
5586          */
5587         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5588
5589         if (intel_crtc->config.pixel_target_clock)
5590                 target_clock = intel_crtc->config.pixel_target_clock;
5591         else
5592                 target_clock = adjusted_mode->clock;
5593
5594         lane = ironlake_get_lanes_required(target_clock, link_bw,
5595                                            intel_crtc->config.pipe_bpp);
5596
5597         intel_crtc->fdi_lanes = lane;
5598
5599         if (intel_crtc->config.pixel_multiplier > 1)
5600                 link_bw *= intel_crtc->config.pixel_multiplier;
5601         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5602                                link_bw, &m_n);
5603
5604         intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5605 }
5606
5607 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5608                                       intel_clock_t *clock, u32 *fp,
5609                                       intel_clock_t *reduced_clock, u32 *fp2)
5610 {
5611         struct drm_crtc *crtc = &intel_crtc->base;
5612         struct drm_device *dev = crtc->dev;
5613         struct drm_i915_private *dev_priv = dev->dev_private;
5614         struct intel_encoder *intel_encoder;
5615         uint32_t dpll;
5616         int factor, num_connectors = 0;
5617         bool is_lvds = false, is_sdvo = false, is_tv = false;
5618
5619         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5620                 switch (intel_encoder->type) {
5621                 case INTEL_OUTPUT_LVDS:
5622                         is_lvds = true;
5623                         break;
5624                 case INTEL_OUTPUT_SDVO:
5625                 case INTEL_OUTPUT_HDMI:
5626                         is_sdvo = true;
5627                         if (intel_encoder->needs_tv_clock)
5628                                 is_tv = true;
5629                         break;
5630                 case INTEL_OUTPUT_TVOUT:
5631                         is_tv = true;
5632                         break;
5633                 }
5634
5635                 num_connectors++;
5636         }
5637
5638         /* Enable autotuning of the PLL clock (if permissible) */
5639         factor = 21;
5640         if (is_lvds) {
5641                 if ((intel_panel_use_ssc(dev_priv) &&
5642                      dev_priv->lvds_ssc_freq == 100) ||
5643                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5644                         factor = 25;
5645         } else if (is_sdvo && is_tv)
5646                 factor = 20;
5647
5648         if (clock->m < factor * clock->n)
5649                 *fp |= FP_CB_TUNE;
5650
5651         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5652                 *fp2 |= FP_CB_TUNE;
5653
5654         dpll = 0;
5655
5656         if (is_lvds)
5657                 dpll |= DPLLB_MODE_LVDS;
5658         else
5659                 dpll |= DPLLB_MODE_DAC_SERIAL;
5660         if (is_sdvo) {
5661                 if (intel_crtc->config.pixel_multiplier > 1) {
5662                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5663                                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5664                 }
5665                 dpll |= DPLL_DVO_HIGH_SPEED;
5666         }
5667         if (intel_crtc->config.has_dp_encoder &&
5668             intel_crtc->config.has_pch_encoder)
5669                 dpll |= DPLL_DVO_HIGH_SPEED;
5670
5671         /* compute bitmask from p1 value */
5672         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5673         /* also FPA1 */
5674         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5675
5676         switch (clock->p2) {
5677         case 5:
5678                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5679                 break;
5680         case 7:
5681                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5682                 break;
5683         case 10:
5684                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5685                 break;
5686         case 14:
5687                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5688                 break;
5689         }
5690
5691         if (is_sdvo && is_tv)
5692                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5693         else if (is_tv)
5694                 /* XXX: just matching BIOS for now */
5695                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5696                 dpll |= 3;
5697         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5698                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5699         else
5700                 dpll |= PLL_REF_INPUT_DREFCLK;
5701
5702         return dpll;
5703 }
5704
5705 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5706                                   int x, int y,
5707                                   struct drm_framebuffer *fb)
5708 {
5709         struct drm_device *dev = crtc->dev;
5710         struct drm_i915_private *dev_priv = dev->dev_private;
5711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712         struct drm_display_mode *adjusted_mode =
5713                 &intel_crtc->config.adjusted_mode;
5714         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5715         int pipe = intel_crtc->pipe;
5716         int plane = intel_crtc->plane;
5717         int num_connectors = 0;
5718         intel_clock_t clock, reduced_clock;
5719         u32 dpll, fp = 0, fp2 = 0;
5720         bool ok, has_reduced_clock = false;
5721         bool is_lvds = false;
5722         struct intel_encoder *encoder;
5723         int ret;
5724         bool dither, fdi_config_ok;
5725
5726         for_each_encoder_on_crtc(dev, crtc, encoder) {
5727                 switch (encoder->type) {
5728                 case INTEL_OUTPUT_LVDS:
5729                         is_lvds = true;
5730                         break;
5731                 }
5732
5733                 num_connectors++;
5734         }
5735
5736         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5737              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5738
5739         intel_crtc->config.cpu_transcoder = pipe;
5740
5741         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5742                                      &has_reduced_clock, &reduced_clock);
5743         if (!ok) {
5744                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5745                 return -EINVAL;
5746         }
5747         /* Compat-code for transition, will disappear. */
5748         if (!intel_crtc->config.clock_set) {
5749                 intel_crtc->config.dpll.n = clock.n;
5750                 intel_crtc->config.dpll.m1 = clock.m1;
5751                 intel_crtc->config.dpll.m2 = clock.m2;
5752                 intel_crtc->config.dpll.p1 = clock.p1;
5753                 intel_crtc->config.dpll.p2 = clock.p2;
5754         }
5755
5756         /* Ensure that the cursor is valid for the new mode before changing... */
5757         intel_crtc_update_cursor(crtc, true);
5758
5759         /* determine panel color depth */
5760         dither = intel_crtc->config.dither;
5761         if (is_lvds && dev_priv->lvds_dither)
5762                 dither = true;
5763
5764         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5765         if (has_reduced_clock)
5766                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5767                         reduced_clock.m2;
5768
5769         dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5770                                      has_reduced_clock ? &fp2 : NULL);
5771
5772         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5773         drm_mode_debug_printmodeline(mode);
5774
5775         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5776         if (intel_crtc->config.has_pch_encoder) {
5777                 struct intel_pch_pll *pll;
5778
5779                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5780                 if (pll == NULL) {
5781                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5782                                          pipe_name(pipe));
5783                         return -EINVAL;
5784                 }
5785         } else
5786                 intel_put_pch_pll(intel_crtc);
5787
5788         if (intel_crtc->config.has_dp_encoder)
5789                 intel_dp_set_m_n(intel_crtc);
5790
5791         for_each_encoder_on_crtc(dev, crtc, encoder)
5792                 if (encoder->pre_pll_enable)
5793                         encoder->pre_pll_enable(encoder);
5794
5795         if (intel_crtc->pch_pll) {
5796                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5797
5798                 /* Wait for the clocks to stabilize. */
5799                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5800                 udelay(150);
5801
5802                 /* The pixel multiplier can only be updated once the
5803                  * DPLL is enabled and the clocks are stable.
5804                  *
5805                  * So write it again.
5806                  */
5807                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5808         }
5809
5810         intel_crtc->lowfreq_avail = false;
5811         if (intel_crtc->pch_pll) {
5812                 if (is_lvds && has_reduced_clock && i915_powersave) {
5813                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5814                         intel_crtc->lowfreq_avail = true;
5815                 } else {
5816                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5817                 }
5818         }
5819
5820         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5821
5822         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5823          * ironlake_check_fdi_lanes. */
5824         intel_crtc->fdi_lanes = 0;
5825         if (intel_crtc->config.has_pch_encoder)
5826                 ironlake_fdi_set_m_n(crtc);
5827
5828         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5829
5830         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5831
5832         /* Set up the display plane register */
5833         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5834         POSTING_READ(DSPCNTR(plane));
5835
5836         ret = intel_pipe_set_base(crtc, x, y, fb);
5837
5838         intel_update_watermarks(dev);
5839
5840         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5841
5842         return fdi_config_ok ? ret : -EINVAL;
5843 }
5844
5845 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5846                                      struct intel_crtc_config *pipe_config)
5847 {
5848         struct drm_device *dev = crtc->base.dev;
5849         struct drm_i915_private *dev_priv = dev->dev_private;
5850         uint32_t tmp;
5851
5852         tmp = I915_READ(PIPECONF(crtc->pipe));
5853         if (!(tmp & PIPECONF_ENABLE))
5854                 return false;
5855
5856         if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5857                 pipe_config->has_pch_encoder = true;
5858
5859         return true;
5860 }
5861
5862 static void haswell_modeset_global_resources(struct drm_device *dev)
5863 {
5864         struct drm_i915_private *dev_priv = dev->dev_private;
5865         bool enable = false;
5866         struct intel_crtc *crtc;
5867         struct intel_encoder *encoder;
5868
5869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5870                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5871                         enable = true;
5872                 /* XXX: Should check for edp transcoder here, but thanks to init
5873                  * sequence that's not yet available. Just in case desktop eDP
5874                  * on PORT D is possible on haswell, too. */
5875         }
5876
5877         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5878                             base.head) {
5879                 if (encoder->type != INTEL_OUTPUT_EDP &&
5880                     encoder->connectors_active)
5881                         enable = true;
5882         }
5883
5884         /* Even the eDP panel fitter is outside the always-on well. */
5885         if (dev_priv->pch_pf_size)
5886                 enable = true;
5887
5888         intel_set_power_well(dev, enable);
5889 }
5890
5891 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5892                                  int x, int y,
5893                                  struct drm_framebuffer *fb)
5894 {
5895         struct drm_device *dev = crtc->dev;
5896         struct drm_i915_private *dev_priv = dev->dev_private;
5897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898         struct drm_display_mode *adjusted_mode =
5899                 &intel_crtc->config.adjusted_mode;
5900         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5901         int pipe = intel_crtc->pipe;
5902         int plane = intel_crtc->plane;
5903         int num_connectors = 0;
5904         bool is_cpu_edp = false;
5905         struct intel_encoder *encoder;
5906         int ret;
5907         bool dither;
5908
5909         for_each_encoder_on_crtc(dev, crtc, encoder) {
5910                 switch (encoder->type) {
5911                 case INTEL_OUTPUT_EDP:
5912                         if (!intel_encoder_is_pch_edp(&encoder->base))
5913                                 is_cpu_edp = true;
5914                         break;
5915                 }
5916
5917                 num_connectors++;
5918         }
5919
5920         if (is_cpu_edp)
5921                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5922         else
5923                 intel_crtc->config.cpu_transcoder = pipe;
5924
5925         /* We are not sure yet this won't happen. */
5926         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5927              INTEL_PCH_TYPE(dev));
5928
5929         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5930              num_connectors, pipe_name(pipe));
5931
5932         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5933                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5934
5935         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5936
5937         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5938                 return -EINVAL;
5939
5940         /* Ensure that the cursor is valid for the new mode before changing... */
5941         intel_crtc_update_cursor(crtc, true);
5942
5943         /* determine panel color depth */
5944         dither = intel_crtc->config.dither;
5945
5946         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5947         drm_mode_debug_printmodeline(mode);
5948
5949         if (intel_crtc->config.has_dp_encoder)
5950                 intel_dp_set_m_n(intel_crtc);
5951
5952         intel_crtc->lowfreq_avail = false;
5953
5954         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5955
5956         if (intel_crtc->config.has_pch_encoder)
5957                 ironlake_fdi_set_m_n(crtc);
5958
5959         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5960
5961         intel_set_pipe_csc(crtc);
5962
5963         /* Set up the display plane register */
5964         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5965         POSTING_READ(DSPCNTR(plane));
5966
5967         ret = intel_pipe_set_base(crtc, x, y, fb);
5968
5969         intel_update_watermarks(dev);
5970
5971         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5972
5973         return ret;
5974 }
5975
5976 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5977                                     struct intel_crtc_config *pipe_config)
5978 {
5979         struct drm_device *dev = crtc->base.dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5982         uint32_t tmp;
5983
5984         if (!intel_using_power_well(dev_priv->dev) &&
5985             cpu_transcoder != TRANSCODER_EDP)
5986                 return false;
5987
5988         tmp = I915_READ(PIPECONF(cpu_transcoder));
5989         if (!(tmp & PIPECONF_ENABLE))
5990                 return false;
5991
5992         /*
5993          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5994          * DDI E. So just check whether this pipe is wired to DDI E and whether
5995          * the PCH transcoder is on.
5996          */
5997         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
5998         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5999             I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
6000                 pipe_config->has_pch_encoder = true;
6001
6002         return true;
6003 }
6004
6005 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6006                                int x, int y,
6007                                struct drm_framebuffer *fb)
6008 {
6009         struct drm_device *dev = crtc->dev;
6010         struct drm_i915_private *dev_priv = dev->dev_private;
6011         struct drm_encoder_helper_funcs *encoder_funcs;
6012         struct intel_encoder *encoder;
6013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014         struct drm_display_mode *adjusted_mode =
6015                 &intel_crtc->config.adjusted_mode;
6016         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6017         int pipe = intel_crtc->pipe;
6018         int ret;
6019
6020         drm_vblank_pre_modeset(dev, pipe);
6021
6022         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6023
6024         drm_vblank_post_modeset(dev, pipe);
6025
6026         if (ret != 0)
6027                 return ret;
6028
6029         for_each_encoder_on_crtc(dev, crtc, encoder) {
6030                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6031                         encoder->base.base.id,
6032                         drm_get_encoder_name(&encoder->base),
6033                         mode->base.id, mode->name);
6034                 if (encoder->mode_set) {
6035                         encoder->mode_set(encoder);
6036                 } else {
6037                         encoder_funcs = encoder->base.helper_private;
6038                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6039                 }
6040         }
6041
6042         return 0;
6043 }
6044
6045 static bool intel_eld_uptodate(struct drm_connector *connector,
6046                                int reg_eldv, uint32_t bits_eldv,
6047                                int reg_elda, uint32_t bits_elda,
6048                                int reg_edid)
6049 {
6050         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6051         uint8_t *eld = connector->eld;
6052         uint32_t i;
6053
6054         i = I915_READ(reg_eldv);
6055         i &= bits_eldv;
6056
6057         if (!eld[0])
6058                 return !i;
6059
6060         if (!i)
6061                 return false;
6062
6063         i = I915_READ(reg_elda);
6064         i &= ~bits_elda;
6065         I915_WRITE(reg_elda, i);
6066
6067         for (i = 0; i < eld[2]; i++)
6068                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6069                         return false;
6070
6071         return true;
6072 }
6073
6074 static void g4x_write_eld(struct drm_connector *connector,
6075                           struct drm_crtc *crtc)
6076 {
6077         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078         uint8_t *eld = connector->eld;
6079         uint32_t eldv;
6080         uint32_t len;
6081         uint32_t i;
6082
6083         i = I915_READ(G4X_AUD_VID_DID);
6084
6085         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6086                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6087         else
6088                 eldv = G4X_ELDV_DEVCTG;
6089
6090         if (intel_eld_uptodate(connector,
6091                                G4X_AUD_CNTL_ST, eldv,
6092                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6093                                G4X_HDMIW_HDMIEDID))
6094                 return;
6095
6096         i = I915_READ(G4X_AUD_CNTL_ST);
6097         i &= ~(eldv | G4X_ELD_ADDR);
6098         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6099         I915_WRITE(G4X_AUD_CNTL_ST, i);
6100
6101         if (!eld[0])
6102                 return;
6103
6104         len = min_t(uint8_t, eld[2], len);
6105         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6106         for (i = 0; i < len; i++)
6107                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6108
6109         i = I915_READ(G4X_AUD_CNTL_ST);
6110         i |= eldv;
6111         I915_WRITE(G4X_AUD_CNTL_ST, i);
6112 }
6113
6114 static void haswell_write_eld(struct drm_connector *connector,
6115                                      struct drm_crtc *crtc)
6116 {
6117         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6118         uint8_t *eld = connector->eld;
6119         struct drm_device *dev = crtc->dev;
6120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6121         uint32_t eldv;
6122         uint32_t i;
6123         int len;
6124         int pipe = to_intel_crtc(crtc)->pipe;
6125         int tmp;
6126
6127         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6128         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6129         int aud_config = HSW_AUD_CFG(pipe);
6130         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6131
6132
6133         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6134
6135         /* Audio output enable */
6136         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6137         tmp = I915_READ(aud_cntrl_st2);
6138         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6139         I915_WRITE(aud_cntrl_st2, tmp);
6140
6141         /* Wait for 1 vertical blank */
6142         intel_wait_for_vblank(dev, pipe);
6143
6144         /* Set ELD valid state */
6145         tmp = I915_READ(aud_cntrl_st2);
6146         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6147         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6148         I915_WRITE(aud_cntrl_st2, tmp);
6149         tmp = I915_READ(aud_cntrl_st2);
6150         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6151
6152         /* Enable HDMI mode */
6153         tmp = I915_READ(aud_config);
6154         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6155         /* clear N_programing_enable and N_value_index */
6156         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6157         I915_WRITE(aud_config, tmp);
6158
6159         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6160
6161         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6162         intel_crtc->eld_vld = true;
6163
6164         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6165                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6166                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6167                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6168         } else
6169                 I915_WRITE(aud_config, 0);
6170
6171         if (intel_eld_uptodate(connector,
6172                                aud_cntrl_st2, eldv,
6173                                aud_cntl_st, IBX_ELD_ADDRESS,
6174                                hdmiw_hdmiedid))
6175                 return;
6176
6177         i = I915_READ(aud_cntrl_st2);
6178         i &= ~eldv;
6179         I915_WRITE(aud_cntrl_st2, i);
6180
6181         if (!eld[0])
6182                 return;
6183
6184         i = I915_READ(aud_cntl_st);
6185         i &= ~IBX_ELD_ADDRESS;
6186         I915_WRITE(aud_cntl_st, i);
6187         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6188         DRM_DEBUG_DRIVER("port num:%d\n", i);
6189
6190         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6191         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6192         for (i = 0; i < len; i++)
6193                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6194
6195         i = I915_READ(aud_cntrl_st2);
6196         i |= eldv;
6197         I915_WRITE(aud_cntrl_st2, i);
6198
6199 }
6200
6201 static void ironlake_write_eld(struct drm_connector *connector,
6202                                      struct drm_crtc *crtc)
6203 {
6204         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6205         uint8_t *eld = connector->eld;
6206         uint32_t eldv;
6207         uint32_t i;
6208         int len;
6209         int hdmiw_hdmiedid;
6210         int aud_config;
6211         int aud_cntl_st;
6212         int aud_cntrl_st2;
6213         int pipe = to_intel_crtc(crtc)->pipe;
6214
6215         if (HAS_PCH_IBX(connector->dev)) {
6216                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6217                 aud_config = IBX_AUD_CFG(pipe);
6218                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6219                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6220         } else {
6221                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6222                 aud_config = CPT_AUD_CFG(pipe);
6223                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6224                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6225         }
6226
6227         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6228
6229         i = I915_READ(aud_cntl_st);
6230         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6231         if (!i) {
6232                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6233                 /* operate blindly on all ports */
6234                 eldv = IBX_ELD_VALIDB;
6235                 eldv |= IBX_ELD_VALIDB << 4;
6236                 eldv |= IBX_ELD_VALIDB << 8;
6237         } else {
6238                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6239                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6240         }
6241
6242         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6243                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6244                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6245                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6246         } else
6247                 I915_WRITE(aud_config, 0);
6248
6249         if (intel_eld_uptodate(connector,
6250                                aud_cntrl_st2, eldv,
6251                                aud_cntl_st, IBX_ELD_ADDRESS,
6252                                hdmiw_hdmiedid))
6253                 return;
6254
6255         i = I915_READ(aud_cntrl_st2);
6256         i &= ~eldv;
6257         I915_WRITE(aud_cntrl_st2, i);
6258
6259         if (!eld[0])
6260                 return;
6261
6262         i = I915_READ(aud_cntl_st);
6263         i &= ~IBX_ELD_ADDRESS;
6264         I915_WRITE(aud_cntl_st, i);
6265
6266         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6267         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6268         for (i = 0; i < len; i++)
6269                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6270
6271         i = I915_READ(aud_cntrl_st2);
6272         i |= eldv;
6273         I915_WRITE(aud_cntrl_st2, i);
6274 }
6275
6276 void intel_write_eld(struct drm_encoder *encoder,
6277                      struct drm_display_mode *mode)
6278 {
6279         struct drm_crtc *crtc = encoder->crtc;
6280         struct drm_connector *connector;
6281         struct drm_device *dev = encoder->dev;
6282         struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284         connector = drm_select_eld(encoder, mode);
6285         if (!connector)
6286                 return;
6287
6288         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6289                          connector->base.id,
6290                          drm_get_connector_name(connector),
6291                          connector->encoder->base.id,
6292                          drm_get_encoder_name(connector->encoder));
6293
6294         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6295
6296         if (dev_priv->display.write_eld)
6297                 dev_priv->display.write_eld(connector, crtc);
6298 }
6299
6300 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6301 void intel_crtc_load_lut(struct drm_crtc *crtc)
6302 {
6303         struct drm_device *dev = crtc->dev;
6304         struct drm_i915_private *dev_priv = dev->dev_private;
6305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306         int palreg = PALETTE(intel_crtc->pipe);
6307         int i;
6308
6309         /* The clocks have to be on to load the palette. */
6310         if (!crtc->enabled || !intel_crtc->active)
6311                 return;
6312
6313         /* use legacy palette for Ironlake */
6314         if (HAS_PCH_SPLIT(dev))
6315                 palreg = LGC_PALETTE(intel_crtc->pipe);
6316
6317         for (i = 0; i < 256; i++) {
6318                 I915_WRITE(palreg + 4 * i,
6319                            (intel_crtc->lut_r[i] << 16) |
6320                            (intel_crtc->lut_g[i] << 8) |
6321                            intel_crtc->lut_b[i]);
6322         }
6323 }
6324
6325 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6326 {
6327         struct drm_device *dev = crtc->dev;
6328         struct drm_i915_private *dev_priv = dev->dev_private;
6329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6330         bool visible = base != 0;
6331         u32 cntl;
6332
6333         if (intel_crtc->cursor_visible == visible)
6334                 return;
6335
6336         cntl = I915_READ(_CURACNTR);
6337         if (visible) {
6338                 /* On these chipsets we can only modify the base whilst
6339                  * the cursor is disabled.
6340                  */
6341                 I915_WRITE(_CURABASE, base);
6342
6343                 cntl &= ~(CURSOR_FORMAT_MASK);
6344                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6345                 cntl |= CURSOR_ENABLE |
6346                         CURSOR_GAMMA_ENABLE |
6347                         CURSOR_FORMAT_ARGB;
6348         } else
6349                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6350         I915_WRITE(_CURACNTR, cntl);
6351
6352         intel_crtc->cursor_visible = visible;
6353 }
6354
6355 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6356 {
6357         struct drm_device *dev = crtc->dev;
6358         struct drm_i915_private *dev_priv = dev->dev_private;
6359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6360         int pipe = intel_crtc->pipe;
6361         bool visible = base != 0;
6362
6363         if (intel_crtc->cursor_visible != visible) {
6364                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6365                 if (base) {
6366                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6367                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6368                         cntl |= pipe << 28; /* Connect to correct pipe */
6369                 } else {
6370                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6371                         cntl |= CURSOR_MODE_DISABLE;
6372                 }
6373                 I915_WRITE(CURCNTR(pipe), cntl);
6374
6375                 intel_crtc->cursor_visible = visible;
6376         }
6377         /* and commit changes on next vblank */
6378         I915_WRITE(CURBASE(pipe), base);
6379 }
6380
6381 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6382 {
6383         struct drm_device *dev = crtc->dev;
6384         struct drm_i915_private *dev_priv = dev->dev_private;
6385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386         int pipe = intel_crtc->pipe;
6387         bool visible = base != 0;
6388
6389         if (intel_crtc->cursor_visible != visible) {
6390                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6391                 if (base) {
6392                         cntl &= ~CURSOR_MODE;
6393                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6394                 } else {
6395                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6396                         cntl |= CURSOR_MODE_DISABLE;
6397                 }
6398                 if (IS_HASWELL(dev))
6399                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6400                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6401
6402                 intel_crtc->cursor_visible = visible;
6403         }
6404         /* and commit changes on next vblank */
6405         I915_WRITE(CURBASE_IVB(pipe), base);
6406 }
6407
6408 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6409 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6410                                      bool on)
6411 {
6412         struct drm_device *dev = crtc->dev;
6413         struct drm_i915_private *dev_priv = dev->dev_private;
6414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6415         int pipe = intel_crtc->pipe;
6416         int x = intel_crtc->cursor_x;
6417         int y = intel_crtc->cursor_y;
6418         u32 base, pos;
6419         bool visible;
6420
6421         pos = 0;
6422
6423         if (on && crtc->enabled && crtc->fb) {
6424                 base = intel_crtc->cursor_addr;
6425                 if (x > (int) crtc->fb->width)
6426                         base = 0;
6427
6428                 if (y > (int) crtc->fb->height)
6429                         base = 0;
6430         } else
6431                 base = 0;
6432
6433         if (x < 0) {
6434                 if (x + intel_crtc->cursor_width < 0)
6435                         base = 0;
6436
6437                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6438                 x = -x;
6439         }
6440         pos |= x << CURSOR_X_SHIFT;
6441
6442         if (y < 0) {
6443                 if (y + intel_crtc->cursor_height < 0)
6444                         base = 0;
6445
6446                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6447                 y = -y;
6448         }
6449         pos |= y << CURSOR_Y_SHIFT;
6450
6451         visible = base != 0;
6452         if (!visible && !intel_crtc->cursor_visible)
6453                 return;
6454
6455         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6456                 I915_WRITE(CURPOS_IVB(pipe), pos);
6457                 ivb_update_cursor(crtc, base);
6458         } else {
6459                 I915_WRITE(CURPOS(pipe), pos);
6460                 if (IS_845G(dev) || IS_I865G(dev))
6461                         i845_update_cursor(crtc, base);
6462                 else
6463                         i9xx_update_cursor(crtc, base);
6464         }
6465 }
6466
6467 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6468                                  struct drm_file *file,
6469                                  uint32_t handle,
6470                                  uint32_t width, uint32_t height)
6471 {
6472         struct drm_device *dev = crtc->dev;
6473         struct drm_i915_private *dev_priv = dev->dev_private;
6474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6475         struct drm_i915_gem_object *obj;
6476         uint32_t addr;
6477         int ret;
6478
6479         /* if we want to turn off the cursor ignore width and height */
6480         if (!handle) {
6481                 DRM_DEBUG_KMS("cursor off\n");
6482                 addr = 0;
6483                 obj = NULL;
6484                 mutex_lock(&dev->struct_mutex);
6485                 goto finish;
6486         }
6487
6488         /* Currently we only support 64x64 cursors */
6489         if (width != 64 || height != 64) {
6490                 DRM_ERROR("we currently only support 64x64 cursors\n");
6491                 return -EINVAL;
6492         }
6493
6494         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6495         if (&obj->base == NULL)
6496                 return -ENOENT;
6497
6498         if (obj->base.size < width * height * 4) {
6499                 DRM_ERROR("buffer is to small\n");
6500                 ret = -ENOMEM;
6501                 goto fail;
6502         }
6503
6504         /* we only need to pin inside GTT if cursor is non-phy */
6505         mutex_lock(&dev->struct_mutex);
6506         if (!dev_priv->info->cursor_needs_physical) {
6507                 unsigned alignment;
6508
6509                 if (obj->tiling_mode) {
6510                         DRM_ERROR("cursor cannot be tiled\n");
6511                         ret = -EINVAL;
6512                         goto fail_locked;
6513                 }
6514
6515                 /* Note that the w/a also requires 2 PTE of padding following
6516                  * the bo. We currently fill all unused PTE with the shadow
6517                  * page and so we should always have valid PTE following the
6518                  * cursor preventing the VT-d warning.
6519                  */
6520                 alignment = 0;
6521                 if (need_vtd_wa(dev))
6522                         alignment = 64*1024;
6523
6524                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6525                 if (ret) {
6526                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6527                         goto fail_locked;
6528                 }
6529
6530                 ret = i915_gem_object_put_fence(obj);
6531                 if (ret) {
6532                         DRM_ERROR("failed to release fence for cursor");
6533                         goto fail_unpin;
6534                 }
6535
6536                 addr = obj->gtt_offset;
6537         } else {
6538                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6539                 ret = i915_gem_attach_phys_object(dev, obj,
6540                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6541                                                   align);
6542                 if (ret) {
6543                         DRM_ERROR("failed to attach phys object\n");
6544                         goto fail_locked;
6545                 }
6546                 addr = obj->phys_obj->handle->busaddr;
6547         }
6548
6549         if (IS_GEN2(dev))
6550                 I915_WRITE(CURSIZE, (height << 12) | width);
6551
6552  finish:
6553         if (intel_crtc->cursor_bo) {
6554                 if (dev_priv->info->cursor_needs_physical) {
6555                         if (intel_crtc->cursor_bo != obj)
6556                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6557                 } else
6558                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6559                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6560         }
6561
6562         mutex_unlock(&dev->struct_mutex);
6563
6564         intel_crtc->cursor_addr = addr;
6565         intel_crtc->cursor_bo = obj;
6566         intel_crtc->cursor_width = width;
6567         intel_crtc->cursor_height = height;
6568
6569         intel_crtc_update_cursor(crtc, true);
6570
6571         return 0;
6572 fail_unpin:
6573         i915_gem_object_unpin(obj);
6574 fail_locked:
6575         mutex_unlock(&dev->struct_mutex);
6576 fail:
6577         drm_gem_object_unreference_unlocked(&obj->base);
6578         return ret;
6579 }
6580
6581 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6582 {
6583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6584
6585         intel_crtc->cursor_x = x;
6586         intel_crtc->cursor_y = y;
6587
6588         intel_crtc_update_cursor(crtc, true);
6589
6590         return 0;
6591 }
6592
6593 /** Sets the color ramps on behalf of RandR */
6594 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6595                                  u16 blue, int regno)
6596 {
6597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6598
6599         intel_crtc->lut_r[regno] = red >> 8;
6600         intel_crtc->lut_g[regno] = green >> 8;
6601         intel_crtc->lut_b[regno] = blue >> 8;
6602 }
6603
6604 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6605                              u16 *blue, int regno)
6606 {
6607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6608
6609         *red = intel_crtc->lut_r[regno] << 8;
6610         *green = intel_crtc->lut_g[regno] << 8;
6611         *blue = intel_crtc->lut_b[regno] << 8;
6612 }
6613
6614 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6615                                  u16 *blue, uint32_t start, uint32_t size)
6616 {
6617         int end = (start + size > 256) ? 256 : start + size, i;
6618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619
6620         for (i = start; i < end; i++) {
6621                 intel_crtc->lut_r[i] = red[i] >> 8;
6622                 intel_crtc->lut_g[i] = green[i] >> 8;
6623                 intel_crtc->lut_b[i] = blue[i] >> 8;
6624         }
6625
6626         intel_crtc_load_lut(crtc);
6627 }
6628
6629 /* VESA 640x480x72Hz mode to set on the pipe */
6630 static struct drm_display_mode load_detect_mode = {
6631         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6632                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6633 };
6634
6635 static struct drm_framebuffer *
6636 intel_framebuffer_create(struct drm_device *dev,
6637                          struct drm_mode_fb_cmd2 *mode_cmd,
6638                          struct drm_i915_gem_object *obj)
6639 {
6640         struct intel_framebuffer *intel_fb;
6641         int ret;
6642
6643         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6644         if (!intel_fb) {
6645                 drm_gem_object_unreference_unlocked(&obj->base);
6646                 return ERR_PTR(-ENOMEM);
6647         }
6648
6649         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6650         if (ret) {
6651                 drm_gem_object_unreference_unlocked(&obj->base);
6652                 kfree(intel_fb);
6653                 return ERR_PTR(ret);
6654         }
6655
6656         return &intel_fb->base;
6657 }
6658
6659 static u32
6660 intel_framebuffer_pitch_for_width(int width, int bpp)
6661 {
6662         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6663         return ALIGN(pitch, 64);
6664 }
6665
6666 static u32
6667 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6668 {
6669         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6670         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6671 }
6672
6673 static struct drm_framebuffer *
6674 intel_framebuffer_create_for_mode(struct drm_device *dev,
6675                                   struct drm_display_mode *mode,
6676                                   int depth, int bpp)
6677 {
6678         struct drm_i915_gem_object *obj;
6679         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6680
6681         obj = i915_gem_alloc_object(dev,
6682                                     intel_framebuffer_size_for_mode(mode, bpp));
6683         if (obj == NULL)
6684                 return ERR_PTR(-ENOMEM);
6685
6686         mode_cmd.width = mode->hdisplay;
6687         mode_cmd.height = mode->vdisplay;
6688         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6689                                                                 bpp);
6690         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6691
6692         return intel_framebuffer_create(dev, &mode_cmd, obj);
6693 }
6694
6695 static struct drm_framebuffer *
6696 mode_fits_in_fbdev(struct drm_device *dev,
6697                    struct drm_display_mode *mode)
6698 {
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         struct drm_i915_gem_object *obj;
6701         struct drm_framebuffer *fb;
6702
6703         if (dev_priv->fbdev == NULL)
6704                 return NULL;
6705
6706         obj = dev_priv->fbdev->ifb.obj;
6707         if (obj == NULL)
6708                 return NULL;
6709
6710         fb = &dev_priv->fbdev->ifb.base;
6711         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6712                                                                fb->bits_per_pixel))
6713                 return NULL;
6714
6715         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6716                 return NULL;
6717
6718         return fb;
6719 }
6720
6721 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6722                                 struct drm_display_mode *mode,
6723                                 struct intel_load_detect_pipe *old)
6724 {
6725         struct intel_crtc *intel_crtc;
6726         struct intel_encoder *intel_encoder =
6727                 intel_attached_encoder(connector);
6728         struct drm_crtc *possible_crtc;
6729         struct drm_encoder *encoder = &intel_encoder->base;
6730         struct drm_crtc *crtc = NULL;
6731         struct drm_device *dev = encoder->dev;
6732         struct drm_framebuffer *fb;
6733         int i = -1;
6734
6735         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6736                       connector->base.id, drm_get_connector_name(connector),
6737                       encoder->base.id, drm_get_encoder_name(encoder));
6738
6739         /*
6740          * Algorithm gets a little messy:
6741          *
6742          *   - if the connector already has an assigned crtc, use it (but make
6743          *     sure it's on first)
6744          *
6745          *   - try to find the first unused crtc that can drive this connector,
6746          *     and use that if we find one
6747          */
6748
6749         /* See if we already have a CRTC for this connector */
6750         if (encoder->crtc) {
6751                 crtc = encoder->crtc;
6752
6753                 mutex_lock(&crtc->mutex);
6754
6755                 old->dpms_mode = connector->dpms;
6756                 old->load_detect_temp = false;
6757
6758                 /* Make sure the crtc and connector are running */
6759                 if (connector->dpms != DRM_MODE_DPMS_ON)
6760                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6761
6762                 return true;
6763         }
6764
6765         /* Find an unused one (if possible) */
6766         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6767                 i++;
6768                 if (!(encoder->possible_crtcs & (1 << i)))
6769                         continue;
6770                 if (!possible_crtc->enabled) {
6771                         crtc = possible_crtc;
6772                         break;
6773                 }
6774         }
6775
6776         /*
6777          * If we didn't find an unused CRTC, don't use any.
6778          */
6779         if (!crtc) {
6780                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6781                 return false;
6782         }
6783
6784         mutex_lock(&crtc->mutex);
6785         intel_encoder->new_crtc = to_intel_crtc(crtc);
6786         to_intel_connector(connector)->new_encoder = intel_encoder;
6787
6788         intel_crtc = to_intel_crtc(crtc);
6789         old->dpms_mode = connector->dpms;
6790         old->load_detect_temp = true;
6791         old->release_fb = NULL;
6792
6793         if (!mode)
6794                 mode = &load_detect_mode;
6795
6796         /* We need a framebuffer large enough to accommodate all accesses
6797          * that the plane may generate whilst we perform load detection.
6798          * We can not rely on the fbcon either being present (we get called
6799          * during its initialisation to detect all boot displays, or it may
6800          * not even exist) or that it is large enough to satisfy the
6801          * requested mode.
6802          */
6803         fb = mode_fits_in_fbdev(dev, mode);
6804         if (fb == NULL) {
6805                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6806                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6807                 old->release_fb = fb;
6808         } else
6809                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6810         if (IS_ERR(fb)) {
6811                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6812                 mutex_unlock(&crtc->mutex);
6813                 return false;
6814         }
6815
6816         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6817                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6818                 if (old->release_fb)
6819                         old->release_fb->funcs->destroy(old->release_fb);
6820                 mutex_unlock(&crtc->mutex);
6821                 return false;
6822         }
6823
6824         /* let the connector get through one full cycle before testing */
6825         intel_wait_for_vblank(dev, intel_crtc->pipe);
6826         return true;
6827 }
6828
6829 void intel_release_load_detect_pipe(struct drm_connector *connector,
6830                                     struct intel_load_detect_pipe *old)
6831 {
6832         struct intel_encoder *intel_encoder =
6833                 intel_attached_encoder(connector);
6834         struct drm_encoder *encoder = &intel_encoder->base;
6835         struct drm_crtc *crtc = encoder->crtc;
6836
6837         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6838                       connector->base.id, drm_get_connector_name(connector),
6839                       encoder->base.id, drm_get_encoder_name(encoder));
6840
6841         if (old->load_detect_temp) {
6842                 to_intel_connector(connector)->new_encoder = NULL;
6843                 intel_encoder->new_crtc = NULL;
6844                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6845
6846                 if (old->release_fb) {
6847                         drm_framebuffer_unregister_private(old->release_fb);
6848                         drm_framebuffer_unreference(old->release_fb);
6849                 }
6850
6851                 mutex_unlock(&crtc->mutex);
6852                 return;
6853         }
6854
6855         /* Switch crtc and encoder back off if necessary */
6856         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6857                 connector->funcs->dpms(connector, old->dpms_mode);
6858
6859         mutex_unlock(&crtc->mutex);
6860 }
6861
6862 /* Returns the clock of the currently programmed mode of the given pipe. */
6863 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6864 {
6865         struct drm_i915_private *dev_priv = dev->dev_private;
6866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6867         int pipe = intel_crtc->pipe;
6868         u32 dpll = I915_READ(DPLL(pipe));
6869         u32 fp;
6870         intel_clock_t clock;
6871
6872         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6873                 fp = I915_READ(FP0(pipe));
6874         else
6875                 fp = I915_READ(FP1(pipe));
6876
6877         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6878         if (IS_PINEVIEW(dev)) {
6879                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6880                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6881         } else {
6882                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6883                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6884         }
6885
6886         if (!IS_GEN2(dev)) {
6887                 if (IS_PINEVIEW(dev))
6888                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6889                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6890                 else
6891                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6892                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6893
6894                 switch (dpll & DPLL_MODE_MASK) {
6895                 case DPLLB_MODE_DAC_SERIAL:
6896                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6897                                 5 : 10;
6898                         break;
6899                 case DPLLB_MODE_LVDS:
6900                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6901                                 7 : 14;
6902                         break;
6903                 default:
6904                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6905                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6906                         return 0;
6907                 }
6908
6909                 /* XXX: Handle the 100Mhz refclk */
6910                 intel_clock(dev, 96000, &clock);
6911         } else {
6912                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6913
6914                 if (is_lvds) {
6915                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6916                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6917                         clock.p2 = 14;
6918
6919                         if ((dpll & PLL_REF_INPUT_MASK) ==
6920                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6921                                 /* XXX: might not be 66MHz */
6922                                 intel_clock(dev, 66000, &clock);
6923                         } else
6924                                 intel_clock(dev, 48000, &clock);
6925                 } else {
6926                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6927                                 clock.p1 = 2;
6928                         else {
6929                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6930                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6931                         }
6932                         if (dpll & PLL_P2_DIVIDE_BY_4)
6933                                 clock.p2 = 4;
6934                         else
6935                                 clock.p2 = 2;
6936
6937                         intel_clock(dev, 48000, &clock);
6938                 }
6939         }
6940
6941         /* XXX: It would be nice to validate the clocks, but we can't reuse
6942          * i830PllIsValid() because it relies on the xf86_config connector
6943          * configuration being accurate, which it isn't necessarily.
6944          */
6945
6946         return clock.dot;
6947 }
6948
6949 /** Returns the currently programmed mode of the given pipe. */
6950 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6951                                              struct drm_crtc *crtc)
6952 {
6953         struct drm_i915_private *dev_priv = dev->dev_private;
6954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6955         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6956         struct drm_display_mode *mode;
6957         int htot = I915_READ(HTOTAL(cpu_transcoder));
6958         int hsync = I915_READ(HSYNC(cpu_transcoder));
6959         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6960         int vsync = I915_READ(VSYNC(cpu_transcoder));
6961
6962         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6963         if (!mode)
6964                 return NULL;
6965
6966         mode->clock = intel_crtc_clock_get(dev, crtc);
6967         mode->hdisplay = (htot & 0xffff) + 1;
6968         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6969         mode->hsync_start = (hsync & 0xffff) + 1;
6970         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6971         mode->vdisplay = (vtot & 0xffff) + 1;
6972         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6973         mode->vsync_start = (vsync & 0xffff) + 1;
6974         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6975
6976         drm_mode_set_name(mode);
6977
6978         return mode;
6979 }
6980
6981 static void intel_increase_pllclock(struct drm_crtc *crtc)
6982 {
6983         struct drm_device *dev = crtc->dev;
6984         drm_i915_private_t *dev_priv = dev->dev_private;
6985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6986         int pipe = intel_crtc->pipe;
6987         int dpll_reg = DPLL(pipe);
6988         int dpll;
6989
6990         if (HAS_PCH_SPLIT(dev))
6991                 return;
6992
6993         if (!dev_priv->lvds_downclock_avail)
6994                 return;
6995
6996         dpll = I915_READ(dpll_reg);
6997         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6998                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6999
7000                 assert_panel_unlocked(dev_priv, pipe);
7001
7002                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7003                 I915_WRITE(dpll_reg, dpll);
7004                 intel_wait_for_vblank(dev, pipe);
7005
7006                 dpll = I915_READ(dpll_reg);
7007                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7008                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7009         }
7010 }
7011
7012 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7013 {
7014         struct drm_device *dev = crtc->dev;
7015         drm_i915_private_t *dev_priv = dev->dev_private;
7016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017
7018         if (HAS_PCH_SPLIT(dev))
7019                 return;
7020
7021         if (!dev_priv->lvds_downclock_avail)
7022                 return;
7023
7024         /*
7025          * Since this is called by a timer, we should never get here in
7026          * the manual case.
7027          */
7028         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7029                 int pipe = intel_crtc->pipe;
7030                 int dpll_reg = DPLL(pipe);
7031                 int dpll;
7032
7033                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7034
7035                 assert_panel_unlocked(dev_priv, pipe);
7036
7037                 dpll = I915_READ(dpll_reg);
7038                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7039                 I915_WRITE(dpll_reg, dpll);
7040                 intel_wait_for_vblank(dev, pipe);
7041                 dpll = I915_READ(dpll_reg);
7042                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7043                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7044         }
7045
7046 }
7047
7048 void intel_mark_busy(struct drm_device *dev)
7049 {
7050         i915_update_gfx_val(dev->dev_private);
7051 }
7052
7053 void intel_mark_idle(struct drm_device *dev)
7054 {
7055         struct drm_crtc *crtc;
7056
7057         if (!i915_powersave)
7058                 return;
7059
7060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7061                 if (!crtc->fb)
7062                         continue;
7063
7064                 intel_decrease_pllclock(crtc);
7065         }
7066 }
7067
7068 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7069 {
7070         struct drm_device *dev = obj->base.dev;
7071         struct drm_crtc *crtc;
7072
7073         if (!i915_powersave)
7074                 return;
7075
7076         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7077                 if (!crtc->fb)
7078                         continue;
7079
7080                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7081                         intel_increase_pllclock(crtc);
7082         }
7083 }
7084
7085 static void intel_crtc_destroy(struct drm_crtc *crtc)
7086 {
7087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088         struct drm_device *dev = crtc->dev;
7089         struct intel_unpin_work *work;
7090         unsigned long flags;
7091
7092         spin_lock_irqsave(&dev->event_lock, flags);
7093         work = intel_crtc->unpin_work;
7094         intel_crtc->unpin_work = NULL;
7095         spin_unlock_irqrestore(&dev->event_lock, flags);
7096
7097         if (work) {
7098                 cancel_work_sync(&work->work);
7099                 kfree(work);
7100         }
7101
7102         drm_crtc_cleanup(crtc);
7103
7104         kfree(intel_crtc);
7105 }
7106
7107 static void intel_unpin_work_fn(struct work_struct *__work)
7108 {
7109         struct intel_unpin_work *work =
7110                 container_of(__work, struct intel_unpin_work, work);
7111         struct drm_device *dev = work->crtc->dev;
7112
7113         mutex_lock(&dev->struct_mutex);
7114         intel_unpin_fb_obj(work->old_fb_obj);
7115         drm_gem_object_unreference(&work->pending_flip_obj->base);
7116         drm_gem_object_unreference(&work->old_fb_obj->base);
7117
7118         intel_update_fbc(dev);
7119         mutex_unlock(&dev->struct_mutex);
7120
7121         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7122         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7123
7124         kfree(work);
7125 }
7126
7127 static void do_intel_finish_page_flip(struct drm_device *dev,
7128                                       struct drm_crtc *crtc)
7129 {
7130         drm_i915_private_t *dev_priv = dev->dev_private;
7131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7132         struct intel_unpin_work *work;
7133         unsigned long flags;
7134
7135         /* Ignore early vblank irqs */
7136         if (intel_crtc == NULL)
7137                 return;
7138
7139         spin_lock_irqsave(&dev->event_lock, flags);
7140         work = intel_crtc->unpin_work;
7141
7142         /* Ensure we don't miss a work->pending update ... */
7143         smp_rmb();
7144
7145         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7146                 spin_unlock_irqrestore(&dev->event_lock, flags);
7147                 return;
7148         }
7149
7150         /* and that the unpin work is consistent wrt ->pending. */
7151         smp_rmb();
7152
7153         intel_crtc->unpin_work = NULL;
7154
7155         if (work->event)
7156                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7157
7158         drm_vblank_put(dev, intel_crtc->pipe);
7159
7160         spin_unlock_irqrestore(&dev->event_lock, flags);
7161
7162         wake_up_all(&dev_priv->pending_flip_queue);
7163
7164         queue_work(dev_priv->wq, &work->work);
7165
7166         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7167 }
7168
7169 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7170 {
7171         drm_i915_private_t *dev_priv = dev->dev_private;
7172         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7173
7174         do_intel_finish_page_flip(dev, crtc);
7175 }
7176
7177 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7178 {
7179         drm_i915_private_t *dev_priv = dev->dev_private;
7180         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7181
7182         do_intel_finish_page_flip(dev, crtc);
7183 }
7184
7185 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7186 {
7187         drm_i915_private_t *dev_priv = dev->dev_private;
7188         struct intel_crtc *intel_crtc =
7189                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7190         unsigned long flags;
7191
7192         /* NB: An MMIO update of the plane base pointer will also
7193          * generate a page-flip completion irq, i.e. every modeset
7194          * is also accompanied by a spurious intel_prepare_page_flip().
7195          */
7196         spin_lock_irqsave(&dev->event_lock, flags);
7197         if (intel_crtc->unpin_work)
7198                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7199         spin_unlock_irqrestore(&dev->event_lock, flags);
7200 }
7201
7202 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7203 {
7204         /* Ensure that the work item is consistent when activating it ... */
7205         smp_wmb();
7206         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7207         /* and that it is marked active as soon as the irq could fire. */
7208         smp_wmb();
7209 }
7210
7211 static int intel_gen2_queue_flip(struct drm_device *dev,
7212                                  struct drm_crtc *crtc,
7213                                  struct drm_framebuffer *fb,
7214                                  struct drm_i915_gem_object *obj)
7215 {
7216         struct drm_i915_private *dev_priv = dev->dev_private;
7217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7218         u32 flip_mask;
7219         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7220         int ret;
7221
7222         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7223         if (ret)
7224                 goto err;
7225
7226         ret = intel_ring_begin(ring, 6);
7227         if (ret)
7228                 goto err_unpin;
7229
7230         /* Can't queue multiple flips, so wait for the previous
7231          * one to finish before executing the next.
7232          */
7233         if (intel_crtc->plane)
7234                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7235         else
7236                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7237         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7238         intel_ring_emit(ring, MI_NOOP);
7239         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7240                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7241         intel_ring_emit(ring, fb->pitches[0]);
7242         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7243         intel_ring_emit(ring, 0); /* aux display base address, unused */
7244
7245         intel_mark_page_flip_active(intel_crtc);
7246         intel_ring_advance(ring);
7247         return 0;
7248
7249 err_unpin:
7250         intel_unpin_fb_obj(obj);
7251 err:
7252         return ret;
7253 }
7254
7255 static int intel_gen3_queue_flip(struct drm_device *dev,
7256                                  struct drm_crtc *crtc,
7257                                  struct drm_framebuffer *fb,
7258                                  struct drm_i915_gem_object *obj)
7259 {
7260         struct drm_i915_private *dev_priv = dev->dev_private;
7261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7262         u32 flip_mask;
7263         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7264         int ret;
7265
7266         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7267         if (ret)
7268                 goto err;
7269
7270         ret = intel_ring_begin(ring, 6);
7271         if (ret)
7272                 goto err_unpin;
7273
7274         if (intel_crtc->plane)
7275                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7276         else
7277                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7278         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7279         intel_ring_emit(ring, MI_NOOP);
7280         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7281                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7282         intel_ring_emit(ring, fb->pitches[0]);
7283         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7284         intel_ring_emit(ring, MI_NOOP);
7285
7286         intel_mark_page_flip_active(intel_crtc);
7287         intel_ring_advance(ring);
7288         return 0;
7289
7290 err_unpin:
7291         intel_unpin_fb_obj(obj);
7292 err:
7293         return ret;
7294 }
7295
7296 static int intel_gen4_queue_flip(struct drm_device *dev,
7297                                  struct drm_crtc *crtc,
7298                                  struct drm_framebuffer *fb,
7299                                  struct drm_i915_gem_object *obj)
7300 {
7301         struct drm_i915_private *dev_priv = dev->dev_private;
7302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7303         uint32_t pf, pipesrc;
7304         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7305         int ret;
7306
7307         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7308         if (ret)
7309                 goto err;
7310
7311         ret = intel_ring_begin(ring, 4);
7312         if (ret)
7313                 goto err_unpin;
7314
7315         /* i965+ uses the linear or tiled offsets from the
7316          * Display Registers (which do not change across a page-flip)
7317          * so we need only reprogram the base address.
7318          */
7319         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7320                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7321         intel_ring_emit(ring, fb->pitches[0]);
7322         intel_ring_emit(ring,
7323                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7324                         obj->tiling_mode);
7325
7326         /* XXX Enabling the panel-fitter across page-flip is so far
7327          * untested on non-native modes, so ignore it for now.
7328          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7329          */
7330         pf = 0;
7331         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7332         intel_ring_emit(ring, pf | pipesrc);
7333
7334         intel_mark_page_flip_active(intel_crtc);
7335         intel_ring_advance(ring);
7336         return 0;
7337
7338 err_unpin:
7339         intel_unpin_fb_obj(obj);
7340 err:
7341         return ret;
7342 }
7343
7344 static int intel_gen6_queue_flip(struct drm_device *dev,
7345                                  struct drm_crtc *crtc,
7346                                  struct drm_framebuffer *fb,
7347                                  struct drm_i915_gem_object *obj)
7348 {
7349         struct drm_i915_private *dev_priv = dev->dev_private;
7350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7351         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7352         uint32_t pf, pipesrc;
7353         int ret;
7354
7355         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7356         if (ret)
7357                 goto err;
7358
7359         ret = intel_ring_begin(ring, 4);
7360         if (ret)
7361                 goto err_unpin;
7362
7363         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7364                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7365         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7366         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7367
7368         /* Contrary to the suggestions in the documentation,
7369          * "Enable Panel Fitter" does not seem to be required when page
7370          * flipping with a non-native mode, and worse causes a normal
7371          * modeset to fail.
7372          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7373          */
7374         pf = 0;
7375         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7376         intel_ring_emit(ring, pf | pipesrc);
7377
7378         intel_mark_page_flip_active(intel_crtc);
7379         intel_ring_advance(ring);
7380         return 0;
7381
7382 err_unpin:
7383         intel_unpin_fb_obj(obj);
7384 err:
7385         return ret;
7386 }
7387
7388 /*
7389  * On gen7 we currently use the blit ring because (in early silicon at least)
7390  * the render ring doesn't give us interrpts for page flip completion, which
7391  * means clients will hang after the first flip is queued.  Fortunately the
7392  * blit ring generates interrupts properly, so use it instead.
7393  */
7394 static int intel_gen7_queue_flip(struct drm_device *dev,
7395                                  struct drm_crtc *crtc,
7396                                  struct drm_framebuffer *fb,
7397                                  struct drm_i915_gem_object *obj)
7398 {
7399         struct drm_i915_private *dev_priv = dev->dev_private;
7400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7401         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7402         uint32_t plane_bit = 0;
7403         int ret;
7404
7405         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7406         if (ret)
7407                 goto err;
7408
7409         switch(intel_crtc->plane) {
7410         case PLANE_A:
7411                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7412                 break;
7413         case PLANE_B:
7414                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7415                 break;
7416         case PLANE_C:
7417                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7418                 break;
7419         default:
7420                 WARN_ONCE(1, "unknown plane in flip command\n");
7421                 ret = -ENODEV;
7422                 goto err_unpin;
7423         }
7424
7425         ret = intel_ring_begin(ring, 4);
7426         if (ret)
7427                 goto err_unpin;
7428
7429         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7430         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7431         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7432         intel_ring_emit(ring, (MI_NOOP));
7433
7434         intel_mark_page_flip_active(intel_crtc);
7435         intel_ring_advance(ring);
7436         return 0;
7437
7438 err_unpin:
7439         intel_unpin_fb_obj(obj);
7440 err:
7441         return ret;
7442 }
7443
7444 static int intel_default_queue_flip(struct drm_device *dev,
7445                                     struct drm_crtc *crtc,
7446                                     struct drm_framebuffer *fb,
7447                                     struct drm_i915_gem_object *obj)
7448 {
7449         return -ENODEV;
7450 }
7451
7452 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7453                                 struct drm_framebuffer *fb,
7454                                 struct drm_pending_vblank_event *event)
7455 {
7456         struct drm_device *dev = crtc->dev;
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         struct drm_framebuffer *old_fb = crtc->fb;
7459         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7461         struct intel_unpin_work *work;
7462         unsigned long flags;
7463         int ret;
7464
7465         /* Can't change pixel format via MI display flips. */
7466         if (fb->pixel_format != crtc->fb->pixel_format)
7467                 return -EINVAL;
7468
7469         /*
7470          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7471          * Note that pitch changes could also affect these register.
7472          */
7473         if (INTEL_INFO(dev)->gen > 3 &&
7474             (fb->offsets[0] != crtc->fb->offsets[0] ||
7475              fb->pitches[0] != crtc->fb->pitches[0]))
7476                 return -EINVAL;
7477
7478         work = kzalloc(sizeof *work, GFP_KERNEL);
7479         if (work == NULL)
7480                 return -ENOMEM;
7481
7482         work->event = event;
7483         work->crtc = crtc;
7484         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7485         INIT_WORK(&work->work, intel_unpin_work_fn);
7486
7487         ret = drm_vblank_get(dev, intel_crtc->pipe);
7488         if (ret)
7489                 goto free_work;
7490
7491         /* We borrow the event spin lock for protecting unpin_work */
7492         spin_lock_irqsave(&dev->event_lock, flags);
7493         if (intel_crtc->unpin_work) {
7494                 spin_unlock_irqrestore(&dev->event_lock, flags);
7495                 kfree(work);
7496                 drm_vblank_put(dev, intel_crtc->pipe);
7497
7498                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7499                 return -EBUSY;
7500         }
7501         intel_crtc->unpin_work = work;
7502         spin_unlock_irqrestore(&dev->event_lock, flags);
7503
7504         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7505                 flush_workqueue(dev_priv->wq);
7506
7507         ret = i915_mutex_lock_interruptible(dev);
7508         if (ret)
7509                 goto cleanup;
7510
7511         /* Reference the objects for the scheduled work. */
7512         drm_gem_object_reference(&work->old_fb_obj->base);
7513         drm_gem_object_reference(&obj->base);
7514
7515         crtc->fb = fb;
7516
7517         work->pending_flip_obj = obj;
7518
7519         work->enable_stall_check = true;
7520
7521         atomic_inc(&intel_crtc->unpin_work_count);
7522         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7523
7524         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7525         if (ret)
7526                 goto cleanup_pending;
7527
7528         intel_disable_fbc(dev);
7529         intel_mark_fb_busy(obj);
7530         mutex_unlock(&dev->struct_mutex);
7531
7532         trace_i915_flip_request(intel_crtc->plane, obj);
7533
7534         return 0;
7535
7536 cleanup_pending:
7537         atomic_dec(&intel_crtc->unpin_work_count);
7538         crtc->fb = old_fb;
7539         drm_gem_object_unreference(&work->old_fb_obj->base);
7540         drm_gem_object_unreference(&obj->base);
7541         mutex_unlock(&dev->struct_mutex);
7542
7543 cleanup:
7544         spin_lock_irqsave(&dev->event_lock, flags);
7545         intel_crtc->unpin_work = NULL;
7546         spin_unlock_irqrestore(&dev->event_lock, flags);
7547
7548         drm_vblank_put(dev, intel_crtc->pipe);
7549 free_work:
7550         kfree(work);
7551
7552         return ret;
7553 }
7554
7555 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7556         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7557         .load_lut = intel_crtc_load_lut,
7558 };
7559
7560 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7561 {
7562         struct intel_encoder *other_encoder;
7563         struct drm_crtc *crtc = &encoder->new_crtc->base;
7564
7565         if (WARN_ON(!crtc))
7566                 return false;
7567
7568         list_for_each_entry(other_encoder,
7569                             &crtc->dev->mode_config.encoder_list,
7570                             base.head) {
7571
7572                 if (&other_encoder->new_crtc->base != crtc ||
7573                     encoder == other_encoder)
7574                         continue;
7575                 else
7576                         return true;
7577         }
7578
7579         return false;
7580 }
7581
7582 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7583                                   struct drm_crtc *crtc)
7584 {
7585         struct drm_device *dev;
7586         struct drm_crtc *tmp;
7587         int crtc_mask = 1;
7588
7589         WARN(!crtc, "checking null crtc?\n");
7590
7591         dev = crtc->dev;
7592
7593         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7594                 if (tmp == crtc)
7595                         break;
7596                 crtc_mask <<= 1;
7597         }
7598
7599         if (encoder->possible_crtcs & crtc_mask)
7600                 return true;
7601         return false;
7602 }
7603
7604 /**
7605  * intel_modeset_update_staged_output_state
7606  *
7607  * Updates the staged output configuration state, e.g. after we've read out the
7608  * current hw state.
7609  */
7610 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7611 {
7612         struct intel_encoder *encoder;
7613         struct intel_connector *connector;
7614
7615         list_for_each_entry(connector, &dev->mode_config.connector_list,
7616                             base.head) {
7617                 connector->new_encoder =
7618                         to_intel_encoder(connector->base.encoder);
7619         }
7620
7621         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7622                             base.head) {
7623                 encoder->new_crtc =
7624                         to_intel_crtc(encoder->base.crtc);
7625         }
7626 }
7627
7628 /**
7629  * intel_modeset_commit_output_state
7630  *
7631  * This function copies the stage display pipe configuration to the real one.
7632  */
7633 static void intel_modeset_commit_output_state(struct drm_device *dev)
7634 {
7635         struct intel_encoder *encoder;
7636         struct intel_connector *connector;
7637
7638         list_for_each_entry(connector, &dev->mode_config.connector_list,
7639                             base.head) {
7640                 connector->base.encoder = &connector->new_encoder->base;
7641         }
7642
7643         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7644                             base.head) {
7645                 encoder->base.crtc = &encoder->new_crtc->base;
7646         }
7647 }
7648
7649 static int
7650 pipe_config_set_bpp(struct drm_crtc *crtc,
7651                     struct drm_framebuffer *fb,
7652                     struct intel_crtc_config *pipe_config)
7653 {
7654         struct drm_device *dev = crtc->dev;
7655         struct drm_connector *connector;
7656         int bpp;
7657
7658         switch (fb->pixel_format) {
7659         case DRM_FORMAT_C8:
7660                 bpp = 8*3; /* since we go through a colormap */
7661                 break;
7662         case DRM_FORMAT_XRGB1555:
7663         case DRM_FORMAT_ARGB1555:
7664                 /* checked in intel_framebuffer_init already */
7665                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7666                         return -EINVAL;
7667         case DRM_FORMAT_RGB565:
7668                 bpp = 6*3; /* min is 18bpp */
7669                 break;
7670         case DRM_FORMAT_XBGR8888:
7671         case DRM_FORMAT_ABGR8888:
7672                 /* checked in intel_framebuffer_init already */
7673                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7674                         return -EINVAL;
7675         case DRM_FORMAT_XRGB8888:
7676         case DRM_FORMAT_ARGB8888:
7677                 bpp = 8*3;
7678                 break;
7679         case DRM_FORMAT_XRGB2101010:
7680         case DRM_FORMAT_ARGB2101010:
7681         case DRM_FORMAT_XBGR2101010:
7682         case DRM_FORMAT_ABGR2101010:
7683                 /* checked in intel_framebuffer_init already */
7684                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7685                         return -EINVAL;
7686                 bpp = 10*3;
7687                 break;
7688         /* TODO: gen4+ supports 16 bpc floating point, too. */
7689         default:
7690                 DRM_DEBUG_KMS("unsupported depth\n");
7691                 return -EINVAL;
7692         }
7693
7694         pipe_config->pipe_bpp = bpp;
7695
7696         /* Clamp display bpp to EDID value */
7697         list_for_each_entry(connector, &dev->mode_config.connector_list,
7698                             head) {
7699                 if (connector->encoder && connector->encoder->crtc != crtc)
7700                         continue;
7701
7702                 /* Don't use an invalid EDID bpc value */
7703                 if (connector->display_info.bpc &&
7704                     connector->display_info.bpc * 3 < bpp) {
7705                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7706                                       bpp, connector->display_info.bpc*3);
7707                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7708                 }
7709         }
7710
7711         return bpp;
7712 }
7713
7714 static struct intel_crtc_config *
7715 intel_modeset_pipe_config(struct drm_crtc *crtc,
7716                           struct drm_framebuffer *fb,
7717                           struct drm_display_mode *mode)
7718 {
7719         struct drm_device *dev = crtc->dev;
7720         struct drm_encoder_helper_funcs *encoder_funcs;
7721         struct intel_encoder *encoder;
7722         struct intel_crtc_config *pipe_config;
7723         int plane_bpp;
7724
7725         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7726         if (!pipe_config)
7727                 return ERR_PTR(-ENOMEM);
7728
7729         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7730         drm_mode_copy(&pipe_config->requested_mode, mode);
7731
7732         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7733         if (plane_bpp < 0)
7734                 goto fail;
7735
7736         /* Pass our mode to the connectors and the CRTC to give them a chance to
7737          * adjust it according to limitations or connector properties, and also
7738          * a chance to reject the mode entirely.
7739          */
7740         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7741                             base.head) {
7742
7743                 if (&encoder->new_crtc->base != crtc)
7744                         continue;
7745
7746                 if (encoder->compute_config) {
7747                         if (!(encoder->compute_config(encoder, pipe_config))) {
7748                                 DRM_DEBUG_KMS("Encoder config failure\n");
7749                                 goto fail;
7750                         }
7751
7752                         continue;
7753                 }
7754
7755                 encoder_funcs = encoder->base.helper_private;
7756                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7757                                                 &pipe_config->requested_mode,
7758                                                 &pipe_config->adjusted_mode))) {
7759                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7760                         goto fail;
7761                 }
7762         }
7763
7764         if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7765                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7766                 goto fail;
7767         }
7768         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7769
7770         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7771         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7772                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7773
7774         return pipe_config;
7775 fail:
7776         kfree(pipe_config);
7777         return ERR_PTR(-EINVAL);
7778 }
7779
7780 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7781  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7782 static void
7783 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7784                              unsigned *prepare_pipes, unsigned *disable_pipes)
7785 {
7786         struct intel_crtc *intel_crtc;
7787         struct drm_device *dev = crtc->dev;
7788         struct intel_encoder *encoder;
7789         struct intel_connector *connector;
7790         struct drm_crtc *tmp_crtc;
7791
7792         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7793
7794         /* Check which crtcs have changed outputs connected to them, these need
7795          * to be part of the prepare_pipes mask. We don't (yet) support global
7796          * modeset across multiple crtcs, so modeset_pipes will only have one
7797          * bit set at most. */
7798         list_for_each_entry(connector, &dev->mode_config.connector_list,
7799                             base.head) {
7800                 if (connector->base.encoder == &connector->new_encoder->base)
7801                         continue;
7802
7803                 if (connector->base.encoder) {
7804                         tmp_crtc = connector->base.encoder->crtc;
7805
7806                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7807                 }
7808
7809                 if (connector->new_encoder)
7810                         *prepare_pipes |=
7811                                 1 << connector->new_encoder->new_crtc->pipe;
7812         }
7813
7814         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7815                             base.head) {
7816                 if (encoder->base.crtc == &encoder->new_crtc->base)
7817                         continue;
7818
7819                 if (encoder->base.crtc) {
7820                         tmp_crtc = encoder->base.crtc;
7821
7822                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7823                 }
7824
7825                 if (encoder->new_crtc)
7826                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7827         }
7828
7829         /* Check for any pipes that will be fully disabled ... */
7830         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7831                             base.head) {
7832                 bool used = false;
7833
7834                 /* Don't try to disable disabled crtcs. */
7835                 if (!intel_crtc->base.enabled)
7836                         continue;
7837
7838                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7839                                     base.head) {
7840                         if (encoder->new_crtc == intel_crtc)
7841                                 used = true;
7842                 }
7843
7844                 if (!used)
7845                         *disable_pipes |= 1 << intel_crtc->pipe;
7846         }
7847
7848
7849         /* set_mode is also used to update properties on life display pipes. */
7850         intel_crtc = to_intel_crtc(crtc);
7851         if (crtc->enabled)
7852                 *prepare_pipes |= 1 << intel_crtc->pipe;
7853
7854         /*
7855          * For simplicity do a full modeset on any pipe where the output routing
7856          * changed. We could be more clever, but that would require us to be
7857          * more careful with calling the relevant encoder->mode_set functions.
7858          */
7859         if (*prepare_pipes)
7860                 *modeset_pipes = *prepare_pipes;
7861
7862         /* ... and mask these out. */
7863         *modeset_pipes &= ~(*disable_pipes);
7864         *prepare_pipes &= ~(*disable_pipes);
7865
7866         /*
7867          * HACK: We don't (yet) fully support global modesets. intel_set_config
7868          * obies this rule, but the modeset restore mode of
7869          * intel_modeset_setup_hw_state does not.
7870          */
7871         *modeset_pipes &= 1 << intel_crtc->pipe;
7872         *prepare_pipes &= 1 << intel_crtc->pipe;
7873
7874         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7875                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7876 }
7877
7878 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7879 {
7880         struct drm_encoder *encoder;
7881         struct drm_device *dev = crtc->dev;
7882
7883         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7884                 if (encoder->crtc == crtc)
7885                         return true;
7886
7887         return false;
7888 }
7889
7890 static void
7891 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7892 {
7893         struct intel_encoder *intel_encoder;
7894         struct intel_crtc *intel_crtc;
7895         struct drm_connector *connector;
7896
7897         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7898                             base.head) {
7899                 if (!intel_encoder->base.crtc)
7900                         continue;
7901
7902                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7903
7904                 if (prepare_pipes & (1 << intel_crtc->pipe))
7905                         intel_encoder->connectors_active = false;
7906         }
7907
7908         intel_modeset_commit_output_state(dev);
7909
7910         /* Update computed state. */
7911         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7912                             base.head) {
7913                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7914         }
7915
7916         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7917                 if (!connector->encoder || !connector->encoder->crtc)
7918                         continue;
7919
7920                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7921
7922                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7923                         struct drm_property *dpms_property =
7924                                 dev->mode_config.dpms_property;
7925
7926                         connector->dpms = DRM_MODE_DPMS_ON;
7927                         drm_object_property_set_value(&connector->base,
7928                                                          dpms_property,
7929                                                          DRM_MODE_DPMS_ON);
7930
7931                         intel_encoder = to_intel_encoder(connector->encoder);
7932                         intel_encoder->connectors_active = true;
7933                 }
7934         }
7935
7936 }
7937
7938 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7939         list_for_each_entry((intel_crtc), \
7940                             &(dev)->mode_config.crtc_list, \
7941                             base.head) \
7942                 if (mask & (1 <<(intel_crtc)->pipe)) \
7943
7944 static bool
7945 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7946                           struct intel_crtc_config *pipe_config)
7947 {
7948         if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7949                 DRM_ERROR("mismatch in has_pch_encoder "
7950                           "(expected %i, found %i)\n",
7951                           current_config->has_pch_encoder,
7952                           pipe_config->has_pch_encoder);
7953                 return false;
7954         }
7955
7956         return true;
7957 }
7958
7959 void
7960 intel_modeset_check_state(struct drm_device *dev)
7961 {
7962         drm_i915_private_t *dev_priv = dev->dev_private;
7963         struct intel_crtc *crtc;
7964         struct intel_encoder *encoder;
7965         struct intel_connector *connector;
7966         struct intel_crtc_config pipe_config;
7967
7968         list_for_each_entry(connector, &dev->mode_config.connector_list,
7969                             base.head) {
7970                 /* This also checks the encoder/connector hw state with the
7971                  * ->get_hw_state callbacks. */
7972                 intel_connector_check_state(connector);
7973
7974                 WARN(&connector->new_encoder->base != connector->base.encoder,
7975                      "connector's staged encoder doesn't match current encoder\n");
7976         }
7977
7978         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7979                             base.head) {
7980                 bool enabled = false;
7981                 bool active = false;
7982                 enum pipe pipe, tracked_pipe;
7983
7984                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7985                               encoder->base.base.id,
7986                               drm_get_encoder_name(&encoder->base));
7987
7988                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7989                      "encoder's stage crtc doesn't match current crtc\n");
7990                 WARN(encoder->connectors_active && !encoder->base.crtc,
7991                      "encoder's active_connectors set, but no crtc\n");
7992
7993                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7994                                     base.head) {
7995                         if (connector->base.encoder != &encoder->base)
7996                                 continue;
7997                         enabled = true;
7998                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7999                                 active = true;
8000                 }
8001                 WARN(!!encoder->base.crtc != enabled,
8002                      "encoder's enabled state mismatch "
8003                      "(expected %i, found %i)\n",
8004                      !!encoder->base.crtc, enabled);
8005                 WARN(active && !encoder->base.crtc,
8006                      "active encoder with no crtc\n");
8007
8008                 WARN(encoder->connectors_active != active,
8009                      "encoder's computed active state doesn't match tracked active state "
8010                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8011
8012                 active = encoder->get_hw_state(encoder, &pipe);
8013                 WARN(active != encoder->connectors_active,
8014                      "encoder's hw state doesn't match sw tracking "
8015                      "(expected %i, found %i)\n",
8016                      encoder->connectors_active, active);
8017
8018                 if (!encoder->base.crtc)
8019                         continue;
8020
8021                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8022                 WARN(active && pipe != tracked_pipe,
8023                      "active encoder's pipe doesn't match"
8024                      "(expected %i, found %i)\n",
8025                      tracked_pipe, pipe);
8026
8027         }
8028
8029         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8030                             base.head) {
8031                 bool enabled = false;
8032                 bool active = false;
8033
8034                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8035                               crtc->base.base.id);
8036
8037                 WARN(crtc->active && !crtc->base.enabled,
8038                      "active crtc, but not enabled in sw tracking\n");
8039
8040                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8041                                     base.head) {
8042                         if (encoder->base.crtc != &crtc->base)
8043                                 continue;
8044                         enabled = true;
8045                         if (encoder->connectors_active)
8046                                 active = true;
8047                 }
8048                 WARN(active != crtc->active,
8049                      "crtc's computed active state doesn't match tracked active state "
8050                      "(expected %i, found %i)\n", active, crtc->active);
8051                 WARN(enabled != crtc->base.enabled,
8052                      "crtc's computed enabled state doesn't match tracked enabled state "
8053                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8054
8055                 memset(&pipe_config, 0, sizeof(pipe_config));
8056                 active = dev_priv->display.get_pipe_config(crtc,
8057                                                            &pipe_config);
8058                 WARN(crtc->active != active,
8059                      "crtc active state doesn't match with hw state "
8060                      "(expected %i, found %i)\n", crtc->active, active);
8061
8062                 WARN(active &&
8063                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
8064                      "pipe state doesn't match!\n");
8065         }
8066 }
8067
8068 static int __intel_set_mode(struct drm_crtc *crtc,
8069                             struct drm_display_mode *mode,
8070                             int x, int y, struct drm_framebuffer *fb)
8071 {
8072         struct drm_device *dev = crtc->dev;
8073         drm_i915_private_t *dev_priv = dev->dev_private;
8074         struct drm_display_mode *saved_mode, *saved_hwmode;
8075         struct intel_crtc_config *pipe_config = NULL;
8076         struct intel_crtc *intel_crtc;
8077         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8078         int ret = 0;
8079
8080         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8081         if (!saved_mode)
8082                 return -ENOMEM;
8083         saved_hwmode = saved_mode + 1;
8084
8085         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8086                                      &prepare_pipes, &disable_pipes);
8087
8088         *saved_hwmode = crtc->hwmode;
8089         *saved_mode = crtc->mode;
8090
8091         /* Hack: Because we don't (yet) support global modeset on multiple
8092          * crtcs, we don't keep track of the new mode for more than one crtc.
8093          * Hence simply check whether any bit is set in modeset_pipes in all the
8094          * pieces of code that are not yet converted to deal with mutliple crtcs
8095          * changing their mode at the same time. */
8096         if (modeset_pipes) {
8097                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8098                 if (IS_ERR(pipe_config)) {
8099                         ret = PTR_ERR(pipe_config);
8100                         pipe_config = NULL;
8101
8102                         goto out;
8103                 }
8104         }
8105
8106         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8107                 intel_crtc_disable(&intel_crtc->base);
8108
8109         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8110                 if (intel_crtc->base.enabled)
8111                         dev_priv->display.crtc_disable(&intel_crtc->base);
8112         }
8113
8114         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8115          * to set it here already despite that we pass it down the callchain.
8116          */
8117         if (modeset_pipes) {
8118                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8119                 crtc->mode = *mode;
8120                 /* mode_set/enable/disable functions rely on a correct pipe
8121                  * config. */
8122                 to_intel_crtc(crtc)->config = *pipe_config;
8123                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8124         }
8125
8126         /* Only after disabling all output pipelines that will be changed can we
8127          * update the the output configuration. */
8128         intel_modeset_update_state(dev, prepare_pipes);
8129
8130         if (dev_priv->display.modeset_global_resources)
8131                 dev_priv->display.modeset_global_resources(dev);
8132
8133         /* Set up the DPLL and any encoders state that needs to adjust or depend
8134          * on the DPLL.
8135          */
8136         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8137                 ret = intel_crtc_mode_set(&intel_crtc->base,
8138                                           x, y, fb);
8139                 if (ret)
8140                         goto done;
8141         }
8142
8143         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8144         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8145                 dev_priv->display.crtc_enable(&intel_crtc->base);
8146
8147         if (modeset_pipes) {
8148                 /* Store real post-adjustment hardware mode. */
8149                 crtc->hwmode = pipe_config->adjusted_mode;
8150
8151                 /* Calculate and store various constants which
8152                  * are later needed by vblank and swap-completion
8153                  * timestamping. They are derived from true hwmode.
8154                  */
8155                 drm_calc_timestamping_constants(crtc);
8156         }
8157
8158         /* FIXME: add subpixel order */
8159 done:
8160         if (ret && crtc->enabled) {
8161                 crtc->hwmode = *saved_hwmode;
8162                 crtc->mode = *saved_mode;
8163         }
8164
8165 out:
8166         kfree(pipe_config);
8167         kfree(saved_mode);
8168         return ret;
8169 }
8170
8171 int intel_set_mode(struct drm_crtc *crtc,
8172                      struct drm_display_mode *mode,
8173                      int x, int y, struct drm_framebuffer *fb)
8174 {
8175         int ret;
8176
8177         ret = __intel_set_mode(crtc, mode, x, y, fb);
8178
8179         if (ret == 0)
8180                 intel_modeset_check_state(crtc->dev);
8181
8182         return ret;
8183 }
8184
8185 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8186 {
8187         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8188 }
8189
8190 #undef for_each_intel_crtc_masked
8191
8192 static void intel_set_config_free(struct intel_set_config *config)
8193 {
8194         if (!config)
8195                 return;
8196
8197         kfree(config->save_connector_encoders);
8198         kfree(config->save_encoder_crtcs);
8199         kfree(config);
8200 }
8201
8202 static int intel_set_config_save_state(struct drm_device *dev,
8203                                        struct intel_set_config *config)
8204 {
8205         struct drm_encoder *encoder;
8206         struct drm_connector *connector;
8207         int count;
8208
8209         config->save_encoder_crtcs =
8210                 kcalloc(dev->mode_config.num_encoder,
8211                         sizeof(struct drm_crtc *), GFP_KERNEL);
8212         if (!config->save_encoder_crtcs)
8213                 return -ENOMEM;
8214
8215         config->save_connector_encoders =
8216                 kcalloc(dev->mode_config.num_connector,
8217                         sizeof(struct drm_encoder *), GFP_KERNEL);
8218         if (!config->save_connector_encoders)
8219                 return -ENOMEM;
8220
8221         /* Copy data. Note that driver private data is not affected.
8222          * Should anything bad happen only the expected state is
8223          * restored, not the drivers personal bookkeeping.
8224          */
8225         count = 0;
8226         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8227                 config->save_encoder_crtcs[count++] = encoder->crtc;
8228         }
8229
8230         count = 0;
8231         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8232                 config->save_connector_encoders[count++] = connector->encoder;
8233         }
8234
8235         return 0;
8236 }
8237
8238 static void intel_set_config_restore_state(struct drm_device *dev,
8239                                            struct intel_set_config *config)
8240 {
8241         struct intel_encoder *encoder;
8242         struct intel_connector *connector;
8243         int count;
8244
8245         count = 0;
8246         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8247                 encoder->new_crtc =
8248                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8249         }
8250
8251         count = 0;
8252         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8253                 connector->new_encoder =
8254                         to_intel_encoder(config->save_connector_encoders[count++]);
8255         }
8256 }
8257
8258 static void
8259 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8260                                       struct intel_set_config *config)
8261 {
8262
8263         /* We should be able to check here if the fb has the same properties
8264          * and then just flip_or_move it */
8265         if (set->crtc->fb != set->fb) {
8266                 /* If we have no fb then treat it as a full mode set */
8267                 if (set->crtc->fb == NULL) {
8268                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8269                         config->mode_changed = true;
8270                 } else if (set->fb == NULL) {
8271                         config->mode_changed = true;
8272                 } else if (set->fb->pixel_format !=
8273                            set->crtc->fb->pixel_format) {
8274                         config->mode_changed = true;
8275                 } else
8276                         config->fb_changed = true;
8277         }
8278
8279         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8280                 config->fb_changed = true;
8281
8282         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8283                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8284                 drm_mode_debug_printmodeline(&set->crtc->mode);
8285                 drm_mode_debug_printmodeline(set->mode);
8286                 config->mode_changed = true;
8287         }
8288 }
8289
8290 static int
8291 intel_modeset_stage_output_state(struct drm_device *dev,
8292                                  struct drm_mode_set *set,
8293                                  struct intel_set_config *config)
8294 {
8295         struct drm_crtc *new_crtc;
8296         struct intel_connector *connector;
8297         struct intel_encoder *encoder;
8298         int count, ro;
8299
8300         /* The upper layers ensure that we either disable a crtc or have a list
8301          * of connectors. For paranoia, double-check this. */
8302         WARN_ON(!set->fb && (set->num_connectors != 0));
8303         WARN_ON(set->fb && (set->num_connectors == 0));
8304
8305         count = 0;
8306         list_for_each_entry(connector, &dev->mode_config.connector_list,
8307                             base.head) {
8308                 /* Otherwise traverse passed in connector list and get encoders
8309                  * for them. */
8310                 for (ro = 0; ro < set->num_connectors; ro++) {
8311                         if (set->connectors[ro] == &connector->base) {
8312                                 connector->new_encoder = connector->encoder;
8313                                 break;
8314                         }
8315                 }
8316
8317                 /* If we disable the crtc, disable all its connectors. Also, if
8318                  * the connector is on the changing crtc but not on the new
8319                  * connector list, disable it. */
8320                 if ((!set->fb || ro == set->num_connectors) &&
8321                     connector->base.encoder &&
8322                     connector->base.encoder->crtc == set->crtc) {
8323                         connector->new_encoder = NULL;
8324
8325                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8326                                 connector->base.base.id,
8327                                 drm_get_connector_name(&connector->base));
8328                 }
8329
8330
8331                 if (&connector->new_encoder->base != connector->base.encoder) {
8332                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8333                         config->mode_changed = true;
8334                 }
8335         }
8336         /* connector->new_encoder is now updated for all connectors. */
8337
8338         /* Update crtc of enabled connectors. */
8339         count = 0;
8340         list_for_each_entry(connector, &dev->mode_config.connector_list,
8341                             base.head) {
8342                 if (!connector->new_encoder)
8343                         continue;
8344
8345                 new_crtc = connector->new_encoder->base.crtc;
8346
8347                 for (ro = 0; ro < set->num_connectors; ro++) {
8348                         if (set->connectors[ro] == &connector->base)
8349                                 new_crtc = set->crtc;
8350                 }
8351
8352                 /* Make sure the new CRTC will work with the encoder */
8353                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8354                                            new_crtc)) {
8355                         return -EINVAL;
8356                 }
8357                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8358
8359                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8360                         connector->base.base.id,
8361                         drm_get_connector_name(&connector->base),
8362                         new_crtc->base.id);
8363         }
8364
8365         /* Check for any encoders that needs to be disabled. */
8366         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8367                             base.head) {
8368                 list_for_each_entry(connector,
8369                                     &dev->mode_config.connector_list,
8370                                     base.head) {
8371                         if (connector->new_encoder == encoder) {
8372                                 WARN_ON(!connector->new_encoder->new_crtc);
8373
8374                                 goto next_encoder;
8375                         }
8376                 }
8377                 encoder->new_crtc = NULL;
8378 next_encoder:
8379                 /* Only now check for crtc changes so we don't miss encoders
8380                  * that will be disabled. */
8381                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8382                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8383                         config->mode_changed = true;
8384                 }
8385         }
8386         /* Now we've also updated encoder->new_crtc for all encoders. */
8387
8388         return 0;
8389 }
8390
8391 static int intel_crtc_set_config(struct drm_mode_set *set)
8392 {
8393         struct drm_device *dev;
8394         struct drm_mode_set save_set;
8395         struct intel_set_config *config;
8396         int ret;
8397
8398         BUG_ON(!set);
8399         BUG_ON(!set->crtc);
8400         BUG_ON(!set->crtc->helper_private);
8401
8402         /* Enforce sane interface api - has been abused by the fb helper. */
8403         BUG_ON(!set->mode && set->fb);
8404         BUG_ON(set->fb && set->num_connectors == 0);
8405
8406         if (set->fb) {
8407                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8408                                 set->crtc->base.id, set->fb->base.id,
8409                                 (int)set->num_connectors, set->x, set->y);
8410         } else {
8411                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8412         }
8413
8414         dev = set->crtc->dev;
8415
8416         ret = -ENOMEM;
8417         config = kzalloc(sizeof(*config), GFP_KERNEL);
8418         if (!config)
8419                 goto out_config;
8420
8421         ret = intel_set_config_save_state(dev, config);
8422         if (ret)
8423                 goto out_config;
8424
8425         save_set.crtc = set->crtc;
8426         save_set.mode = &set->crtc->mode;
8427         save_set.x = set->crtc->x;
8428         save_set.y = set->crtc->y;
8429         save_set.fb = set->crtc->fb;
8430
8431         /* Compute whether we need a full modeset, only an fb base update or no
8432          * change at all. In the future we might also check whether only the
8433          * mode changed, e.g. for LVDS where we only change the panel fitter in
8434          * such cases. */
8435         intel_set_config_compute_mode_changes(set, config);
8436
8437         ret = intel_modeset_stage_output_state(dev, set, config);
8438         if (ret)
8439                 goto fail;
8440
8441         if (config->mode_changed) {
8442                 if (set->mode) {
8443                         DRM_DEBUG_KMS("attempting to set mode from"
8444                                         " userspace\n");
8445                         drm_mode_debug_printmodeline(set->mode);
8446                 }
8447
8448                 ret = intel_set_mode(set->crtc, set->mode,
8449                                      set->x, set->y, set->fb);
8450                 if (ret) {
8451                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8452                                   set->crtc->base.id, ret);
8453                         goto fail;
8454                 }
8455         } else if (config->fb_changed) {
8456                 intel_crtc_wait_for_pending_flips(set->crtc);
8457
8458                 ret = intel_pipe_set_base(set->crtc,
8459                                           set->x, set->y, set->fb);
8460         }
8461
8462         intel_set_config_free(config);
8463
8464         return 0;
8465
8466 fail:
8467         intel_set_config_restore_state(dev, config);
8468
8469         /* Try to restore the config */
8470         if (config->mode_changed &&
8471             intel_set_mode(save_set.crtc, save_set.mode,
8472                            save_set.x, save_set.y, save_set.fb))
8473                 DRM_ERROR("failed to restore config after modeset failure\n");
8474
8475 out_config:
8476         intel_set_config_free(config);
8477         return ret;
8478 }
8479
8480 static const struct drm_crtc_funcs intel_crtc_funcs = {
8481         .cursor_set = intel_crtc_cursor_set,
8482         .cursor_move = intel_crtc_cursor_move,
8483         .gamma_set = intel_crtc_gamma_set,
8484         .set_config = intel_crtc_set_config,
8485         .destroy = intel_crtc_destroy,
8486         .page_flip = intel_crtc_page_flip,
8487 };
8488
8489 static void intel_cpu_pll_init(struct drm_device *dev)
8490 {
8491         if (HAS_DDI(dev))
8492                 intel_ddi_pll_init(dev);
8493 }
8494
8495 static void intel_pch_pll_init(struct drm_device *dev)
8496 {
8497         drm_i915_private_t *dev_priv = dev->dev_private;
8498         int i;
8499
8500         if (dev_priv->num_pch_pll == 0) {
8501                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8502                 return;
8503         }
8504
8505         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8506                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8507                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8508                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8509         }
8510 }
8511
8512 static void intel_crtc_init(struct drm_device *dev, int pipe)
8513 {
8514         drm_i915_private_t *dev_priv = dev->dev_private;
8515         struct intel_crtc *intel_crtc;
8516         int i;
8517
8518         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8519         if (intel_crtc == NULL)
8520                 return;
8521
8522         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8523
8524         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8525         for (i = 0; i < 256; i++) {
8526                 intel_crtc->lut_r[i] = i;
8527                 intel_crtc->lut_g[i] = i;
8528                 intel_crtc->lut_b[i] = i;
8529         }
8530
8531         /* Swap pipes & planes for FBC on pre-965 */
8532         intel_crtc->pipe = pipe;
8533         intel_crtc->plane = pipe;
8534         intel_crtc->config.cpu_transcoder = pipe;
8535         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8536                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8537                 intel_crtc->plane = !pipe;
8538         }
8539
8540         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8541                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8542         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8543         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8544
8545         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8546 }
8547
8548 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8549                                 struct drm_file *file)
8550 {
8551         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8552         struct drm_mode_object *drmmode_obj;
8553         struct intel_crtc *crtc;
8554
8555         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8556                 return -ENODEV;
8557
8558         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8559                         DRM_MODE_OBJECT_CRTC);
8560
8561         if (!drmmode_obj) {
8562                 DRM_ERROR("no such CRTC id\n");
8563                 return -EINVAL;
8564         }
8565
8566         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8567         pipe_from_crtc_id->pipe = crtc->pipe;
8568
8569         return 0;
8570 }
8571
8572 static int intel_encoder_clones(struct intel_encoder *encoder)
8573 {
8574         struct drm_device *dev = encoder->base.dev;
8575         struct intel_encoder *source_encoder;
8576         int index_mask = 0;
8577         int entry = 0;
8578
8579         list_for_each_entry(source_encoder,
8580                             &dev->mode_config.encoder_list, base.head) {
8581
8582                 if (encoder == source_encoder)
8583                         index_mask |= (1 << entry);
8584
8585                 /* Intel hw has only one MUX where enocoders could be cloned. */
8586                 if (encoder->cloneable && source_encoder->cloneable)
8587                         index_mask |= (1 << entry);
8588
8589                 entry++;
8590         }
8591
8592         return index_mask;
8593 }
8594
8595 static bool has_edp_a(struct drm_device *dev)
8596 {
8597         struct drm_i915_private *dev_priv = dev->dev_private;
8598
8599         if (!IS_MOBILE(dev))
8600                 return false;
8601
8602         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8603                 return false;
8604
8605         if (IS_GEN5(dev) &&
8606             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8607                 return false;
8608
8609         return true;
8610 }
8611
8612 static void intel_setup_outputs(struct drm_device *dev)
8613 {
8614         struct drm_i915_private *dev_priv = dev->dev_private;
8615         struct intel_encoder *encoder;
8616         bool dpd_is_edp = false;
8617         bool has_lvds;
8618
8619         has_lvds = intel_lvds_init(dev);
8620         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8621                 /* disable the panel fitter on everything but LVDS */
8622                 I915_WRITE(PFIT_CONTROL, 0);
8623         }
8624
8625         if (!IS_ULT(dev))
8626                 intel_crt_init(dev);
8627
8628         if (HAS_DDI(dev)) {
8629                 int found;
8630
8631                 /* Haswell uses DDI functions to detect digital outputs */
8632                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8633                 /* DDI A only supports eDP */
8634                 if (found)
8635                         intel_ddi_init(dev, PORT_A);
8636
8637                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8638                  * register */
8639                 found = I915_READ(SFUSE_STRAP);
8640
8641                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8642                         intel_ddi_init(dev, PORT_B);
8643                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8644                         intel_ddi_init(dev, PORT_C);
8645                 if (found & SFUSE_STRAP_DDID_DETECTED)
8646                         intel_ddi_init(dev, PORT_D);
8647         } else if (HAS_PCH_SPLIT(dev)) {
8648                 int found;
8649                 dpd_is_edp = intel_dpd_is_edp(dev);
8650
8651                 if (has_edp_a(dev))
8652                         intel_dp_init(dev, DP_A, PORT_A);
8653
8654                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8655                         /* PCH SDVOB multiplex with HDMIB */
8656                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8657                         if (!found)
8658                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8659                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8660                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8661                 }
8662
8663                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8664                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8665
8666                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8667                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8668
8669                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8670                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8671
8672                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8673                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8674         } else if (IS_VALLEYVIEW(dev)) {
8675                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8676                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8677                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8678
8679                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8680                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8681                                         PORT_B);
8682                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8683                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8684                 }
8685         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8686                 bool found = false;
8687
8688                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8689                         DRM_DEBUG_KMS("probing SDVOB\n");
8690                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8691                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8692                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8693                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8694                         }
8695
8696                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8697                                 DRM_DEBUG_KMS("probing DP_B\n");
8698                                 intel_dp_init(dev, DP_B, PORT_B);
8699                         }
8700                 }
8701
8702                 /* Before G4X SDVOC doesn't have its own detect register */
8703
8704                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8705                         DRM_DEBUG_KMS("probing SDVOC\n");
8706                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8707                 }
8708
8709                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8710
8711                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8712                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8713                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8714                         }
8715                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8716                                 DRM_DEBUG_KMS("probing DP_C\n");
8717                                 intel_dp_init(dev, DP_C, PORT_C);
8718                         }
8719                 }
8720
8721                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8722                     (I915_READ(DP_D) & DP_DETECTED)) {
8723                         DRM_DEBUG_KMS("probing DP_D\n");
8724                         intel_dp_init(dev, DP_D, PORT_D);
8725                 }
8726         } else if (IS_GEN2(dev))
8727                 intel_dvo_init(dev);
8728
8729         if (SUPPORTS_TV(dev))
8730                 intel_tv_init(dev);
8731
8732         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8733                 encoder->base.possible_crtcs = encoder->crtc_mask;
8734                 encoder->base.possible_clones =
8735                         intel_encoder_clones(encoder);
8736         }
8737
8738         intel_init_pch_refclk(dev);
8739
8740         drm_helper_move_panel_connectors_to_head(dev);
8741 }
8742
8743 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8744 {
8745         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8746
8747         drm_framebuffer_cleanup(fb);
8748         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8749
8750         kfree(intel_fb);
8751 }
8752
8753 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8754                                                 struct drm_file *file,
8755                                                 unsigned int *handle)
8756 {
8757         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8758         struct drm_i915_gem_object *obj = intel_fb->obj;
8759
8760         return drm_gem_handle_create(file, &obj->base, handle);
8761 }
8762
8763 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8764         .destroy = intel_user_framebuffer_destroy,
8765         .create_handle = intel_user_framebuffer_create_handle,
8766 };
8767
8768 int intel_framebuffer_init(struct drm_device *dev,
8769                            struct intel_framebuffer *intel_fb,
8770                            struct drm_mode_fb_cmd2 *mode_cmd,
8771                            struct drm_i915_gem_object *obj)
8772 {
8773         int ret;
8774
8775         if (obj->tiling_mode == I915_TILING_Y) {
8776                 DRM_DEBUG("hardware does not support tiling Y\n");
8777                 return -EINVAL;
8778         }
8779
8780         if (mode_cmd->pitches[0] & 63) {
8781                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8782                           mode_cmd->pitches[0]);
8783                 return -EINVAL;
8784         }
8785
8786         /* FIXME <= Gen4 stride limits are bit unclear */
8787         if (mode_cmd->pitches[0] > 32768) {
8788                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8789                           mode_cmd->pitches[0]);
8790                 return -EINVAL;
8791         }
8792
8793         if (obj->tiling_mode != I915_TILING_NONE &&
8794             mode_cmd->pitches[0] != obj->stride) {
8795                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8796                           mode_cmd->pitches[0], obj->stride);
8797                 return -EINVAL;
8798         }
8799
8800         /* Reject formats not supported by any plane early. */
8801         switch (mode_cmd->pixel_format) {
8802         case DRM_FORMAT_C8:
8803         case DRM_FORMAT_RGB565:
8804         case DRM_FORMAT_XRGB8888:
8805         case DRM_FORMAT_ARGB8888:
8806                 break;
8807         case DRM_FORMAT_XRGB1555:
8808         case DRM_FORMAT_ARGB1555:
8809                 if (INTEL_INFO(dev)->gen > 3) {
8810                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8811                         return -EINVAL;
8812                 }
8813                 break;
8814         case DRM_FORMAT_XBGR8888:
8815         case DRM_FORMAT_ABGR8888:
8816         case DRM_FORMAT_XRGB2101010:
8817         case DRM_FORMAT_ARGB2101010:
8818         case DRM_FORMAT_XBGR2101010:
8819         case DRM_FORMAT_ABGR2101010:
8820                 if (INTEL_INFO(dev)->gen < 4) {
8821                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8822                         return -EINVAL;
8823                 }
8824                 break;
8825         case DRM_FORMAT_YUYV:
8826         case DRM_FORMAT_UYVY:
8827         case DRM_FORMAT_YVYU:
8828         case DRM_FORMAT_VYUY:
8829                 if (INTEL_INFO(dev)->gen < 5) {
8830                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8831                         return -EINVAL;
8832                 }
8833                 break;
8834         default:
8835                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8836                 return -EINVAL;
8837         }
8838
8839         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8840         if (mode_cmd->offsets[0] != 0)
8841                 return -EINVAL;
8842
8843         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8844         intel_fb->obj = obj;
8845
8846         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8847         if (ret) {
8848                 DRM_ERROR("framebuffer init failed %d\n", ret);
8849                 return ret;
8850         }
8851
8852         return 0;
8853 }
8854
8855 static struct drm_framebuffer *
8856 intel_user_framebuffer_create(struct drm_device *dev,
8857                               struct drm_file *filp,
8858                               struct drm_mode_fb_cmd2 *mode_cmd)
8859 {
8860         struct drm_i915_gem_object *obj;
8861
8862         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8863                                                 mode_cmd->handles[0]));
8864         if (&obj->base == NULL)
8865                 return ERR_PTR(-ENOENT);
8866
8867         return intel_framebuffer_create(dev, mode_cmd, obj);
8868 }
8869
8870 static const struct drm_mode_config_funcs intel_mode_funcs = {
8871         .fb_create = intel_user_framebuffer_create,
8872         .output_poll_changed = intel_fb_output_poll_changed,
8873 };
8874
8875 /* Set up chip specific display functions */
8876 static void intel_init_display(struct drm_device *dev)
8877 {
8878         struct drm_i915_private *dev_priv = dev->dev_private;
8879
8880         if (HAS_DDI(dev)) {
8881                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8882                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8883                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8884                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8885                 dev_priv->display.off = haswell_crtc_off;
8886                 dev_priv->display.update_plane = ironlake_update_plane;
8887         } else if (HAS_PCH_SPLIT(dev)) {
8888                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8889                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8890                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8891                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8892                 dev_priv->display.off = ironlake_crtc_off;
8893                 dev_priv->display.update_plane = ironlake_update_plane;
8894         } else if (IS_VALLEYVIEW(dev)) {
8895                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8896                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8897                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8898                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8899                 dev_priv->display.off = i9xx_crtc_off;
8900                 dev_priv->display.update_plane = i9xx_update_plane;
8901         } else {
8902                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8903                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8904                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8905                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8906                 dev_priv->display.off = i9xx_crtc_off;
8907                 dev_priv->display.update_plane = i9xx_update_plane;
8908         }
8909
8910         /* Returns the core display clock speed */
8911         if (IS_VALLEYVIEW(dev))
8912                 dev_priv->display.get_display_clock_speed =
8913                         valleyview_get_display_clock_speed;
8914         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8915                 dev_priv->display.get_display_clock_speed =
8916                         i945_get_display_clock_speed;
8917         else if (IS_I915G(dev))
8918                 dev_priv->display.get_display_clock_speed =
8919                         i915_get_display_clock_speed;
8920         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8921                 dev_priv->display.get_display_clock_speed =
8922                         i9xx_misc_get_display_clock_speed;
8923         else if (IS_I915GM(dev))
8924                 dev_priv->display.get_display_clock_speed =
8925                         i915gm_get_display_clock_speed;
8926         else if (IS_I865G(dev))
8927                 dev_priv->display.get_display_clock_speed =
8928                         i865_get_display_clock_speed;
8929         else if (IS_I85X(dev))
8930                 dev_priv->display.get_display_clock_speed =
8931                         i855_get_display_clock_speed;
8932         else /* 852, 830 */
8933                 dev_priv->display.get_display_clock_speed =
8934                         i830_get_display_clock_speed;
8935
8936         if (HAS_PCH_SPLIT(dev)) {
8937                 if (IS_GEN5(dev)) {
8938                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8939                         dev_priv->display.write_eld = ironlake_write_eld;
8940                 } else if (IS_GEN6(dev)) {
8941                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8942                         dev_priv->display.write_eld = ironlake_write_eld;
8943                 } else if (IS_IVYBRIDGE(dev)) {
8944                         /* FIXME: detect B0+ stepping and use auto training */
8945                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8946                         dev_priv->display.write_eld = ironlake_write_eld;
8947                         dev_priv->display.modeset_global_resources =
8948                                 ivb_modeset_global_resources;
8949                 } else if (IS_HASWELL(dev)) {
8950                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8951                         dev_priv->display.write_eld = haswell_write_eld;
8952                         dev_priv->display.modeset_global_resources =
8953                                 haswell_modeset_global_resources;
8954                 }
8955         } else if (IS_G4X(dev)) {
8956                 dev_priv->display.write_eld = g4x_write_eld;
8957         }
8958
8959         /* Default just returns -ENODEV to indicate unsupported */
8960         dev_priv->display.queue_flip = intel_default_queue_flip;
8961
8962         switch (INTEL_INFO(dev)->gen) {
8963         case 2:
8964                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8965                 break;
8966
8967         case 3:
8968                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8969                 break;
8970
8971         case 4:
8972         case 5:
8973                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8974                 break;
8975
8976         case 6:
8977                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8978                 break;
8979         case 7:
8980                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8981                 break;
8982         }
8983 }
8984
8985 /*
8986  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8987  * resume, or other times.  This quirk makes sure that's the case for
8988  * affected systems.
8989  */
8990 static void quirk_pipea_force(struct drm_device *dev)
8991 {
8992         struct drm_i915_private *dev_priv = dev->dev_private;
8993
8994         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8995         DRM_INFO("applying pipe a force quirk\n");
8996 }
8997
8998 /*
8999  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9000  */
9001 static void quirk_ssc_force_disable(struct drm_device *dev)
9002 {
9003         struct drm_i915_private *dev_priv = dev->dev_private;
9004         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9005         DRM_INFO("applying lvds SSC disable quirk\n");
9006 }
9007
9008 /*
9009  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9010  * brightness value
9011  */
9012 static void quirk_invert_brightness(struct drm_device *dev)
9013 {
9014         struct drm_i915_private *dev_priv = dev->dev_private;
9015         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9016         DRM_INFO("applying inverted panel brightness quirk\n");
9017 }
9018
9019 struct intel_quirk {
9020         int device;
9021         int subsystem_vendor;
9022         int subsystem_device;
9023         void (*hook)(struct drm_device *dev);
9024 };
9025
9026 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9027 struct intel_dmi_quirk {
9028         void (*hook)(struct drm_device *dev);
9029         const struct dmi_system_id (*dmi_id_list)[];
9030 };
9031
9032 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9033 {
9034         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9035         return 1;
9036 }
9037
9038 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9039         {
9040                 .dmi_id_list = &(const struct dmi_system_id[]) {
9041                         {
9042                                 .callback = intel_dmi_reverse_brightness,
9043                                 .ident = "NCR Corporation",
9044                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9045                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9046                                 },
9047                         },
9048                         { }  /* terminating entry */
9049                 },
9050                 .hook = quirk_invert_brightness,
9051         },
9052 };
9053
9054 static struct intel_quirk intel_quirks[] = {
9055         /* HP Mini needs pipe A force quirk (LP: #322104) */
9056         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9057
9058         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9059         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9060
9061         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9062         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9063
9064         /* 830/845 need to leave pipe A & dpll A up */
9065         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9066         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9067
9068         /* Lenovo U160 cannot use SSC on LVDS */
9069         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9070
9071         /* Sony Vaio Y cannot use SSC on LVDS */
9072         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9073
9074         /* Acer Aspire 5734Z must invert backlight brightness */
9075         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9076
9077         /* Acer/eMachines G725 */
9078         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9079
9080         /* Acer/eMachines e725 */
9081         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9082
9083         /* Acer/Packard Bell NCL20 */
9084         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9085
9086         /* Acer Aspire 4736Z */
9087         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9088 };
9089
9090 static void intel_init_quirks(struct drm_device *dev)
9091 {
9092         struct pci_dev *d = dev->pdev;
9093         int i;
9094
9095         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9096                 struct intel_quirk *q = &intel_quirks[i];
9097
9098                 if (d->device == q->device &&
9099                     (d->subsystem_vendor == q->subsystem_vendor ||
9100                      q->subsystem_vendor == PCI_ANY_ID) &&
9101                     (d->subsystem_device == q->subsystem_device ||
9102                      q->subsystem_device == PCI_ANY_ID))
9103                         q->hook(dev);
9104         }
9105         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9106                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9107                         intel_dmi_quirks[i].hook(dev);
9108         }
9109 }
9110
9111 /* Disable the VGA plane that we never use */
9112 static void i915_disable_vga(struct drm_device *dev)
9113 {
9114         struct drm_i915_private *dev_priv = dev->dev_private;
9115         u8 sr1;
9116         u32 vga_reg = i915_vgacntrl_reg(dev);
9117
9118         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9119         outb(SR01, VGA_SR_INDEX);
9120         sr1 = inb(VGA_SR_DATA);
9121         outb(sr1 | 1<<5, VGA_SR_DATA);
9122         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9123         udelay(300);
9124
9125         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9126         POSTING_READ(vga_reg);
9127 }
9128
9129 void intel_modeset_init_hw(struct drm_device *dev)
9130 {
9131         intel_init_power_well(dev);
9132
9133         intel_prepare_ddi(dev);
9134
9135         intel_init_clock_gating(dev);
9136
9137         mutex_lock(&dev->struct_mutex);
9138         intel_enable_gt_powersave(dev);
9139         mutex_unlock(&dev->struct_mutex);
9140 }
9141
9142 void intel_modeset_init(struct drm_device *dev)
9143 {
9144         struct drm_i915_private *dev_priv = dev->dev_private;
9145         int i, j, ret;
9146
9147         drm_mode_config_init(dev);
9148
9149         dev->mode_config.min_width = 0;
9150         dev->mode_config.min_height = 0;
9151
9152         dev->mode_config.preferred_depth = 24;
9153         dev->mode_config.prefer_shadow = 1;
9154
9155         dev->mode_config.funcs = &intel_mode_funcs;
9156
9157         intel_init_quirks(dev);
9158
9159         intel_init_pm(dev);
9160
9161         if (INTEL_INFO(dev)->num_pipes == 0)
9162                 return;
9163
9164         intel_init_display(dev);
9165
9166         if (IS_GEN2(dev)) {
9167                 dev->mode_config.max_width = 2048;
9168                 dev->mode_config.max_height = 2048;
9169         } else if (IS_GEN3(dev)) {
9170                 dev->mode_config.max_width = 4096;
9171                 dev->mode_config.max_height = 4096;
9172         } else {
9173                 dev->mode_config.max_width = 8192;
9174                 dev->mode_config.max_height = 8192;
9175         }
9176         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9177
9178         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9179                       INTEL_INFO(dev)->num_pipes,
9180                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9181
9182         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9183                 intel_crtc_init(dev, i);
9184                 for (j = 0; j < dev_priv->num_plane; j++) {
9185                         ret = intel_plane_init(dev, i, j);
9186                         if (ret)
9187                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9188                                               pipe_name(i), sprite_name(i, j), ret);
9189                 }
9190         }
9191
9192         intel_cpu_pll_init(dev);
9193         intel_pch_pll_init(dev);
9194
9195         /* Just disable it once at startup */
9196         i915_disable_vga(dev);
9197         intel_setup_outputs(dev);
9198
9199         /* Just in case the BIOS is doing something questionable. */
9200         intel_disable_fbc(dev);
9201 }
9202
9203 static void
9204 intel_connector_break_all_links(struct intel_connector *connector)
9205 {
9206         connector->base.dpms = DRM_MODE_DPMS_OFF;
9207         connector->base.encoder = NULL;
9208         connector->encoder->connectors_active = false;
9209         connector->encoder->base.crtc = NULL;
9210 }
9211
9212 static void intel_enable_pipe_a(struct drm_device *dev)
9213 {
9214         struct intel_connector *connector;
9215         struct drm_connector *crt = NULL;
9216         struct intel_load_detect_pipe load_detect_temp;
9217
9218         /* We can't just switch on the pipe A, we need to set things up with a
9219          * proper mode and output configuration. As a gross hack, enable pipe A
9220          * by enabling the load detect pipe once. */
9221         list_for_each_entry(connector,
9222                             &dev->mode_config.connector_list,
9223                             base.head) {
9224                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9225                         crt = &connector->base;
9226                         break;
9227                 }
9228         }
9229
9230         if (!crt)
9231                 return;
9232
9233         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9234                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9235
9236
9237 }
9238
9239 static bool
9240 intel_check_plane_mapping(struct intel_crtc *crtc)
9241 {
9242         struct drm_device *dev = crtc->base.dev;
9243         struct drm_i915_private *dev_priv = dev->dev_private;
9244         u32 reg, val;
9245
9246         if (INTEL_INFO(dev)->num_pipes == 1)
9247                 return true;
9248
9249         reg = DSPCNTR(!crtc->plane);
9250         val = I915_READ(reg);
9251
9252         if ((val & DISPLAY_PLANE_ENABLE) &&
9253             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9254                 return false;
9255
9256         return true;
9257 }
9258
9259 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9260 {
9261         struct drm_device *dev = crtc->base.dev;
9262         struct drm_i915_private *dev_priv = dev->dev_private;
9263         u32 reg;
9264
9265         /* Clear any frame start delays used for debugging left by the BIOS */
9266         reg = PIPECONF(crtc->config.cpu_transcoder);
9267         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9268
9269         /* We need to sanitize the plane -> pipe mapping first because this will
9270          * disable the crtc (and hence change the state) if it is wrong. Note
9271          * that gen4+ has a fixed plane -> pipe mapping.  */
9272         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9273                 struct intel_connector *connector;
9274                 bool plane;
9275
9276                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9277                               crtc->base.base.id);
9278
9279                 /* Pipe has the wrong plane attached and the plane is active.
9280                  * Temporarily change the plane mapping and disable everything
9281                  * ...  */
9282                 plane = crtc->plane;
9283                 crtc->plane = !plane;
9284                 dev_priv->display.crtc_disable(&crtc->base);
9285                 crtc->plane = plane;
9286
9287                 /* ... and break all links. */
9288                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9289                                     base.head) {
9290                         if (connector->encoder->base.crtc != &crtc->base)
9291                                 continue;
9292
9293                         intel_connector_break_all_links(connector);
9294                 }
9295
9296                 WARN_ON(crtc->active);
9297                 crtc->base.enabled = false;
9298         }
9299
9300         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9301             crtc->pipe == PIPE_A && !crtc->active) {
9302                 /* BIOS forgot to enable pipe A, this mostly happens after
9303                  * resume. Force-enable the pipe to fix this, the update_dpms
9304                  * call below we restore the pipe to the right state, but leave
9305                  * the required bits on. */
9306                 intel_enable_pipe_a(dev);
9307         }
9308
9309         /* Adjust the state of the output pipe according to whether we
9310          * have active connectors/encoders. */
9311         intel_crtc_update_dpms(&crtc->base);
9312
9313         if (crtc->active != crtc->base.enabled) {
9314                 struct intel_encoder *encoder;
9315
9316                 /* This can happen either due to bugs in the get_hw_state
9317                  * functions or because the pipe is force-enabled due to the
9318                  * pipe A quirk. */
9319                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9320                               crtc->base.base.id,
9321                               crtc->base.enabled ? "enabled" : "disabled",
9322                               crtc->active ? "enabled" : "disabled");
9323
9324                 crtc->base.enabled = crtc->active;
9325
9326                 /* Because we only establish the connector -> encoder ->
9327                  * crtc links if something is active, this means the
9328                  * crtc is now deactivated. Break the links. connector
9329                  * -> encoder links are only establish when things are
9330                  *  actually up, hence no need to break them. */
9331                 WARN_ON(crtc->active);
9332
9333                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9334                         WARN_ON(encoder->connectors_active);
9335                         encoder->base.crtc = NULL;
9336                 }
9337         }
9338 }
9339
9340 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9341 {
9342         struct intel_connector *connector;
9343         struct drm_device *dev = encoder->base.dev;
9344
9345         /* We need to check both for a crtc link (meaning that the
9346          * encoder is active and trying to read from a pipe) and the
9347          * pipe itself being active. */
9348         bool has_active_crtc = encoder->base.crtc &&
9349                 to_intel_crtc(encoder->base.crtc)->active;
9350
9351         if (encoder->connectors_active && !has_active_crtc) {
9352                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9353                               encoder->base.base.id,
9354                               drm_get_encoder_name(&encoder->base));
9355
9356                 /* Connector is active, but has no active pipe. This is
9357                  * fallout from our resume register restoring. Disable
9358                  * the encoder manually again. */
9359                 if (encoder->base.crtc) {
9360                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9361                                       encoder->base.base.id,
9362                                       drm_get_encoder_name(&encoder->base));
9363                         encoder->disable(encoder);
9364                 }
9365
9366                 /* Inconsistent output/port/pipe state happens presumably due to
9367                  * a bug in one of the get_hw_state functions. Or someplace else
9368                  * in our code, like the register restore mess on resume. Clamp
9369                  * things to off as a safer default. */
9370                 list_for_each_entry(connector,
9371                                     &dev->mode_config.connector_list,
9372                                     base.head) {
9373                         if (connector->encoder != encoder)
9374                                 continue;
9375
9376                         intel_connector_break_all_links(connector);
9377                 }
9378         }
9379         /* Enabled encoders without active connectors will be fixed in
9380          * the crtc fixup. */
9381 }
9382
9383 void i915_redisable_vga(struct drm_device *dev)
9384 {
9385         struct drm_i915_private *dev_priv = dev->dev_private;
9386         u32 vga_reg = i915_vgacntrl_reg(dev);
9387
9388         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9389                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9390                 i915_disable_vga(dev);
9391         }
9392 }
9393
9394 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9395  * and i915 state tracking structures. */
9396 void intel_modeset_setup_hw_state(struct drm_device *dev,
9397                                   bool force_restore)
9398 {
9399         struct drm_i915_private *dev_priv = dev->dev_private;
9400         enum pipe pipe;
9401         u32 tmp;
9402         struct drm_plane *plane;
9403         struct intel_crtc *crtc;
9404         struct intel_encoder *encoder;
9405         struct intel_connector *connector;
9406
9407         if (HAS_DDI(dev)) {
9408                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9409
9410                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9411                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9412                         case TRANS_DDI_EDP_INPUT_A_ON:
9413                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9414                                 pipe = PIPE_A;
9415                                 break;
9416                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9417                                 pipe = PIPE_B;
9418                                 break;
9419                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9420                                 pipe = PIPE_C;
9421                                 break;
9422                         default:
9423                                 /* A bogus value has been programmed, disable
9424                                  * the transcoder */
9425                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9426                                 intel_ddi_disable_transcoder_func(dev_priv,
9427                                                 TRANSCODER_EDP);
9428                                 goto setup_pipes;
9429                         }
9430
9431                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9432                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9433
9434                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9435                                       pipe_name(pipe));
9436                 }
9437         }
9438
9439 setup_pipes:
9440         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9441                             base.head) {
9442                 enum transcoder tmp = crtc->config.cpu_transcoder;
9443                 memset(&crtc->config, 0, sizeof(crtc->config));
9444                 crtc->config.cpu_transcoder = tmp;
9445
9446                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9447                                                                  &crtc->config);
9448
9449                 crtc->base.enabled = crtc->active;
9450
9451                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9452                               crtc->base.base.id,
9453                               crtc->active ? "enabled" : "disabled");
9454         }
9455
9456         if (HAS_DDI(dev))
9457                 intel_ddi_setup_hw_pll_state(dev);
9458
9459         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9460                             base.head) {
9461                 pipe = 0;
9462
9463                 if (encoder->get_hw_state(encoder, &pipe)) {
9464                         encoder->base.crtc =
9465                                 dev_priv->pipe_to_crtc_mapping[pipe];
9466                 } else {
9467                         encoder->base.crtc = NULL;
9468                 }
9469
9470                 encoder->connectors_active = false;
9471                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9472                               encoder->base.base.id,
9473                               drm_get_encoder_name(&encoder->base),
9474                               encoder->base.crtc ? "enabled" : "disabled",
9475                               pipe);
9476         }
9477
9478         list_for_each_entry(connector, &dev->mode_config.connector_list,
9479                             base.head) {
9480                 if (connector->get_hw_state(connector)) {
9481                         connector->base.dpms = DRM_MODE_DPMS_ON;
9482                         connector->encoder->connectors_active = true;
9483                         connector->base.encoder = &connector->encoder->base;
9484                 } else {
9485                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9486                         connector->base.encoder = NULL;
9487                 }
9488                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9489                               connector->base.base.id,
9490                               drm_get_connector_name(&connector->base),
9491                               connector->base.encoder ? "enabled" : "disabled");
9492         }
9493
9494         /* HW state is read out, now we need to sanitize this mess. */
9495         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9496                             base.head) {
9497                 intel_sanitize_encoder(encoder);
9498         }
9499
9500         for_each_pipe(pipe) {
9501                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9502                 intel_sanitize_crtc(crtc);
9503         }
9504
9505         if (force_restore) {
9506                 /*
9507                  * We need to use raw interfaces for restoring state to avoid
9508                  * checking (bogus) intermediate states.
9509                  */
9510                 for_each_pipe(pipe) {
9511                         struct drm_crtc *crtc =
9512                                 dev_priv->pipe_to_crtc_mapping[pipe];
9513
9514                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9515                                          crtc->fb);
9516                 }
9517                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9518                         intel_plane_restore(plane);
9519
9520                 i915_redisable_vga(dev);
9521         } else {
9522                 intel_modeset_update_staged_output_state(dev);
9523         }
9524
9525         intel_modeset_check_state(dev);
9526
9527         drm_mode_config_reset(dev);
9528 }
9529
9530 void intel_modeset_gem_init(struct drm_device *dev)
9531 {
9532         intel_modeset_init_hw(dev);
9533
9534         intel_setup_overlay(dev);
9535
9536         intel_modeset_setup_hw_state(dev, false);
9537 }
9538
9539 void intel_modeset_cleanup(struct drm_device *dev)
9540 {
9541         struct drm_i915_private *dev_priv = dev->dev_private;
9542         struct drm_crtc *crtc;
9543         struct intel_crtc *intel_crtc;
9544
9545         drm_kms_helper_poll_fini(dev);
9546         mutex_lock(&dev->struct_mutex);
9547
9548         intel_unregister_dsm_handler();
9549
9550
9551         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9552                 /* Skip inactive CRTCs */
9553                 if (!crtc->fb)
9554                         continue;
9555
9556                 intel_crtc = to_intel_crtc(crtc);
9557                 intel_increase_pllclock(crtc);
9558         }
9559
9560         intel_disable_fbc(dev);
9561
9562         intel_disable_gt_powersave(dev);
9563
9564         ironlake_teardown_rc6(dev);
9565
9566         mutex_unlock(&dev->struct_mutex);
9567
9568         /* Disable the irq before mode object teardown, for the irq might
9569          * enqueue unpin/hotplug work. */
9570         drm_irq_uninstall(dev);
9571         cancel_work_sync(&dev_priv->hotplug_work);
9572         cancel_work_sync(&dev_priv->rps.work);
9573
9574         /* flush any delayed tasks or pending work */
9575         flush_scheduled_work();
9576
9577         /* destroy backlight, if any, before the connectors */
9578         intel_panel_destroy_backlight(dev);
9579
9580         drm_mode_config_cleanup(dev);
9581
9582         intel_cleanup_overlay(dev);
9583 }
9584
9585 /*
9586  * Return which encoder is currently attached for connector.
9587  */
9588 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9589 {
9590         return &intel_attached_encoder(connector)->base;
9591 }
9592
9593 void intel_connector_attach_encoder(struct intel_connector *connector,
9594                                     struct intel_encoder *encoder)
9595 {
9596         connector->encoder = encoder;
9597         drm_mode_connector_attach_encoder(&connector->base,
9598                                           &encoder->base);
9599 }
9600
9601 /*
9602  * set vga decode state - true == enable VGA decode
9603  */
9604 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9605 {
9606         struct drm_i915_private *dev_priv = dev->dev_private;
9607         u16 gmch_ctrl;
9608
9609         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9610         if (state)
9611                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9612         else
9613                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9614         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9615         return 0;
9616 }
9617
9618 #ifdef CONFIG_DEBUG_FS
9619 #include <linux/seq_file.h>
9620
9621 struct intel_display_error_state {
9622         struct intel_cursor_error_state {
9623                 u32 control;
9624                 u32 position;
9625                 u32 base;
9626                 u32 size;
9627         } cursor[I915_MAX_PIPES];
9628
9629         struct intel_pipe_error_state {
9630                 u32 conf;
9631                 u32 source;
9632
9633                 u32 htotal;
9634                 u32 hblank;
9635                 u32 hsync;
9636                 u32 vtotal;
9637                 u32 vblank;
9638                 u32 vsync;
9639         } pipe[I915_MAX_PIPES];
9640
9641         struct intel_plane_error_state {
9642                 u32 control;
9643                 u32 stride;
9644                 u32 size;
9645                 u32 pos;
9646                 u32 addr;
9647                 u32 surface;
9648                 u32 tile_offset;
9649         } plane[I915_MAX_PIPES];
9650 };
9651
9652 struct intel_display_error_state *
9653 intel_display_capture_error_state(struct drm_device *dev)
9654 {
9655         drm_i915_private_t *dev_priv = dev->dev_private;
9656         struct intel_display_error_state *error;
9657         enum transcoder cpu_transcoder;
9658         int i;
9659
9660         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9661         if (error == NULL)
9662                 return NULL;
9663
9664         for_each_pipe(i) {
9665                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9666
9667                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9668                         error->cursor[i].control = I915_READ(CURCNTR(i));
9669                         error->cursor[i].position = I915_READ(CURPOS(i));
9670                         error->cursor[i].base = I915_READ(CURBASE(i));
9671                 } else {
9672                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9673                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9674                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9675                 }
9676
9677                 error->plane[i].control = I915_READ(DSPCNTR(i));
9678                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9679                 if (INTEL_INFO(dev)->gen <= 3) {
9680                         error->plane[i].size = I915_READ(DSPSIZE(i));
9681                         error->plane[i].pos = I915_READ(DSPPOS(i));
9682                 }
9683                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9684                         error->plane[i].addr = I915_READ(DSPADDR(i));
9685                 if (INTEL_INFO(dev)->gen >= 4) {
9686                         error->plane[i].surface = I915_READ(DSPSURF(i));
9687                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9688                 }
9689
9690                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9691                 error->pipe[i].source = I915_READ(PIPESRC(i));
9692                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9693                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9694                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9695                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9696                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9697                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9698         }
9699
9700         return error;
9701 }
9702
9703 void
9704 intel_display_print_error_state(struct seq_file *m,
9705                                 struct drm_device *dev,
9706                                 struct intel_display_error_state *error)
9707 {
9708         int i;
9709
9710         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9711         for_each_pipe(i) {
9712                 seq_printf(m, "Pipe [%d]:\n", i);
9713                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9714                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9715                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9716                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9717                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9718                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9719                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9720                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9721
9722                 seq_printf(m, "Plane [%d]:\n", i);
9723                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9724                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9725                 if (INTEL_INFO(dev)->gen <= 3) {
9726                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9727                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9728                 }
9729                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9730                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9731                 if (INTEL_INFO(dev)->gen >= 4) {
9732                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9733                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9734                 }
9735
9736                 seq_printf(m, "Cursor [%d]:\n", i);
9737                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9738                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9739                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9740         }
9741 }
9742 #endif